W144HT

W144 SPECTRALINEAR | Alldatasheet

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Technical content

Features

• Maximized electromagnetic interference (EMI) suppression using Cypress’ Spread Spectrum technology  Single chip system frequency synthesizer for Intel ® 440BX AGPset  Two copies of CPU output  Six copies of PCI output 1  One 48 MHz output for USB  One 24 MHz output for SIO  Two buffered reference outputs  One IOAPIC output  Thirteen SDRAM outputs provide support for three DIMMs  Supports frequencies up to 150 MHz 2C interface for programming  Power management control inputs Note: 1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping while ** has an internal pull down resistor.

Table 1. Pin Selectable Frequency

Rev 1.0,November 21, 2006 Page 2 of 13 Pin Description Pin Name No. Type Description CPU_F 44 O Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to VDDQ2. See Tables 1 and 6 for detailed frequency information. CPU1 43 O CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI2:5 10, 11, 12, O PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI1/FS3 8 I/O Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through serial input interface, see Tables 1 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. PCI_F/MODE 7 I/O Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 1 and 6. This output is not affected by the PCI_STOP# input. When an input, sets function of pin 2. CLK_STOP# 41 I CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected clock outputs start, beginning with a full clock cycle (2–3 CPU clock latency). IOAPIC 47 O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW. 48MHz/FS0 26 I/O 48 MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will be latched, which will set clock frequencies as described in Table 1. 24MHz/FS1 25 I/O 24 MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip . Upon power-up FS1 input will be latched, which will set clock frequencies as described in Table 1. REF1/FS2 46 I/O I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which will set clock frequencies as described in Table 1. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. REF0/ (PCI_STOP#) 2I / O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. SDRAMIN 15 I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:11, SDRAM_F). SDRAM0:11 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 O Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. SDRAM_F 40 O Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN input which is not affected by the CLK_STOP# input SCLK 24 I Clock pin for I 2C Circuitry SDATA 23 I/O Data pin for I2C Circuitry X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 1, 6, 14, 19, 27, 30, P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply. VDDQ2 42, 48 P Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Connect to 2.5V or 3.3V. GND 3, 9, 16, 22, 33, 39, G Ground Connections: Connect all ground pins to the common system ground plane.

normally made upon system initialization, if any are required. functions of the serial data interface. Data is written to the W144 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4. Table 3. Serial Data Interface Control Functions Summary Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Enables or disables spread spectrum clocking. For EMI reduction. Output Three-state Puts clock output into a high-impedance state. Production PCB testing. Table 4. Byte Writing Sequence

1 Slave Address 11010010 Commands the W144 to accept the bits in Data Bytes 0–6 for internal

1. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver). addressed slave receiver on the serial data bus. receiver on the serial data bus.

1. Bits are written MSB (most significant bit) first, which is bit 7.

available through the serial data interface. Table 7 details the select functions for Byte 0, bits 1 and 0.

4 Data Byte 0 Refer to Table 5 The data bits in Data Bytes 0–7 set internal W144 registers that control

functions, refer to Table 5, Data Byte Serial Configuration Map.

5 Data Byte 1

6 Data Byte 2

7 Data Byte 3

8 Data Byte 4

9 Data Byte 5

10 Data Byte 6

11 Data Byte 7

Table 4. Byte Writing Sequence (continued) Table 5. Data Bytes 0-7 Serial Configuration Map

Rev 1.0,November 21, 2006 Page 7 of 13 Data Byte 2 7– –( R e s e r v e d ) – – 0 6 7 PCI_F Clock Output Disable Low Active 1 5 – – (Reserved) – – 0 4 13 PCI5 Clock Output Disable Low Active 1 3 12 PCI4 Clock Output Disable Low Active 1 2 11 PCI3 Clock Output Disable Low Active 1 1 10 PCI2 Clock Output Disable Low Active 1 0 8 PCI1 Clock Output Disable Low Active 1 Data Byte 3 7– –( R e s e r v e d ) – – 0 6– –( R e s e r v e d ) – – 0 5 26 48MHz Clock Output Disable Low Active 1 4 25 24MHz Clock Output Disable Low Active 1 3– –( R e s e r v e d ) – – 0 2 21, 20, 18, 17 SDRAM8:11 Clock Output Disable Low Active 1 1 32, 31, 29, 28 SDRAM4:7 Clock Output Disable Low Active 1 0 38, 37, 35, 34 SDRAM0:3 Clock Output Disable Low Active 1 Data Byte 4 7– –( R e s e r v e d ) – – 0 6– –( R e s e r v e d ) – – 0 5– –( R e s e r v e d ) – – 0 4– –( R e s e r v e d ) – – 0 3– –( R e s e r v e d ) – – 0 2– –( R e s e r v e d ) – – 0 1– –( R e s e r v e d ) – – 0 0– –( R e s e r v e d ) – – 0 Data Byte 5 7– –( R e s e r v e d ) – – 0 6– –( R e s e r v e d ) – – 0 5– –( R e s e r v e d ) – – 0 4 47 IOAPIC Clock Output Disable Low Active 1 3– –( R e s e r v e d ) – – 0 2– –( R e s e r v e d ) – – 0 1 46 REF1 Clock Output Disable Low Active 1 0 2 REF0 Clock Output Disable Low Active 1 Data Byte 6 7– –( R e s e r v e d ) – – 0 6– –( R e s e r v e d ) – – 0 5– –( R e s e r v e d ) – – 0 4– –( R e s e r v e d ) – – 0 3– –( R e s e r v e d ) – – 0

Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes[2] Table 7. Select Function for Data Byte 0, Bits 0:1

1. CPU and PCI frequency selections are listed in Table 1 and Table 6.

Rev 1.0,November 21, 2006 Page 9 of 13 Absolute Maximum Conditions[3] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPU_F, CPU1 = 100.2 MHz Outputs Loaded[4] –2 6 0 – m A IDD 2.5V Supply Current CPU_F, CPU1 = 100.2 MHz Outputs Loaded[4] –2 5 – m A Logic Inputs VIL Input Low Voltage GND – 0.3 –0 . 8 V VIH Input High Voltage 2.0 – V DDQ3 + 0.3 V IIL Input Low Current[5] –– – 2 5 PA IIH Input High Current[5] ––1 0 PA IIL Input Low Current (SEL100/66#) – – –5 PA IIH Input High Current (SEL100/66#) – – +5 PA Clock Outputs VOL Output Low Voltage I OL = 1 mA – – 50 mV VOH Output High Voltage I OH = 1 mA 3.1 – – V VOH Output High Voltage CPU_F,1, IOAPIC IOH = –1 mA 2.2 – – V IOL Output Low Current CPU_F, CPU1 V OL = 1.25V 27 57 97 mA PCI_F, PCI1:5 V OL = 1.5V 20.5 53 139 mA IOAPIC V OL = 1.25V 40 85 140 mA REF0:1 V OL = 1.5V 25 37 76 mA 48MHz V OL = 1.5V 25 37 76 mA 24MHz V OL = 1.5V 25 37 76 mA IOH Output High Current CPU_F, CPU1 V OH = 1.25V 25 55 97 mA PCI_F, PCI1:5 V OH = 1.5V 31 55 139 mA IOAPIC V OH = 1.25V 40 87 155 mA REF0:1 V OH = 1.5V 27 44 94 mA 48MHz V OH = 1.5V 27 44 94 mA 24MHz V OH = 1.5V 25 37 76 mA Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. All clock outputs loaded with 6" 60 : traces with 22-pF capacitors. 5. W144 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.

Rev 1.0,November 21, 2006 Page 10 of 13 TA = 0°C to +70°C; V DDQ3 = 3.3V±5%; V DDQ2 = 2.5V±5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. Crystal Oscillator VTH X1 Input threshold Voltage[6] VDDQ3 = 3.3V – 1.65 – V CLOAD Load Capacitance, Imposed on External Crystal[7] –1 4 – p F CIN,X1 X1 Input Capacitance[8] Pin X2 unconnected – 28 – pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 – – 5 pF COUT Output Pin Capacitance – – 6 pF LIN Input Pin Inductance – – 7 nH Parameter Description Test Condition Min. Typ. Max. Unit CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6 MHz CPU = 100.2 MHz tP Period Measured on rising edge at 1.25 15 – 15.5 9.98 – 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.6 – – 3.3 – – ns tL Low Time Duration of clock cycle below 0.4V 5.3 – – 3.1 – – ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1.5 – 4 1.5 – 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1.5 – 4 1.5 – 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 – 55 45 – 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. – – 200 – – 200 ps tSK Output Skew Measured on rising edge at 1.25V – – 250 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. ––3––3 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. –2 0– –2 0– : Notes: 6. X1 input threshold voltage (typical) is V DDQ3/2. 7. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

Rev 1.0,November 21, 2006 Page 11 of 13 SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments CPU = 66.6 MHz CPU = 100.2 MHz tP Period Measured on rising edge at 1.5V 30 – – 30 – – ns tH High Time Duration of clock cycle above 2.4V, at min. edge rate (1.5V/ns) 5.6 – – 3.3 – – ns tL Low Time Duration of clock cycle below 0.4V, at min. edge rate (1.5V/ns 5.3 – – 3.1 – – ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 – 4 1.5 – 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 – 4 1.5 – 4 V/ns tPLH Prop Delay LH Input edge rate faster than 1V/ns 1 – 5 1 – 5 ns tPHL Prop Delay HL Input edge rate faster than 1 V/ns 1 – 5 1 – 5 ns tD Duty Cycle Measured on rising and falling edge at 1.5V,at min. edge rate (1.5 V/ns) 4 5–5 5 4 5–5 5 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. – – 250 – – 250 ps tSK Output Skew Measured on rising edge at 1.5V – – 250 – – 250 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 – 4 1.5 – 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. ––3––3 m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. –3 0– –3 0– : PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF) Parameter Description T est Condition/Comments CPU = 66.6/100.2 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 29.9 – – ns tH High Time Duration of clock cycle above 2.4V 12.0 – – ns tL Low Time Duration of clock cycle below 0.4V 12.0 – – ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 – 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 – 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. –– 2 5 0 p s tSK Output Skew Measured on rising edge at 1.5V – – 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 – 4.0 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. –– 3 . 0 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. –3 0– :

Rev 1.0,November 21, 2006 Page 12 of 13 IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100.2 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 – 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 – 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 – 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. –– 1 . 5 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. –1 5– : REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100.2 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 – 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2V / n s tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. ––3 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. –4 0– : 48 MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz Parameter Description Test Condition/Comments CPU = 66.6/100.2 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by PLL divider ratio (see p/q below) –48.008– MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm p/q PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) –57/17 t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 – 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 – 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. ––3 m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. –4 0– : 24 MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz Parameter Description Test Condition/Comments CPU = 66.6/100.2 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by PLL divider ratio (see p/q below) 24.004 MHz fD Deviation from 24 MHz (24.004 – 24)/24 +167 ppm p/q PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) 57/34 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 – 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 – 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 %

Rev 1.0, November 21, 2006 Page 13 of 13 W144 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Package Drawing and Dimension fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. ––3 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. –4 0– :

Ordering Information

Ordering Code Package Type W144H 48-Pin SSOP (300-mil) W144HT 48-Pin SSOP (300-mil) – Tape and Reel 24 MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz (continued) Parameter Description Test Condition/Comments CPU = 66.6/100.2 MHz UnitMin. Typ. Max. 4 8 - L e a dS h r u n kS m a l lO u t l i n eP a c k a g eO 4 8