VERSAKIT-30XX RAMTRON | Alldatasheet
Document overview
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Technical content
User Guide Rev 2.0 This user gui de addresses the features, setup and operation of th e VersaKit d evelopment system fo r t he evalu ation and programming of Ramtron’ s hi gh pe rformance, fully- integrated, FRAM-Enhanced™, 8051- based VRS51L3xxx microcontrollers. Table of Contents Ramtron International Corporation ♦ http://www.ramtron.com
1850 Ramtron Drive Colorado Springs ♦ MCU customer service: 1-800-943-4625, 1-514-871-2447 x 208
Colorado, USA, 80921 1-800-545-FRAM, 1-719-481-7000 page 1 of 28
1 VersaKit-30xx Development System Overview
The VersaKit-30xx development kit is a plug-and-play evaluation system for the VRS51L3xxx series of high performance, fully-integrated, FRAM-Enhanced™ 8051 microcontrollers. The VersaKit-30xx provides a compl ete and comprehensive programming and development platform, with ample prototyping space and easy access to chip peripherals and I/Os. The VersaKit-30xx development system features:
- VRS51L3074 in QFP-64 package soldered onboard (contact Ramtron for details on the VRS51L3174 in QFP-44 package and the VRS51L2070)
- FM31xx MCU companion, FM25xx SPI FRAM and FM24xx I²C FRAM devices installed
- 5x2 header to connect VJTAG-USB programming/debugging interface
- 2 DB9 serial port female connectors and 1 onboard RS-232 transceiver with configuration jumper
- Tact switches for manual reset and external interrupt of the processor
- Four sets of 16 probing points around VRS51L3074 device
- 22x2 header alongside prototyping area to access QFP-44 device pins (header pin number corresponds to device pin number)
- 32x2 header alongside prototyping area to access QFP-64 device pins (header pin number corresponds to the device pin number)
- Prototyping space
- Character LCD interface header footprint
- External crystal footprint
- 8 uncommitted user LEDs
- Onboard 3.3V regulator with power-on LED
- Optional regulator footprint
1.1 The VersaKit-30xx content:
o Development board that supports the VRS51L3074 (or the VRS51L2070) o VJTAG-USB programming/debugging interface o USB Cable o 6V Power supply Figure 1: VersaKit-30xx www.ramtron.com page 2 of 28
1.2 Supported Devices
The VersaKit-30xx ships with a VRS51L3074-40-Q soldered onto the development board. VRS51L3174 Evaluation Note that the VersaKit-30xx can also b e used for e valuation of the VRS51 L3174 (44-pin versi on of the VRS51L3074), since its peripherals are a subset of th e VRS51L3074. A dedicated development board will be available for the 44-pin VRS51L3174 (part number VersaKit-31xx) in the future that is based on the VersaKit-30xx (there is a 44-pin QFP footprint under the i nstalled VRS5 1L3074 on th e VersaKit-30 xx devboard for this purpose). Users should co ntact Ramtron for VersaKit-31xx availability. In the short term, code can be developed on th e VRS51L3074 and easily ported to the VRS51L3174. This user guide will address features associated with the VersaKit-31xx development board.
2 Overview of the VersaKit-30xx Development Board
The figure below offers a detailed look at the Versa Kit-30xx development board and its principal features, which will be addressed in this document. Figure 2: VersaKit-30xx development board www.ramtron.com page 3 of 28
2.1 Power Supply Requirements
power supply connected to PJ1. The VJTAG-USB provides up to about 110mA of power to the devboard or target board. with the VersaKit-30xx. This should be connected to PJ1 on the devboard and can supply up to 300mA. Note: If the external power supply is connected to PJ1, remove the JP1 jumper on the VJTAG-USB board. Table 1. Development board power supply specifications you choose meets the requirements above before using it with the development board. Ensure that the input voltage supplied to the devboard PWR-IN input is always below 11 volts.
2.2 VersaKit-30xx Devboard: Onboard Power Supply Configuration Regulators & JP1 Jumper
available via two 4x2 header footprints located on each side of the prototyping area. VDD to the Reg102-3.3 regulator output. may become hot when the regulators are operating. Warning: It is mandatory to remove resistor R9 when installing a regulator in position U4.
P1, P2 - RS-232 DB9 Connectors for Serial Ports The development board includes a 2-channel RS-232 transceiver and two DB9 connectors to access the VRS51L3074’s UARTs. P1 – Provides access to VRS51L3074 UART 0 P2 – Provides access to VRS51L3074 UART 1 A set of fo ur jumpers enables the P1 and P2 connectors to be assigned to the UARTs. A set of four headers (JP2, JP3, JP4, JP5) located directly below the P1 DB9 Connector configures the connection between the VRS51L3074, the RS-232 transceiver and DB9 connectors P1 and P2. Several configurations are possible with different header settings, but the two configurations below are the most typical: Typical Configuration 1 JP2 1-2 VRS51L3074 UART1 P1.2-RXD1 routed on P1 JP3 1-2 VRS51L3074 UART1 P1.3-TXD1 routed on P1 JP4 1-2 VRS51L3074 UART0 P3.0-RXD0 routed on P2 JP5 1-2 VRS51L3074 UART0 P3.1-TXD0 routed on P2 JP2 JP3 1 1 JP4 JP5 1 1 Typical Configuration 2 JP2 2-3 VRS51L3074 UART1 RXD1a routed on P1 (alternate UART1 pins) JP3 2-3 VRS51L3074 UART1 TXD1a routed on P1 (alternate UART1 pins) JP4 2-3 VRS51L3074 UART0 P2.4-RXD0a routed on P2 (alternate UART1 pins) JP5 2-3 VRS51L3074 UART0 P2.3-TXD0a routed on P2 (alternate UART1 pins) JP2 JP3 1 1 JP4 JP5 1 1 Figure 4: Typical configurations for headers and serial ports 2.4 www.ramtron.com page 5 of 28
2.4.1 Probe headers for peripheral and I/O access around the VRS51L3074 QFP-64
The follo wing figure shows th e pin connections o f the head er footprints l ocated around VRS51L 3074-40-Q on t he development board: Figure 7: Probing vias around the VRS51L3074
2.4.2 Header footprints for VRS51L3074 QFP-64 peripherals and I/O access
To access the VRS51L3074 I/Os a nd peripherals, the d evboard provides a 6 4-pin header footprint nea r the prototyping area. This header footprint provides access to all pins on the chip. The diagram below shows the header footprint pin-out. P1.5 - SDO P3.0 - RXD0 - PC0.1 P1.7 - SDI – SDA* RESET P4.4 P1.1-CS1-T2EX P1.3 - CS3 - TXD1 P1.0 - CS0-T2IN P4.0-T1OUT P2.1-PWM1-AD9 P2.3-PWM3-TXD0*-AD11 P2.5-PWM5-AD13 P3.1 - TXD0 P0.2-AD2 P4.3-TDI P0.6-AD6 P0.4-AD4 CM0-ALE P0.0-AD0 P2.7-PWM7-AD15 VDD P1.6 - SCK-SCL*-PC1.3 P1.2-CS2-RXD1-PC1.1-T2OUT* P1.4 – SS-T1OUT* P4.5 - T0OUT P3.6-WR XTAL1-P4.6 GND P2.0-PWM0-AD8 P2.2-PWM2-AD10 P0.5 - AD5 P4.2-TDO P0.7 - AD7 P0.3 - AD3 P0.1 - AD1 P4.1-TME P2.4-PWM4-RXD0*-AD12 P2.6-PWM6-AD14 P3.3-INT1-PC1.0 P3.7-RD XTAL2-P4.7 P3.5-T1-SDA-T1IN P3.2 - INT0 - PC0.0 P3.4-SCL-T0IN -PC0.3 37 39 41 43 2 4 68 10 12 14 16 18 20 22 24 26 28 30 32 38 40 42 44 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 331 57 59 61 63 46 48 50 52 58 60 62 64 45 47 49 51 53 P5.1 - PWM1* P5.3 - PWM3* P5.0 – PWM0* P5.2 – PWM2* GND P5.4 – PWM4* P5.6 – PWM6*P5.5 – PWM5* P5.7 – PWM7* VDD T1EX-TXD1* RXD1-T0EX-PC1.2 P6.7-A7 P6.5-A5P6.6-A6 P6.4-A4 P6.2-A2 P6.3-A3 P6.1-A1 P6.0-A0 H17 – VRS51L3074 QFP-64 Peripheral and I/O Access Figure 8: Pin description of H17 I/O and peripheral access www.ramtron.com page 7 of 28
2.4.3 Probe headers for peripherals and I/O access around the VRS51L3174 QFP-44
The followi ng figure sho ws the pin co nnections of the header footprint s loca ted arou nd VRS51L 3174 QFP-4 4 on the development board: Figure 9: Probing vias around the VRS51L3174
2.4.4 Header footprints for VRS51L3174 QFP-44 peripheral and I/O access
To access the VRS51L3174 QFP-44 I/Os and peripherals, the development board provides a 44-pin header footprint near the prototyping area. This header footprint provides access to all the pins on the chip. The diagram below describes the header footprint pin-outs. P1.5 - SDO P3.0 - RXD0 - PC0.1 P1.7 - SDI – SDA* RESET P4.4 P1.1-CS1-T2EX P1.3 - CS3 - TXD1 P1.0 - CS0-T2IN P4.0-T1OUT P2.1-PWM1-AD9 P2.3-PWM3-TXD0*-AD11 P2.5-PWM5-AD13 P3.1 - TXD0 P0.2-AD2 P4.3-TDI P0.6-AD6 P0.4-AD4 CM0-ALE P0.0-AD0 P2.7-PWM7-AD15 VDD P1.6 - SCK-SCL*-PC1.3 P1.2-CS2-RXD1-PC1.1-T2OUT* P1.4 – SS-T1OUT* P4.3 - T0OUT P3.6-WR XTAL1-P4.6 GND P2.0-PWM0-AD8 P2.2-PWM2-AD10 P0.5 - AD5 P4.2-TDO P0.7 - AD7 P0.3 - AD3 P0.1 - AD1 P4.1-TME P2.4-PWM4-RXD0*-AD12 P2.6-PWM6-AD14 P3.3-INT1-PC1.0 P3.7-RD XTAL2-P4.7 P3.5-T1-SDA-T1IN P3.2 - INT0 - PC0.0 P3.4-SCL-T0IN -PC0.3 H16 – VRS51L3174 QFP-44 Peripherals and I/Os access 37 39 41 43 2 4 68 10 12 14 16 18 20 22 24 26 28 30 32 38 40 42 44 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 331 Figure 10; Pin description of H21 access to VRS51L3174 QFP-44 peripherals www.ramtron.com page 8 of 28
Ground Points on the Development Board The VersaKit-30xx development board provides a g round access point (S1) located above t he H18 Header on the right side of the PCB. This point can be used to connect measurement instruments to ground.
2.5 Tact Switches
The development board includes two tact switches: o SW1 – VRS 51L3074 Re set S witch. This switch allows a m anual reset of the V RS51L3074 devi ce. The VRS51L3074 reset is active low. Note: During programming or i n-circuit debugging of the VRS51 L3074, do n ot press SW1. Doing so could result in loss of synchronization between the Versa Ware JTAG software and VRS51L3074 debugger. o SW2 – V RS51L3074 Interrupt Switch. This switch allows users to manually send a low pulse to the devi ce’s INT0 pin. A connection can be established from the SW2 to the VRS51L3074 INT1 pin by installing a 0Ω resistor at position R28 and removing the 0Ω resistor from R27.
2.6 User LEDs
The develo pment boa rd i ncludes a se t of eight uncommitt ed, 3 mm, gree n u ser LEDs. The ano de of each LE D i s connected to the board’s VCCMCU supply line through a 680R current limiting resistor, while the cathode of each LED is connected to the user LED’s H13 header footprint.
2.7 Character LCD Module Header Footprint
The d evelopment bo ard feature s a he ader footpri nt (L CD1) fo r easy in stallation of a cha racter LCD module. When installed, the character LCD module header footprint and the VRS51L3074 are configured as follows: Table 2: Character LCD header footprint pin-out LCD Connected to LCD Data [7:4] P0 [7:4] LCD Data [3:0] Not connected LCD E P0.2 LCD RW P0.1 LCD RS P0.0 LCD VEE Accessible through H9 Most character LCD modules require a 5V supply. The LCD supply is accessed through H14. If the LCD module operates from 3.3V, a 0Ω resistor can be installed at position R31 to connect the LCD module supply and the devboard supply. The LCD drive pin (VEE) is accessible through H9. The LCD driving voltage that must be applied on the VEE pin of the LCD module depends on t he LCD type and varies among different manufacturers. Please consult the d atasheet of your specific L CD module to e stablish the proper voltag e. For your convenience, we have in cluded a n unp opulated 080 5 resistor footprint between t he H9 and the LCD VEE pin, as well as a 0805 capacitor footprint between the LCD VEE pin and the development board ground. The LCD module backlight pins are accessible via the H15 2x1 header footprint www.ramtron.com page 9 of 28
2.8 Onboard FM24C64 I2C FRAM, FM25CL64 SPI FRAM and FM31256 MCU Companion
A 5V, 64Kb I²C F RAM device (FM24CL64) is included with the development board at position U8. Th e SCL and SDA lines of FM24C64 are connected to the H12 2x1 header footprint. The development board also features a FM31256 Processor Companion including FRAM at position U8, featuring 256Kb of FRAM memory, a real-time clock (RTC), a wat chdog timer, an event counter and power fail monitoring circuitry. A 32 kHz crystal required for driving the FM31256’s RTC is also included on the PCB. Two 2K Ω pull-up resistors (R15 a nd R16) a re co nnected between the 3. 3V su pply a nd the SDA and SCL li nes, respectively. Two h eader footprints are provided for accessing the FM3164 I/Os. T he FM3164’s I²C communications interface is connected to H12. Finally, an F M25CL64, a 3V 64Kb SPI FRAM, is al so in stalled on the d evelopment board at po sition U5. Th e devi ce communication interface I/Os are accessible through the H7 header footprint.
3 Overview of the VJTAG-USB interface
The VJTAG-USB boa rd i s a USB-based JTAG i nterface fo r in-circuit pro gramming a nd de bugging of Ra mtron’s VRS51L3074 and other JTAG-based microcontrollers. The VJTAG-USB connects directly to the VersaKit-30xx devboard and can be used on any prototype/production board featuring a Ramtron JTAG based MCU. The following figure depicts the VJTAG-USB interface and its principal features. Figure 11: VJTAG-USB Interface www.ramtron.com page 10 of 28
3.1 VJTAG-USB Power Supply Considerations and JP1 Header
The VJTAG-USB interface takes po wer via the USB serial bus; It can be used to provide a 3.3V supply to eith er the devboard or the connected target board, provided that the power current consumption does not exceed \`~100mA in total. The JP1 Jumper provides a connection between the VJTAG-USB 3.3V power supply and the target board 3.3V power. If the target board gets its power supply from an external source, such as a DC ada ptor, we recommended removing the JP1 Jumper.
3.2 Power and Status LEDs
The VJTAG-USB features two green surface mount LEDs indicating the state of the board. The power LED is connected to the 3.3V supply of the VJTA G-USB. Depending on the state of the USB driver, when the USB cable is connected to the VJTAG-USB, the power LED may either turn ON or stay OFF. However, when the Versa Ware JTAG software is activated and the target device is recognized, the power LED will turn on and remain on. If the USB ca ble is disconnected from the VJTAG-USB board wh ile the Versa Ware JTAG is idling, when you reconnect the board, the power LED will remain off until the <Synchronize> button is clicked. The status LED reports on communication between the Versa Ware JTAG software and the VJTAG-USB board. Table 3: VJTAB-USB LED Functions Status LED Programmer Mode Debug Mode Off Versa Ware J TAG Software is idling: The program in th e target may or may not run. Status LED should be ON or blinking Sporadic blinking Indicates that the Vers a Ware JTAG Software and the V JTAG- USB board are communicating Some operat ions such as <Restart>, will m ake both power and status LEDs ,blink Blink X The target processor device is executing code On X The target processor has halted www.ramtron.com page 11 of 28
3.3 H2 JTAG Interface Connector
The VJTAG-USB features a 5x2 female so cket (H2), located on t he bottom si de of t he PCB. H2 is use d to access t he JTAG interface port of the VRS51L3074, which is installed on the devboard or target board. On the devboard, the JTAG interface is accessed using a 5x2 male header. The header pin-out is shown below: Figure 12: VJTAG-USB interface connector pin-out The P WRCTRL li ne on t he ta rget board’s JTAG header i s op tional. However, if the target boa rd supply is fro m an external source and the o nboard regulator does not have a po wer control fea ture, uncheck “Automatic power control” in the Versa Ware JTAG Software Device Options window. Figure 13: Versa Ware Automatic power control setting www.ramtron.com page 12 of 28
4 Minimal Configuration of the Target Board
The follo wing diagram de monstrates the targ et bo ard configuration req uired for in-circuit prog ramming and in -circuit debugging of the VRS51L2070/3074 using the VJTAG-USB interface. Figure 14: JTAG interface access on target board www.ramtron.com page 13 of 28
5 Development Kit Setup for VRS51L3074 Evaluation
5.1 VersaKit-30xx Hardware Setup
The VRS51L3074 includes a Versa-JTAG programming/debugging interface port, accessed via the 5x2 header at position H2 (JTAG) on the development board. To evaluate the VRS51L3074, use the VersaKit-30xx VJTAG-USB to interface with Ramtron’s Windows®-based Versa Ware JTAG programming/debugging software. Figure 15: VJTAG-USB interface for programming and debugging the VRS51L3074
5.1.1 Basic VersaKit-30xx setup for VRS51L3074 evaluation
Setup of the VersaKit-30x x is quick a nd easy. Fail ure to perform the setu p operations in the re commended order may result in software/OS instability. First, insert the VJTAG -USB into the Ve rsaKit-30xx devboard’s Header H2 so that the CN1, USB conn ector sits di rectly above the rightmost DB9 connector. If the VJTAG -USB is goi ng to provide th e power supply for the de vboard, then a jumper should be in serted at positio n JP1. If the board i s going to receive power from an external source, remove t he jumper from JP1. Figure 16: Step 1: Install the VJTAG-USB on the development board Next, connect the external power supply to the devboard (if required) and then connect the USB cable to the VJTAG-USB cboard. www.ramtron.com page 14 of 28
5.2 Overview of the Versa Ware JTAG Software
Versa Ware JTAG is a Windows®-based software tool that provides a user-friendly development platform for all Ramtron microcontrollers featuring a JTAG interface (the VRS51L2xxx, VRS51L3xxx and future derivatives). The Versa Ware JTAG Software is composed of two parts: o Versa Ware JTAG Programmer The Versa Ware JTAG Programmer is used to p erform operations such as erase, program, read, etc., on the ta rget device’s Flash memory. o Versa Ware JTAG Debugger The Versa Ware JTAG Debugger is a user interface that links the in-circuit debugger and the source code. All Ramtron MCUs with a JTAG i nterface include an integrated d ebugger that enables in-application debugging of the device via its JTAG interface. The Versa Ware JTAG Debugger is compatible with the SDCC, Keil and Ride compilers. The Versa Ware JTA G softwa re was develope d o n Wind ows XP, but shou ld ope rate properly o n Wi ndows Vi sta and Windows 2000 operating systems. It sh ould also work on a Window 98 SE operating system on a computer with a UBS interface. Users with out a USB interface, can use Ramtron’s parallel port version of the JTAG interface. Please contact Ramtron to order one. The following window shows the in-circuit debugger in action when the source code XRAM, SFR page 0, and watch list windows are open and the program is halted at a breakpoint. Figure 19: Versa Ware JTAG debugger window The Versa Ware JTAG De bugger provides a comp rehensive set of configuration options allowing users to tailor th e user interface, watch variables and breakpoints settings. www.ramtron.com page 16 of 28
5.3 Installing the Versa Ware JTAG Software
Installing the Versa Ware JTAG software is a two-step process that is handled automatically by the installation program.
- Versa Ware JTAG software installation
- Prolific PL2303X USB driver installation As with mo st softwa re/driver install ations, we sugg est creat ing a System Restore point be fore ru nning the setup. T o install Versa Ware JTAG, run the Versa_Ware_JTAG_3x_SETUP.exe file available for do wnload on the Ramtron Web site and follow the instructions provided by the installation wizard. Figure 20: Versa Ware JTAG Setup www.ramtron.com page 17 of 28
5.4 Getting Started Using the Versa Ware JTAG Software
Once the software is i nstalled, it can be run directly from the setup program, or by clicking on the Ve rsa Ware JTAG shortcut created during the installation process.
5.4.1 Versa Ware JTAG programming interface
Upon startup, the software will attempt to connect to the VJTAG-USB interface. Action Toolbar File Information Window Status Bar Figure 21: Versa Ware JTAG programming interface Most of the functions provided by the Versa Ware JTAG software are executable via the action toolbar. To download a HEX file into the VRS51L3074: 1. Ensure that the Versa-JTAG interface is properly connected to the H2 header of the development board. 2. Click on the synchronize button. The status bar should show: “VRS51L3074-40-Q waiting for instruction”. 3. Click open to select the HEX file to be programmed into the VRS51L3074. 4. Click erase then program to era se and program the Flash. By default, after this process i s complete, t he program will start. www.ramtron.com page 18 of 28
synchronize button can be used to halt execution of the VRS51L3074 program and put the device into program mode. The run button restarts program execution. The options button allo ws configuring the programming options, set the Flash security options, and a ctivates the in - circuit debugger. Figure 22: Versa Ware JTAG Device Options Changes to any of the device options will become effective the next time an erase then program operation is initiated. www.ramtron.com page 19 of 28
5.4.2 Using the Versa Ware JTAG Debugger
Once the program is loaded into the VRS51L3074 Flash memory and the debugger is enabled, activate the debugger by clicking on the debugger button. Upon startup, the debugger will halt the processor at address 0x0000 and wait. Figure 23: Versa Ware Debugger upon startup Once the debugger starts, you can either run the program at full speed by clicking on run or set a breakpoint anywhere in the code by either double clicking on a specific code line and then pressing run or by setting the breakpoint manually. Alternatively, you can manually set breakpoints anywhere in the code by clicking the breakpoint setting button www.ramtron.com page 20 of 28
Once a breakpoint is reached, you can either:
- Restart the program by clicking again on run
- Single step through the code by clicking on step
- View/Edit the SFR, IRAM, XRAM memory location by clicking SFR , IRAM and XRAM buttons. When step is cli cked, the processor will execute the current instruction and step to the next instruction (and actually stop). T he SFR, IRAM, XRAM or FRAM memory content can be viewed and edited at a ny time after a bre akpoint is reached (this includes step mode). The debugger provides table and list view options for the SFR, IRAM, XRAM and FRAM memory areas. It is also possible to open multiple windows for each of these memory areas. Editing a given SFR, IRAM, XRAM and FRAM memory cell is simple:
- Double click on the memory location to be edited.
- Type in the new value to be written.
- Press <Enter> or double click another memory location. Notes on the SFR edition: In the case of the SFR memory location, it is important to note that some registers are partially or totally read or write only or can only be accessed when the related peripheral is activated. The SFR edition feature allows the user to partially control the peripheral.
5.5 Updating the Code without exiting the debugger
If during a debug session, you want to modify the code, recompile and reload the code into the Flash memory. The Versa Ware JTAG allows you to reload the code in Flash memory without exiting the Versa Ware JTAG debugging environment. To do this, open the editor, modify the code and recompile it. Then return to the debugger and click on erase then program button. Note that all the breakpoints you have set will be lost.
5.6 Exiting the Debugger
To exit the debugger, click on stop debugging . This will bring you back in the Versa Ware JTAG programming environment. www.ramtron.com page 22 of 28
5.7 Summary of Versa Ware JTAG Debugger Commands
The following table summ arizes the Ve rsa Ware JTAG Debugger commands. Please con sult the Versa Ware JTAG help for a detailed description of software features. Table 4: Debugger command set Command Toolbar Toolbar button Menu Keyboard Shortcut Stop Debugging Debugger Action Halt Debugger Action Ctrl + Backspace Run Debugger Action F7 Step Debugger Action F6 Jump Debugger Action Restart Debugger Action Breakpoint Settings Debugger Breakpoint Ctrl + Shift + B Toggle Breakpoint 0 Breakpoint Ctrl + B Toggle Breakpoint 1 - 5 Breakpoint Ctrl + F1 to Ctrl + F5 Run to Cursor Breakpoint F12 View Program Trace Debugger View Ctrl + Shift + T View SFR Debugger View Ctrl + Shift/Alt + S View XRAM Debugger View Ctrl + Shift/Alt + X View IRAM Debugger View Ctrl + Shift/Alt + I View FRAM (VRS51L307x) Debugger View Ctrl + Shift + F View Watch Debugger View Ctrl + Shift + W View Toolbars View View Options View Ctrl + Shift + V Add Watch Debugger Watch Edit Watch Debugger Watch Remove Watch Debugger Watch Force Watch Debugger Watch Refresh Debugger View Ctrl + R View C files View View C + Asm View View Assembler files View Cascade View Window Tile View Window 60:40 Horizontal View Window 75:25 Vertical View Window Find Edit Ctrl + F Find Next Edit F3 Copy Edit Ctrl + C Next Function Block Edit Ctrl + PgDn Previous Function Block Edit Ctrl + PgUp Go to Address Edit Ctrl + Alt + G Go to Line Edit Ctrl + Shift + G Go to Stopped Edit Ctrl + G Erase then Program Program Flash F5 Erase Page Program Flash Read Flash Program Flash Help topics About Versa Ware JTAG Help www.ramtron.com page 23 of 28
6 VersaKit-30xx Development Board Schematics
6.1 VRS51L3074
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6.2 VRS51L3074 Peripheral Access
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6.3 RS-232 Interface and Reset
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6.4 Accessories
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6.5 Pow er Supply
Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. Customers should obtain the most current and relevant information before placing orders. Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Ramtron parts. Ramtron assumes no liability for applications assistance or customer product design. Life support – Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling Ramtron products for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages resulting from such applications. I²C is a trademark of Koninklijke Philips Electronics NV. www.ramtron.com page 28 of 28