V6108 EMMICRO | Alldatasheet

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Technical content

Features

‰ Serial data input / output ‰ Low dynamic current, 5 µA max. ‰ Low standby current , 1 µA max. ‰ Separate input and display voltages ‰ Wide power supply range : VDD (logic) 2 to 8V, VLCD (display) VDD to 12V ‰ On-chip latches separate control and display sections ‰ Drives up to 40 LCD segments in direct drive ‰ Crossfree cascadable ‰ Schmitt Trigger on the inputs ‰ 30 ns (typ.) glitch filter on every input ‰ High noise immunity ‰ Segment outputs short circuit protected ‰ LCD blanking function ‰ -40 to +85°C temperature range ‰ On request extended temperature range, -40 to +125°C ‰ QFP52 and TAB packages Typical Operating Configuration Fig. 1 Pin Assignment Fig. 2 EM MICROELECTRONIC - MARIN SA

R V6108 Copyright © 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com Absolute Maximum Ratings Parameter Symbol Conditions Logic supply voltage VDD -0.3V to +10V LCD supply voltage (Note1) VLCD -0.3V to +14V Voltage at DI, CLK, STR, FR, R, DO VLOGIC -0.3V to VDD + 0.3V Voltage at S1 to S40 VDISP VDD to VLCD + 0.3V Storage temperature range TSTO -65 to 150°C Power dissipation PMAX 100 mW Maximum electrostatic discharge to MIL-STD-883C method 3015.7 with ref. to VSS VSmax 1000V Max. soldering conditions TS 250°C x 10s Table 1 Note 1 : VLCD has to be higher or equal to VDD Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min Max Unit Operating Temperature (Note 1) TA -40 +125 °C Logic supply voltage VDD 2.0 8 V LCD supply voltage VLCD VDD 12 V Table 2 Note 1 : The maximum operating temperature is confirmed by sampling at initial device qualification . In production, all devices are tested at +85°C. On request devices tested at +125°C can be supplied

Electrical Characteristics

Unless otherwise specified: VDD= 5V ± 10%, VLCD= 12V and TA=-40 to +85°C. Parameter Symbol Conditions Min Typ Max Unit Static supply current IDD See note 1 0.1 1 µA Static supply current ILCD See note 1 0.1 1 µA Dynamic supply current IDD See note 1 & 2 55 75 µA Dynamic supply current ILCD See note 1 & 3 0.6 5 µA All input Signals Low level input voltage VIL 0.8 V High level input voltage VIH 3.8 3.5 V Leakage input current IIL VIN=VSS or VIN=VDD 1 µA Data Output DO High level output voltage VOH IH=100µA VDD=VLCD =4.5V VDD -100 mV Low level output voltage VOL IL=100µA VDD=VLCD =4.5V VSS +100 mV Driver Output S1…S40 High level output voltage VSH IH=20µA VDD=VLCD =4.5V VLCD -100 mV Low level output voltage VSL IL=20µA VDD=VLCD =4.5V VSS +100 mV Short Circuit Current ISC only one output 0.9 2 mA Table 3 Note 1: Tested with VIL = VSS , VIH = VDD Note 2: Tested with fCL = 100kHz, FDI = 50kHz, 50 pF on each segment Note 3: Tested with fFL = 64Hz, fCL = 0Hz, 50 pF on each segment Timing Characteristics Unless otherwise specified: VDD= 5V ± 10%, VLCD= 12V and TA=-40 to +85°C. Parameter Symbol Conditions Min Typ Max Unit Clock high pulse width tCH 500 ns Clock low pulse width tCL 500 ns Clock and FR rise time tCR 500 ns Clock and FR fall time tCF 500 ns Data input setup time tDS 250 ns Data input hold time tDH 0 ns Data output propagation tPD CLOAD = 50pF 600 800 ns CLK falling to STR rising tP 50 ns STR falling to CLK falling tD 250 ns STR pulse width tSTR 200 ns FR frequency fFR 64 Hz (note1) 1 (note2) mHz Delay S1 – S40 fall time tSF 0.5 1 µs Delay S1 – S40 rise time tSR 2.9 5 µs Note 1: Recommended frame frequency Table 4 Note 2: Maximum test frequency

R V6108 Timing Waveforms Fig. 3 VOL S1….S40 versus VLCD at -40, +25°C and +85°C. Fig. 4 Copyright © 2004, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com

R V6108 VOH S1….S40 versus VLCD at -40, +25°C and +85°C. Fig. 5 VOL DO versus VDD at -40, +25°C and +85°C. Fig. 6 Copyright © 2004, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com

R V6108 VOH DO versus VDD at -40, +25°C and +85°C. Fig. 7 Block Diagram Fig. 8 Note 1: F = Noise Filter Note 2: LS = Voltage Level Shifter Pin Assignments Name Function S1….S40 Segment drive outputs VLCD Power supply for the LCD VDD Power supply for logic FR Input for segment frequency control DI Serial data input DO Serial data output CLK Clock input STR Strobes the input data into the output latches R Display blank control input VSS Supply ground Table 5 Copyright © 2004, EM Microelectronic-Marin SA 5 www.emmicroelectronic.com

R V6108 Functional Description Supply voltages VLCD, VDD , VSS VDD is the p ositive supply line for the log ic and VLCD for the display signals. VLCD h as to be e qual or higher than VDD . All voltages are specified relative VSS. Data Input / Output (DI / DO) The data input pin (DI) accep ts serial data fr om the data source. The data is clocked in a rate determined by the clock in put frequ ency (CL K). A logic “1” on DI corresponds to a visi ble segment when the backplane is driven by a signal corresponding to logic “0”. The data at DO i s equal to th e da ta at D I de layed by 40 clo ck periods. In order to c ascade devices the DO of o ne chip must be connected to DI of the following chip (see Fig.1). CLK Input The clock in put pin ( CLK) is used to cl ock the DI serial data int o the 40-bit shift reg ister. Loa ding, shifting a nd outputting of the data occ urs at the falling edge of this clock (see Fig.3). When cascading devices , all CLK lines should be tied together. STR Input The strobe input pin (STR) is used to latch the input data shifted int o the 40-bit sh ift register. T he latched d ata is held for displ ay. A log ic “1” on the ST R input transfers the data co ntained in th e shift register cells to the corresponding latches. T he latches rema in open d uring the whole ti me ST R remains at lo gic “1”. W hen cascading devices the S TR lines sh ould al l b e connected. R Input When R is a ctive (hi gh), t he d isplay is bla nked: al l segment outp uts are tie d V SS.. R does not clear th e information in the latches. Segment Driver The number of segment drivers available on the ch ip is 40. Eac h s egment dr iver c an be used a s back plane- driver. If t wo or more driv ers are c onnected to gether, care must be t aken to ens ure the drivers do not c ause circuit malfunction by driving one against the other. FR Input This input c ontrols th e s egment outp ut s witching frequency according to T able 6. It must be connected to an external clock signal. When cascading devices, their FR inputs may all be connected to a common signal. Segment Switching Table Latched Signal (DI) 0= VIL 1= VIH Signal FR Segment Voltage 0= Vss 1= VLCD 0 0 0 0 1 1 1 0 1 1 1 0 Table 6 Typical Applications Type V6108 Circuits Driving a 79 Segment Display Fig.9 Copyright © 2004, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com

R V6108 Cascaded V6108 TAB for Direct Drive Application Fig.10 Package and Ordering Information Dimensions of Chip Form Dimensions in microns Fig.11 Chip size is X = 3302 by Y= 2159 microns or X = 130 by Y = 85 mils Note : The origin (0,0) is the lower left coordinate of center pads. The lower left corner of the chip shows distances to origin. Copyright © 2004, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com

R V6108 Side view and recommended Solder Area Fig.12 Package and Ordering Information The V6108 is available in the following packages: When ordering, please specify the complete part number and package. QFP52, pin plastic package V6108 52F TAB, tape automated bonding V6108 TAB Chip form V6108 Chip * *on request EM Microelectronic-Marin SA canno t as sume r espon sibility for us e of any ci rcuitry desc ribed o ther t han circuitry entirely em bodi ed in an EM M icroelectronic-Marin SA product. EM M icroelectronic-Marin SA reserves the right to change the circuitry and s peci fications w ithout notice at any t ime. You a re s trongl y ur ged t o en sure t hat t he information gi ven has not been super seded by a more up-to-date ver sion. © EM Microelectronic-Marin SA, 09/04, Rev.C Copyright © 2004, EM Microelectronic-Marin SA 8 www.emmicroelectronic.com