H6006B1SO8A | DigiCamel IC Datasheet

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H6006 EMMICRO | Alldatasheet

Document overview

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Technical content

Features

Failsafe watchdog function: timeout warning after 1st timeout period, reset after 2nd timeout period, reset remains active to avoid further failures Standard timeout period and power-on reset time (10 ms), externally programmable if required V IN monitoring with 3 standard or programmable trigger voltages for: power-on reset initialization, advanced power-fail warning ( SAVE ), reset at power-down ( RES ) V DD monitoring: power-on reset initialization enabled only if VDD ≥ 3.5 V Internal voltage reference Works down to 1.5 V supply voltage Push-pull or Open drain outputs Low current consumption Available for normal and extended temperature range SO8 package

Applications

Microprocessor and microcontroller systems Point of sales equipment Telecom products Automotive subsystems Typical Operating Configuration Pin Assignment EM MICROELECTRONIC - MARIN SA Voltage Regulator 5 V H6006 GND Fig. 1 Micro- processor I/O VDD TO SAVE RES VIN TCL VSS INT NMI RES SO8 VDD H6006 Fig. 2 VIN TCL RC VSS TO SAVE RES

R H6006 Copyright © 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com Absolute Maximum Ratings Parameter Symbol Conditions Voltage VDD to VSS V DD -0.3 to +8 V Voltage at any pin to VSS V MIN -0.3 Voltage at any pin to VDD(except VIN) VMAX +0.3 Voltage at VIN to VSS V INMAX +15 V Current at any output I MAX ±10 mA Storage temperature T STO -65… +150 °C Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in pr otection against high static voltages or electric fields; ho wever, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, pr oper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min. Typ Max. Units Operating temperature Industrial T AI -40 +85 °C Supply voltage V DD 1.5 5.5 V Comparator input voltage Version A2, A3, B2,B3 VIN 0 V DD V Version B1 V IN 0 12 V RC-oscillator programming (see Fig. 15) External capacitance C1 100 nF External resistance R1 10 kΩ Table 2

Electrical Characteristics

VDD = 5.0 V, TA = -40 to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units VDD activation threshold V ON T A = 25 °C 3 3.5 V VDD deactivation threshold V OFF T A = 25 °C V ON - 1.5 V Supply current I DD RC open, TCL= 5 V, V IN = 0 V 50 140 µA Input VIN,, TCL Leakage current I IP V SS ≤ VIP ≤ VDD; TA = 85 °C 0.005 µA Input current on pin VIN I IN Version B1; V IN = 10 V 100 180 µA TCL input low level V IL 0.8 V TCL input high level V IH 2.4 V TO , RES . SAVE Outputs Leakage current I OLK Versions A2, A3; V OUT = VDD 0 .05 1 µA Drive currents (all versions) I OL V OL = 0.4 V 3.2 8 mA I OL V DD = 3.5 V; VOL = 0.4 V 2 mA I OL V DD = 1.6 V; VOL = 0.4 V 80 µA Drive currents I OH V OH = 4.0 V 3.2 8 mA (versions B1, B2, B3)1) I OH V DD = 3.5 V; VOH ≥ 2.8 V 2 mA I OH V DD = 1.6 V; VOH = VDD-0.4 80 µA 1)Versions: An = open drain outputs; Bn = push-pull outputs Table 3 VIN Surveillance Voltage thresholds at TA = 25 °C Version1) Comparator Reference Input Resistance RVIN Thresholds Threshold Tolerance Ratio Tolerance 3) B1 V DD 100k Ω 9.00 8.00 7.00 2) ± 5% +2% A2, B2 V DD ~100M Ω 2.25 2.00 1.75 2) ± 5% +2% A3, B3 Band-gap reference ~100M Ω 2.00 1.95 1.90 ± 10% +2% 1) Versions: An = open drain outputs; Bn = push-pull outputs 2) at VDD = 5 V 3) Threshold ratio as VSH/VSL or VSL/VRL Table 4

R H6006 Copyright © 2004, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com Timing Characteristics VDD = 5.0 V, TA = −40 °C to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units Propagation delays TCL to output pins TDIDO 250 500 ns VIN to output pins TAIDO Excluding debounce time T DB 4 10 µs Logic transition times on all output pins TTR Load 10 kΩ, 100 pF 30 100 ns Timeout period TTO RC open, unshielded , TA =25 °C 6 10 16 ms TTO RC open, unshielded (not tested) 4.5 20 ms TTCL input pulse width TTCL 150 ns Power-on reset debounce TDB T TO/32 ms Table 5 Timing Waveforms Voltage Reaction: VDD Monitoring Voltage Reaction: VIN Monitoring VON VOFF VDD VIN monitoring enabled Fig. 3 VSH VSL VRL SAVE Conditions: VDD > VON No timeout VIN TTO TTO TDB TDB Timer Start Power-on Reset Timer Stop Timer Start Power-on Reset No Power-on Reset (as VIN > VRL) Fig. 4 RES

R H6006 Copyright © 2004, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com Timer Reaction Combined Voltage and Timer Reaction Block Diagram TCL TTCL TTO Conditions: VIN > VRL after power-up sequence. Timer Reset Timer Reset Timer Reset TO Timeout RES Timeout Fig. 5 TO RES TTO TTO VIN VSH TDB SAVE TTO Power-on Reset TO Timeout RES Timeout TO Timeout Timer Stop Timer Reset Fig. 6 VSL VRL RES TO TCL TTO TTO TTO OSC Timer TCL TO Save Control RES Reset Control SAVE Band-Gap Reference VIN 1 2 VDD VSH VSL VRL VSS Fig. 7RC Version Connections A2, B2 A3, B3 1 and 3

1 V IN Volta ge monitoring input

2 TCL Timer clear input signal

3 RC RC oscillator tuning input

4 V SS GND terminal

5 RES Reset output

6 SAVE Save output

7 TO Timer output signal

8 V DD Positive supply voltage terminal

The circuit is powered through the V DD and V SS pins. It monitors both its own V DD supply and a voltage applied to the VIN input. VDD Monitoring During power-up the V IN monitoring is disabled and RES and SAVE stay active low as long as V DD is below VON (3.5 V). As soon as V DD reaches the V ON level, the state of the outputs depend on the watchdog timer and the volt-age at V IN relative to the thresholds (see Fig. 3 and 4). If the supply voltage V DD falls back below V OFF (1.5 V) the watchdog timer and the V IN monitoring are disabled and the outputs SAVE and RES are active low. The VDD line should be free of spikes. VIN Monitoring The analog voltage comparators compare the voltage applied to V IN (typically connected to the in put of the voltage regulator) with the stabilized supply voltage V DD (versions B1, A2, B2) or with the bandgap voltage (versions A3, B3) (see Fig. 7). At power-up, when V DD reached V ON and V IN reaches the V SH level, the SAVE output goes high, and the timer starts running, setting RES high after the time TTO (see Fig. 4). If VIN falls below VSL, the SAVE output goes low and stays low until VIN rises again above VSH. If VIN falls below the voltage VRL, the RES output will go low and the on-chip timer will stop. When VIN rises again above V SH, the timer will initiate a power-up sequence. The RES output may however be influenced independently of the voltage V IN by the timer action, see section “Combined Voltage and Timer Action”. Monitoring the rough DC side of the regulator as shown in Fig. 12 is the only way to have advanced warning at power-down. Spikes on V IN should be filtered if they are likely to drop below VSL. The combination of V IN and V DD monitoring provide high system security: if V IN rises much faster than V DD, then the device starts the power-on sequence only when V DD reached VON (Fig. 3). Short circuits on the regulated supply voltage can be detected. Voltage Thresholds on VIN The H6006 is available with 3 different sets of thresholds : Version B1: with internal voltage divider, resulting in thresholds for direct monitoring of the unregulated voltage without external components. Version A2, B2: for monitoring of all unregulated voltage, where custom programming is required. Fixed resistor values can be used for programming. Version A3, B3: for monitoring of regulated voltage, where no unregulated voltage is available (the tolerance is ±10 %, see Table 4. For tighter tolerances, trimming can be used, see Fig. 10). Voltage Regulator any voltage 5 V VIN VSS VDD H6006 A2, B2 Note : the internal threshold levels are 2.25 / 2.00 / 1.75 V at VDD = 5 V (thresholds dependent on VDD) RVIN = ~ 100 MΩ. Fig. 9 SAVE RES Voltage Regulator > 9 V 5 V VIN VSS VDD H6006 B1 Note: The threshold levels are 9/8/7 V normally.These are divided internally by 4 to give internal thres- holds of 2.25 / 2 / 1.75 V. V DD = 5 V (thresholds dependent on VDD). RVIN = ~ 100 kΩ. Fig. 8 SAVE RES

5 V ± 10%

H6006 A3, B3 Note: the internal threshold levels are 2.00 / 1.95 / 1.90 V (thresholds dependent on the internal bandgap reference) RVIN = ~ 100 MΩ. Fig. 10 SAVE RES

R H6006 Copyright © 2004, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com Monitoring of the unregulated voltage require versions B1, A2 and B2. The versions are based on the principle that V DD rises with V IN on power-up and V DD holds up for a certain time after VIN starts dropping on power-down. The version B1 has a 100 k Ω nominal resistance from V IN to V SS (internal voltage divider). The versions A2, B2, A3 and B3 have high impedance V IN inputs (see Fig. 7 and Table 4) for external threshold voltage programming by a voltage divider on pin VIN. The levels obtained are proportional to the internal levels VSH, V SL and V RL on the chip itself (see Electrical Specifications). Timer Programming With pin RC unconnected, the on-chip RC oscillator together with its divider chain give a timeout T TO of typically 10 ms. For programming a different T TO, an approximation for calculating component values is given by the formula: 1.024 R 0.8V5.5 1.6)C(320.75T DD TO •

++= R 1 min. = 10 kΩ, C1 max. = 1 µF If R 1 is in MΩ and C1 in pF, TTO will be in ms. Thus, a resistor decreases and a capacitor increases the interval to timeout. By using both external components, excellent temperature stability of T TO can be achieved. With TCL tied to either V DD or V SS, a precise square wave of period 2 x T TO is generated at the output TO . The oscillator and watchdog timer run so long as the chip is powered with at least the minimum positive supply voltage specified (V ON), and so long as V IN remains above the level V RL after a power-up sequence. If the timer function is not required, input TCL should be tied to output TO to give a simple voltage monitor (see Fig. 14). Timer Clearing and RES Action A negative edge or a negative pulse at the TCL input longer than 150 ns will reset the timer and set TO high. If a further TCL signal edge or pulse is applied before T TO timeout, TO will stay high and the timer will again be reset to zero (see Fig. 5). If no TCL signal is applied before the TTO timeout, TO will start to generate a square wave of period 2 x TTO starting with a low state. If no TCL signal is applied during the first low state of TO , then the RES output will go low and stay low until the next TCL signal, or until a fresh power-up sequence. Combined Voltage and Timer Action The combination of voltage and timer action is illustrated by the sequence of events shown in Fig. 6. One timeout period after VIN reached VSH, during power-up, RES goes inactive high. No TCL pulse will have any effect until this power-on reset delay is completed. A fter completing the power-up sequence the watchdog timer starts acting. If no TCL pulse occurs, the timeout warning TO goes active low after one timeout period T TO. After each subsequent timeout period without a timer clear pulse TCL , TO changes its polarity providing a square wave signal. RES activates at the end of the first low state of the TO signal. A TCL pulse clears the watchdog timer and resets the TO and RES output inactive high again. A voltage drop below the V RL level overrides the timer and immediately forces RES and SAVE active low and disables TO . Any further TCL pulse has no effect until the next power-up sequence has complete Typical Applications H6006 RAM R1 = 470 kΩ SEL Adress Decoder RD IR 2 C1 = 220 pF Microprocessor Latched Address Bus Fig. 11TTO =~ 30 ms Voltage Regulator Monitored Voltage >9 V 5 V VIN RC VSS VDD RESET TCL TO SAVE RES CS Disable IR 1

R H6006 Copyright © 2004, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com Voltage Monitor with Spike Suppression Watchdog and Power-On Reset V DD Monitoring and Power-On Reset External Programming of RC Oscillator Voltage Regulator 330 nF 2.7 kΩ

10 VDC

5 VDC

Fig. 12 Versions A1 or B1 VIN VSS VDD H6006 TCL TO SAVE RES If only VDD monitoring is used, (i.e.VIN and VDD common) then the version A3 or B3 with its constant thresholds are recommended. The power-on reset function is still available as the V DD monitoring is active. Fig. 13 VIN VSS VDD TO SAVE RES H6006 A3, B3 TCL VIN monitoring and watchdog function not used. Versions A3 and B3 only. Fig. 14 VIN VSS VDD TO RES H6006 A3, B3 TCL C1 increases TTO R1 shortens TTo Note: using both external components R1 and C1 allows to achieve tighter timeout period tolerances. This circuit provides independent programming of both timeout period and power-on reset delay. VSS VDD TO RES H6006 TCL VSS VDD TO RES H6006 TCL VSS VDD TO RES H6006 TCL RC RC RC2 Fig. 15

Package Information

Dimensions of 8-Pin SOIC Package Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.93 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 2 3 4 5 6 7 8 H L 0 - 8° C E A1 A B e D Dimensions in mm Fig. 16

Ordering Information

When ordering, please specify the complete Part Number Part Number Version Threshol d (see Table 4) Outpu t Type Package Delivery Form Package Marking (first line) Temperature Range H6006A2SO8A 8-pin SOIC Stick 6006A2 H6006A2SO8B A2 2.00 8-pin SOIC Tape & Reel 6006A2 H6006A3SO8A* 8-pin SOIC Stick 6006A3 H6006A3SO8B* A3 1.95 Open drain 8-pin SOIC Tape & Reel 6006A3 H6006B1SO8A 8-pin SOIC Stick 6006B1 H6006B1SO8B* B1 8.00 8-pin SOIC Tape & Reel 6006B1 H6006B2SO8A 8-pin SOIC Stick 6006B2 H6006B2SO8B B2 2.00 8-pin SOIC Tape & Reel 6006B2 H6006B3SO8A 8-pin SOIC Stick 6006B3 H6006B3SO8B B3 1.95 Push- pull 8-pin SOIC Tape & Reel 6006B3 -40 to +85 °C * = non stock item. Might be available on request and upon minimum order quantity (please contact EM Microelectronic). Note: Other versions are no longer available EM Microelectronic-Marin SA cannot assume responsibility fo r use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. © EM Microelectronic-Marin SA, 07/04, Rev. G

Product Information

H6006B1SO8A specifications and overview.

Summary

Failsafe Watchdog

Description

The H6006 is a monolithic low power CMOS device combining a programmable digital timer and a series of voltage comparators on the same chip. The device is specially convenient for Watch-Dog functions such as microprocessor and supply voltage monitoring. The watchdog part is designed to be used in all applications where it is important that after the occurrence of a malfunction the microprocessor system is stopped to avoid further damage. The timeout warning signal ( TO ) can be used to try to reactivate the system before halting it. The voltage monitoring part provides double security by combining both unregulated voltage and regulated voltage monitoring simultaneously. The H6006 initializes the power on reset after VIN reached VSH and VDD raises above 3.5 V. If VIN drops below VSL, the H6006 gives an advanced warning signal for register saving and if the voltage drops further below VRL, RES goes active. The H6006 functions at any supply voltage down to 1.5 V and is therefore particularly suited for start-up and shut-down control of microprocessor systems

Source title H6006B1SO8A Datasheet(PDF) - EM Microelectronic - MARIN SA

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