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UDA1380

Integrated Circuit Syst...

Stereo audio coder-decoder for MD, CD and MP3

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2002 Sep 16
1 FEATURES
1.1 General
1.2 Multiple format data input interface
1.3 Multiple format data output interface
1.4 ADC front-end features
1.5 DAC features
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION
8.1 Clock modes
8.2 ADC analog front-end
8.3 Decimation filter (ADC)
8.4 Interpolation filter (DAC)
8.5 Noise shaper
8.6 FSDAC
8.7 Headphone driver
8.8 Digital and analog mixers (DAC)
8.9 Application modes
8.10 Power-on reset
8.11 Power-down requirements
8.12 Plop prevention
8.13 Digital audio data input and output
9 L3-BUS INTERFACE DESCRIPTION
9.1 Introduction
9.2 Device addressing
9.3 Slave address
9.4 Register addressing
9.5 Data write mode
9.6 Data read mode
10.1 Addressing
10.2 WRITE cycle
10.3 READ cycle
11 REGISTER MAPPING
11.1 Evaluation modes and clock settings
11.3 Power control settings
11.4 Analog mixer settings
11.5 Reserved
11.6 Master volume control
11.7 Mixer volume control
11.8 Mode, bass boost and treble
11.9 Master mute, channel de-emphasis and mute
11.10 Mixer, silence detector and oversampling
11.11 Decimator volume control
11.12 PGA settings and mute
11.13 ADC settings
11.14 AGC settings
11.15 Restore L3 default values (software reset)
11.16 Headphone driver and interpolation filter
11.17 Decimator read-out
12 LIMITING VALUES
13 HANDLING
14 THERMAL CHARACTERISTICS
15 QUALITY SPECIFICATION
16 DC CHARACTERISTICS
17 AC CHARACTERISTICS
18 TIMING
19 APPLICATION INFORMATION
20 PACKAGE OUTLINES
21 SOLDERING
21.1 Introduction to soldering surface mount
21.2 Reflow soldering
21.3 Wave soldering
21.4 Manual soldering
21.5 Suitability of surface mount IC packages for
22 DATA SHEET STATUS
23 DEFINITIONS
24 DISCLAIMERS
25 PURCHASE OF PHILIPS I

Product speciﬁcation 2002 Sep 16 INTEGRATED CIRCUITS UDA1380 Stereo audio coder-decoder for MD, CD and MP3

2002 Sep 16 3

Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

1 FEATURES

1.1 General

2.4 to 3.6 V power supply
5 V tolerant digital inputs (at 2.4 to 3.6 V power supply)
24-bit data path for Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)
Selectable control via L3-bus microcontroller interface or I 2C-bus interface; choice of 2 device addresses in L3-bus and I2C-bus mode Remark : This device does not have a static mode
Supports sample frequencies from 8 to 55 kHz for the ADC part, and 8 to 100 kHz for the DAC part. The ADC cannot support DVD audio (96 kHz audio), only Mini-Disc (MD), Compact-Disc (CD) and Moving Picture Experts Group Layer-3 Audio (MP3). For playback 8 to 100 kHz is specified. DVD playback is supported
Power management unit: – Separate power control for ADC, Automatic Volume Control (AVC), DAC, Phase Locked Loop (PLL) and headphone driver – Analog blocks like ADC and Programmable Gain Amplifier (PGA) have a block to power-down the bias circuits – When ADC and/or DAC are powered-down, also the clocks to these blocks are stopped to save power Remark: By default, when the IC is powered-up, the complete chip will be in the Power-down mode.
ADC part and DAC part can run at different frequencies, either system clock or Word Select PLL (WSPLL)
ADC and PGA plus integrated high-pass filter to cancel DC offset
The decimation filter is equipped with a digital Automatic Gain Control (AGC)
Mono microphone input with Low Noise Amplifier (LNA) of 29 dB fixed gain and Variable Gain Control (VGA) from 0 to 30 dB in steps of 2 dB
Integrated digital filter plus DAC
Separate single-ended line output and one stereo headphone output, capable of driving a 16Ω load. The headphone driver has a built-in short-circuit protection with status bits which can be read out from the L3-bus or I 2C-bus interface
Digital silence detection in the interpolator (playback) with read-out status via L3-bus or I2C-bus interface
Easy application.

1.2 Multiple format data input interface

Slave BCK and WS signals
I2S-bus format
MSB-justified format compatible
LSB-justified format compatible.

1.3 Multiple format data output interface

Select option for digital output interface: either the decimator output (ADC signal) or the output signal of the digital mixer which is in the interpolator DSP
Selectable master or slave BCK and WS signals for digital ADC output Remark : SYSCLK must be applied in WSPLL mode and master mode
I 2S-bus format
MSB-justified format compatible
LSB-justified format compatible.

1.4 ADC front-end features

ADC plus decimator can run at either WSPLL, regenerating the clock from WSI signal, or on SYSCLK
Stereo line input with PGA: gain range from 0 to 24 dB in steps of 3 dB
LNA with 29 dB fixed gain for mono microphone input, including VGA with gain from 0 to 30 dB in steps of 2 dB
Digital left and right independent volume control and mute from +24 to−63.5 dB in steps of 0.5 dB.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

1.5 DAC features

DAC plus interpolator can run at either WSPLL (regenerating the clock from WSI) or at SYSCLK
Separate digital logarithmic volume control for left and right channels via L3-bus or I2C-bus from 0 to−78 dB in steps of 0.25 dB
Digital tone control, bass boost and treble via L3-bus or I2C-bus interface
Digital de-emphasis for sample frequencies of: 32, 44.1, 48 and 96 kHz via L3-bus or I2C-bus interface
Cosine roll-off soft mute function
Output signal polarity control via L3-bus or I2C-bus interface
Digital mixer for mixing ADC output signal and digital serial input signal, if they run at the same sampling frequency.

2 APPLICATIONS

This audio coder-decoder is suitable for home and portable applications like MD, CD and MP3 players.

3 GENERAL DESCRIPTION

The UDA1380 is a stereo audio coder-decoder, available in TSSOP32 (UDA1380TT) and HVQFN32 (UDA1380HN) packages. All functions and features are identical for both package versions. The term ‘UDA1380’ in this document refers to both UDA1380TT and UDA1380HN, unless particularly specified. The front-end of the UDA1380 is equipped with a stereo line input, which has a PGA control, and a mono microphone input with an LNA and a VGA. The digital decimation filter is equipped with an AGC which can be used in case of voice-recording. The DAC part is equipped with a stereo line output and a headphone driver output. The headphone driver is capable of driving a 16Ω load. The headphone driver is also capable of driving a headphone without the need for external DC decoupling capacitors, since the headphone can be connected to a pin V REF(HP) on the chip. In addition, there is a built-in short-circuit protection for the headphone driver output which, in case of short-circuit, limits the current through the operational amplifiers and signals the event via its L3-bus or I 2C-bus register. The UDA1380 also supports an application mode in which the coder-decoder itself is not running, but an analog signal, for instance coming from an FM tuner, can be controlled in gain, and applied to the output via the headphone driver and line outputs. The UDA1380 supports the I 2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 18, 20 or 24 bits (LSB-justified 24 bits is only supported for the output interface). The UDA1380 has sound processing features in playback mode, de-emphasis, volume, mute, bass boost and treble which can be controlled by the L3-bus or I 2C-bus interface.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

4 QUICK REFERENCE DATA

VDDD =V DDA(AD) =V DDA(DA) =V DDA(HP) = 3.0 V; Tamb =2 5°C; RL =5k Ω ; all voltages measured with respect to ground; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(AD) ADC analog supply voltage 2.4 3.0 3.6 V VDDA(DA) DAC analog supply voltage 2.4 3.0 3.6 V VDDA(HP) headphone analog supply voltage 2.4 3.0 3.6 V VDDD digital supply voltage 2.4 3.0 3.6 V IDDA(AD) ADC analog supply current one ADC and microphone ampliﬁer enabled; fs = 48 kHz − 4.5 − mA two ADCs and PGA enabled; fs =4 8k H z − 7.0 − mA all ADCs and PGAs power-down, but AVC activated; fs =4 8k H z − 3.3 − mA all ADCs, PGAs and LNA power-down; fs =4 8k H z − 1.0 −µ A IDDA(DA) DAC analog supply current operating mode; fs = 48 kHz − 3.4 − mA Power-down mode; fs = 48 kHz − 0.1 −µ A IDDA(HP) headphone analog supply current no signal applied (quiescent current)− 0.9 − mA Power-down mode − 0.1 −µ A IDDD digital supply current operating mode; fs = 48 kHz − 10.0 − mA playback mode; fs = 48 kHz − 5.0 − mA record mode; fs = 48 kHz − 6.0 − mA Power-down mode; fs = 48 kHz − 1.0 −µ A IDD(tot) total supply current playback mode (without headphone); fs =4 8k H z − 9.0 − mA playback mode (with headphone); no signal; fs =4 8k H z − 8.8 − mA record mode (audio); fs = 48 kHz − 13.0 − mA record mode (speech); fs =4 8k H z − 10.0 − mA record mode (audio and speech); fs =4 8k H z − 13.0 − mA fully operating; fs =4 8k H z − 23.0 − mA signal mix-in operating, using FSDAC, AVC (with headphone); no signal; f s =4 8k H z − 12.0 − mA Power-down mode; fs = 48 kHz − 2.0 −µ A Tamb ambient temperature −40 − +85 °C

2002 Sep 16 6

Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Analog-to-digital converter (supply voltage 3.0 V) D o digital output level at 0 dB setting; Vi(rms)= 1.0 V −− 1 − dBFS (THD+N)/S48 total harmonic distortion- plus-noise to signal ratio at f s =4 8k H z at−1 dBFS −− 85 − dB at−60 dBFS; A-weighted −− 37 − dB S/N48 signal-to-noise ratio at fs =4 8k H z Vi= 0 V; A-weighted − 97 − dB α cs channel separation − 100 − dB LNA input plus analog-to-digital converter (supply voltage 3.0 V) Vi(rms) input voltage (RMS value) at 0 dBFS digital output; 2.2 kΩ source impedance −− 35 mV (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB −− 74 − dB at−60 dB; A-weighted −− 25 − dB S/N48 signal-to-noise ratio at fs =4 8k H z Vi= 0 V; A-weighted − 85 − dB α cs channel separation − 70 − dB Digital-to-analog converter(supply voltage 3.0 V) Vo(rms) output voltage (RMS value) at 0 dBFS digital input; note 1− 0.9 − V (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB −− 88 − dB at−60 dB; A-weighted −− 40 − dB (THD+N)/S96 total harmonic distortion-plus-noise to signal ratio at f s = 96 kHz at 0 dB −− 80 − dB at−60 dB; A-weighted −− 37 − dB S/N48 signal-to-noise ratio at fs =4 8k H z code = 0; A-weighted − 100 − dB S/N96 signal-to-noise ratio at fs =9 6k H z code = 0; A-weighted − 97 − dB α cs channel separation − 90 − dB AVC (line input via ADC input; output on line output and headphone driver; supply voltage 3.0 V) Vi(rms) input voltage (RMS value) − 150 − mV (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB −− 80 − dB at−60 dB; A-weighted −− 28 − dB S/N48 signal-to-noise ratio at fs =4 8k H z Vi= 0 V; A-weighted − 87 − dB SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2002 Sep 16 7

5 ORDERING INFORMATION

Headphone driver (supply voltage 3.0 V) P o(rms) output power (RMS value) at 0 dBFS digital input; RL =1 6Ω− 35 − mW (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB; RL =1 6Ω− − 60 − dB at 0 dB; RL =5k Ω− − 82 − dB at−60 dB; A-weighted −− 24 − dB S/N48 signal-to-noise ratio at fs =4 8k H z code = 0; A-weighted − 90 − dB α cs channel separation R L =1 6Ω using pin VREF(HP) ; no DC decoupling capacitors; note 2 − 60 − dB R L =1 6Ω single-ended application with DC decoupling capacitors (100µF typical) − 68 − dB R L =3 2Ω single-ended application with DC decoupling capacitors (100µF typical) − 74 − dB Power consumption (supply voltage 3.0 V; f s = 48 kHz) Ptot total power dissipation playback mode (without headphone)− 27 − mW playback mode (with headphone) − 27 − mW record mode (audio) − 39 − mW record mode (speech) − 31 − mW record mode (audio and speech) − 40 − mW full operation − 69 − mW Power-down mode − 6 −µ W TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION UDA1380TT TSSOP32 plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm SOT487-1 UDA1380HN HVQFN32 plastic, heatsink very thin quad ﬂat package; no leads; 32 terminals; body 5× 5 × 0.85 mm SOT617-1 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

6 BLOCK DIAGRAM

handbook, full pagewidth MGU526 9 (5) 31 (27) 3 (31) 5 (1) 13 (9) 7 (3) 8 (4) 10 (6) 11 (7) 12 (8) 27 (23) RESET VINL VINM BCKI BCKO DATAO WSI WSO DATAI VOUTL 14 (10) 17 (13) 1 (29) 16 (12) 18 (14) 19 (15) 15 (11) 25 (21) VOUTR L3DATA/SDA SEL_L3_IIC RTCB L3CLOCK/SCL L3MODE FSDAC ADC n.c. ANA VC WSPLL SDC SDCMIC AMP L3 or I2C-BUS INTERFACE ANA VC HEADPHONE DRIVER HEADPHONE DRIVER VSSD VSSA(DA)VDDA(HP) VOUTRHPVOUTLHP VREF(HP) INTERPOLATION FILTER NOISE SHAPER DSP FEATURES DATA INPUT INTERFACE 26 (22) VDDA(DA) DATA OUTPUT INTERFACE AGC DC-CANCELLATION FILTER DECIMATION FILTER SYSCLK VSSA(HP) 20 (16) 21 (17) VINR 30 (26) VSSA(AD) 32 (28) VDDA(AD) 4 (32) VADCP 2 (30) VADCN 29 (25) VREF 6 (2) VDDD FSDAC SDCPGA PGA UDA1380TT (UDA1380HN) +29 dB ADC Fig.1 Block diagram. Pin numbers for UDA1380HN in parentheses.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

7 PINNING

VINR 1 29 analog pad ADC input right, also connected to the mixer input of the FSDAC VADCN 2 30 analog pad ADC reference voltage VINM 3 31 analog pad microphone input V ADCP 4 32 analog pad ADC reference voltage RESET 5 1 5 V tolerant digital input pad; push-pull; TTL with hysteresis; pull-down pin RESET with pull-down, for making Power-On Reset (POR) V DDD 6 2 digital supply pad digital supply voltage BCKO 7 3 5 V tolerant digital bidirectional pad; push-pull input; 3-state output; 5 ns slew-rate control; TTL with hysteresis bit clock output WSO 8 4 word select output DATAO 9 5 output pad; push-pull; 5 ns slew-rate control; CMOS data output BCKI 10 6 5 V tolerant digital input pad; push-pull; TTL with hysteresis bit clock input WSI 11 7 word select input DATAI 12 8 data input SYSCLK 13 9 system clock 256f s, 384fs, 512fs or 768fs input VSSD 14 10 digital ground pad digital ground RTCB 15 11 5 V tolerant digital input pad; push-pull; TTL with hysteresis; pull-down test control input, to be connected to digital ground in the application L3MODE 16 12 5 V tolerant digital bidirectional pad; push-pull input; 3-state output; 5 ns slew-rate control; TTL with hysteresis L3-bus mode input or pin A1 for I 2C-bus slave address setting L3CLOCK/SCL 17 13 5 V tolerant digital input pad; push-pull; TTL with hysteresis L3-bus or I2C-bus clock input L3DATA/SDA 18 14 I 2C-bus pad; 400 kHz I2C-bus speciﬁcation L3-bus or I2C-bus data input and output SEL_L3_IIC 19 15 5 V tolerant digital input pad; push-pull; TTL with hysteresis input channel select VSSA(HP) 20 16 analog ground pad headphone ground VOUTRHP 21 17 analog pad headphone output right V REF(HP) 22 18 analog pad headphone reference voltage VOUTLHP 23 19 analog pad headphone output left V DDA(HP) 24 20 analog supply pad headphone supply voltage VOUTR 25 21 analog pad DAC output right V DDA(DA) 26 22 analog supply pad DAC analog supply voltage VOUTL 27 23 analog pad DAC output left

2002 Sep 16 10

Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 VSSA(DA) 28 24 analog ground pad DAC analog ground VREF 29 25 analog pad ADC and DAC reference voltage VSSA(AD) 30 26 analog ground pad ADC analog ground VINL 31 27 analog pad ADC input left, also connected to the mixer input of the FSDAC VDDA(AD) 32 28 analog supply pad ADC analog supply voltage SYMBOL PIN TYPE DESCRIPTION UDA1380TT UDA1380HN handbook, halfpage UDA1380TT MGU525 VINR VADCN VINM VADCP RESET VDDD BCKO WSO DATAO BCKI WSI DATAI SYSCLK VSSD RTCB L3MODE VDDA(AD) VINL VSSA(AD) VREF VSSA(DA) VOUTL VDDA(DA) VOUTR VDDA(HP) VOUTLHP VREF(HP) VOUTRHP VSSA(HP) SEL_L3_IIC L3DATA/SDA L3CLOCK/SCL Fig.2 Pin configuration UDA1380TT. handbook, halfpage UDA1380HN RESET VDDD BCKO WSO DATAO BCKI WSI DATAI VREF VSSA(AD) VINL VDDA(AD) VINR VADCN VINM VADCP VOUTRHP VREF(HP) VDDA(HP) VSSA(DA) VDDA(DA) VOUTR VOUTL VOUTLHP SYSCLK VSSD RTCB L3MODE L3DATA/SDA SEL_L3_IIC VSSA(HP) L3CLOCK/SCL MGW778 Fig.3 Pin configuration UDA1380HN.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8 FUNCTIONAL DESCRIPTION

8.1 Clock modes

There are two clock systems:

A SYSCLK signal, coming from the system or the SSA1 chip
A WSPLL which generates the internal clocks from the incoming WSI signal. The system frequency applied to pin SYSCLK is selectable. The options are 256f s, 384fs, 512fs and 768fs. The system clock must be locked in frequency to the digital interface signals. Remark : Since there is neither a fixed reference clock available in the IC itself, nor a fixed clock available in the system the IC is in, there is no auto sample rate conversion detection circuitry. The system can run in several modes, using the two clock systems:
Both the DAC and the ADC part can run at the applied SYSCLK input. In this case the WSPLL is powered-down
The ADC can run at the SYSCLK input, and at the same time the DAC part can run (at a different frequency) at the clock re-generated from the WSI signal
The ADC and the DAC can both run at the clock regenerated from the WSI signal.

8.1.1 WSPLL

The WSPLL is meant to lock onto the WSI input signal, and regenerates a 256fs and 128fs signal for the FSDAC and the interpolator core (and for the decimator if needed). Since the operating range of the WSPLL is from 75 to 150 MHz, the complete range of 8 to 100 kHz sampling frequency must be divided into smaller parts, as given in Table 1, using Fig.4 as a reference. This means that the user must set the input range of the WSI input signal. In case the SYSCLK is used for clocking the complete system (decimator including interpolator) the WSPLL must be powered-down with bit ADC_CLK via the L3-bus or I 2C-bus. The SEL_LOOP_DIV[1:0] can be controlled by the PLL1 and PLL0 bits in the L3-bus or I2C-bus register. handbook, halfpage VCOWSI DIV1 128fs (digital parts) 256fs (ADC and FSDAC) PRE1 MGU527 Fig.4 WSPLL set-up. Table 1 WSPLL divider settings WORD SELECT FREQUENCY (kHz) SEL_LOOP_DIV[1:0] PRE1 DIV1 VCO FREQUENCY (MHz) 6.25 to 12.5 00 8 1536 76 to 15312.5 to 25 01 4 1536 25 to 50 10 2 1536 50 to 100 11 2 768

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.1.2 C LOCK DISTRIBUTION

Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain. For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the L3-bus and I2C-bus registers (ADC_CLK). The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (fs). This applies to the DAC part only; the ADC part can run from 8 to 55 kHz. handbook, full pagewidth DECIMATOR I2S-BUS OUTPUT BLOCK I2S-BUS INPUT BLOCK L3 or I2C-BUS REGISTER DECIMATOR ADC 128fs 128fs enable clock 256/384/512/768fs enable clock ADC_CLK CLK_DIVSYSCLK WSPLLWSI FSDAC INTERPOLATOR L3 or I2C-BUS REGISTER INTERPOLATOR 128fs 128fs 256fs enable clock MGU528 enable clock DAC_CLK Fig.5 Clock routing for the main blocks inside the coder-decoder.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.2 ADC analog front-end

The analog front-end of the UDA1380 consists of one stereo ADC with a selector in front of it (see Fig.6). Using this selector one can either select the microphone input with the microphone amplifier (LNA) with a fixed 29 dB gain and VGA (no PGA, since a real microphone amplifier is much better with respect to noise), or the line input which has a PGA for having 0 or 6 dB gain (for supporting 1 and 2 V (RMS) input). The PGA also provides gain control from 0 to 24 dB in steps of 3 dB. Remarks :

The input impedance of the PGA (line input) is 12 kΩ , for the LNA this is 5 kΩ
The LNA is standard equipped with a microphone power supply. Since this normally requires two extra pins, this feature will not be used inside the UDA1380. Instead, the microphone supply block is replaced by the VGA block. 8.2.1 A PPLICATIONS AND POWER -DOWN MODES The following Power-down modes and functional modes are supported:
Power-down mode in which the power consumption is very low (only leakage currents) In this mode there is no reference voltage at the line input
Line input mode, in which the PGA can be used
Microphone mode, in which the rest of the non-used PGAs and ADCs are powered-down
Mixed PGA and LNA mode: one line input and one microphone input. More information on the analog frond-end is given in Section 8.11.1. handbook, full pagewidth PGA ADC SEL_MIC bitstream right ADC SDC bitstream left MGU530 PGA (27) (29) (31) VINL 1VINR VINM SDC LNA SDC Fig.6 Analog front-end. Pin numbers for UDA1380HN in parentheses.

8.2.2 LNA WITH VGA

The LNA is equipped with a VGA. The function of the VGA is to have additional variable analog gain from 0 to 30 dB in steps of 2 dB. This provides more flexibility in the choice of the microphone. 8.2.3 A PPLICATIONS WITH 2V( RMS )INPUT For the line input it is preferable to have 0 dB and 6 dB gain settings in order to be able to apply both 1 and 2 V (RMS) input signals, using a series resistance. For this purpose a PGA is used which has 0 to 24 dB gain, in steps of 3 dB.

2002 Sep 16 14

Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 In applications in which a 2 V (RMS) input signal is used, a1 2kΩ resistor must be used in series with the input of the ADC (see Fig.7). This forms a voltage divider together with the internal ADC resistor and ensures that the voltage, applied to the input of the IC, never exceeds 1 V (RMS). Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is applied to the ADC in the same application, the gain switch must be set to 6 dB. An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 2; the power supply voltage is assumed to be 3 V. Table 2 Application modes using input gain stage

8.3 Decimation ﬁlter (ADC)

s is performed in two stages. The first stage realizes a characteristic with a decimation factor of 16. The second stage consists of 3 half-band filters, each decimating by a factor 2. The filter characteristics are shown in Table 3. Table 3 Decimation ﬁlter characteristics 8.3.1 O VERLOAD DETECTION The UDA1380 is equipped with an overload detector which can be read out from the L3-bus or I2C-bus interface. In practice the output is used to indicate whenever the output data, in either the output of the left or right channel, exceeds−1 dB (the actual figure is−1.16 dB) of the maximum possible digital swing. When this condition is detected the output bit OVERFLOW in the L3-bus register is forced to logic 1 for at least 512f s cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement.

8.3.2 V OLUME CONTROL

The decimator is equipped with a digital volume control. This volume control is separate for left and right and can be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via the L3-bus or I 2C-bus interface. The range is from +24 dB to−63.5 dB and mutes in steps of 0.5 dB.

8.3.3 M UTE

The decimator is equipped with a dB-linear mute which mutes the signal in 256 steps of 0.5 dB.

8.3.4 AGC FUNCTION

The decimation filter is equipped with an AGC block. This function is intended, when enabled, to keep the output signal at a constant level. The AGC can be used for microphone applications in which the distance to the microphone is not always the same. The AGC can be enabled via an L3-bus or I 2C-bus bit by setting the bit to logic 1. In that case it bypasses the digital volume control. Via the L3-bus or I 2C-bus interface also some other settings of the AGC, like the attack and decay settings and the target level settings, can be made. Remark : The DC filter before the decimation filter must be enabled by setting the L3-bus or I 2C-bus bit SKIP_DCFIL to logic 0 when AGC is in operation; otherwise the output will be disturbed by the DC offset added in the ADC. RESISTOR (12 kΩ ) INPUT GAIN SWITCH MAXIMUM INPUT VOLTAGE Present 0 dB 2 V (RMS) 6 dB 1 V (RMS) Absent 0 dB 1 V (RMS) 6 dB 0.5 V (RMS) handbook, halfpage MGU529 VREF VDDA = 3 V VINL, VINR 31, (27, 29) PGA 12 kΩ external resistor 12 kΩinput signal

2 V (RMS)

Fig.7 ADC front-end with PGA (line input). Pin numbers for UDA1380HN in parentheses. xsin ITEM CONDITION VALUE (dB) Pass-band ripple 0 to 0.45fs 0.01 Stop band >0.55f s −70 Dynamic range 0 to 0.45f s >135 Digital output level at 0 dB input analog −1.5

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.4 Interpolation ﬁlter (DAC)

The interpolation digital filter interpolates from 1 to 64fs or to 128fs, by cascading FIR filters, see Table 4. The interpolator is equipped with several sound features like volume control, mute, de-emphasis and tone control. Table 4 Interpolation ﬁlter characteristics 8.4.1 DIGITAL MUTE Muting the DAC will result in a cosine roll-off soft mute, using 4× 32 = 128 samples in normal mode (or 3 ms at 44.1 kHz sampling frequency). The cosine roll-off curve is illustrated in Fig.8. These cosine roll-off functions are implemented for both the digital mixer and the master mute inside the DAC data path, see Section 8.8. 8.4.2 S OUND FEATURES In addition, there are basic sound features:

dB-linear volume control using 14-bit coefficients in steps of 0.25 dB: range 0 to−78 dB maximum suppression and−∞ dB: applies to both master volume and mixing volume control
De-emphasis for 32, 44.1, 48 and 96 kHz for both channel 1 and 2 (selectable independently)
Treble, which is selectable gain for high frequencies (positive gain only), the edge frequency of the treble is fixed (depends on the sampling frequency). Can be set for left and right independently: – Two settings: f c = 1.5 kHz and fc = 3 kHz, assuming sampling frequency is 44.1 kHz – Both settings have 0 to 6 dB gain range in steps of 2 dB
Bass boost, which is selectable gain for low frequencies (positive gain only). The edge frequency of the bass boost is fixed and depends on the sampling frequency. Can be set for left and right independently: – Two settings: f c = 250 Hz and fc = 300 Hz, assuming sampling frequency is 44.1 kHz – First setting: 0 to 18 dB gain range in steps of 2 dB – Second setting: 0 to 24 dB gain range in steps of 2 dB.

8.5 Noise shaper

The noise shaper consists of two mono 3rd-order noise shapers and one time-multiplexed stereo 5th-order noise shaper. The order of the noise shaper can be chosen between 3rd-order (which runs at 128f s) and 5th-order (which runs at 64fs) via bit SEL_NS in the L3-bus or I2C-bus register. The preferable choice for the noise shaper order is:

3rd-order noise shaper is preferred at low sampling frequencies, for instance between 8 and 32 kHz. This is for preventing out-of-band noise from the noise shaper to move into the audio band
5th-order noise shaper is normally used at higher sampling frequencies, normally from 32 to 100 kHz. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using an FSDAC. ITEM CONDITION VALUE (dB) Pass-band ripple 0 to 0.45f s ±0.025 Stop band >0.55f s −60 Dynamic range 0 to 0.45f s >135 handbook, halfpage 01 0 51 5 2 5 0.8 MGU119 0.6 0.4 0.2 t (ms) mute factor Fig.8 Mute as a function of raised cosine roll-off, displayed assuming 44.1 kHz.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.6 FSDAC

8.6.1 G ENERAL INFORMATION

The Filter-Stream Digital-to-Analog Converter (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream (running at either 64f s for the 5th-order noise shaper or 128fs for the 3rd-order noise shaper) of the noise shaper into an analog output voltage. The filter coefficients are implemented as current sources, and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity are achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal, capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage. Remark: When the FSDAC is powered-down, the output of the FSDAC becomes high impedance. 8.6.2 A NALOG MIXER INPUT The FSDAC has a mixer input, which makes it possible to mix an analog signal to the output signal of the FSDAC itself. In schematic form this is given in Fig.9. This mixer input can be used for instance for mixing-in a GSM signal or an FM signal directly to the line output. In the UDA1380, the mixer input is connected from the ADC line input via an AVC unit. Remark : Before the AVC unit can be used stand-alone, meaning without the digital part running, first the DAC part must be initialised in order to have the DAC output generating zero current. Otherwise the signal will be clipped.

8.7 Headphone driver

The UDA1380 is equipped with a headphone driver which can deliver 36 mW (at 3.0 V power supply) into a 16Ω load. The headphone driver does not need external DC decoupling capacitors because it can be DC coupled with respect to a special headphone output reference voltage. This saves two external capacitors (which is quite useful in a portable device). The headphone driver is equipped with short-circuit protection on all three operational amplifiers (left, right and the virtual ground). Each of the operational amplifiers has a signalling bit which becomes logic 1 in case the limiter is activated, for instance in case of a short-circuit. This means the microcontroller in the system can poll the L3-bus or I 2C-bus register of the headphone driver and as soon as, and for as long as, the short-circuit detection bits are activated, the microcontroller can signal the user that something is wrong or power-down the headphone driver (for instance, for energy-saving purposes). Remark: To improve headphone channel separation performance, the distance between V REF(HP) and the micro speaker port must be minimized.

8.8 Digital and analog mixers (DAC)

8.8.1 D IGITAL MIXER

The ADC output signal and digital input signal can be mixed without external DSP as shown in Fig.10. This mixer can be controlled via the microcontroller interface, and must only be enabled when the ADC and the DAC are running at the same frequency. In addition, the mixer output signal can also be applied to the I 2S-bus output interface. handbook, halfpage MGU531 FSDAC to analog mixer input bitstream Fig.9 Mixing signals to the FSDAC output (analog domain).

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, full pagewidth MGU532 BASS-BOOST AND TREBLE VOLUME AND MUTE DE-EMPHASIS VOLUME AND MUTE INTERPOLATION FILTER I2S-BUS OUTPUT BLOCK master SEL_SOURCE 2fs 1fsVOLUME AND MUTE DE-EMPHASIS mixing before sound features mixing after sound features from digital data input (channel 1) data from decimation filter (channel 2) to inter- polation filter Fig.10 Digital mixer (DAC).

8.8.2 A NALOG MIXER

The analog mixer, which uses the mixer input of the FSDAC, can mix a signal into the FSDAC output signal via an AVC unit (see Fig.11). The mixer can be used to mix a signal into the FSDAC output signal and play it via the headphone driver without the complete coder-decoder running. The analog control range is 0 to−64.5 dB and mutes in steps of 1.5 dB, with a gain of 16.5 dB (so actually the range is from +16.5 dB to−48 dB plus mute).handbook, full pagewidth MGU533 RESISTOR NETWORK AVC[5:0] L3 or I2C-bus control bits enable mixer (EN_AVC) to FSDAC mixer input PON_AVC from analog front-end Fig.11 Analog mixer configuration.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.9 Application modes

The operation mode can be set with pin SEL_L3_IIC, either to L3-bus mode (LOW) or to the I2C-bus mode (HIGH) as given in Table 5. For all features in microcontroller mode see Chapter 9. Table 5 Pin function in the selected mode Remark : In the I2C-bus mode there is a bit A1 which sets the LSB bit of the address of the UDA1380. In L3-bus mode this bit is not available, meaning the device has only one L3-bus device address.

8.10 Power-on reset

The UDA1380 has a dedicated pin RESET, which has a pull-down resistor. This way a Power-on reset circuit can be made with a capacitor and a resistor at the pin. The internal pull-down resistor cannot be used because of the 5 V tolerant nature of the pad. The pull-down resistor is shielded from the outside world by a transmission gate in order to support 5 V tolerance. The reset timing is determined by the external capacitor and resistor which are connected to the pin RESET, and the internal pull-down resistor. By the Power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the L3-bus and I 2C-bus control modes. Remark : The reset time should be at least 1µs, and during the reset time the system clock should be running. In case the WSPLL is selected as the clock source, a clock must be connected to the SYSCLK input in order to have proper reset of the L3-bus or I 2C-bus registers. This is because by default the clock source is set to SYSCLK.

8.11 Power-down requirements

The following blocks have power-down control via the L3-bus or I2C-bus interface:

Microphone amplifier (LNA) including its Single-Ended to Differential Converter (SDC) and VGA
ADC plus SDC and the PGA, for left and right separate
Bias generation circuit for the front-end and the FSDAC
Headphone driver
WSPLL
FSDAC. Clocks of the decimator, interpolator and the analog blocks have separate enable and disable controls. PIN L3-BUS MODE SEL_L3_IIC = L I2C-BUS MODE SEL_L3_IIC = H L3CLOCK/SCL L3CLOCK SCL L3MODE L3MODE A1 L3DATA/SDA L3DATA SDA

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.11.1 A NALOG FRONT -END

Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is done via separate L3-bus or I2C-bus bits. handbook, full pagewidth PGA PGA_GAINCTRLR PGA_GAINCTRLL ADC bitstream right ADC SDC bitstream left MGU534 PGAVINL VINR VINM SDC LNA SDC PON_PGAL PON_ADCL PON_BIAS FE BIAS VREF PON_PGAR PON_ADCRPON_LNA (27) (29) (31) Fig.12 Analog front-end power-down. Pin numbers for UDA1380HN in parentheses.

8.11.2 FSDAC POWER CONTROL

The FSDAC block has power-on pins: one of which shuts down the DAC itself, but leaves the output still at VREF voltage (which is half the power supply). This function is set by the bit PON_DAC in the L3-bus or I 2C-bus register. A second L3-bus or I2C-bus bit shuts down the complete bias circuit of the FSDAC, via bit PON_BIAS in the L3-bus or I 2C-bus register. This bit PON_BIAS acts the same as given in Fig.12 for the analog front-end.

8.12 Plop prevention

Plops are ticks and other strange sounds, that can occur when a part of a device is powered-up or powered-down, or when switching between modes is done. Some ways to prevent plops from occurring are:

When the FSDAC or headphone driver must be powered-down, first a digital mute is applied. After that the FSDAC or headphone driver can be powered-down. In case the FSDAC or headphone driver must be powered-up, first the analog part is switched on, then the digital part is demuted
When the ADC must be powered-down, a digital mute sequence must be applied. When the digital output signal is completely muted, the ADC can be powered-down. In case the ADC must be powered-up, first the analog part must be powered-up, then the digital part must be demuted
When there is a change of for example clock divider settings or clock source (selecting between SYSCLK and WSPLL clock), then also digital mute for that block (either decimator or interpolator) should be used. Remark : All items mentioned in Section 8.12 are not ‘hard-wired’ implemented, but to be followed by the users as a guideline for plop prevention.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

8.13 Digital audio data input and output

The supported audio formats for the control modes are:

I2S-bus
MSB-justified
LSB-justified, 16 bits
LSB-justified, 18 bits
LSB-justified, 20 bits
LSB-justified, 24 bits (only for the output interface). The bit clock BCK can be up to 128fs, or in other words the BCK frequency is 128 times the WS frequency or less: f BCK ≤ 128fWS Remark : The WS edge must coincide with the negative edge of the BCK at all times, for proper operation of the digital I/O data interface. Figure 13 shows the interface signals. 8.13.1 D IGITAL AUDIO INPUT INTERFACE The digital audio input interface is slave only, meaning the system must provide the WSI and BCKI signals (next to the DATAI signal). Either the WSPLL locks onto the WSI signal and provides the internal clocks for the interpolator and the FSDAC, or a system clock must be applied which must be in frequency lock to the digital data input interface signals. 8.13.2 D IGITAL AUDIO OUTPUT INTERFACE The digital audio output interface can be either master or slave. The data source for the data output can be selected from either the decimator (ADC front-end) or the digital mixer output. Remark: The digital mixer output is only valid if both the decimator and the interpolator run at the same clock:
In slave mode the signals on pins BCKO, WSO and SYSCLK must be applied from the application (signals must be in frequency lock) and the UDA1380 returns the DATAO signal from the decimator. The applied signal from pin BCKO can be for instance: 32f s, 48fs, 64fs, 96fs or 128fs
In master mode the SYSCLK signal must be applied from the system, but the UDA1380 returns with the BCKO, WSO and the DATAO signals. For the BCKO clock, there are 2 general rules: – When the SYSCLK is either 256f s or 512fs, the BCKO frequency is supposed to be 64fs – When the SYSCLK is either 384fs or 768fs, the BCKO signal should be 48fs. The slave and master modes can be selected by the bit Serial Interface Mode (SIM) in the L3-bus or I2C-bus interface.

9 L3-BUS INTERFACE DESCRIPTION

The UDA1380 has an L3-bus microcontroller interface mode. Controllable system and digital sound processing features are:

Software reset
System clock frequency (selection between 256f 384fs, 512fs and 768fs clock divider settings)
Clock mode setting, for instance, which block runs at which clock, and clock enabling
Power control for the WSPLL
Data input and data output format control, for input and output independently including data source selection for the digital output interface
ADC features: – Digital mute – AGC enable and settings – Polarity control – Input line amplifier control (0 to 24 dB in steps of 3 dB) – DC filtering control – Digital gain control (+24 to−63 dB gain in steps of 0.5 dB) for left and right – Power control – VGA of the microphone input – Selection of line or microphone input
DAC and headphone driver features: – Power control FSDAC and headphone driver – Polarity control – Mixing control (only available when both decimator and interpolator run at the same speed). This includes the mixer volumes, mute and mixer position switch – De-emphasis control – Master volume and balance control – Flat/minimum/maximum settings for the bass boost and treble – Tone control: bass boost and treble – Master mute control – Headphone driver short-circuit protection status bits.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 ndbook, full pagewidth MSB B2 B3 B4 B5 B6 LEFT LSB-JUSTIFIED FORMAT 20 BITS WS BCK DATA RIGHT 1518 1720 19 2 1 B19 LSB MSB B2 B3 B4 B5 B6 1518 1720 19 2 1 B19 LSB MSB MSBB2 21> = 812 3 LEFT I2S-BUS FORMAT WS BCK DATA RIGHT 3 > = 8 MSB B2 MBL121 B5 B6 B7 B8 B9 B10 LEFT LSB-JUSTIFIED FORMAT 24 BITS WS BCK DATA RIGHT 1518 1720 1922 212324 2 1 B3 B4MSB B2 B23 LSB B5 B6 B7 B8 B9 B10 1518 1720 1922 212324 21 B3 B4MSB B2 B23 LSB MSB B2 LEFT LSB-JUSTIFIED FORMAT 16 BITS WS BCK DATA RIGHT 15 2 1 B15 LSB MSB B2 15 2 1 B15 LSB MSB B2 B3 B4 LEFT LSB-JUSTIFIED FORMAT 18 BITS WS BCK DATA RIGHT 1518 17 2 1 MSB B2 B3 B4B17 LSB 16 1518 17 2 1 B17 LSB MSB-JUSTIFIED FORMAT WS LEFT RIGHT 321321 MSB B2 MSB LSB LSB MSB B2B2 > = 8 > = 8 BCK DATA Fig.13 Serial interface input and output formats.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

9.1 Introduction

The exchange of data and control information between the microcontroller and the UDA1380, is accomplished through a serial hardware interface comprising the following pins: L3DATA/SDA: microcontroller interface data line L3MODE: microcontroller interface mode line L3CLOCK/SCL: microcontroller interface clock line. Information transfer via the microcontroller bus is organized LSB first, and in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Inside the microcontroller there is a hand-shake mechanism which takes care of proper data transfer from the microcontroller clock, to the destination clock domains. This means that when data is sent to the microcontroller interface, the system clock must be running.

9.2 Device addressing

The device addressing mode is used to select a device for subsequent data transfer. The address mode is characterized by the signal on pin L3MODE being LOW and a burst of 8 pulses on pin L3CLOCK/SCL, accompanied by 8 bits. The fundamental timing is shown in Figs 14 and 15. Basically, two types of transfer can be defined: data transfer to the device, and data transfer from the device, as given in Table 6. Table 6 Selection of data transfer Table 6 shows that there are two types of data transfers: DATA and STATUS which can be read and written. Table 6 also shows that the DATA and STATUS read and write actions are combined. The device address consists of one byte, which is split-up in two parts:

Bits 7 to 2 represent a 6-bit device address. In the UDA1380 this is 000001
Bits 1 to 0 called Data Operation Mode, or DOM bits, represent the type of data transfer according to Table 6.

9.3 Slave address

The UDA1380 acts as a slave receiver or a slave transmitter. Therefore the signals L3CLOCK and L3MODE are only input signals. The data signal L3DATA is a bidirectional line. The UDA1380 slave address is shown in Table 7. Table 7 L3 slave address

9.4 Register addressing

After sending the device address, including the flags (the DOM bits) whether information is read or written, one byte is sent with the destination register address using 7 bits, and one bit which signals whether information will be read or written. The fundamental timing for L3 is given in Fig.19. Basically there are three forms for register addressing:

Register addressing for L3 write: the first bit is a logic 0 indicating a write action to the destination register, followed by seven register address bits
Prepare read addressing: the first bit of the byte is logic 1; signalling data will be read from the register indicated
The read action itself: in this case the device returns a register address prior to sending data from that register. When the first bit of the byte is logic 0, the register address was valid, in case the first bit is a logic 1 the register address was invalid. Remarks :
Each time a new destination address needs to be written, the device address must be sent again
When addressing the device for the first time after power-up of the device, at least one L3 clock-cycle must be given to enable the L3 interface. DOM BIT 1 DOM BIT 0 TRANSFER 0 0 not used 0 1 not used 1 0 DATA and STATUS write or pre-read 1 1 DATA and STATUS read (MSB) BIT (LSB) 000001

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

9.5 Data write mode

For writing data to a device, four bytes must be sent. Figure 14 explains the data write mode in a signal diagram:

One byte with the device address, being ‘00000110’, which is including the LSB code 01 for signalling write to the device
One byte starting with a logic 0 for signalling write, followed by 7 bits indicating the destination address
Two data bytes. The SYSCLK signal must be applied in data write mode. Table 8 L3 write data Notes 1. First bit in time. 2. Last bit in time. L3 MODE DATA TYPE BIT (1) 123456 7 (2) Addressing mode device address 0 1 1 0 0 0 0 0 Data transfer 1 register address 0 A6 A5 A4 A3 A2 A1 A0 Data transfer 2 MS data byte D15 D14 D13 D12 D11 D10 D9 D8 Data transfer 3 LS data byte D7 D6 D5 D4 D3 D2 D1 D0

9.6 Data read mode

For reading from the device, first a prepare-read must be done. After this, the device address is sent again. The device then returns with the register address, indicating whether the address was valid or not, and the data of the register. The following five steps explain this procedure, and an example of transmission is given in Fig.15.

One byte with the device address, being ‘00000110’, which is including the LSB code 01 for signalling write to the address
One byte is sent with the register address from which it needs to be read. This byte starts with a logic 1, which indicates that there will be a read action from the register
One byte with the device address including ‘11’ is sent to the device, being 00000111. The ‘11’ indicates that the device must write data to the microcontroller, then the microcontroller frees the L3DATA-bus so the UDA1380 can send the register address byte and its two-byte contents
The device now writes the requested register address on the bus, indicating whether the requested register was valid or not (logic 0 means valid, logic 1 means invalid)
The device writes the data from the requested register on the bus, being two bytes. The SYSCLK signal must be applied in data read mode.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 9 L3 prepare read data Notes 1. First bit in time. 2. Last bit in time. Table 10L3 read data Notes 1. First bit in time. 2. Last bit in time. 3. Data transfer from the UDA1380 to the microcontroller. L3 MODE DATA TYPE BIT (1) 123456 7 (2) Addressing mode device address 01100000 Data transfer 1 register address 1 A6 A5 A4 A3 A2 A1 A0 L3 MODE DATA TYPE BIT 0(1) 123456 7 (2) Addressing mode device address 1 1 1 0 0 0 0 0 Data transfer 1; note 3 register address 0: valid 1: invalid A6 A5 A4 A3 A2 A1 A0 Data transfer 2; note 3 MS data byte D15 D14 D13 D12 D11 D10 D9 D8 Data transfer 3; note 3 LS data byte D7 D6 D5 D4 D3 D2 D1 D0

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 MGU535 L3CLOCK L3MODE L3DATA 0 write device address DOM bits register address data byte 1 data byte 2 Fig.14 Data write mode for L3 version 2. MGU536 L3CLOCK L3MODE L3DATA 0 read valid/non-valid device address prepare read send by the device DOM bits register address device address register address data byte 1 data byte 2 11 1 0/11 Fig.15 Data read mode for L3 version 2.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

10 I2C-BUS INTERFACE DESCRIPTION

The UDA1380 supports I2C-bus microcontroller interface mode as well as the L3-bus mode; all features can be controlled by the microcontroller with the same register addresses as in the L3-bus mode. The exchange of data and control information between the microcontroller and the UDA1380 in I 2C-bus mode is accomplished through a serial hardware interface comprising the following pins: L3CLOCK/SCL: microcontroller interface clock line, SCL L3MODE: sets the bit A1of the I 2C-bus device address L3DATA/SDA: microcontroller interface data line, SDA. Figure 20 shows the clock and data timing of the I2C-bus transfer.

10.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The UDA1380 device address is [A6 to A0] 00110(A1)0, with bit A1 as the address selection bit (two addresses possible). 10.1.1 D EVICE ADDRESS (PIN A1) The UDA1380 acts as either a slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. Table 11 shows the device address of the UDA1380. The device can be set to one of the two addresses by using bit A1 (which is pin L3MODE) to select. Table 11I 2C-bus device address

10.1.2 R EGISTER ADDRESS

Table 12 shows the register address format of the UDA1380. The register mapping in I2C-bus mode is the same as for the L3-bus interface. Table 12I2C-bus register address (MSB) BIT (LSB) 00 1 1 0 A 1 0 R / W (MSB) BIT (LSB)

0 A 6 A 5 A 4A 3A 2A 1 A 0

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

10.2 WRITE cycle

Table 13 shows the I2C-bus configuration for a WRITE cycle. The WRITE cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes. The format of the WRITE cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address ‘00110A10’ and a logic 0 (WRITE) for the bit R/ 3. This is followed by an acknowledge (A) by the UDA1380. 4. After this the microcontroller writes the register address (ADDR) (8 bits) where the writing of the register content of the UDA1380 must start. 5. The UDA1380 acknowledges this register address (A). 6. The UDA1380 sends the two-bytes data with the Most Significant (MS) byte first, and then the Least Significant (LS) byte, each time acknowledged by the microcontroller. 7. The UDA1380 stops this cycle by generating an acknowledge (A). 8. Finally, the UDA1380 frees the I 2C-bus and the microcontroller can generate a stop condition (P). Table 13Master transmitter writes to UDA1380 registers in the I2C-bus mode INITIAL BYTE ACKNOWLEDGE FROM UDA1380 START DEVICE ADDRESS R/W REGISTER ADDRESS MS data byte LS data byte STOP auto increment if repeated n groups of 2 bytes are transmitted

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

10.3 READ cycle

Table 14 shows the I2C-bus configuration for a READ cycle. The READ cycle is used to read the data values from the internal registers. The format of the READ cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address ‘00110A10’ and a logic 0 (WRITE) for the bit R/ 3. This is followed by an acknowledge (A) by the UDA1380. 4. After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1380 must start. 5. The UDA1380 acknowledges this register address. 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address ‘00110A10’ again, but this time followed by a logic 1 (READ) of the bit R/ 8. The UDA1380 sends the two-bytes register contents with the Most Significant (MS) byte first, and then the Least Significant (LS) byte, each time acknowledged by the microcontroller. 9. The microcontroller stops this cycle by generating a negative acknowledge (NA). 10. Finally, the UDA1380 frees the I 2C-bus and the microcontroller can generate a stop condition (P). Table 14Master transmitter reads from the UDA1380 registers in the I2C-bus mode INITIAL BYTE ACKNOWLEDGE FROM UDA1380 ACKNOWLEDGE FROM MICROCONTROLLER DEVICE ADDRESS R/W REGISTER ADDRESS R/W MS data byte LS data byte auto increment if repeated n groups of 2 bytes are transmitted

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11 REGISTER MAPPING

Table 15Register map of control settings (write) Table 16Register map of status bits (read-out) REGISTER ADDRESS FUNCTION System settings (running at the L3-bus or I2C-bus clock itself) 00H evaluation modes, WSPLL settings, clock divider and clock selectors 01H I 2S-bus I/O settings 02H power control settings 03H analog mixer settings 04H reserved Interpolation ﬁlter (running at 128f s interpolator clock) 10H master volume control 11H mixer volume control 12H mode selection, left and right bass boost, and treble settings 13H master mute, channel 1 and channel 2 de-emphasis and channel mute 14H mixer, silence detector and interpolation ﬁlter oversampling settings Decimator (running at 128f s decimator clock) 20H decimator volume control 21H PGA settings and mute 22H ADC settings 23H AGC settings Software reset 7FH restore L3-default values REGISTER ADDRESS FUNCTION Headphone driver and interpolation ﬁlter 18H interpolation ﬁlter status Decimator 28H decimator status

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.1 Evaluation modes and clock settings

Table 17Register address 00H Table 18Description of register bits BIT 15 14 13 12 11 10 9 8 Symbol EV2 EV1 EV0 − EN_ADC EN_DEC EN_DAC EN_INT Default 0 0 0 0 0 1 0 1 BIT 7 6 5 4 3 2 1 0 Symbol −− ADC_CLK DAC_CLK sys_div1 sys_div0 PLL1 PLL0 Default 0 0 0 0 0 0 1 0 BIT SYMBOL DESCRIPTION 15 to 13 EV[2:0] Evaluation bits. Bits EV2, EV1 and EV0 are special control bits for manufacturer’s evaluation and must always be kept at their default values for normal operation of UDA1380; default value 000, see Table 17. 12 − default value 0 11 EN_ADC ADC clock enable. A 1-bit value to enable the system clock (from SYSCLK input) to the analog part of the ADC. See Fig.5 for more detailed information. When this bit is logic 0: clock to ADC disabled and when this bit is logic 1: clock to ADC running. Default value 0. 10 EN_DEC Decimator clock enable. A 1-bit value to enable the 128f s clock to the decimator, the 128fs part of the I2S-bus output block and the clock to the ADC L3-bus or I2C-bus registers. See Fig.5 for more detailed information. When this bit is logic 0: clock to the decimator disabled. When this bit is logic 1: clock to the decimator running. Default value 1. 9 EN_DAC FSDAC clock enable.A 1-bit value to enable the 256f s clock to the analog part of the FSDAC. See Fig.5 for more detailed information. When this bit is logic 0: clock to FSDAC disabled. When this bit is logic 1: clock to the FSDAC running. Default value 0. 8 EN_INT Interpolator clock enable. A 1-bit value to enable the 128f s clock to the interpolator, the 128fs part of the I2S-bus input block and the interpolator registers of the L3-bus or I2C-bus interface. See Fig.5 for more detailed information. When this bit is logic 0: clock to the interpolator disabled. When this bit is logic 1: clock to the interpolator running. Default value 1. 7 and 6 − default value 00 5 ADC_CLK ADC clock select. A 1-bit value to select the 128f s clock and the clock of the analog part for the decimator and the ADC. This can either be the clock derived from the SYSCLK input or from the WSPLL. When this bit is logic 0: SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 19Dividers for system clock input Table 20WSPLL settings 4 DAC_CLK DAC clock select. A 1-bit signal to select the clocks for the DAC (interpolator and FSDAC analog block). In both cases the clocks must be 128f s and 256fs (for the analog part), but in one case the clock is derived from the WSI clock, and in the other case the clock is derived from the SYSCLK. When this bit is logic 0: SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0. 3 and 2 sys_div[1:0] Dividers for system clock input. A 2-bit value to select the proper division factor for the SYSCLK input in such a way that a128f s clock will be generated from the SYSCLK clock signal. The 128fs clock is needed for clocking the decimator and interpolator. Default value 00, see Table 19. 1 and 0 PLL[1:0] WSPLL setting. A 2-bit value to select the WSPLL input frequency range. These set the proper divider setting for the WSPLL. The input is the WSI signal, the output inside the IC is a 128f s and a 256fs clock. Default value 10, see Table 20. sys_div1 sys_div0 INPUT CLOCK ON PIN SYSCLK 0 0 256f s (default) 0 1 384f s 1 0 512f s 1 1 768f s PLL1 PLL0 INPUT FREQUENCY RANGE (kHz) ON PIN WSI 0 0 6.25 to 12.5 0 1 12.5 to 25 1 0 25 to 50 (default) 1 1 50 to 100 BIT SYMBOL DESCRIPTION

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.2 I2S-bus input and output settings

Table 21Register address 01H Table 22Description of register bits Table 23Digital data input formats BIT 15 14 13 12 11 10 9 8 Symbol −−−−− SFORI2 SFORI1 SFORI0 Default 00000000 B I T 76543210 Symbol − SEL_ SOURCE − SIM − SFORO2 SFORO1 SFORO0 Default 00000000 BIT SYMBOL DESCRIPTION 15 to 11 − default value 00000 10 to 8 SFORI[2:0] Digital data input formats. A 3-bit value to select the digital input data format (DATAI input).Default value 000, see Table 23. 7 − default value 0 6 SEL_SOURCE Digital output interface mode settings. A 1-bit value SEL_SOURCE to set the mode of the digital output interface source to either the decimator output or the digital mixer output. When this bit is logic 0: source digital output interface mode, set to decimator. When this bit is logic 1: source digital output interface mode, set to digital mixer output. Default value 0. 5 − default value 0 4 SIM Digital output interface mode settings. A 1-bit value SIM sets the mode of the digital output interface. The speed of the BCKO pad, being 64f s or 48fs, is selected by the bits sys_div[1:0]. In case the 384fs or 768fs mode is selected the output clock is 48fs, in case 256fs or 512fs is selected, the BCKO is 64fs. When this bit is logic 0: mode of digital output interface is set to slave. When this bit is logic 1: mode of digital output interface is set to master. Default value 0. 3 − default value 0 2 to 0 SFORO[2:0] Digital data output formats.A 3-bit value to set the digital data output format (on pin DATAO). Default value 000, see Table 24. SFORI2 SFORI1 SFORI0 SERIAL_FORMAT_DAI 000 I 2S-bus (default) 0 0 1 LSB-justiﬁed, 16 bits 0 1 0 LSB-justiﬁed, 18 bits 0 1 1 LSB-justiﬁed, 20 bits 1 0 1 MSB-justiﬁed 1 0 0 not used: mapped to I 2S-bus 110 111

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 24Digital data output formats

11.3 Power control settings

11.3.1 P OWER CONTROL SETTING BIAS CIRCUITS

Using a 1-bit value, the power control settings of the bias circuits of the ADC, AVC and FSDAC can be set. When this bit is set to logic 0, the complete bias circuits of the analog front-end and the FSDAC are shut down. In this case, the reference voltage disappears from the input of the ADCs and LNA and the output of the FSDAC, this can cause plops, but saves power. Table 25Register address 02H Table 26Description of register bits SFORO2 SFORO1 SFORO0 SERIAL_FORMAT_DAO 000 I 2S-bus (default) 0 0 1 LSB-justiﬁed, 16 bits 0 1 0 LSB-justiﬁed, 18 bits 0 1 1 LSB-justiﬁed, 20 bits 1 0 0 LSB-justiﬁed, 24 bits 1 0 1 MSB-justiﬁed 1 1 0 not used: mapped to I 2S-bus 111 BIT 15 14 13 12 11 10 9 8 Symbol PON_PLL − PON_HP −− PON_DAC − PON_ BIAS Default 00000000 B I T 76543210 Symbol EN_AVC PON_AVC − PON_LNA PON_ PGAL PON_ ADCL PON_ PGAR PON_ ADCR Default 00000000 BIT SYMBOL DESCRIPTION 15 PON_PLL Power-on WSPLL. When this bit is logic 0: power-off; when this bit is logic 1: power-on. Default value 0. 14 − default value 0 13 PON_HP Power-on headphone driver.A 1-bit value to switch the headphone driver into power-on or Power-down mode. When this bit is logic 0: headphone driver is powered-off; when this bit is logic 1: headphone driver is powered-on. Default value 0. 12 and 11 − default value 00 10 PON_DAC Power-on DAC. A 1-bit value to switch the DAC into power-on or Power-down mode. In this Power-down mode the V REF (half the power supply voltage) will remain on the FSDAC output. When this bit is logic 0: DAC is powered-off; when this bit is logic 1: DAC is powered-on. Default value 0. 9 − default value 0

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 8 PON_BIAS Power-on BIAS.A 1-bit value to set the power control setting of the ADC, AVC and FSDAC. When this bit is logic 0: ADC, AVC and FSDAC bias circuits are powered-off; when this bit is logic 1: Power-on bias for ADC, AVC and FSDAC. Default value 0. 7 EN_AVC Enable control AVC.A 1-bit value to enable or disable the analog mixer. When this bit is logic 0: analog mixer is disabled; when this bit is logic 1: analog mixer is enabled. Default value 0. 6 PON_AVC Power-on AVC. A 1-bit value to have power-on control for the analog mixer. When this bit is logic 0: analog mixer powered-off; when this bit is logic 1: analog mixer powered-on. Default value 0. 5 − default value 0 4 PON_LNA Power-on LNA. A 1-bit value to power-on the LNA and SDC. When this bit is logic 0: LNA and SDC are powered-off; when this bit is logic 1: LNA and SDC are powered-on. Default value 0. 3 PON_PGAL Power-on PGAL. A 1-bit value to have power-on control for the PGA left. When this bit is logic 0: left PGA is powered-off; when this bit is logic 1: left PGA is powered-on. Default value 0. 2 PON_ADCL Power-on ADCL. A 1-bit value to have power-on control for the ADC left. When this bit is logic 0: left ADC is powered-off; when this bit is logic 1: left ADC is powered-on. Default value 0. 1 PON_PGAR Power-on PGAR. A 1-bit value to have power-on control for the PGA right. When this bit is logic 0: right PGA is powered-off; when this bit is logic 1: right PGA is powered-on. Default value 0. 0 PON_ADCR Power-on ADCR. A 1-bit value to have power-on control for the ADC right. When this bit is logic 0: right ADC is powered-off; when this bit is logic 1: right ADC is powered-on. Default value 0. BIT SYMBOL DESCRIPTION

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.4 Analog mixer settings

Table 27Register address 03H Table 28Description of register bits BIT 15 14 13 12 11 10 9 8 Symbol −− AVCL5 AVCL4 AVCL3 AVCL2 AVCL1 AVCL0 Default 0 0 1 1 1 1 1 1 B I T 76543210 Symbol −− AVCR5 AVCR4 AVCR3 AVCR2 AVCR1 AVCR0 Default 0 0 1 1 1 1 1 1 BIT SYMBOL DESCRIPTION 15 and 14 − default value 00 13 to 8 AVCL[5:0] Analog volume control. A 6-bit value to program the left master volume attenuation. The range is from +16.5 to−48 and−∞ dB in steps of 1.5 dB. The 16.5 dB gain is there to boost the 150 mV (RMS) which comes from for instance an FM tuner IC to 1 V (RMS) needed to drive the headphone driver full-swing. Default value 111111, see Table 29. 7 and 6 − default value 00 5 to 0 AVCR[5:0] Analog volume control. A 6-bit value to program the right master volume attenuation. The range is from +16.5 to−48 and−∞ dB in steps of 1.5 dB. The 16.5 dB gain is there to boost the 150 mV (RMS) which comes from for instance an FM tuner IC to 1 V (RMS) needed to drive the headphone driver full-swing. Default value 111111, see Table 29.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 29Analog volume control

11.5 Reserved

Bits RSV12, RSV11, RSV10, RSV02, RSV01, and RSV00 are special control bits for manufacturer’s evaluation and must always be kept at their default values for normal operation of UDA1380. Table 30Register address 04H Table 31Description of the register bits AVCL5 AVCR5 AVCL4 AVCR4 AVCL3 AVCR3 AVCL2 AVCR2 AVCL1 AVCR1 AVCL0 AVCR0 VOLUME (dB) 000000 16.5 000001 1 5 000010 13.5 000011 1 2 000100 10.5 :::::: : 101011 −48 101100 −∞ :::::: : 111111 −∞ (default) BIT 15 14 13 12 11 10 9 8 Symbol −−−−− RSV12 RSV11 RSV10 B I T 76543210 Symbol −−−−− RSV02 RSV01 RSV00 BIT SYMBOL DESCRIPTION 15 to 11 − not used 10 RSV12 Reserved bit. Default value 0 9 RSV11 Reserved bit. Default value 1 8 RSV10 Reserved bit. Default value 0 7t o3 − not used 2 RSV02 Reserved bit. Default value 0 1 RSV01 Reserved bit. Default value 1 0 RSV00 Reserved bit. Default value 0

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.6 Master volume control

Table 32Register address 10H Table 33Description of the register bits Table 34Master volume control bits BIT 15 14 13 12 11 10 9 8 Symbol MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0 Default 00000000 B I T 76543210 Symbol MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0 Default 00000000 BIT SYMBOL DESCRIPTION 15 to 8 MVCR_[7:0] Master volume control right. An 8-bit value to program the right channel volume attenuation. The range is from 0 to−78 dB and−∞ dB in steps of 0.25 dB. Default value 00000000, see Table 34. 7 to 0 MVCL_[7:0] Master volume control left. An 8-bit value to program the left channel volume attenuation. The range is from 0 to−78 dB and−∞ dB in steps of 0.25 dB. Default value 00000000, see Table 34. MVCR_7 MVCL_7 MVCR_6 MVCL_6 MVCR_5 MVCL_5 MVCR_4 MVCL_4 MVCR_3 MVCL_3 MVCR_2 MVCL_2 MVCR_1 MVCL_1 MVCR_0 MVCL_0 VOLUME (dB) 00000000 0 (default) 00000001 −0.25 00000010 −0.50 00000011 −0.75 00000100 −1 :::::::: : 11001000 −50 11001100 −51 11001101 −51.25 11001110 −51.50 11001111 −51.75 11010000 −52 11010100 −54 11011000 −56 :::::::: : 11101100 −66 11110000 −69 11110100 −72 11111000 −78 11111100 −∞

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.7 Mixer volume control

Table 35Register address 11H Table 36Description of the register bits Table 37Digital mixer volume control BIT 15 14 13 12 11 10 9 8 Symbol VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0 Default 1 1 1 1 1 1 1 1 BIT 7 6 5 4 3 2 1 0 Symbol VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0 Default 0 0 0 0 0 0 0 0 BIT SYMBOL DESCRIPTION 15 to 8 VC2_[7:0] Digital mixer volume control. An 8-bit value to program the channel 2 volume attenuation. The range is 0 to−72 dB and−∞ dB in steps of 0.25 dB. Default value for channel 2 is 00000000, see Table 37. 7 to 0 VC1_[7:0] Digital mixer volume control. An 8-bit value to program the channel 1 volume attenuation. The range is 0 to−72 dB and−∞ dB in steps of 0.25 dB. Default value for channel 1 is 11111111, see Table 37. VC2_7 VC1_7 VC2_6 VC1_6 VC2_5 VC1_5 VC2_4 VC1_4 VC2_3 VC1_3 VC2_2 VC1_2 VC2_1 VC1_1 VC2_0 VC1_0 VOLUME (dB) 000000000 00000001 −0.25 00000010 −0.50 00000011 −0.75 00000100 −1 ::::::::: 10110100 −45 10110101 −45.25 10110110 −45.50 10110111 −45.75 10111000 −46 10111100 −48 11000000 −50 ::::::::: 11010100 −60 11011000 −63 11011100 −66 11100000 −72

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.8 Mode, bass boost and treble

Table 38Register address 12H Table 39Description of register bits Table 40Flat/minimum/maximum setting bits 11100100 −∞ ::::::::: 11111100 −∞ BIT 15 14 13 12 11 10 9 8 Symbol M1 M0 TRL1 TRL0 BBL3 BBL2 BBL1 BBL0 Default 0 0 0 0 0 0 0 0 B I T 76543210 Symbol −− TRR1 TRR0 BBR3 BBR2 BBR1 BBR0 Default 0 0 0 0 0 0 0 0 BIT SYMBOL DESCRIPTION 15 and 14 M[1:0] Flat/minimum/maximum setting. A 2-bit value to program the mode of the sound processing ﬁlters of bass boost and treble. Default value 00, see Table 40. 13 and 12 TRL[1:0] Treble setting left. A 2-bit value to program the mode of the sound processing ﬁlter of treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41. 11 to 8 BBL[3:0] Bass boost setting left.A 4-bit value to program the bass boost setting, which can be set for left and right independently. The used set depends on the bits M1 and M0. Default value 0000, see Table 42. 7 and 6 − default value 00 5 and 4 TRR[1:0] Treble setting right. A 2-bit value to program the mode of the sound processing ﬁlter of treble. Default value 00, see Table 41. 3 to 0 BBR[3:0] Bass boost setting right. A 4-bit value to program the bass boost setting, which can be set for left and right independently. The used set depends on the mode bits. Default value 0000, see Table 42. M1 M0 MODE 0 0 ﬂat (default) 0 1 minimum 1 0 minimum 1 1 maximum VC2_7 VC1_7 VC2_6 VC1_6 VC2_5 VC1_5 VC2_4 VC1_4 VC2_3 VC1_3 VC2_2 VC1_2 VC2_1 VC1_1 VC2_0 VC1_0 VOLUME (dB)

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 41Treble setting bits Table 42Bass boost setting bits TRL1 TRR1 TRL0 TRR0 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB) 0 0 0 (default) 0 (default) 0 (default) 01 0 2 2 10 0 4 4 11 0 6 6 BBL3 BBR3 BBL2 BBR2 BBL1 BBR1 BBL0 BBR0 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB) 0000 0 (default) 0 (default) 0 (default) 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 1 0 1 0 0110 0 1 2 1 2 0111 0 1 4 1 4 1000 0 1 6 1 6 1001 0 1 8 1 8 1010 0 1 8 2 0 1011 0 1 8 2 2 1100 0 1 8 2 4 1101 0 1 8 2 4 1110 0 1 8 2 4 1111 0 1 8 2 4

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.9 Master mute, channel de-emphasis and mute

Table 43Register address 13H Table 44Description of register bits Table 45De-emphasis selection bits BIT 15 14 13 12 11 10 9 8 Symbol − MTM −− MT2 DE2_2 DE2_1 DE2_0 Default 0 1 0 0 1 0 0 0 BIT 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 BIT SYMBOL DESCRIPTION 15 − default value 0 14 MTM Master mute.A 1-bit value to enable the digital mute for the master. When this bit is logic 0: no soft mute of master. When this bit is logic 1: soft mute of master. Default value 1. 13 and 12 − default value 00 11 MT2 Channel 2 mute. A 1-bit value to enable the digital mute for channel 2. After enabling the mixer, bit MT2 must be set to logic 0. When this bit is logic 0: no soft mute of channel 2. When this bit is logic 1: soft mute of channel 2 (default value 1, meaning that channel 2 is always muted, even when the mixer is enabled). 10 to 8 DE2_[2:0] De-emphasis. A 3-bit value to enable the digital de-emphasis ﬁlter for channel 1 and 2. Default value 000, see Table 45. 7t o4 − default value 0000 3 MT1 Channel 1 mute. A 1-bit value to enable the digital mute for channel 1. When this bit is logic 0: no soft mute of channel 1. When this bit is logic 1: soft mute of channel 1. Default value 0. 2 to 0 DE1_[2:0] De-emphasis. A 3-bit value to enable the digital de-emphasis ﬁlter for channel 1 and 2. Default value 000, see Table 45. DE2_2 DE1_2 DE2_1 DE1_1 DE2_0 DE1_0 FUNCTION 0 0 0 off (default) 0 0 1 32 kHz 0 1 0 44.1 kHz 0 1 1 48 kHz 1 0 0 96 kHz

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.10 Mixer, silence detector and oversampling settings

Table 46Register address 14H Table 47Description of register bits BIT 15 14 13 12 11 10 9 8 Symbol DA_POL_INV SEL_NS MIX_POS MIX −−−− Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol SILENCE SDET_ON SD_VALUE1 SD_VALUE0 −− OS1 OS0 Default 0 0 0 0 0 0 0 0 BIT SYMBOL DESCRIPTION 15 DA_POL_INV DAC polarity control. A 1-bit value to control the signal polarity of the DAC output signal. When this bit is logic 0: DAC output not inverted. When this bit is logic 1: DAC output inverted. Default value 0. 14 SEL_NS Noise shaper order select. A 1-bit value to select between the 3rd-order and the 5th-order noise shaper. When this bit is logic 0: select 3rd-order noise shaper. When this bit is logic 1: select 5th-order noise shaper. Default value 0. 13 MIX_POS Mixer signal control. A 2-bit value to select the digital mixer settings inside the interpolation ﬁlter. Default value 0. Default the mixer is off, see Table 48.

12 MIX

11 to 8 − default value 0000 7 SILENCE Silence detector. A 1-bit value to force the DAC output to silence. When this bit is logic 0: no overruling. The setting of the FSDAC silence switch depends on the status of the digital silence detector circuit and the master_mute status. When this bit is logic 1: overruling. The FSDAC silence switch is activated, independent of the status of the digital silence detector circuit or the master_mute status. Default value 0. 6 SDET_ON Silence detector enable. A 1-bit value to enable the digital silence detector. When this bit is logic 0: silence detection circuit disabled. When this bit is logic 1: silence detection circuit enabled. Default value 0. 5 and 4 SD_VALUE[1:0] Silence detector settings. A 2-bit value to program the silence detector, the number of ‘ZERO’ samples counted before the silence detector signals whether there has been digital silence. Default value 00, see Table 49. 3 and 2 − default value 00 1 and 0 OS[1:0] Oversampling input settings.A 2-bit value to select the oversampling input mode. Default value 00, see Table 50.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 48Mixer signal control setting bits Table 49Silence detector setting bits Table 50Oversampling input setting bits

11.11 Decimator volume control

Table 51Register address 20H Table 52Description of register bits MIX_POS MIX FUNCTION 0 0 no mixing; default 1 0 volume of channel 1 is forced to 0 dB and volume of channel 2 is forced to −∞ dB 0 1 mixing is done before the sound processing: input signals are automatically scaled by 6 dB in order to prevent clipping during adding; after the addition, the 6 dB scaling is compensated 1 1 mixing is done after the sound processing: input signals are automatically scaled in order to prevent clipping during adding SD_VALUE1 SD_VALUE0 FUNCTION 0 0 3200 samples; default 0 1 4800 samples 1 0 9600 samples 1 1 19200 samples OS1 OS0 FUNCTION 0 0 single-speed input is normal input; mixing possible; default 0 1 double-speed input is after ﬁrst half-band; no mixing possible 1 0 quad-speed input is in front of noise shaper; no mixing possible 1 1 reserved BIT 15 14 13 12 11 10 9 8 Symbol ML_DEC7 ML_DEC6 ML_DEC5 ML_DEC4 ML_DEC3 ML_DEC2 ML_DEC1 ML_DEC0 Default 00000000 B I T76543210 Symbol MR_DEC7 MR_DEC6 MR_DEC5 MR_DEC4 MR_DEC3 MR_DEC2 MR_DEC1 MR_DEC0 Default 00000000 BIT SYMBOL DESCRIPTION 15 to 8 ML_DEC[7:0] ADC volume control left.An 8-bit value to program the gain of the decimator for left and right independently. The ranges are +24 to−63.5 dB and−∞ dB in steps of 0.5 dB. The default setting is 0 dB (value 00000000), see Table 53. 7 to 0 MR_DEC[7:0] ADC volume control right. An 8-bit value to program the gain of the decimator for left and right independently. The ranges are +24 to−63.5 dB and−∞ dB in steps of 0.5 dB. The default setting is 0 dB (value 00000000), see Table 53.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 53ADC volume control setting bits

11.12 PGA settings and mute

Table 54Register address 21H Table 55Description of register bits ML_DEC7 MR_DEC7 ML_DEC6 MR_DEC6 ML_DEC5 MR_DEC5 ML_DEC4 MR_DEC4 ML_DEC3 MR_DEC3 ML_DEC2 MR_DEC2 ML_DEC1 MR_DEC1 ML_DEC0 MR_DEC0 GAIN (dB) 00110000 2 4 00101111 23.5 00101110 2 3 :::::::: : 00000010 1 000000010 . 5 00000000 0 (default) 11111111 −0.5 :::::::: : 10000100 −62 10000011 −62.5 10000010 −63 10000001 −63.5 10000000 −∞ BIT 15 14 13 12 11 10 9 8 Symbol MT_ADC −−− PGA_GAIN CTRLR3 PGA_GAIN CTRLR2 PGA_GAIN CTRLR1 PGA_GAIN CTRLR0 Default 1 0 0 0 0000 B I T 7 6 5 4 3210 CTRLL3 PGA_GAIN CTRLL2 PGA_GAIN CTRLL1 PGA_GAIN CTRLL0 Default 0 0 0 0 0000 BIT SYMBOL DESCRIPTION 15 MT_ADC Decimator mute.A 1-bit value to enable the digital linear mute. When this bit is logic 0: no muting. When this bit is logic 1: muting. Default value 1. 14 to 12 − default value 000

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 56ADC input ampliﬁer PGA gain setting bits

11.13 ADC settings

Table 57Register address 22H Table 58Description of register bits 11 to 8 PGA_GAIN CTRLR[3:0] ADC input ampliﬁer right gain settings.A 4-bit value to program the gain of the input ampliﬁer. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB. The gain control of the PGA is independent for left and right. Default value 0000, see Table 56. 7t o4 − default value 0 3 to 0 PGA_GAIN CTRLL[3:0] ADC input ampliﬁer left gain settings. A 4-bit value to program the gain of the input ampliﬁer. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB. The gain control of the PGA is independent for left and right. Default value 0000, see Table 56. PGA_GAINCTRLR3 PGA_GAINCTRLL3 PGA_GAINCTRLR2 PGA_GAINCTRLL2 PGA_GAINCTRLR1 PGA_GAINCTRLL1 PGA_GAINCTRLR0 PGA_GAINCTRLL0 PGA_GAIN (dB) 0000 0 (default) 00013 00106 00119 0100 1 2 0101 1 5 0110 1 8 0111 2 1 1XXX 2 4 BIT 15 14 13 12 11 10 9 8 Symbol −−− ADCPOL_ INV VGA_CTRL3 VGA_CTRL2 VGA_CTRL1 VGA_CTRL0 Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol −−− − SEL_LNA SEL_MIC SKIP_DCFIL EN_DCFIL Default 0 0 0 0 0 0 1 0 BIT SYMBOL DESCRIPTION 15 to 13 − default value 000 12 ADCPOL_INV ADC polarity control. A 1-bit value to select ADC polarity. When this bit is logic 0: polarity of ADC non-inverting. When this bit is logic 1: polarity of ADC inverting. Default value 0. 11 to 8 VGA_CTRL[3:0] Microphone input VGA gain settings. A 4-bit value to program the gain of the LNA in the microphone input channel. The range is 0 to 30 dB in steps of 2 dB. Default value 0000, see Table 59. BIT SYMBOL DESCRIPTION

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 59Microphone input VGA gain setting bits 7t o4 − default value 0000 3 SEL_LNA Line input select.A 1-bit value to set the multiplexer in the analog front-end to select between the LNA or the enable-in input for the left ADC. When this bit is logic 0: select line input. When this bit is logic 1: select LNA for the left ADC. Default value 0. 2 SEL_MIC Microphone input select.A 1-bit value to set the multiplexer at the ADC right channel output (on bit-stream level) which selects either the right channel data or the left channel data, in case only the microphone input is used. In that case the microphone signal can be applied to the decimator for both left and right. When this bit is logic 0: select right channel ADC. When this bit is logic 1: select left channel ADC (for instance for microphone input). Default value 0. 1 SKIP_DCFIL DC ﬁlter bypass. A 1-bit value set to skip the DC ﬁlter which is just before the decimator. This DC ﬁlter is there to compensate for the DC offset added in the ADC (to remove idle tones from the audio band). This DC signal added (the DC dither) must not be ampliﬁed in order to prevent clipping. Therefore this DC offset is removed ﬁrst. When this bit is logic 0: DC ﬁlter enabled. When this bit is logic 1: DC ﬁlter bypassed. Default value 1. 0 EN_DCFIL DC ﬁlter enable. A 1-bit value set to enable the DC ﬁlter which is at the output of the decimator (running at 1f s). When this bit is logic 0: DC ﬁlter disabled. When this bit is logic 1: DC ﬁlter enabled. Default value 0. VGA_CTRL3 VGA_CTRL2 VGA_CTRL1 VGA_CTRL0 LNA GAIN (dB) 0000 0 (default) 00012 00104 00116 01008 0101 1 0 0110 1 2 0111 1 4 1000 1 6 1001 1 8 1010 2 0 1011 2 2 1100 2 4 1101 2 6 1110 2 8 1111 3 0 BIT SYMBOL DESCRIPTION

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.14 AGC settings

Table 60Register address 23H Table 61Description of register bits Table 62AGC time constant setting bits BIT 15 14 13 12 11 10 9 8 Symbol −−− − − AGC_TIME2 AGC_TIME1 AGC_TIME0 Default 0 0 0 0 0000 B I T 7 6 5 4 3210 Symbol −−− − AGC_LEVEL1 AGC_LEVEL0 − AGC_EN Default 0 0 0 0 0000 BIT SYMBOL DESCRIPTION 15 to 11 − Default value 00000. 10 to 8 AGC_TIME[2:0] AGC time constant settings.A 3-bit value to set the AGC time constants, being the attack and decay time constants. The given constants are for 44.1 and 8 kHz sampling frequencies, and must be scaled either down or up according to the sampling frequency used. Default value 000, see Table 62. 7t o4 − default value 0000 3 and 2 AGC_LEVEL[1:0] AGC target level settings.A 2-bit value to set the AGC target level. Default value 00, see Table 63. 1 − default value 0 0 AGC_EN AGC enable control. A 1-bit value to enable or disable the AGC. When the AGC is enabled, the bit SKIP_DCFIL must be set to logic 0 to avoid disturbance on the output signal due to the DC offset added in the ADC. When this bit is logic 0: AGC off, manual gain control via the left and right decimator volume control. When this bit is logic 1: AGC enabled, with manual microphone gain setting via VGA. Default value 0. AGC_TIME2 AGC_TIME1 AGC_TIME0 AGC SETTING 44.1 kHz SAMPLING 8 kHz SAMPLING ATTACK TIME (ms) DECAY TIME (ms) ATTACK TIME (ms) DECAY TIME (ms) 0 0 0 11 100 61 551 (default) 0 0 1 16 100 88.2 551 0 1 0 11 200 61 1102 0 1 1 16 200 88.2 1102 1 0 0 21 200 116 1102 1 0 1 11 400 61 2205 1 1 0 16 400 88.2 2205 1 1 1 21 400 116 2205

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Table 63AGC target level setting bits

11.15 Restore L3 default values (software reset)

Table 64Register address 7FH

11.16 Headphone driver and interpolation ﬁlter (read-out)

Table 65Register address 18H Table 66Description of the register bits AGC_LEVEL1 AGC_LEVEL0 AGC TARGET LEVEL VALUE (dBFS) 00 −5.5 (default) 01 −8 10 −11.5 11 −14 BIT 15 14 13 12 11 10 9 8 B I T 76543 2 1 0 BIT 15 14 13 12 11 10 9 8 B I T 76543 2 1 0 Symbol − SDETR2 SDETL2 SDETR1 SDETL1 MUTE_ STATE_M MUTE_ STATE_CH2 MUTE_ STATE_CH1 BIT SYMBOL DESCRIPTION 15 to 11 − not used 10 HP_STCTV Headphone driver short-circuit detection. When this bit is logic 0: headphone driver is not short-circuit protected. When this bit is logic 1: headphone driver short-circuit protection is activated. 9 HP_STCTL Left headphone driver short-circuit detection. When this bit is logic 0: left channel headphone driver is not short-circuit protected. When this bit is logic 1: left channel headphone driver short-circuit protection is activated. 8 HP_STCTR Right headphone driver short-circuit detection. When this bit is logic 0: right channel headphone driver not short-circuit protected. When this bit is logic 1: right channel headphone driver short-circuit protection activated. 7 − not used 6 SDETR2 Interpolator silence detect channel 2 right. When this bit is logic 0: interpolator on channel 2 right input has detected no silence. When this bit is logic 1: interpolator on channel 2 right input has detected silence. 5 SDETL2 Interpolator silence detect channel 2 left. When this bit is logic 0: interpolator on channel 2 left input has detected no silence. When this bit is logic 1: interpolator on channel 2 left input has detected silence.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

11.17 Decimator read-out

Table 67Register address 28H Table 68Description of the register bits 4 SDETR1 Interpolator silence detect channel 1 right. When this bit is logic 0: interpolator on channel 1 right input has detected no silence. When this bit is logic 1: interpolator on channel 1 right input has detected silence. 3 SDETL1 Interpolator silence detect channel 1 left. When this bit is logic 0: interpolator on channel 1 left input has detected no silence. When this bit is logic 1: interpolator on channel 1 left input has detected silence. 2 MUTE_STATE_M Interpolator muting. A 1-bit value which signals whether the interpolator has reached mute or not. When this bit is logic 0: interpolator is not muted. When this bit is logic 1: interpolator is muted. 1 MUTE_STATE_CH2 Interpolator muting channel 2.When this bit is logic 0: interpolator channel 2 is not muted. When this bit is logic 1: interpolator channel 2 is muted. 0 MUTE_STATE_CH1 Interpolator muting channel 1.When this bit is logic 0: interpolator channel 1 is not muted. When this bit is logic 1: interpolator channel 1 is muted. BIT 15 14 13 12 11 10 9 8 BIT 7 6 5 4 3 2 1 0 Symbol −−− AGC_STAT − MT_ADC_STAT − OVERFLOW BIT SYMBOL DESCRIPTION 15 to 5 − not used 4 AGC_STAT AGC gain status. A 1-bit value which signals whether the AGC gain exceeds 8 dB or not. Only valid when the AGC is switched on. When this bit is logic 0: AGC gain <8 dB. When this bit is logic 1: AGC gain≥8d B . 3 − not used 2 MT_ADC_STAT Decimator mute. A 1-bit value which signals whether the decimator has reached mute or not. When this bit is logic 0: decimator has not muted. When this bit is logic 1: decimator has muted. 1 − not used 0 OVERFLOW Digital output overﬂow detection. A 1-bit value which signals whether the digital output amplitude exceeds−1.16 dB or not. When this bit is logic 0: no overﬂow detected (read-out). When this bit is logic 1: overﬂow detected (read-out). BIT SYMBOL DESCRIPTION

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

12 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134). Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75µH series inductor. 4. DAC operation after short-circuiting cannot be warranted.

13 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is advised to take normal precautions appropriate to handling MOS devices.

14 THERMAL CHARACTERISTICS

15 QUALITY SPECIFICATION

“SNW-FQ-611D” . SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage note 1 − 4V Txtal(max) maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage note 2 −1100 +1100 V note 3 −250 +250 V Ilu(prot) latch-up protection current Tamb = 125°C; VDD = 3.6 V − 200 mA Isc(DAC) short-circuit current of DAC Tamb =0 °C; VDD = 3 V; note 4 output short-circuited to VSSA(DA) − 450 mA output short-circuited to VDDA(DA) − 325 mA SYMBOL PARAMETER CONDITIONS VALUE UNIT R th(j-a) thermal resistance from junction to ambient in free air 85 K/W

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

16 DC CHARACTERISTICS

VDDD =V DDA(AD) =V DDA(DA) =V DDA(HP) = 3.0 V; Tamb =2 5°C; RL =5k Ω ; all voltages measured with respect to ground; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies;note 1 VDDA(AD) ADC analog supply voltage 2.4 3.0 3.6 V VDDA(DA) DAC analog supply voltage 2.4 3.0 3.6 V VDDA(HP) headphone analog supply voltage 2.4 3.0 3.6 V VDDD digital supply voltage 2.4 3.0 3.6 V IDDA(AD) ADC analog supply current one ADC and microphone ampliﬁer enabled; fs = 48 kHz − 4.5 − mA two ADCs and PGA enabled; fs = 48 kHz − 7.0 − mA all ADCs and PGAs power-down, but AVC activated; fs = 48 kHz − 3.3 − mA all ADCs, PGAs and LNA power-down; fs =4 8k H z − 1.0 −µ A IDDA(DA) DAC analog supply current operating mode; fs = 48 kHz − 3.4 − mA Power-down mode; fs = 48 kHz − 0.1 −µ A IDDA(HP) headphone analog supply current no signal applied (quiescent current) − 0.9 − mA Power-down mode − 0.1 −µ A IDDD digital supply current operating mode; fs = 48 kHz − 10.0 − mA playback mode; fs =4 8k H z − 5.0 − mA record mode; fs = 48 kHz − 6.0 − mA Power-down mode; fs = 48 kHz − 1.0 −µ A IDD(tot) total supply current playback mode (without headphone); fs =4 8k H z − 9.0 − mA playback mode (with headphone); no signal; fs = 48 kHz − 8.8 − mA record mode (audio); fs = 48 kHz − 13.0 − mA record mode (speech); fs = 48 kHz − 10.0 − mA record mode (audio and speech); fs = 48 kHz − 13.0 − mA fully operating; fs = 48 kHz − 23.0 − mA signal mix-in operating, using FSDAC, AVC (with headphone); no signal; f s = 48 kHz − 12.0 − mA Power-down mode; fs = 48 kHz − 2.0 −µ A

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Notes 1. All supply connections must be made to the same power supply unit. 2. V DDA =V DDA(DA) =V DDA(AD) . 3. When higher capacitive loads must be driven, a 100Ω resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. Digital input pins (5 V tolerant TTL compatible) VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage −0.5 − +0.8 V ILI input leakage current −− 1 µA C i input capacitance −− 10 pF Digital output pins VOH HIGH-level output voltage IOH = −2 mA 0.85V DDD −− V VOL LOW-level output voltage IOL =2m A −− 0.4 V Reference voltage VREF reference voltage with respect to V SSA(AD) ; note 2 0.45V DDA 0.5VDDA 0.55VDDA V R o(VREF) output resistance on pin VREF − 12.5 − kΩ Analog-to-digital converter VADCP positive reference voltage of the ADC − VDDA(AD) − V VADCN negative reference voltage of the ADC − 0 − V R i input resistance − 12 − kΩ C i input capacitance − 24 − pF Digital-to-analog converter R L load resistance 3 −− kΩ C L load capacitance note 3 −− 50 pF Power consumption (supply voltage 3.0 V; fs = 48 kHz) Ptot total power dissipation playback mode (without headphone) − 27 − mW playback mode (with headphone)− 27 − mW record mode (audio) − 39 − mW record mode (speech) − 31 − mW record mode (audio and speech)− 40 − mW full operation − 69 − mW Power-down mode − 6 −µ W SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

17 AC CHARACTERISTICS

VDDD =V DDA(AD) =V DDA(DA) =V DDA(HP) = 3.0 V; fi= 1 kHz at−1 dB; Tamb =2 5°C; RL =5k Ω ; all voltages measured with respect to ground; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter D o digital output level 0 dB setting; V i(rms)= 1.0 V −− 1 − dBFS 3 dB setting; Vi(rms)= 708 mV −− 1 − dBFS 6 dB setting; Vi(rms)= 501 mV −− 1 − dBFS 9 dB setting; Vi(rms)= 354 mV −− 1 − dBFS 12 dB setting; Vi(rms)= 252 mV −− 1 − dBFS 15 dB setting; Vi(rms)= 178 mV −− 1 − dBFS 18 dB setting; Vi(rms)= 125 mV −− 1 − dBFS 21 dB setting; Vi(rms)=8 9m V −− 1 − dBFS 24 dB setting; Vi(rms)=6 3m V −− 1 − dBFS ΔVi unbalance between channels − <0.1 − dB (THD + N)/S48 total harmonic distortion-plus-noise to signal at f s = 48 kHz at−1 dBFS 0 dB setting −− 85 − dB 3 dB setting −− 85 − dB 6 dB setting −− 85 − dB 9 dB setting −− 85 − dB 12 dB setting −− 84 − dB 15 dB setting −− 83 − dB 18 dB setting −− 82 − dB 21 dB setting −− 80 − dB 24 dB setting −− 78 − dB at−60 dBFS; A-weighted 0 dB setting −− 37 − dB 3 dB setting −− 36 − dB 6 dB setting −− 36 − dB 9 dB setting −− 36 − dB 12 dB setting −− 35 − dB 15 dB setting −− 34 − dB 18 dB setting −− 33 − dB 21 dB setting −− 32 − dB 24 dB setting −− 30 − dB S/N48 signal-to-noise ratio at fs = 48 kHz Vi= 0 V; A-weighted − 97 − dB α cs channel separation − 100 − dB PSRR power supply rejection ratio f ripple= 1 kHz; Vripple= 30 mV (p-p) − 80 − dB

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 LNA input plus analog-to-digital converter Vi(rms) input voltage (RMS value) at 0 dBFS digital output; 2.2 kΩ source impedance −− 35 mV (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB −− 74 − dB at−60 dB; A-weighted −− 25 − dB S/N48 signal-to-noise ratio at fs = 48 kHz Vi= 0 V; A-weighted − 85 − dB α cs channel separation − 70 − dB Digital-to-analog converter Vo(rms) output voltage (RMS value) at 0 dBFS digital input; note 1− 0.9 − V ΔVo unbalance between channels − <0.1 − dB (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB −− 88 − dB at−60 dB; A-weighted −− 40 − dB (THD+N)/S96 total harmonic distortion-plus-noise to signal ratio at f s = 96 kHz at 0 dB −− 80 − dB at−60 dB; A-weighted −− 37 − dB S/N48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted − 100 − dB S/N96 signal-to-noise ratio at fs = 96 kHz code = 0; A-weighted − 97 − dB α cs channel separation − 90 − dB PSRR power supply rejection ratio f ripple= 1 kHz; Vripple= 30 mV (p-p) − 60 − dB Headphone driver Po(rms) output power (RMS value) at 0 dBFS digital input, assuming RL =1 6Ω − 35 − mW (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB; RL =1 6Ω− − 60 − dB at 0 dB; RL =5k Ω− − 82 − dB at−60 dB; A-weighted −− 24 − dB α cs channel separation R L =1 6Ω using pin VREF(HP) ; no DC decoupling capacitors; note 2 − 60 − dB R L =1 6Ω single-ended application with DC decoupling capacitors (100µF typical) − 68 − dB R L =3 2Ω single-ended application with DC decoupling capacitors (100µF typical) − 74 − dB S/N 48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted − 90 − dB SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Notes 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 2. Channel separation performance is measured at the IC pin. AVC (line input via ADC input, output on line output and headphone driver) V i(rms) input voltage (RMS value) − 150 − mV (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at f s = 48 kHz at 0 dB −− 80 − dB at−60 dB; A-weighted −− 28 − dB S/N48 signal-to-noise ratio at fs = 48 kHz Vi= 0 V; A-weighted − 87 − dB α cs channel separation − 82 − dB SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

18 TIMING

VDDD =V DDA(AD) =V DDA(DA) =V DDA(HP) = 2.7 to 3.6 V; Tamb = −20 to +85°C; all voltages referenced to ground; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing;note 1 Tsys system clock cycle time f sys = 256fs 35 81 250 ns fsys = 384fs 23 54 170 ns fsys = 512fs 17 41 130 ns fsys = 768fs 17 27 90 ns tCWL system clock LOW time f sys < 19.2 MHz 0.3T sys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4T sys − 0.6Tsys ns tCWH system clock HIGH time f sys < 19.2 MHz 0.3T sys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4T sys − 0.6Tsys ns Serial interface input/output data timing(see Fig.17) fBCK bit clock frequency −− 128fs Hz Tcy(BCK) bit clock cycle time −− 1⁄128Tcy(s)(2) s tBCKH bit clock HIGH time 30 −− ns tBCKL bit clock LOW time 30 −− ns tr rise time −− 20 ns tf fall time −− 20 ns tsu(WS) word select set-up time 10 −− ns th(WS) word select hold time 10 −− ns tsu(DATAI) data input set-up time 10 −− ns th(DATAI) data input hold time 10 −− ns th(DATAO) data output hold time 0 −− ns td(DATAO-BCK) data output to bit clock delay −− 30 ns td(DATAO-WS) data output to word select delay −− 30 ns L3-bus interface timing(see Figures 18 and 19) tr rise time note 3 −− 10 ns/V tf fall time note 3 −− 10 ns/V Tcy(CLK)L3 L3CLOCK cycle time note 4 500 −− ns tCLK(L3)H L3CLOCK HIGH time note 4 250 −− ns tCLK(L3)L L3CLOCK LOW time note 4 250 −− ns tsu(L3)A L3MODE set-up time in address mode 190 −− ns th(L3)A L3MODE hold time in address mode 190 −− ns tsu(L3)D L3MODE set-up time in data transfer mode 190 −− ns th(L3)D L3MODE hold time in data transfer mode 190 −− ns

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 Notes 1. The typical value of the timing is specified at 48 kHz sampling frequency (see Fig.16). 2. T cy(s) is the cycle time of the sample frequency. 3. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as short as possible. 4. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to1⁄64fs cycle. 5. C b is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. 6. After this period, the first clock pulse is generated. 7. To be suppressed by the input filter. t stp(L3) L3MODE stop time in data transfer mode 190 −− ns tsu(L3)DA L3DATA set-up time in address and data transfer mode 190 −− ns th(L3)DA L3DATA hold time in address and data transfer mode 30 −− ns tsu(L3)R L3DATA set-up time for read data 50 −− ns th(L3)R L3DATA hold time for read data 360 −− ns ten(L3)R L3DATA enable time for read data 380 −− ns tdis(L3)R L3DATA disable time for read data 50 −− ns I2C-bus interface timing;see Fig.20 fSCL SCL clock frequency 0 − 400 kHz tLOW SCL LOW time 1.3 −− µ s tHIGH SCL HIGH time 0.6 −− µ s tr rise time SDA and SCL note 5 20 + 0.1C b − 300 ns tf fall time SDA and SCL note 5 20 + 0.1C b − 300 ns tHD;STA hold time START condition note 6 0.6 −− µ s tSU;STA set-up time repeated START 0.6 −− µ s tSU;STO set-up time STOP condition 0.6 −− µ s tBUF bus free time between a STOP and START condition 1.3 −− µ s tSU;DAT data set-up time 100 −− ns tHD;DAT data hold time 0 −− µ s tSP pulse width of spikes note 7 0 − 50 ns C b capacitive load for each bus line −− 400 pF SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, full pagewidth MGR984 Tsys tCWH tCWL Fig.16 Timing of system clock. handbook, full pagewidth MGS756 WS BCK DATAO DATAI tftr th(WS) tsu(WS) tBCKH tBCKL Tcy(BCK) th(DATAO) tsu(DATAI) th(DATAI) td(DATAO-BCK) td(DATAO-WS) Fig.17 Serial interface input data timing.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, full pagewidth th(L3)A th(L3)DAtsu(L3)DA Tcy(CLK)(L3) BIT 0 L3MODE L3CLOCK L3DATA BIT 7 MGL723 tCLK(L3)H tCLK(L3)L tsu(L3)A tsu(L3)A th(L3)A Fig.18 Timing of address mode. handbook, full pagewidth tstp(L3) tsu(L3)D th(L3)DA ten(L3)R th(L3)R tsu(L3)DA th(L3)DTcy(CLK)L3 BIT 0 L3MODE L3CLOCK L3DATA read L3DATA write BIT 7 MGU015 tCLK(L3)H tCLK(L3)L tsu(L3)R tdis(L3)R Fig.19 Timing of data transfer mode for write and read.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, full pagewidth MBC611 P S Sr P tSU;STO t SPtHD;STA tSU;STAtSU;DAT tf tHIGH tr tHD;DAT tLOW tHD;STA tBUF SDA SCL Fig.20 Timing of the I2C-bus transfer.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

19 APPLICATION INFORMATION

handbook, full pagewidth MGU537 100 µF (16 V) 100 µF (16 V) VDDA VDDD BLM31A601S BLM31A601S +3 V ground 2 (30) VADCN UDA1380TT (UDA1380HN) 31 (27) (23) 27 VREF VREF(HP) VOUTRHP VOUTLHP VADCP VSSA(HP) 47 Ω 47 µF 18 (14) 17 (13) VINL VINR (21) 25 VOUTL 100 Ω 10 kΩ 0 Ω 16 (12) SYSCLK L3DATA/SDA L3CLOCK/SCL L3MODE 19 (15)SEL_L3_IIC 12 (8) 11 (7) 10 (6) DATAI WSI BCKI 15 (11)RTCB VDDA VDDA VDDD VDDA(HP) RESET 10 µF (16 V) 47 µF (16 V) 4.7 µF (16 V) 100 nF (63 V) (5) 9DATAO (4) 8WSO (3) 7BCKO (25) 29 (17) 21 0 Ω (19) 23 (18) 22 100 µF (16 V) 100 nF (63 V) 100 nF (63 V) 100 µF (16 V) 100 Ω 47 kΩ VDDA(AD) VDDDVSSA(AD) VSSD 1 Ω 100 µF (16 V) 100 nF (63 V) VDDA 10 Ω VDDD VDDA(DA)VSSA(DA) 26 (22)28 (24) 1 Ω 100 µF (16 V) 100 nF (63 V) VDDA left output VOUTR 100 Ω 10 kΩ 47 µF (16 V) right output headphone left input 13 (9) (16 V) 1 (29) 47 µF right input (16 V) VINM 3 (31) 47 µFmicro- phone input system clock (16 V) Fig.21 Application diagram. Pin numbers for UDA1380HN in parentheses.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

20 PACKAGE OUTLINES

UNIT A 1 A 2 A 3 bp cD (1) E(2) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.15 0.05 0.95 0.85 0.30 0.19 0.20 0.09 11.10 10.90 6.20 6.00 0.65 8.30 7.90 0.78 0.48 o o0.10 0.100.201.00 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT487-1 MO-153 97-06-11 99-12-27 w M bp D Z e 0.25 11 6 32 17 θ A A 1 A 2 Lp detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm SOT487-1 A max. 1.10 pin 1 index

2002 Sep 16 63

Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380 0.51.00 A 4 max. EhbUNIT ye REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 5.05 4.95 D h 3.25 2.95 5.05 4.95 3.25 2.95 3.5 3.50.35 0.180.80 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT617-1 MO-220 0.50 0.30 L 0.2 v 0.1 w 0 2.5 5 mm scale SOT617-1 HVQFN32: plastic, heatsink very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A max. A A4 detail X yy1 Ce L Eh D h e b 91 6 32 25 178 X D E C B A terminal 1 index area 01-06-07 01-08-08 pin 1 index 1/2 e 1/2 e AC C B∅ v M ∅ w M E (1) Note 1. Plastic or metal protrusions of 0.076 mm maximum per side are not included. D (1)

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

21 SOLDERING

21.1 Introduction to soldering surface mount

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.

21.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250°C. The top-surface temperature of the packages should preferable be kept below 220°C for thick/large packages, and below 235°C for small/thin packages.

21.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:

Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis ispreferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

21.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

21.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

For more detailed information on the BGA packages refer to the“(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. PACKAGE (1) SOLDERING METHOD WAVE REFLOW (2) BGA, LBGA, LFBGA, SQFP , TFBGA, VFBGA not suitable suitable HBCC, HBGA, HLQFP , HSQFP , HSOP , HTQFP , HTSSOP , HVQFN, HVSON, SMS not suitable(3) suitable PLCC (4), SO, SOJ suitable suitable LQFP , QFP , TQFP not recommended (4)(5) suitable SSOP , TSSOP , VSO not recommended (6) suitable

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

22 DATA SHEET STATUS

Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was DATA SHEET STATUS (1) PRODUCT STATUS (2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. Preliminary data Qualiﬁcation This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notiﬁcation (CPCN) procedure SNW-SQ-650A.

23 DEFINITIONS

Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

24 DISCLAIMERS

Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

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Philips Semiconductors Product speciﬁcation Stereo audio coder-decoder for MD, CD and MP3 UDA1380

25 PURCHASE OF PHILIPS I 2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

© Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Printed in The Netherlands 753503/02/pp68 Date of release:2002 Sep 16 Document order number: 9397 750 09937

Product Information

UDA1380 specifications and overview.

Summary

Stereo audio coder-decoder for MD, CD and MP3

Description

Stereo audio coder-decoder for MD, CD and MP3

Source title UDA1380 Datasheet(PDF) - Integrated Circuit Systems

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