ICS83026I-01 ICST | Alldatasheet

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www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS83026I-01 is a low skew, 1-to-2 Dif- ferential-to-LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The differential input can accept most dif- ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL out- puts. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.

FEATURES

  • Two LVCMOS / LVTTL outputs
  • Differential CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 350MHz
  • Output skew: 15ps (maximum)
  • Part-to-part skew: 600ps (maximum)
  • Additive phase jitter, RMS: 0.03ps (typical)
  • Small 8 lead SOIC package saves board space
  • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT ICS83026I-01 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View VDD CLK nCLK OE CLK nCLK OE HiPerClockS™ ICS VDDO GND ICS83026I-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VDD CLK nCLK OE VDDO GND

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. CONTROL FUNCTION TABLE

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V D D e g a tlo V ylp p u S e vitis o P V V O D D e g a tlo V ylp p u S t u p t u O V V V I D D t n e rr u C ylp p u S r e w o P A m I O D D t n e rr u C ylp p u S t u p t u O A m TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.375V TO 3.465V, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H I e g a tlo V h gi H t u p n I E O V D D V V L I e g a tlo V w o L t u p n I E O V I H I t n e rr u C h gi H t u p n I E O V D D V N I V A µ I L I t n e rr u C w o L t u p n I E O V D D V V N I V A µ V H O e g a tlo V h gi H t u p t u O E T O N V O D D V V V O D D V V V L O e g a tlo V w o L t u p t u O E T O N V h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t O D D n oitc e s n oit a m r o f n I t n e m e r u s a e M r e t e m a r a P e e S m a r g aid "tiu c ri C ts e T d a o L t u p t u O ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA

8 Lead SOIC

112.7°C/W (0 lfpm)

8 Lead TSSOP

101.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H I e g a tlo V h gi H t u p n I E O V D D V V L I e g a tlo V w o L t u p n I E O V I H I t n e rr u C h gi H t u p n I E O V D D V N I V A µ I L I t n e rr u C w o L t u p n I E O V D D V V N I V A µ V H O e g a tlo V h gi H t u p t u O I H O A µ V O D D V I H O A m V O D D V V L O e g a tlo V w o L t u p t u O I L O A µ V I L O A m V

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O z H M t D P E T O N ale D n oit a g a p o r P z H M s n t o k s E T O N w e k S t u p t u O s p t p p k s E T O N w e k S tr a P o t-tr a P s p t tij o t r e f e r S M R e ttiJ e s a h P e vitid d A r e ff u B n oitc e S r e ttiJ e s a h P e vitid d A s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O z H M z H M ≤ƒ≤ z H M z H M ≤ƒ≤ z H M V o t t nio p g nis s o r c t u p nilait n e r e ffid e h t m o rf d e r u s a e M E T O N O D D u p t u o e h t f o n oitid n o c d a olla u q e h ti w d n a e g a tlo v ylp p u s e m a s e h t t a st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e M O D D h ti w d n a s e g a tlo v ylp p u s e m a s e h t t a g nit a r e p o s e civ e d t n e r e ffid n o st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e m e r a st u p t u o e h t e civ e d h c a e n o st u p ni f o e p yt e m a s e h t g nis U n oitid n o c d a olla u q e O D D d r a d n a t S C E D E J h ti w e c n a d r o c c a ni d e nif e d si r e t e m a r a p sih T E T O N TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U I H I t n e rr u C h gi H t u p n I K L C n V N I V D D V A µ K L C V N I V D D V A µ I L I t n e rr u C w o L t u p n I K L C n V N I V V D D V A µ K L C V N I V V D D V A µ V P P E T O N e g a tlo V t u p n I k a e P o k a e P V V R M C E T O N e g a tlo V t u p n I e d o M n o m m o C D N G V D D V V E T O N P P V p e e k o tle v elt e sff o t n eiciff u s si e r e h t t a h t d e div o r p V d e e c x e n a c L I V s n oit a cilp p a d e d n e elg nis r o F E T O N V si K L C n K L C r o f e g a tlo v t u p ni m u m ix a m e h t D D V si e g a tlo v e d o m n o m m o C E T O N V s a d e nif e d H I .

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O z H M t D P E T O N ale D n oit a g a p o r P z H M s n t o k s E T O N w e k S t u p t u O s p t p p k s E T O N w e k S tr a P o t-tr a P s p t tij e ttiJ e s a h P e vitid d A r e ff u B e s a h P e vitid d A o t r e f e r S M R n oitc e S r e ttiJ s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O z H M z H M ≤ƒ≤ z H M z H M ≤ƒ≤ z H M V o t t nio p g nis s o r c t u p nilait n e r e ffid e h t m o rf d e r u s a e M E T O N O D D u p t u o e h t f o n oitid n o c d a olla u q e h ti w d n a e g a tlo v ylp p u s e m a s e h t t a st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e M O D D h ti w d n a s e g a tlo v ylp p u s e m a s e h t t a g nit a r e p o s e civ e d t n e r e ffid n o st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e m e r a st u p t u o e h t e civ e d h c a e n o st u p ni f o e p yt e m a s e h t g nis U n oitid n o c d a olla u q e O D D d r a d n a t S C E D E J h ti w e c n a d r o c c a ni d e nif e d si r e t e m a r a p sih T E T O N l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O z H M t D P E T O N ale D n oit a g a p o r P z H M s n t o k s E T O N w e k S t u p t u O s p t p p k s E T O N w e k S tr a P o t-tr a P s p t tij e ttiJ e s a h P e vitid d A r e ff u B e s a h P e vitid d A o t r e f e r S M R n oitc e S r e ttiJ s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O z H M z H M ≤ƒ≤ z H M z H M ≤ƒ≤ z H M V o t t nio p g nis s o r c t u p nilait n e r e ffid e h t m o rf d e r u s a e M E T O N O D D u p t u o e h t f o n oitid n o c d a olla u q e h ti w d n a e g a tlo v ylp p u s e m a s e h t t a st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e M O D D h ti w d n a s e g a tlo v ylp p u s e m a s e h t t a g nit a r e p o s e civ e d t n e r e ffid n o st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e m e r a st u p t u o e h t e civ e d h c a e n o st u p ni f o e p yt e m a s e h t g nis U n oitid n o c d a olla u q e O D D d r a d n a t S C E D E J h ti w e c n a d r o c c a ni d e nif e d si r e t e m a r a p sih T E T O N

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER Input/Output Additive Phase Jitter at 155.52MHz = 0.03ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10k 100k 10M 100M The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION SCOPE Qx LVCMOS 3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.4±0.125V VDDO -0.9V±0.45V VDD 0.9V±0.45V SCOPE Qx LVCMOS 3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±0.103V VDDO -1.25V±5% VDD 1.25V±5% 3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS 1.65V±5% -1.65V±5% DIFFERENTIAL INPUT LEVEL OUTPUT SKEW PART-TO-PART SKEW V CMR Cross Points V PP GND CLK nCLK VDD tsk(o) VDDO VDDO Qy Qx tsk(pp) VDDO VDDO Qy Qx PART 1 PART 2 VDD, VDDO GND GND GND

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PROPAGATION DELAY Q0, Q1 OUTPUT RISE/FALL TIME Clock Outputs 20% 80% 80% 20% tR tF OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD t PD VDDO CLK nCLK tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0, Q1

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 6A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-012 PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC L O B M Y S s r e t e m illi M M U M I N I M M U M I X A M N A A B C D E e C I S A B H h L α PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 6B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-153 L O B M Y S s r e t e m illi M m u m i n i M m u m i x a M N A A A b c D E C I S A B E e C I S A B L α a a a

TABLE 7. ORDERING INFORMATION for use in life support devices or critical medical instruments. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER T E E H S Y R O T S I H N O I S I V E R v e R e l b a T e g a P e g n a h C f o n o it p ir c s e D e t a D A T n e m n gis s A ni P o t e g a k c a p P O S S T d a e L d e d d A la m r e h T e g a k c a P o t P O S S T d a e L d e d d a s g nit a R m u m ix a M e t ulo s b A e c n a d e p m I elb a t n oit a m r o f n I ytilib aile R P O S S T d a e L d e d d A n ois n e m i D e g a k c a P d n a e nilt u O e g a k c a P P O S S T d a e L d e d d A n oit a m r o f ni g nir e d r o P O S S T d a e L d e d d a elb a T n oit a m r o f n I g nir e d r O A olp n o six a X d e tc e rr o c r e ttiJ e s a h P e vitid d A A C T L II d n a H II r o f s n oitid n o C ts e T d e tc e rr o c s citsir e tc a r a h C C D S O M C V L A T t ellu b e e rf- d a el d e d d a n oitc e S s e r u t a e F d e d d A ni P t u p t u O d e s u n U r o f s n oit a d n e m m o c e R e t o n d n a g nik r a m e b m u n tr a p e e rf- d a el d e d d a elb a T n oit a m r o f n I g nir e d r O