V104 ICST | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

  • Pin & function compatible with the THC63LVD104A
  • Wide pixel clock range: 8 - 90 MHz
  • Supports resolutions from 480p to WXGA
  • Internal PLL does not require external loop filter
  • Clock edge selection for TTL alignment selectable
  • Power down mode
  • Single 3.3V supply
  • Low power consumption CMOS design
  • 64-pin TQFP lead free package Block Diagram Serial to Parallel PLL CLKOUT TEST RA+/- RB+/- RC+/- RD+/- RE+/- RCLK+/- (8 to 90 MHz) PD OE R/F LVDS Input CMOS/TTL Input CMOS/TTL Output RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0

10 BIT LVDS RECEIVER FOR VIDEO

V104 Datasheet 2 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY Pin Assignment Pin Descriptions Pin Number Pin Name Pin Type Pin Description 50, 49 RA+, RA- LVDS IN LVDS Data In 52, 51 RB+, RB- LVDS IN LVDS Data In 55, 54 RC+, RC- LVDS IN LVDS Data In 60, 59 RD+, RD- LVDS IN LVDS Data In 62, 61 RE+, RE- LVDS IN LVDS Data In 57, 56 RCLK+, RCLK- LVDS IN LVDS Clock In 40, 41, 42, 43, 45, 46, 47 RA6 ~ RA0 OUT CMOS/TTL Data Outputs 32, 33, 34, 35, 36, 38, 39 RB6 ~ RB0 OUT CMOS/TTL Data Outputs 22, 24, 25, 26, 27, 28, 29 RC6 ~ RC0 OUT CMOS/TTL Data Outputs 14, 15, 17, 18, 19, 20, 21 RD6 ~ RD0 OUT CMOS/TTL Data Outputs GND TEST 64-pin TQFP PD OE RE6 RE5 RE4 R/F VCC RE3 RE2 RE1 RE0 RD6 RD5 GND RB5 RD4 RD3 RD2 RD1 RD0 RC6 VCC RC5 RC4 RC3 RC2 RC1 RC0 GND CLKOUT RB6 RB4 RB3 RB2 VCC RB1 RB0 RA6 RA5 RA4 RA3 GND RA2 RA1 RA0 VCC RA- RA+ RB- RB+ LVCC RC- RC+ RCLK- RCLK+ LGND RD- RD+ RE- RE+ PGND PVCC

V104 Datasheet 3 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY **Rxn x = A, B, C, D, E 6, 7, 8, 10, 11, 12, 13 RE6 ~ RE0 OUT CMOS/TTL Data Outputs. 2 TEST IN Not used. Tie LOW. 3 PD IN HIGH: normal operation; LOW: Power down (all outputs are “L”).

4 OE IN HIGH: Output enable (normal operat ion); LOW: Output disable (all outputs

are high impedance). 5 R/F IN Output Clock triggering edge select. High: Rising edge; Low: Falling edge. 9, 23, 37, 48 VCC Power Power supply pins for TTL outputs and digital circuitry. 31 CLKOUT OUT Clock out. 1, 16, 30, 44 GND Ground Ground pins for TTL outputs and digital circuitry. 53 LVCC Power Power supply pins for LVDS inputs. 58 LGND Ground Ground pins for LVDS inputs. 64 PVCC Power Power supply pin for PLL circuitry. 63 PGND Ground Ground pin for PLL circuitry. Pin Number Pin Name Pin Type Pin Description PD R/F OE Data Outputs (Rxn) CLKOUT 0 0 0 High impedance High impedance

001 A l l 0 F i x e d L o w

0 1 0 High impedance High impedance

011 A l l 0 F i x e d L o w

1 0 0 High impedance High impedance 1 0 1 Data Out Latches output data on falling edge 1 1 0 High impedance High impedance 1 1 1 Data Out Latches output data on rising edge

V104 Datasheet 4 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY External Components The V104 requires no external components. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V104. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VCC -0.3 V to +4.0 V CMOS/TTL Input Voltage -0.3 V to VCC+0.3 V CMOS/TTL Output Voltage -0.3 V to VCC+0.3 V LVDS Receiver Input Voltage -0.3 V to VCC+0.3 V Output Current -30 mA to 30 mA Storage Temperature -55 to +125 °C Junction Temperature 125 °C Soldering Temperature (10 seconds) 260 °C Maximum Power Dissipation @ +25°C 1.0 W Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 °C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V

V104 Datasheet 5 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY

Electrical Characteristics

VDD=3.3 V ±10%, Ambient temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units CMOS/TTL DC Specifications Input High Voltage V IH 2.00 VCC V Input Low Voltage V IL GND 0.80 V Output High Voltage V OH IOH = -4 mA (data) IOH = -8 mA (clock) 2.4 V Output Low Voltage V OL IOH = -4 mA (data) IOH = -8 mA (clock) 0.4 V Input Current I INC 0V<VIN<VCC ±10 µA LVDS Receiver DC Specifications Differential Input High Threshold V TH VOC = 1.2 V 100 mV Differential Input Low Threshold V TL VOC = 1.2 V -100 mV Input Current I INL VIN = 2.4 V / 0V VIN = 3.6 V ±20 µA Parameter Symbol Conditions Typ. Max. Units Supply Current Receiver Supply Current (Gray Scale Pattern) IRCCG fCLKOUT = 90 MHz C L=8 pF, VCC = 3.3 V 70 mA Receiver Supply Current (Checker Pattern) IRCCW fCLKOUT = 90 MHz C L=8 pF, VCC = 3.3 V 112 mA Receiver Power Down Supply Current I RCCS PD = L 10 µA

V104 Datasheet 6 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY Incremental Pattern (Gray Scale) Toggle Pattern (Checker) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X = A, B, C, D, E CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X = A, B, C, D, E

V104 Datasheet 7 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY Thermal Characteristics Parameter Symbol Min. Typ. Max. Units Switching Characteristics CLKOUT Period t RCP 11.1 T 125.0 ns CLK IN High Time t RCH (T-1)/2 ns CLK IN Low Time t RCL (T-1)/2 ns TTL Data Setup to CLKOUT t RS 4.5 ns TTL Data Hold from CLKOUT t RH 2.5 ns TTL Low to High Transition Time t TLH 1.0 2.0 ns TTL High to Low Transition Time t THL 1.0 2.0 ns Input Data Position0 t RIP1 -0.25 0.0 +0.25 ns Input Data Position1 t RIP0 ns Input Data Position2 t RIP6 ns Input Data Position3 t RIP5 ns Input Data Position4 t RIP4 ns Input Data Position5 t RIP3 ns Input Data Position6 t RIP2 ns Phase Lock Loop Set t RPLL 10.0 ms CLKIN Period t RCIP 11.1 125.0 ns Device-device data output skew 0 1.6 ns Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 53 °C/W θJA 1 m/s air flow 40 °C/W θJA 3 m/s air flow 33 °C/W Thermal Resistance Junction to Case θJC 8 °C/W -0.25tRCIP tRCIP +0.25tRCIP 2 -0.25tRCIP 7 2 tRCIP 7 2 +0.25tRCIP 3 -0.25tRCIP 7 3 tRCIP 7 3 +0.25tRCIP 4 -0.25tRCIP 7 4 tRCIP 7 4 +0.25tRCIP 5 -0.25tRCIP 7 5 tRCIP 7 5 +0.25tRCIP 6 -0.25tRCIP 7 6 tRCIP 7 6 +0.25tRCIP

V104 Datasheet 8 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY AC Timing Diagrams TTL Outputs CL = 8 pF TTL Output 20% 80% tTLH tTHL 20% 80% TTL Output Load CLK OUT 2.0 V Rxn x = A, B, C, D, E TTL Outputs 2.0 V 2.0 V 0.8 V 0.8 V 0.8 V0.8 V 2.0 V 2.0 V tRCP R/F = L R/F = H tRS tRH tRCH tRCL Phase Lock Loop Set Time VCC 3.0 V RCLK+/- CLKOUT PD tRPLL 2.0 V 2.0 V

V104 Datasheet 9 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY Min 100 µsec VCC/2 VCC/2VCC PVCC LVCC PD Recommended PD Pin Circuit VCC PD Pin 100 kohm 0.1 µF Power Up Sequence Sequence 1 Sequence 2 VCC PVCC LVCC PD GND VCC

3.0 V VCC

V104 Datasheet 10 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1Rx+/- RCLK+ tRCIP VDIFF = 0V V DIFF = 0V tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 x = A, B, C, D, E LVDS Inputs RE3' RE2' RE1' RE0' RE6 RE5 RE4 RE3 RE2 RE1 RE0 RE6" RA+/- RCLK+ (Differential VDIFF = 0V V DIFF = 0V tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 LVDS Inputs RD3' RD2' RD1' RD0' RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD6" RC3' RC2' RC1' RC0' RC6 RC5 RC4 RC3 RC2 RC1 RC0 RC6" RB3' RB2' RB1' RB0' RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB6" RA3' RA2' RA1' RA0' RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6" Previous Cycle Next Cycle Current Cycle RB+/- RC+/- RD+/- RE+/-

V104 Datasheet 11 1/12/05 Revision 1.6 Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com PRELIMINARY Package Outline and Package Dimensions (64-pin TQFP) Package dimensions are kept current with JEDEC Publication No. 95, variation ACD.

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature V104YLF V104YLF Tubes 64-pin TQFP 0 to +70 ° C V104YLFT V104YLF Tape and Reel 64-pin TQFP 0 to +70 ° C SYMBOL MIN/MAX N6 4 A -- / 1.20 A1 0.05 / 0.15 A2 0.95 / 1.05 b 0.17 / 0.27 c 0.09 / 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.50 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.50 Ref. e 0.50 BASIC L 0.45 / 0.75 θ 0° / 7° ccc -- / 0.08 D3&E3 - ALL DIMENSIONS ARE IN MILLIMETERS.