U4164A

U4164A KEYSIGHT | Alldatasheet

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with Options up to 4 Gb/s State Mode and 10 GHz Timing Mode Data Sheet

02 | Keysight | U4164A Logic Analyzer Module - Data Sheet Table of Contents

03 | Keysight | U4164A Logic Analyzer Module - Data Sheet The Keysight Technologies, Inc. U4164A logic analyzer system combines reliable data capture with powerful analysis and validation tools to enable you to quickly and confidently validate and debug high-speed digital designs operating at speeds up to 4 Gb/s. The U4164A logic analyzer module delivers the following unique capabilities that enable you to make measurements and achieve levels of insight unavailable with other logic analyzers: – Quad sample state mode provides four samples with two different threshold settings from a single-touch connection to high-speed data signals under test 1 – Dual sample, dual threshold state mode – Clock hysteresis allows the user to define a hysteresis range about the clock threshold – 10 GHz ¼ channel conventional and transitional timing mode 2 – Software tool for timing de-skew – 400 Mb (sample) memory depth option – Four speed options corresponding to the state clock rate, data rate, and timing mode sample rates

Applications

– Functional validation of memory systems and other high-speed digital systems operating up to 4 Gb/s – Debug of hardware and software in high-speed digital systems operating up to 4 Gb/s – Qualitative bus level signal integrity insight using eye scan or DDR eye scan

Features

– State capture up to 4 Gb/s on 68 channels, 2.5 Gb/s on 136 channels per module – Reliable data capture on eye openings as small as 100 ps by 100 mV – 12.5 GHz timing zoom with 256 K sample memory – Memory depth up to 400 M samples – Wide variety of probing solutions including BGA, interposer, mid-bus, and flying leads – Up to 10,880 channels in a system using Multiframe User values – C onfidence in state measurements with signal eye openings as small as 100 ps by 100 mV – R apidly view signal integrity information in a matter of minutes on all the buses in your design under a wide variety of operating conditions – Q uickly and easily set up complex DDR and LPDDR measurements – 3 50 MHz, 700 MHz, 1.4 GHz, and 2.5 GHz state speed options: Purchase the level of state speed capture capability you need now and upgrade as your state speed needs increase. The U4164A with the 2.5 GHz state speed option allows you to capture the highest speeds (up to 4 Gb/s) for DDR/LPDDR memory systems – Dual-sample state mode: set separate sample positions and thresholds for DDR/LPDDR read/write captures for data rates less than 2500 Mb/s from one probe point – Quad-sample state mode: set separate sample positions and thresholds for DDR/LPDDR read/write and rising/falling edge captures for data rates greater than 2500 Mb/s from one probe point – C lock hysteresis: avoid false sampling on noisy clock inputs when differential clocks turn off – 1 0 GHz quarter channel conventional and transitional timing mode: Identify timing problems in deep traces with high sample resolution – 4 00 Mb (sample) memory depth option: Capture more system activity so you can debug complex problems when the symptom and root cause are widely separated in time 1. Available in Option -02G 2. Available in Options -01G and -02G Product Description

06 | Keysight | U4164A Logic Analyzer Module - Data Sheet Product Description (Continued) Figure 1E. DDR4 3300 Mb/s state waveform. Figure 1D. DDR4 3300 Mb/s state waveform. There are two methods to capture DDR or LPDDR memory DQ (data) transactions over

2500 Mb/s using the U4164A logic analyzer system:

1. Using quad-sample state mode, the U4164A is sampled on one clock edge, a single probe load is placed on each DQ, and quad-sample mode is used to provide separate read rising, read falling, write rising, and write falling edge captures with sample positions set independently. Read and write thresholds can be set independently. Read rising, read falling, write rising, and write falling edge captures are given different labels in the configuration so that the sample positions can be set independently. 2. Using dual-sample state mode, the U4164A is sampled on one clock edge, double probing of each DQ must be performed and provide separate read DQ and write DQ samples, and dual-sample mode is used to provide a rising and falling edge sample for each DQ, resulting in four samples taken for each DQ signal from two probe loads. Read rising, read falling, write rising, and write falling edge captures are given different labels so the sample positions can be set independently.

07 | Keysight | U4164A Logic Analyzer Module - Data Sheet Dual-sample mode has multiple benefits: 1. For non-DDR or LPDDR memory trace capture, dual-sample state mode allows acquisition of state (synchronous) data at rates up to 4 Gb/s depending on the speed state option purchased. When used in this mode, the data will appear in two labels. One label for rising edge and another for falling edge captures. The logic analyzer will be clocked with one edge of the system clock. Labels can be merged using the Keysight B4602A signal extractor tool. When operated in dual-sample state mode on all pods, the channel count is 68 channels for one U4164A 136 channels for two U4164As, or 204 channels for three U4164A modules combined. Dual-sample state mode can be selected on a per-pod-pair basis, so if you have only a subset of signals that require dual-sample mode, the channel count can be higher. 2. For DDR/LPDDR memory signals up to 2.5 Gb/s, dual-sample state mode allows separation of read data samples from write data samples. The B4661A DDR2/3/4 decoder or the B4661A LPDDR/2/3/4 decoder reassembles the data to align with the associated commands. (There’s no need for the B4602A tool for DDR and LPDDR solutions.) 3. For DDR4 and LPDDR4 memory solutions over 2.5 Gb/s using dual-sample state mode, double probing is required to capture read and write DQ signals and dual-sample state mode is used to capture rising and falling edge DQ samples. Using this technique, a maximum of 34 DDR4 or LPDDR4 DQ signals operating over 2.5 Gb/s can be captured per U4164A module. Address, command, and control signals for DDR or LPDDR memory do not require double probing above or below 2.5 Gb/s data rates, so modules with a mixture of address, command and DQ signals may have higher signal count depending on how the signals are routed into the U4164A. Quad-Sample State Mode Quad-sample state mode enables four samples with two different threshold settings from a single-touch connection to high-speed data signals under test. This results in four unique sample positions at two unique thresholds. Single-touch connection preserves probe routing space and minimized probe load on high-speed digital systems. DDR4 and LPDDR4 probing for data rates over 2.5 Gb/s are examples of where single-touch probing enables high-speed trace capture using quad-sample mode to capture read and write DQ (data) at different thresholds with rising and falling edge samples for both read and write data to sample, trigger, and display DDR4 and LPDDR4 at data rates up to 4 Gb/s. When operated in quad-sample state mode on all pods, the channel count is 34 channels for one U4164A, 68 channels for two U4164As, or 102 channels for three U4164A modules combined. Quad-sample state mode is only available with U4164A Option -02G. Quad-sample state mode can be selected on a per-pod-pair basis, so if you have only a subset of signals that require quad-sample mode, the channel count can be higher. Dual-Sample State Mode

inactive. In state mode, the U4164A allows one clock input into pod 1 of the clocking module. 7 is available as an “AND” input only when the other clock qualifiers are setup as “OR” inputs. qualifiers are looking for clock enable (CKE) signals on DDR and LPDDR buses. captures from systems where a differential clock input turns off and floats to zero volts. millivolts around threshold between 0 and 1 volts. Figure 2. Clock hysteresis selection and setting in clock thresholds window. The settings shown were used to capture an LPDDR4 system initializing without the use of any clock qualifiers.

Figure 3. Timing zoom can be used to measure the time between the rising edge of the clock and the rising edge of DQS in a DDR system. timing measurements with conventional and transitional timing modes of operation.

conserving logic analyzer memory depth. Figure 4. Mode register trigger allows you to capture key events during initialization without wasting

Figure 5. DDR setup assistant, with 10 simple steps, simplifies the setup of state mode measurements.

sequential patterns at up to 4 Gb/s data rates from any high-speed digital system. the process of creating triggers. Figure 6. Burse recognizer trigger makes it easy to trigger on events in a burst read or write.

Figure 8. Eye scan clearly indicates the DDR3 byte lane shift caused by fly-by routing.

Figure 9. DQS0, DQ6 and CK0 from a DDR4 system probed by an Infiniium scope and displayed in the logic analyzer waveform using View Scope. configurations on the logic analyzer.

16 | Keysight | U4164A Logic Analyzer Module - Data Sheet State modes (synchronous) Conventional and transitional timing modes (asynchronous) Timing zoom Memory depth (samples) Conventional and dual-sample (all state speed options); Quad-sample (available with Option 02G only) Full channel Half channel Quarter channel (requires Option 01G or 02G) All options Standard (base) memory 2 M 2 M 4 M 8 M 256 K U4164A-004 4 M 4 M 8 M 16 M 256 K U4164A-008 8 M 8 M 16 M 32 M 256 K U4164A-016 16 M 16 M 32 M 64 M 256 K U4164A-032 32 M 32 M 64 M 128 M 256 K U4164A-064 64 M 64 M 128 M 200 M 256 K U4164A-128 128 M 128 M 200 M 400 M 256 K U4164A-200 200 M 200 M 400 M 800 M 256 K U4164A-400 400 M 400 M 800 M 1.6 G 256 K Contact Keysight Technologies for information on additional configurations. Note: Memory can be upgraded after purchase. See “Upgrades” in “Ordering Information.” 1. Defined for general purpose use models. For DDR/LPDDR memory applications, either dual-sample or quad-sample modes are used for read/write separation. Quad-sample mode is used to capture rising and falling edge samples of both read and write DDR/LPDDR DQ signals for data rates up to 4 Gb/s from a single probe point. Dual-sample mode is used to capture read and write data instead of higher data rates. Using dual sample mode instead of quad sample mode requires, double probing of DDR/LPDDR data (DQ) to capture data rates over 2.5 Gb/s. Timing operating modes Conventional or transitional timing Full channel Half channel Quarter channel Option -02G / -01G All channels Maximum acquisition rate 2.5 GHz 5 GHz 10 GHz 12.5 GHz Number of available channels in one module 136 68 34 136 Number of available channels in a two module set 272 136 68 272 Number of available channels in a three module set 408 204 102 408 Operating Modes 1 State operating modes Conventional state sampling on both edges of the clock (synchronous) Dual sample state sampling on one clock edge and using dual sample mode to capture rising and falling edge samples (synchronous) Quad sample state sampling on one clock edge and using quad sample mode to capture rising and falling edge samples of both read and write DQ (data bits) on DDR4 or LPDDR4 (synchronous) Option -02G Option -01G Option -700

350 MHz

(standard) Option -02G Option -01G Option -700 (standard) Option -02G Maximum acquisition rate Number of available channels in one module 136 136 136 136 68 68 68 68 34 Number of available channels in a two module set 272 272 272 272 136 136 136 136 68 Number of available channels in a three module set 408 408 408 408 204 204 204 204 102

17 | Keysight | U4164A Logic Analyzer Module - Data Sheet When you need more channels or more functions Multiframe allows you to combine 16 AXIe chassis. 1 One or more Y1223A Multiframe cables to connect multiple frames. Order one fewer Y1223A cables than the total number of frames/chassis to be combined. 1. One PC host is recommended for each AXIe chassis. Optional Software B4661A memory analysis software The Keysight B4661A memory analysis software offers a suite of tools that include the industry’s first protocol compliance violation testing capability across speed changes, a condensed traffic overview for rapid navigation to areas of interest in the logic analyzer trace, powerful performance analysis graphics, and DDR and LPDDR decoders. With the B4661A memory analysis software and a Keysight logic analyzer, users can monitor DDR3/4 or LPDDR2/3/4 systems to debug, improve performance, and validate protocol compliance. Powerful traffic overviews, multiple viewing choices, and real-time compliance violation triggering help identify elusive DDR/LPDDR system violations. The Keysight B4661A memory analysis software provides four standard software features and four licensed memory analysis options. B4661A standard software features – D efault configurations for DDR and LPDDR probing solutions for Keysight logic analyzers – D DR setup assistant – D DR eye finder/eye scan – D DR configuration creator B4661A licensed software options – D DR decoder with physical address trigger tool (B4661A-1xx) – L PDDR decoder (B4661A-2xx) – D DR and LPDDR compliance violation analysis (B4661A-3xx) – Post-process compliance violation analysis real-time compliance violation analysis – DDR3/4 and LPDDR2/3/4 performance analysis (B4661A-4xx) Optional Hardware

Figure 12. The post-process compliance tool includes hyperlinks to quickly jump to and/or mark violations and worst-case violations in the logic analyzer traces, transaction overview, and listing windows.

20 | Keysight | U4164A Logic Analyzer Module - Data Sheet Direct connect probes – Probes that connect directly between a connector or footprint on the device under test and the front panel connector of the logic analyzer. Probe type Model number Channels Maximum data rate Supported signal types Comments Connectorless, Soft Touch Pro U4206A 34 4 Gb/s Single-ended data, Differential or single-ended clock Compatible with the U4164A only. Requires one U4206A per U4164A module. Use only for U4164A quad-sample state or quarter channel timing modes. Refer to U4206A user guide for example that allows for mixed modes of operation (e.g. quad-sample is selectable by pod pair) Connectorless, Soft Touch Pro U4204A 34 4 Gb/s Differential or single-ended data, Differential or single-ended clock Flying lead U4203A 34 1.5 Gb/s Single-ended data, Differential or single-ended clock Mictor U4205A 34 600 Mb/s Single-ended data, Single-ended clock Probe/Cables As Required to Connect to the Target System Model number Description Maximum data rate Comments U4208A Probe/cable, 61-pin ZIF, left wing, no RC, 160-pin direct connect to U4164A 3.2 Gb/s typical Compatible with the U4164A only. For use with W4631A or W4636A DDR4 BGA interposers that include RC network to provide proper signal termination to the logic analyzer. Uses quad-sample state mode to capture DQ signals. U4209A Probe/cable, 61-pin ZIF, right wing, no RC, 160-pin direct connect to U4164A 3.2 Gb/s typical Compatible with the U4164A only. For use with W4631A or W4636A DDR4 BGA interposers. Includes RC network to provide proper signal termination to the logic analyzer. Uses quad-sample state mode to capture DQ signals.

21 | Keysight | U4164A Logic Analyzer Module - Data Sheet General purpose probes as required to connect to the target system. (Probes in this chart require U4201A cables.) Probe type Model number Channels Maximum data rate Supported signal types Number of U4201A required per probe Soft Touch Connectorless Pro Series E5406A 34 (32 data, 2 clock) 4 Gb/s Single-ended data, differential or single-ended clock 1 for each E5406A Soft Touch Connectorless Low Profile E5402A 34 (32 data, 2 clock) 4 Gb/s Single-ended data, differential or single-ended clock 1 for each E5402A Soft Touch Connectorless Classic E5390A 34 (32 data, 2 clock) 4 Gb/s Single-ended data, differential or single-ended clock 1 for each E5390A Soft Touch Connectorless Half-size E5398A 17 (16 data, 1 clock) 4 Gb/s Single-ended data, differential or single-ended clock 1 for every E5398A Soft Touch Connectorless Pro Series E5405B 17 (16 data, 1 clock) 4 Gb/s Differential or single-ended data, differential or single-ended clock 1 for every 2 E5405B Samtec connector E5378A 34 (32 data, 2 clock) 1.5 Gb/s Single-ended data, differential or single-ended clock 1 for each E5378A Samtec connector E5379A 17 (16 data, 1 clock) 1.5 Gb/s Differential or single-ended data, differential or single-ended clock 1 for every 2 E5379A Mictor connector E5380B 34 (32 data, 2 clock) 600 Mb/s Single-ended data, differential or single-ended clock 1 for each E5380B General purpose flying leads E5382B 17 (16 data, 1 clock) 1.5 Gb/s Single-ended data, differential or single-ended clock 1 for every 2 E5382B General purpose flying leads E5381B 17 (16 data, 1 clock) 1.5 Gb/s Differential or single-ended data, differential or single-ended clock 1 for every 2 E5381B Recommended probes for DDR and LPDDR memory include BGA probes, interposers, and Soft Touch mid-bus probes. Interposers are available from FuturePlus Systems or through Keysight. Refer to “Ordering Information.” Information on FuturePlus interposers http://www.futureplus.com/DDR3-Memory/keysight-la-support-overview.html . For additional DDR/2/3/4 and LPDDR/2/3/4 probing options, contact your local Keysight representative www.keysight.com/find/contactus . Probe/Cables As Required to Connect to the Target System (Continued)

22 | Keysight | U4164A Logic Analyzer Module - Data Sheet U4164A State Speed Option Requirements for DDR/LPDDR Data Rates For capture of DDR/LPDDR memory ADD/CMD/DATA DDR/LPDDR data rates Base state clock rate: 350 MHz clock 1 Option 700:

700 MHz

Option 01G:

1.4 GHz clock 1

Option 02G:

2.5 GHz clock

DDR or LPDDR ≤ 700 Mb/s √ √ √ √ DDR3 ≤ 1400 Mb/s √ √ √ ≤ 2500 Mb/s √ √ > 2500 Mb/s √ DDR4 ≤ 2500 Mb/s √ √ > 2500 Mb/s √ LPDDR2 ≤ 1400 Mb/s √ √ √ LPDDR3 ≤ 1400 Mb/s √ √ √ ≤ 2500 Mb/s √ √ LPDDR4 ≤ 2500 Mb/s √ √ > 2500 Mb/s √ 1. Requires dual sample state mode for simultaneous read/write data capture. 2. Requires dual sample state or quad sample mode for simultaneous read/write data capture. Dual sample state mode requires double probing of DQ over 2.5 Gb/s. Quad-sample state mode operates from a single probe load. U4164A Requires – Chassis and host PC – Cables and/or probing to connect to the DUT – Version 6.20 or higher of the logic and protocol analyzer software – Host PC running compatible 64-bit OS (refer to logic and protocol analyzer software download site for latest supported operating systems) U4164A Includes – Qty (1) U4164A logic analyzer module – Qty (2) U4154-61602 flex cables for connecting multiple U4164A modules into module sets

23 | Keysight | U4164A Logic Analyzer Module - Data Sheet Module quantity considerations The following table provides examples of general guidelines for the number of U4164A modules required for a few example applications. Refer to the requirements of your specific devices, interposers and probes to determine the requirements for your application. Minimum Hardware DUT configuration U4164A module requirements General purpose measurement requiring a given number of channels on a single time base Each U4164A has 136 channels. A maximum of three U4164As can be combined for 408 channels DDR4 DIMM Interposer, > 2.5 Gb/s data rates, capture all ADD/CMD/data Three U4164A modules, each with Option 02G DDR2/3/4, 64-bit data, ≤ 2.5 Gb/s data rates, capture all ADD/CMD/data (read and write) Two U4164A modules, each with Option 01G LPDDR1/2/3/4, ≤ 2.5 Gb/s data rates One U4164A module LPDDR4, > 2.5 Gb/s data rates May require up to three U4164A modules (depends on the number of data signals probed and the probing layout) 1. To determine the number of channels, and therefore the number of modules, required for a DDR/LPDDR memory system operating at > 2.5 Gb/s, allocate four U4164A channels for each DDR/LPDDR memory DQ captured. Chassis and controller considerations M9536A embedded AXIe controller M9045B PCIe ExpressCard M9048B PCIe adapter Laptop PC Desktop or rack mount PC Y1200B: x1 to x8 PCIe cables Y1202A: x8 PCIe cables Figure 13.

the FuturePlus FS2510AB DDR4 DIMM interposer, do not require additional U4201A cables. Figure 14. Typical configuration for DDR4 DIMM debug and validation for data rates greater 2500 Mb/s. Note: M9536A controller, if used, must be installed in slot 1.

25 | Keysight | U4164A Logic Analyzer Module - Data Sheet Typical Configurations (Continued) Figure 15. Typical DDR4 BGA interposer configuration for data rates up to 3.2 Gb/s.

1. Using dual sample mode for simultaneous read/write data capture.

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26 | Keysight | U4164A Logic Analyzer Module - Data Sheet All specifications refer to the combination of a U4164A logic analyzer module, U4201A logic analyzer probe cable, and any Keysight Soft Touch probe. Probe variations will influence results. State (Synchronous) sampling mode Maximum state data rate Option 02G, 2.5 GHz state mode (spec) 2.5 Gb/s on 136 channels per U4164A, using either or both edges of clock (spec)

4 Gb/s on 68 channels per U4164A, clocking on either edge of the clock (typ)

Maximum state data rate -01G 1.4 GHz state mode (spec) 2.5 Gb/s on 136 channels per U4164A, using both edges of clock (spec)

2.8 Gb/s on 68 channels per U4164A, clocking on either edge of the clock (typ)

Maximum state data rate Option -700 1.4 Gb/s on 136 channels using both edges of clock (spec) Maximum state data rate 350 MHz standard (base) 700 Mb/s on 136 channels using both edges of clock (spec) Maximum state clock frequency (typ) 2.5 GHz Option -02G

1.4 GHz Option -01G

700 MHz Option -700

350 MHz standard (base)

Minimum state clock frequency 1 (typ) 12.5 MHz (single edge)

6.25 MHz (both edges)

Sample position adjustment resolution (typ) 5 ps or 20 ps Sample position adjustment accuracy (typ) ± 150 ps Minimum data valid window (typ) 100 ps Minimum setup time (typ) 50 ps Minimum hold time (typ) 50 ps Minimum eye height (typ) 100 mV Sample position adjustment range (typ) 7 ns Minimum state clock pulse width (typ) 200 ps Number of clocks (nom) 1 Minimum time between active clock edges (typ) 400 ps Maximum time between active clock edges 1 (typ) 80 ns Number of clock qualifiers 4 (pods 2, 3, 4, and 5 on clocking module) Clock qualifier setup time 150 ps Clock qualifier hold time 150 ps Number of “RESET” clock qualifiers 1 (pod 7 of clocking module) “RESET” clock qualifier setup time 2 ns “RESET” clock qualifier hold time 0 ps Time tag resolution (typ) 80 ps Maximum time count between stored states (typ) 66 days 1. Clock can pause for up to 66 days once every 8 or more edges. Technical Specifications and Characteristics

27 | Keysight | U4164A Logic Analyzer Module - Data Sheet Timing (Asynchronous) sampling mode Full-channel mode Half-channel mode Quarter-channel mode Maximum time between transitions (nom) 66 days Minimum data pulse width (typ) 1 sample period + 200 ps Time interval accuracy (typ) ± (1 sample period + 400 ps + 0.01% of time interval reading) Maximum sample rate (nom) 2.5 GHz 5 GHz 10 GHz Minimum sample period (nom) 400 ps 200 ps 100 ps Pod usage (nom) 1 pod from each All pods Odd from each odd/even pod pair Even signal inputs (0, 2, 4, 6, 8) from odd pod of each odd/ even pair plus clock input Timing Zoom (Asynchronous) sampling mode Timing Zoom sampling rate (nom) 12.5 GHz Timing Zoom memory depth (nom) 256 K samples Trigger characteristics Maximum trigger sequence speed (typ) 2500 MHz (400 ps) Option -02G

1400 MHz (714 ps) Option -01G

700 MHz (1.428 ns) Option -700 350 MHz (2.856 ns) standard (base) module Trigger resources (nom) 16 patterns evaluated as =, ! =, >, > =, <, < = 8 double-bounded ranges evaluated as in range, not in range 4 to 8 burst detectors 4 edge detectors in timing, 3 in transitional timing 1 occurrence counter persequence level 1 timer 3 flags 1 arm in Trigger resource Boolean conditions (nom) Arbitrary Boolean combinations Trigger actions (nom) Goto Trigger and fill memory Trigger and Goto Trigger, send e-mail, and fill memory Store qualification actions (nom) Default (global) and per sequence level Store/don’t store sample Turn on/off default storing Timer actions Start from reset Stop and reset Pause Resume Flag actions Set Clear Pulse set Pulse clear Technical Specifications and Characteristics (Continued)

28 | Keysight | U4164A Logic Analyzer Module - Data Sheet Trigger characteristics (Continued) Maximum trigger sequence levels (nom) 8 Trigger sequence level branching (nom) Arbitrary 4-way if/then/else Trigger position (nom) Start, center, end, or user-defined Maximum occurrence counter (nom) 999,999,999 Maximum pattern width (nom) 128 bits – single label 408 bits – AND of multiple labels across three-card set Maximum range width (nom) 64 bits Timer range (nom) 100 ns to 27 hours (in timing modes) 200 * state clock period to 27 hours (in state mode) Timer resolution (nom) 5 ns Timer accuracy (typ) ± (5 ns + 0.01%) (in timing modes) ± (8 * state clock period + 2 ns + 0.01%) (in state mode) Timer reset latency (nom) 40 ns (in timing modes) 80 * state clock period (in state mode) General Number of channels (nom) 136 in one U4164A 272 in two U4164As combined 408 with three U4164A combined Maximum channels on a single time base and trigger (nom) 408 Number of analyzers (nom) 1 Input signal amplitude V amptd (typ) ≥ 350 mV Supported signal types Single-ended and differential Voltage threshold (typ) –5 to +5 V –4 to +4 V when in dual sample or quad sample state modes Minimum threshold resolution (typ) 2 mV Threshold accuracy (typ) ± (30 mV + 1% of setting) Threshold setting granularity By channel Technical Specifications and Characteristics (Continued)

29 | Keysight | U4164A Logic Analyzer Module - Data Sheet Operating environment Temperature (nom) 0 to +40 °C Humidity (nom) 0 to 80% relative humidity at 40 °C Altitude 0 to 3000 m Vibration Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 0.2 g rms Non-operating environment Temperature (nom) –40 to +75 °C Humidity (nom) 0 to 90% relative humidity at 65 °C Altitude 0 to 15,300 m Vibration (in shipping carton) Random vibration 5 to 500 Hz 10 minutes per axis Approximately 2.41 Swept sine resonant search 5 to 500 Hz 0.50 g (0-peak) 5 minute resonant dwell at 4 resonances per axis Weight 2.34 kg Environmental and Physical Definitions for specifications Specification (spec): Represents warranted performance of a calibrated instrument that has been stored for a minimum of 2 hours within the operating temperature range of 0 to 40 °C, unless otherwise stated, and after a 45 minute warm-up period. The specifications include measurement uncertainty. Data represented in this document are specifications unless otherwise noted. Typical (typ): Represents characteristic performance, which 80% of the instruments manufactured will meet. This data is not warranted, does not include measurement uncertainty, and is valid only at room temperature (approximately 25 °C). Nominal (nom): The expected mean or average performance, or an attribute whose performance is by design, such as the 50 Ω connector. This data is not warranted and is measured at room temperature (approximately 25 °C). Measured (meas): An attribute measured during the design phase for purposes of communicating expected performance, such as amplitude drift vs. time. This data is not warranted and is measured at room temperature (approximately 25 °C).

30 | Keysight | U4164A Logic Analyzer Module - Data Sheet Ordering Model Description U4164A Logic analyzer module, 136 ch, 12.5 GHz TZ, 5 GHz timing, 350 MHz base state speed, 2 Mb (memory depth in samples) U4164A-A6J ANSI Z540-1-1994 calibration State and timing speed options U4164A-700 Increase maximum state speed to 700 MHz U4164A-01G Increase maximum speeds: state to 2.8 Gb/s (1.4 GHz) and timing to 10 GHz U4164A-02G Increase maximum speeds: state to 4 Gb/s (2.5 GHz) and timing to 10 GHz Memory depth options U4164A-004 Increase acquisition memory depth to 4 Mb U4164A-008 Increase acquisition memory depth to 8 Mb U4164A-016 Increase acquisition memory depth to 16 Mb U4164A-032 Increase acquisition memory depth to 32 Mb U4164A-064 Increase acquisition memory depth to 64 Mb U4164A-128 Increase acquisition memory depth to 128 Mb U4164A-200 Increase acquisition memory depth to 200 Mb U4164A-400 Increase acquisition memory depth to 400 Mb Cables, chassis, and embedded controller U4201A Logic analyzer cable for connecting U4161A to 90-pin E53xx and E54xx Series probes N2815A MSO/logic analyzer cable for connecting U4164A to 90-pin logic analyzer probes. (Connects even and/or odd headers of E53xx and E54xx Series 90-pin probes into odd pod of U4164A pod pair only. Useful for dual-sample state mode, not for full-channel mode) M9502A AXIe 2-slot chassis M9505A AXIe 5-slot chassis Y1223A Multiframe cable M9536A AXIe embedded PC controller M9536A-M16 Memory upgrade from 8 GB to 16 GB RAM Upgrades for U4164A logic analyzer modules (after purchase) U4164A state and timing speed upgrades U4164AU-700 Increase maximum state speed to 700 MHz U4164AU-01G Increase maximum speeds: state to 2.8 Gb/s (1.4 GHz) and timing to 10 GHz U4164AU-02G Increase maximum speeds: state to 4 Gb/s (2.5 GHz) and timing to 10 GHz U4164A memory depth upgrades U4164AU-004 Increase acquisition memory depth to 4 Mb U4164AU-008 Increase acquisition memory depth to 8 Mb U4164AU-016 Increase acquisition memory depth to 16 Mb U4164AU-032 Increase acquisition memory depth to 32 Mb U4164AU-064 Increase acquisition memory depth to 64 Mb U4164AU-128 Increase acquisition memory depth to 128 Mb U4164AU-200 Increase acquisition memory depth to 200 Mb U4164AU-400 Increase acquisition memory depth to 400 Mb

31 | Keysight | U4164A Logic Analyzer Module - Data Sheet Ordering (Continued) Optional software B4661A Memory analysis software for logic analyzers. Standard features for DDR/LPDDR include default configurations, Setup Assistant, Configuration Creator, and Eye Finder and Eye Scan. Fixed perpetual licenses B4661A-1FP DDR decoder with physical address trigger tool, fixed perpetual license B4661A-2FP LPDDR decoder, fixed perpetual license B4661A-3FP DDR and LPDDR compliance violation analysis, fixed perpetual license B4661A-4FP DDR3/4 and LPDDR2/3/4 performance analysis, fixed perpetual license Transportable perpetual licenses B4661A-1TP DDR decoder with physical address trigger tool, transportable perpetual license B4661A-2TP LPDDR decoder, transportable perpetual license B4661A-3TP DDR and LPDDR compliance violation analysis, transportable perpetual license B4661A-4TP DDR3/4 and LPDDR2/3/4 performance analysis, transportable perpetual license Floating/server perpetual licenses B4661A-1NP DDR decoder with physical address trigger tool, network/floating perpetual license B4661A-2NP LPDDR decoder, network/floating perpetual license B4661A-3NP DDR and LPDDR compliance violation analysis, network/floating perpetual license B4661A-4NP DDR3/4 LPDDR2/3/4 performance analysis, network/floating perpetual license Other software B4601A Data import tool B4601C Signal-to-parallel analysis pacakage B4602A Signal extractor tool B4655A FPGA dynamic probe for Xilinx B4656A FPGA dynamic probe for Altera Probes and interposers Direct connect probes U4203A Single-ended 34-channel flying lead U4204A Soft Touch Pro Series single-ended 34-channel data, differential clock connectorless probe U4205A Single-ended 34-channel Mictor connector probe U4206A 34-channel, Soft Touch Pro, single-ended, quad x 160-pin direct connect

32 | Keysight | U4164A Logic Analyzer Module - Data Sheet Ordering (Continued) General purpose probes (require U4201A cables) E5405B Pro Series soft touch connectorless probe - differential, for 90-pin cable (17 channels) E5406A Pro Series soft touch connectorless probe - single-ended, for 90-pin cable (34 channels) E5402A Low profile, Pro Series soft touch connectorless probe - single-ended, for 90-pin cable E5390A Soft touch connectorless probe-single-ended, with 90-pin cable connectors E5398A Half-size soft touch connectorless probe with 90-pin cable connectors E5381B Differential flying leads, 17 channels E5382B Single-ended flying leads, 17 channels E5378A Samtec probe-single-ended, with 90-pin cable connectors E5379A Samtec probe-differential, with 90-pin cable connectors E5380B Mictor probe-single-ended, with 90-pin cable connectors DDR4 probes/interposers W4641A Interposer, DDR4 x16 BGA 2-wing single-touch DQ, used with quad-sample mode, requires one U4208A left ZIF probe cable and one U4209A right ZIF probe/cable W4643A Interposer, DDR4 x4/x8 BGA 2-wing single-touch DQ, used with quad-sample mode, requires one U4208A left ZIF probe cable and one U4209A right ZIF probe/cable W4631A Interposers, DDR4 x16 BGA 4-wing double probed DQ, used with dual sample mode and two E5849A ZIF cables or one DDR4 x16 ZIF cable for W4631A W4633A Interposer, DDR4 x4/x8 BGA 3-wing double probed DQ, used with dual sample mode and two E5849A ZIF cables W4636A Interposer, 96 ball BGA, DDR4 x16 2-wing command and reduced data for LA E5849A Cable, high data rate ZIF for use with W4631A and W4633A DDR4 double probed DQ BGA interposers FuturePlus FS2510AB DDR4 3300 DIMM interposer (optional FS1070 conversion kit for FS2510 for data rates over 2.5 Gb/s) FuturePlus FS2512 DDR4 1867 SODIMM interposer DDR3 probes/interposers W3631A DDR3 x16 BGA stacked DRAM under 2 G deep command and data probe for logic analyzer and scope W3633A DDR3 x4/x8 BGA command and data probe for logic analyzer and scope W3636A DDR3 x16 BGA single die command and data probe for logic analyzer and scope (covers > 2 G), for non-stacked DRAM E5847A 46-ch single-ended ZIF probe for DDR3 x4/x8 DRAM BGA probe connection to 90-pin logic analyzer cable E5845A 46-ch single-ended ZIF probe for DDR3 x16 DRAM BGA probe connection to 90-pin logic analyzer cable FuturePlus FS2352B DDR3 2133 DIMM interposer FuturePlus FS2354 DDR3 1600 SODIMM interposer DDR2 probes/interposers W2631B DDR2 x16 BGA ADD/CMD/DATA probe for logic analyzers and scopes W2633B DDR2 x4/x8 BGA ADD/CMD/DATA probe for logic analyzers and scopes Advantage services: calibration and warranty Keysight Advantage Services is committed to your success throughout your equipment’s lifetime. Calibration Description Select Keysight calibration plan R1282A R-50C-011-3 3-year calibration assurance plan (return to Keysight): Priority calibration service covering all calibration costs for 3 years; 15% cheaper than buying stand-alone calibrations. R1282A R-50C-011-5 5-year calibration assurance plan (return to Keysight): Priority calibration service covering all calibration costs for 5 years; 20% cheaper than buying stand-alone calibrations. R1282A R-50C-021-3 ANSI Z540-1-1994 calibration – 3 years R1282A R-50C-021-5 ANSI Z540-1-1994 calibration – 5 years Warranty Description Select coverage R1280A included 3-year warranty (return to Keysight), standard R1280A R-51B-001-5Z 5-year warranty assurance plan (return to Keysight): Priority warranty service includes one-time coverage for an EOS/ESD failure. Warranty and Calibration

33 | Keysight | U4164A Logic Analyzer Module - Data Sheet www.axiestandard.org AdvancedTCA® Extensions for Instrumentation and Test (AXIe) is an open standard that extends the AdvancedTCA for general purpose and semiconductor test. Keysight is a founding member of the AXIe consortium. ATCA ®, AdvancedTCA®, and the ATCA logo are registered US trademarks of the PCI Industrial Computer Manufacturers Group. www.lxistandard.org LAN eXtensions for Instruments puts the power of Ethernet and the Web inside your test systems. Keysight is a founding member of the LXI consortium. www.pxisa.org PCI eXtensions for Instrumentation (PXI) modular instrumentation delivers a rugged, PC-based high-performance measurement and automation system.

34 | Keysight | U4164A Logic Analyzer Module - Data Sheet This information is subject to change without notice. © Keysight Technologies, 2015 - 2016 Published in USA, February 15, 2016 5992-1057EN www.keysight.com myKeysight www.keysight.com/find/mykeysight A personalized view into the information most relevant to you. Three-Year Warranty www.keysight.com/find/ThreeYearWarranty Keysight’s committed to superior product quality and lower total cost of ownership. Keysight is the only test and measurement company with three-year warranty standard on all instruments, worldwide. And, we provide a one-year warranty on many accessories, calibration devices, systems and custom products. Keysight Assurance Plans www.keysight.com/find/AssurancePlans Up to ten years of protection and no budgetary surprises to ensure your instruments are operating to specification, so you can rely on accurate measurements. Keysight Infoline www.keysight.com/find/service Keysight’s insight to best in class information management. Free access to your Keysight equipment company reports and e-library. Keysight Channel Partners www.keysight.com/find/channelpartners Get the best of both worlds: Keysight’s measurement expertise and product breadth, combined with channel partner convenience. PCI-SIG ®, PCIe® and the PCI Express® are US registered trademarks and/or service marks of PCI-SIG. www.keysight.com/find/U4164A From Hewlett-Packard through Agilent to Keysight For more than 75 years, we‘ve been helping you unlock measurement insights. Our unique combination of hardware, software and people can help you reach your next breakthrough. Unlocking measurement insights since 1939.

1939 THE FUTURE

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