81250

81250 KEYSIGHT | Alldatasheet

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Technical content

Parallel Bit Error Ratio Tester Product Overview Version 6.0 The only modular parallel bit error ratio test solution with

• different modules covering a range of data rates from 333 kHz to 13.5 GHz
• up to 66 synchronous input and output channels
• powerful pattern sequencer providing looping and branching on events enabling control of complex tests and devices
• PRBS/PRWS and memory based patterns up to 64Mb
• delay control input for jitter generation
• error detector modules featuring individual CDR
• measurement suite

2Page 2/64 ParBERT 81250 Main Overview Section Page Agilent ParBERT 81250 Overview 3 Fundamental ParBERT platform description 4 ParBERT 81250 key features 6 ParBERT 81250 Measurement software 9 Data editor and postprocessing tools 16 ParBERT 81250 Application examples 17 Agilent N4872A ParBERT 13.5 Gb/s Generator 24 Agilent N4873A ParBERT 13.5 Gb/s Analyzer 24 Agilent N4874A ParBERT 7 Gb/s Generator 31 Agilent N4875A ParBERT 7 Gb/s Analyzer 31 Agilent E4861B ParBERT 3.35 Gb/s Data Module 38 Agilent E4862B ParBERT 3.35 Gb/s Generator Front-End 38 Agilent E4863B ParBERT 3.35 Gb/s Analyzer Front-End 38 Agilent E4832A ParBERT 675 Mb/s Data Module 44 Agilent E4838A ParBERT 675 Mb/s Generator Front-End 44 Agilent E4835A ParBERT 675 Mb/s Analyzer Front-End 44 Agilent E4809A, E4808A and E4805B Central Clock Modules 49 General characteristics 55 Quick ordering guide - overview 58 Product structure - ParBERT 81250 61 Storage of Customer Specific Data 63 Related literature 63 Table of Contents

Agilent ParBERT 81250 Overview The ParBERT 81250 is the fl exible and scalable physical layer test solution that, based on its modular BERT engine, enables characterization of high-speed multi-port devices in the computer, communications and feeding semiconductor industry. The modular ParBERT 81250 can be tailored to individual test needs with up to 132 synchronous channels. Different modules are available for the ParBERT 81250 System that cover data generation and analysis from 333 kb/s up to 13.5 Gb/s. Once purchased in a certain confi guration ParBERT 81250 can easily be extended to fi t future needs protecting your investment. Broad spectrum of applications Originally designed to test and characterize synchronous devices such as a Mux/Demux typical for the communications industry ParBERT 81250 is equally suited for clock synchronous multi-port and multiple serial applications such as can be found in the computer industry. Powerful Pattern sequencer for uninterrupted testing Running complex tests with a variety of test patterns in one shot without stopping the instrument for pattern download is enabled through the powerful ParBERT 81250 pattern sequencer with its up to fi ve nested loop levels and branching on external and internal events or upon SW command. In-depth insight into designs and devices The measurement suite automates the parameter variation of ParBERT’s BER- measurements to achieve and visualize insight into the DUT’s parametric performance, e.g. producing eye diagrams, or doing timing margin analysis with BER-scan bathtub-plots with RJ-DJ jitter decomposition. Jitter injection via the delay control input of the 13.5 / 7 / 3.35 Gb/s Data Generator Modules allows in depth receiver margining including jitter tolerance tests. Application support ParBERT’s software package contains setup and processing tools for 10GbE and SONET/SDH. The N5990A Test Automation Platform enables simple compliance test with ParBERT for different standards such as PCI Express®, MIPI™, display port (DP) and HDMI. Application and product notes describing a variety of test applications with ParBERT are available for download from www.agilent.com/fi nd/ParBERT. ParBERT 81250 key characteristics:

• Modular BERT platform for physical layer test and characterization
• Modules of various speed classes up to 13.5 Gb/s
• Up to 66 synchronous generator and analyzer channels
• Powerful pattern sequencer to control complex devices PRBS/PRWS2) and memory based patterns
• Delay control input to apply external jitter sources3)
• Integrated clock data recovery to test clock-less interfaces4)
• Comprehensive measurement suite Note: 1) 66 or 30 channels max with 3.35Gb/s or 13.5Gb/s modules 2) PRWS, Pseudo Random Word Sequence, is a special hardware generated pattern, based on PRBS, to test Mux/DeMux 3) 3.35 Gb/s, 7Gb/s and 13.5 Gb/s generator modules only 4) 7 Gb/s and 13.5 Gb/s analyzer modules only ParBERT 81250 Main Overview Page 3/64

as a fl exible data generator/ analyzer platform for physical layer test and characterization. It can be used for a large variety of applications and by this meets your individual needs. A module based system The ParBERT 81250 consists of the user SW and the ParBERT modules. These can be categorized by their maximum data rate (675Mb/s, 3.35Gb/s and 7/13.5Gb/s) and their functionality (clock or data). A minimum system consists of one clock module and one data module forming a so-called clock group which is installed in the ParBERT VXI-mainframe. The mainframe can hold multiple clock groups; each is operated through its own graphical user interface (GUI). Three main speed classes The high-speed modules for 13.5 Gb/s and 7 Gb/s are dedicated generator or analyzer modules with one data channel each. The generators provide differential data and full rate clock output. They are equipped with an externally voltage controllable delay line to generate data streams with up to 200ps of peak-to-peak jitter. The analyzer modules feature an integrated clock data recovery CDR. The 3.35 Gb/s data modules can carry up to two generator or analyzer front-ends of any combination. Equivalent to the high speed modules the generator front-ends feature a voltage controlled delay for jitter generation but, according to the lower data rate, with a wider range of 500ps. The 675 Mb/s data module back-ends can hold up to four generator or analyzer front ends and combinations thereof. A special capability of these back- end modules is the internal digital and analog channel- add function which e.g. allows generation of multi-level signals. Up to 132 channels ParBERT 81250 uses the standard VXI mainframe with its 13 slots, where the leftmost slot is always reserved for the so- called slot-0 controller so that 12 slots are available for ParBERT- modules, i.e. clock and data. A maximum of three mainframes can be combined to form a clock synchronous system, which for the 675Mb/s speed class and its 1-slot-wide clock module per frame yields up to 132 data channels (3 x 11 x 4). Fundamental ParBERT platform description Page 4/64 ParBERT 81250 Main Overview

Table 1. Brief selection guide for ParBERT 81250

675 Mb/s

20.834 Mb/s to

3.35 Gb/s

620 Mb/s to

7 Gb/s,

13.5 Gb/s

1. ParBERT 81250 controlled via IEEE 1394 link and external PC

known or not even deterministic. threshold as a criteria (figure 5).

• Auto Bit Sync Finds the proper bit position in a data stream. For memory based patterns a unique detect word is required. Automated phase alignment is optional.
• Fast Bit Sync Possible for PRBS/PRWS only. Especially useful for burst-mode applications, e.g. optical re-circulating loops.
• Auto Delay Align Only the sample point timing of the analyzers is adjusted. The latency between input and output must be within the delay range of the analyzers used. For applications w/o expected data with ParBERT running in data acquisition mode, e.g. for A/D test, proper sample point adjustment can automatically be achieved with the CDR / lane mode (7 and 13Gb/s analyzer modules only) Interrupt-free change of analyzer and generator delay The analyzer sample timing can be adjusted ±1 period while the instrument keeps running w/o interrupting the measurement (see figure 7). For the 13.5 Gb/s, 7 Gb/s and

3.35 Gb/s the delay of the genera-

period while running as well. Figure 7. Analyzer delay can be changed without Figure 6. ParBERT standard mode sequence editor with PRBS/PRWS patterns and data

within its valid data rate range. generate such a modulated clock. Figure 8. Parameter editor for setting multiple frequencies in one system

ParBERT 81250 Measurement Software ParBERT Measurement software consists of six different measurements that deliver graphical and numerical results allowing in- depth characterization for use in R&D and Device Verification (DV). Fast pass/ fail tests a gainst user definable limits for manufacturing purposes are provided as well. ParBERT, as any other BERT, physically can only do one measurement: it digitizes the input signal with respect to a predefined threshold voltage and, at a predefined portion of the bit width (the sample point), compares this to its expected data and counts an error if it doesn’t match the expected binary value. ParBERT Measurement Software automates the variation of these mentioned parameters (sample point timing and threshold voltage) and the repetition of this measurement for a number of subsequent bits and by this allows performing a variety of measurements: 1. BER measurement, targeting the error performance of a complete system under test 2. DUT output level measurement 3. Eye opening 4. DUT output timing measurement 5. Spectral decomposition of jitter allowing in depth pin- and port-wise characterization of the output performance of a transmitter (TX) under test as it is typically required in R&D or during DV. Graphical representation(s) of the test result (e.g., pseudo color plot and contour plots) are available as well as a multitude of extracted or extrapolated numerical values. Pass/fail criteria can be defined for every numerical result, simplifying a fast test against limits making it well suited for manufacturing as well. Reduction of test time as it is usually desired in manufacturing is possible using the 6. Fast eye mask measurement that requires a much smaller number of measured bits. Each of the six measurements is an active-X component, which simplifies its integration into any test executive written with Agilent VEE Pro, National Instruments’ LabVIEW, Excel, Agilent TestExec, C/C++, C# and Microsoft ® VisualBasic. The MUI comprises a Windows (2000, XP or Vista) based GUI that simplifies test set-up and execution. Measurement results can be exported and printed. The measurement software is included in the standard ParBERT 81250 soft ware package. It works as a client to the ParBERT firmware server and can run on that PC that hosts the firmware server and is connected to the HW through the slot -0 controller, or on any other PC that is connected (e.g. via LAN) to this mentioned PC. ParBERT 81250 Main Overview Page 9/64

for root cause failure analysis (e. Table 2. BER measurement

12Page 12/64 ParBERT 81250 Main Overview Eye opening During this measurement both sampling point timing and analyzer thresh old voltage are automatically swept, while BER is recorded and plotted either as a pseudo-color- or a contour-plot (see figure 9 a,b,c), giving the user intuitive and in-depth information of the pulse- or eye-performance of the RX under test. Range and resolution for the measurement parameters and pass/fail values are user definable. Figure 9a/b/c. View the BER for one terminal as a pseudo color plot or contour plot or equal BER at BER threshold Numerical Measurement Results Optimum sample Point delay Optimum threshold Eye opening (Volt)Phase margin Pass/fail For all parameters Each parameter can be individually enabled Graphical Result Displays pseudo color plot BER-contour Two markers: voltage, delay, BER Table 4: Eye opening

according to the dual-dirac model. i.e. the TJ in much shorter time.

2 Markers: delay, BER

Table 6. DUT output timing measurement

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floor and by this pinpointing e.g. sources of undesired crosstalk. data stream (see figure 11b). Table 7. Spectral decomposition of jitter

17 ParBERT 81250 Main Overview Page 17/64

the related measurement task. www.agilent.com/find/ParBERT. synchronous mux/de-mux test e.g. rates as depicted in figure 8. limitations in synchronization. Figure 13. OC 192 example

Figure 14. 10 GbE XAUI module

19 ParBERT 81250 Main Overview Page 19/64

figure 16. ParBERT’s exact timing Figure 15. TDMA bursts travelling upstream on a passive optical network Figure 41: Figure 16. ParBERT based test set-up for characterization of OLT

digital audio/video interface. Agilent TMDS Signal Generator. A clock signal is also provided. Figure 17. Sink test connection setup example

10 MHz Out

10 MHz In

critical areas that require testing. Figure 18. Zoom into the bit level of the D-PHY stimulus signal switching

already defined or in process. external delay control input. a BER below the specified limit.

100 MHz

Figure 19. Example measurement set-up for a PCIe ™ RX test with 4 data lanes

a BER cannot be measured at all. sample point for each channel. Figure 20. Example measurement set-up for an 8bit A/D converter utilizing ParBERT's CDR/

13.5 Gb/s modules require the

• Internal clock mode: The common clock mode is provided by the E4809A

13.5 GHz central clock

Figure 21. N4872A & N4873A and waveform and unchanged system frequency.

• External clock mode: The system also works synchro- nously with an external clock, which is connected to the E4809A clock module.
• CDR mode: To use the N4873A 13.5 Gb/s analyzer CDR capabilities, connect the analyzer’s CDR out to the E4809A clock module’s clock in.

Table 10. N4872A data generator timing specifications (@ 50% of amplitude, 50 Ω to GND)

25 ParBERT 81250 Main Overview Page 25/64

sequence with up to 60 segments. and/or the central sequencer. Table 12. Data rate range, segment length resolution, available memory for synchronization and Table 11. N4872A pattern and sequencing

ended input with 50 Ω impedance. Short circuit current 72 mA max. (1) In single-ended mode, the unused output must be terminated with 50 Ω to GND. be less than 2 V below VOH. External termination voltage must be less than 3 V above VOL. Short circuit current 72 mA max.

1 Hz bandwidth)

< –75dBc with clock module E4809A typ. (1) In single-ended mode, the unused output must be terminated with 50 Ω to GND. be less than 2 V below VOH. External termination voltage must be less than 3 V above VOL. Table 17. Parameters for N4872A ParBERT 13.5 Gb/s generator Table 18. Parameters for N4872A ParBERT 13.5 Gb/s generator

27 ParBERT 81250 Main Overview Page 27/64

Table 19. Parameters for N4872A ParBERT 13.5 Gb/s generator Table 20. Parameters for N4872A ParBERT 13.5 Gb/s generator

• Acquire data from start
• Compare and acquire data around error
• Compare and count erroneous ones and zeros to calculate the bit error rate Receive memory for acquired data is up to 64 Mbit deep, depending on segment length resolution. The stimulus portion of the channel generates expected data and mask data. Mask data is also available at the maximum segment resolution The analyzer is able to synchro- nize on a received data stream by means of a user selectable syn- chronization word. The sync. word has a length of 48 bits and is com- posed of zeros, ones and Xs (“don't cares”). The detect word must be unique within the data stream. Synchronization on a pure PRBS data-stream is done without a detect-word, instead by simply loading a number of the incoming bits into the internal PRBS gener- ator. A pre-condition for this is that the polynomial of the received PRBS is known. The input comparator has differential inputs with 50 Ω impedance. The sensitivity of 50 mV and the common mode range of the comparator allow the testing of all common differential high-speed devices. The user has the choice of using the differential input with or without a termina- tion voltage or as single-ended input (with a termination voltage). The differential mode does not need a threshold voltage, whereas the single-ended mode does. But also in differential mode the user can select one of the two inputs and compare the signal to a threshold voltage. Sampling rate 620 MHz to 13.5 GHz Sample delay Can be specified as leading edge delay in fraction of bits in each channel Start delay range 0 to 100 ns Fine delay range ± 1 period (can be changed without stopping) Delay resolution 100 fs Delay accuracy ±10 ps ± 20 ppm relative to the zero-delay placement (1) Relative delay accuracy ±2 ps ± 2% typ. (1) Skew between modules of same type 20 ps after cable deskewing at customer levels and unchanged system frequency. (1) Number of channels 1, differential or single ended, 2.4 mm (f) Range of operation 620 Mb/s - 13.5 Gb/s Max input amplitude 2 Vpp Input sensitivity 50 mVpp typical @ 10 Gb/s, PRBS 2 31 - 1, and BER 10-12 Input voltage range –2V … +3 (selectable 2V window) Internal termination voltage (can be switched off ) -2.0 to +3.0 V (must be within selected 2 V window) Threshold voltage range –2.0 to + 3.0 V (must be within selected 2 V window) Threshold resolution 1 mV Minimum detectable pulse width 25 ps typ. Phase margin (source: N4872A) 1 UI - 12 ps typ. Impedance 50 Ω typ. (100 Ω differential, if termina- tion voltage is switched off) Analyzer auto-synchronization On PRBS or memory-based data Manual or automatic by: Bit synchronization(2) with or without automatic phase alignment Automatic delay alignment around a start sample delay (range: ± 10 ns) BER Threshold: 10 -4 to 10-9 (2) With PRBS data, analyzers can autosyncronize on incoming PRBS data bits. When using memory-based data, this data must contain a unique 48 bit detect Word at the beginning of the segment, and the generators must be on a separate system clock. Don’t cares within detect word are possible. If several inputs synchronize, the delay diffference between terminals must be smaller than ±5 segment length resolution. Page 28/64 ParBERT 81250 Main Overview

Table 21. N4875A analyzer timing: all timing parameters are measured at ECL levels, terminated Table 22. N4873A pattern and sequencing Table 23. Parameters for N4873A ParBERT 13.5 Gb/s analyzer

recovery of either clock or data. clock source must be independent. high for one segment resolution. Table 24. Parameters for N4873A ParBERT 13.5 Gb/s analyzer - clock data recovery Table 25. Parameters for N4873A 13.5 Gb/s analyzer - AUX OUT

Table 26. Parameters for N4873A 13.5 Gb/s analyzer - AUX IN Table 27. Parameters for N4873A 13.5 Gb/s analyzer - ERROR OUT

Table 28. N4874A data generator timing specifications (@ 50% of amplitude, 50 ž to GND)

• Internal clock mode: The common clock mode is provided by the E4809A

13.5 GHz central clock module,

• External clock mode: The system also works synchronously with an external clock, which is connected to the E4809A clock module.
• CDR mode: To use the N4875A 7 Gb/s analyzer CDR capabilities, connect the analyzer’s CDR out to the E4809A clock module’s clock in.

Figure 22. N4874A & N4875A and waveform and unchanged system frequency.

Table 29. N4874A pattern and sequencing Table 30. Data rate range, segment length resolution, available memory for synchronization and sequence with up to 60 segments. and/or the central sequencer. itself handles the feedback signals.

Table 32. Parameters for N4874A ParBERT 7 Gb/s generator Table 31. Parameters for N4874A ParBERT 7 Gb/s generator (gates) the data to a logic zero. Short circuit current 72 mA max. Cross-point adjustment 20%…80% typ. (1) In single-ended mode, the unused output must be terminated with 50 Ω to GND. be less than 2 V below VOH. External termination voltage must be less than 3 V above VOL. Short circuit current 72 mA max. < - 75 dBc with clock module E4809A typ. (5) In single-ended mode, the unused output must be terminated with 50 Ω to GND. be less than 2 V below VOH. External termination voltage must be less than 3 V above VOL.

Table 33. Parameters for N4874A ParBERT 7 Gb/s generator Table 34. Parameters for N4874A ParBERT 7 Gb/s generator

Table 36. N4875A pattern and sequencing

• Acquire data from start
• Compare and acquire data around error
• Compare and count erroneous ones and zeros to calculate the bit error rate Receive memory for acquired data is up to 64 Mbit deep, depending on segment length resolution. The stimulus portion of the channel generates expected data and mask data. Mask data is also available at the maximum segment resolution The analyzer is able to synchronize on a received data stream by means of a user selectable synchroniza- tion word. The sync. word has a length of 48 bits and is composed of zeros, ones and Xs (“don't cares”). The detect word must be unique within the data stream. Synchronization on a pure PRBS data-stream is done without a detect-word, instead by simply loading a number of the incoming bits into the internal PRBS generator. A pre-condition for this is that the polynomial of the received PRBS is known. The input comparator has differential inputs with 50 Ω impedance. The sensitivity of 50 mV and the common mode range of the comparator allow the Sampling rate 620 MHz to 7 GHz Sample delay Can be specified as leading edge delay in fraction of bits in each channel Start delay range 0 to 100 ns Fine delay range ± 1 period (can be changed without stopping) Delay resolution 100 fs Delay accuracy ±10 ps ± 20 ppm relative to the zero-delay placement (1) Relative delay accuracy ±2 ps ± 2% typ. (1) Skew between modules of same type 20 ps after cable deskewing at customer levels and unchanged system frequency. (1) Analyzer auto-synchronization On PRBS or memory-based data Manual or automatic by: Bit synchronization(2) with or without automatic phase alignment Automatic delay alignment around a start sample delay (range: ± 10 ns) BER Threshold: 10 -4 to 10-9 (2) With PRBS data, analyzers can autosyncronize on incoming PRBS data bits. When using memory-based data, this data must contain a unique 48 bit detect Word at the beginning of the segment, and the generators must be on a separate system clock. Don’t cares within detect word are possible. If several inputs synchronize, the delay diffference between terminals must be smaller than ±5 segment length resolution.

Table 35. N4875A analyzer timing: all timing parameters are measured at ECL levels, terminated input (with a termination voltage).

Table 37. Parameters for N4875A ParBERT 7 Gb/s analyzer Table 38. Parameters for N4875A ParBERT 7 Gb/s analyzer - clock data recovery is high for one segment resolution. Minimum detectable pulse width 25 ps typ. Phase margin (source: N4874A) 1 UI - 12 ps typ.

Table 39. Parameters for N4875A 7 Gb/s analyzer - AUX OUT Table 40. Upgrades 7 Gb/s - 13 Gb/s Table 41. Parameters for N4875A 13.5 Gb/s analyzer - AUX IN Table 42. Parameters for N4875A 13.5 Gb/s analyzer - ERROR OUT

3.35 Gb/s modules are:

• 21 MHz … 3.350 GHz clock/data rate
• 16 Mbit memory depth at each channel
• HW-based PRBS generation up to the polynomial of 2 31 -1
• Analyzer can synchronize on a 48 bit detect word (memory-based data)
• Analyzer can synchronize on a pure PRBS pattern without detect word Timing capabilities The frequency range of the modules is 21 MHz … 3.350 GHz. The ParBERT 3.35 Gb/s front-ends use a multiplying PLL that multi- plies system master clock by 4 or 8. Through the clock module, an external clock source can be used. This external clock must run continuously. If the clock signal is interrupted, the multi- plying PLLs typically needs 100 milliseconds to lock onto the clock again. Frequency range 20.834 MHz to 3.350 GHz Delay = start delay + fine delay Can be specified as leading edge delay in fraction of bits in each channel Start delay range 0 to 200 ns (not limited by period) Fine delay range ±1 period (can be changed without stopping) Delay resolution 1 ps Accuracy data mode ±25 ps ±50 ppm relative to the zero-delay and temperature change within ±10 °C after autocalibration Clock mode ±50 ps ±50 ppm relative to the zero-delay Skew between modules of same type (data mode) 50 ps typ. after deskewing at customer levels and unchanged system frequency The variable delay is available in data mode and pulse mode. In clock mode the timing is fixed. Sequencing The sequencer receives instruc- tions from the clock module. The channel sequencer can generate a sequence with up to 60 segments. An analyzer channel can gener- ate feedback signals which are combined in the clock module for a common response of all parallel channels. With a single receiver channel the channel sequencer itself handles the feedback signals.

Figure 23. E4861B and E4862B with waveform of E4861B generator Table 43. E4861B data generator timing specification (@ 50% of amplitude, 50 Ω to GND)

be smaller than ±5 segment length resolution. Table 44. E4861B analyzer timing all timing parameters are measured at ECL levels, terminated Table 45. E4861B pattern and sequencing

1. Mark ratio is the ratio of ones

which is 1/2 in a normal PRBS. errored and error-free segments. Table 46. Data rate range, segment length resolution, available memory for synchronization and Table 47. Dependancy of PRWS generation and port width.

Short circuit current 72 mA max. Transition times (20% - 80%) < 75 ps; 60 ps typ. Overshoot/ringing 5% +10 mV typ. (1) For output voltages > 3 V the termination voltage ≥ 3 V needs to be applied. (2) External termination voltage must be less than 3 V below VOH. and less than 3 V above VOL. Termination into AC is possible. (3) Measured with E4808A clock module. (4) Specified as intra channel jitter. the generator’s differential output. Table 48. Parameters for generator front-ends E4862B 3.35 Gb/s Table 49. Delay control in

• Acquire data from start
• Compare and acquire data around error
• Compare and count erro neous ones and zeros to calculate the bit error rate The receive memory for acquired data is up to 16 Mbit deep, depending on the segment length resolution. The stimulus portion of the channel generates expect- ed data and mask data. Mask data is also available at the maxi- mum granularity. The analyzer is able to synchro- nize on a received data stream by means of a user-defined detect word. The detect word is defined by the first bits within the expected segment, it has a length of 48 bits and is composed of zeros, ones and Xs (“don’t cares”). The detect word must be unique within the data stream. Synchronization on a pure-PRBS data-stream is done without a detect-word, by simply loading a number of the incoming bits into the internal PRBS generator. A pre-condition for this is that the polynomial of the received PRBS is known. The input comparator has differ- ential inputs with 50 Ω imped- ance. The sensitivity is down to 50 mV and the common mode range of the comparator allows the testing of all common differ- ential high-speed devices.The user has the option of using the differential input with or without a termination voltage or as sin- gle-ended input (with a termina- tion voltage). The differential mode does not need a threshold voltage, whereas the single-ended mode does. But also in differen- tial mode the user can select one of the two inputs and compare the signal to a threshold voltage. Protection Input and output relays switch off automatically, if the absolute maximum voltage window is exceeded.

Figure 26. Eye diagram of E4863B analyzer Table 50. Parameters for analyzer front-ends E4863B 3.35 Gb/s

0 V to 3 V

erator is assigned as a pulse port. NRZ format with variable delay. data are defined by segments. incoming data are compared to. Figure 27. E4832A module

• Bit synchronization
• Auto delay alignment Bit synchronization is possible to cover a bit alignment for a totally unknown number of cycles. Using memory-based data, the first 48 bits within the expected data seg- ment will work as a detect word which the incoming data are compared to. When the incoming data match with this detect word, analysis will begin. Auto delay alignment is per- formed by using the analyzer sampling delay. The sampling delay range is ±50 ns while this is possible. Using auto delay alignment pro- vides synchronization with an absolute timing relation between a group of analyzer channels. This makes skew measurements are possible. Frequency range 333,334 kHz to 675 MHz Delay range 0 to 3.0 µs (not limited by period) Sampling delay resolution 2 ps Accuracy ±50 ps ±50 ppm relative to the zero-delay placement (1) Skew 50 ps typ. after deskewing at customer levels Pulse width Can be specified as width or % of duty cycle Range 750 ps to (period -750 ps) Resolution 2 ps Accuracy ±200 ps ±0.1% Duty cycle 1% to 99%, subject to width limits Sample delay = start delay + fine delay Fine delay can be changed without stopping (2) Sampling rate (3) 333,334 Kb/s to 675 Mb/s Sampling delay ( = start delay + fine delay) range 0 to 3.0 µs (not limited by period) Fine delay range ±1 period Accuracy ±50 ps ±50 ppm relative to the zero-delay placement (3) Resolution 2 ps Skew 50 ps typ. after deskewing at customer levels (1) Valid at 15 to 35 ºC room temperature (2) Conditions: frequency > 20.8 MHz and by using the finest segment length resolution. (3) See tables for front-end deratings

Table 51. E4832A data generator timing specifications Table 52. E4832A analyzer timing; all timing parameters are measured at ECL levels terminated

the auto-synchronization function are unavailable. the terminals must be ±5 segment length resolution. (2) Condition: frequency > 20.8 MHz and by using the finest segment length resolution. Table 53. Pattern and sequencing features of E4832A Table 54. Data rate range, segment length resolution, available memory for synchronization and Table 55. between the capability of generating PRWS and port width, almost all the combinations

• Single-ended normal
• Single-ended compliment
• Differential For termination there is always Ω connected to a programmable termination voltage. In differential mode there is an additional, selectable 100 Ω differential ter- mination. Independent of the selected termination, there is the choice of whether the anaylsis of the incoming signal is performed on the input or true differential. Number of channels 1, differential Impedance 50 Ω typ. Data formats RZ, R1, NRZ, DNRZ Output voltage window –2.2 to +4.4 V (doubles into open up to max.

5 Vpp)

Overshoot/ringing < 7% (< 5% typ). Figure 29. Eye diagram of E4835A analyzer Table 56. Level parameters for differential generator front-end E4838A 675 Mb/s

data back end. In this document one front-end is referred to as E4835A. Table 57. Two differential analyzer front-ends E4835A (1), 667 MSa/s

generator or analyzer or any mix.

• Single
• Looped Infinite loop
• Event handling (branch)
• Synchronization Event handling With event handling, the flow of data generation and analysis can be controlled with external signals at run time. Usage of events
• Start and stop of data
• Match loop
• Integration with other equipment (ATE)
• Trigger on error Agilent E4809A 13.5 GHz Central Clock Module Agilent E4808A High Performance Central Clock Module Agilent E4805B 675 MHz Central Clock Module Technical Specifications Modules/central clock E4805B E4808A E4809A E4832A - ParBERT 675 Mb/s ● ● ● E4861A - ParBERT 2.7/1.6 Gb/s ● ● E4861B - ParBERT 3.35 Gb/s ● ● E4810A/11A - ParBERT 3.3.5 Gb/s optical (1) ● E4866A/67A - ParBERT 10.8 Gb/s (1) ● N4872A/73A - ParBERT 13.5 Gb/s ● E4868B/69B - ParBERT 45 Gb/s (1) ● E4874A/75A - ParBERT 7 Gb/s ● Number of segms ents 1 to 30 (every segment looped once) 1 to 60 (no segment looped) Looping levels Up to 4 nested loops plus one optional infinite loop Loops can be set independently from 1 to 2 20 repetitions Start/stop External input, manual, programmed (stop with E4832A only) Event handling React on internal and external events. Event trigger sources Events can be defined as any combination of the following sources. A maximum of 10 events can be defined. ○ 8-line trigger input pod for TTL signals ○ VXI trigger lines TO and T1 ○ Any capture error/or no error detected by one of the analyzer channels ○ Software command control: an event trigger command issued locally or remotely Reactions to an event can be set per data segment immediately or deferred and can be any combination of: ○ Data segment jump ○ Launch trigger pulse at trigger output of the clock module ○ VXI trigger lines TO and T1 can be set to 01, 10, or 11 Agilent ParBERT 81250 Central Clock Modules Table 58.

Table 59. E4809A, E4808A and E4805B sequencing features Table 60. E4809A, E4808A and E4805B event handling

Table 61. E4809A, E4808A and E4805B trigger pod characteristics Table 62. E4809A clock module specifications clock input multiplier/divider). modules must be the same type.

• Start IN to Trig OUT with 7/13.5 Gb/s
• Start IN to Data OUT with 7/13.5 Gb/s
• IN to Trig OUT without 7/13.5 Gb/s
• IN to Data OUT without 7/13.5 Gb/s 16 ns + (2 * system clock * segment resolution) ± 1 clock (1) 416 ns + (2 * system clock * segment resolution) ± 1 clock (1) 16 ns ± 1 clock (1) 48 ns ± 1 clock (1)

Figure 30. E4809A module

10 MHz reference in

Table 63. Start input using the E4809A master clock. Giga-clock connected modules. be started by an external signal.

Table 65. Clock input Table 66. Trigger input Input transition/slope 30 ps typ.

Table 67. E4805B and E4808A clock module specifications applied to the external input.

• E4832A in range of 334 KHZ to 675 MHz
• E4866A/E4867A (2) in range of 9.5 GHz to 10.8 GHz
• E4861B in range of 20.834 MHz to 3.35 GHz
• E4861A (2) in range of 334 MHz to 2.7 GHz
• E4832A in range of 334 KHZ to 675 MHz Resolution 1 Hz 1 Hz Accuracy ±50 ppm with internal PLL reference ±50 ppm with internal PLL reference (1) May be limited or enhanced by modules or frontends (2) Modules discontinued Ext. clock/ext. reference: This input runs ParBERT 81250 synchronously with an ext. clock, or when a more accurate reference is needed than the internal oscillator. A continuous clock is necessary. A burst clock cannot be used as an external clock. Maximum external clock is 2.7 GHz for the E4805B and 10.8 Gb/s for the E4808A. (Note: no improvement of jitter specifi- cations will be achieved with an external clock). Guided de-skew: Individual semi- automatic deskew per channel is available. The 15447A de-skew probe 15447A allows de-skew on the DUT's (device under test) fixture.

Table 68. External input and ext. clock/ext. ref. input Table 69. Trigger output characteristics E4805B and E4808ATrigger ouput

• Clock mode
• Sequence mode In sequence mode a pulse will be set to mark the start of any segment. In clock mode, the trigger output can supply a clock output of up to 675 MHz. If a higher speed performance clock is needed:
• A 2.7 Gb/s generator can be used to supply a clock output up to 2.7 GHz
• A 10.8 Gb/s generator can be used to supply a clock output up to 10.8 GHz. Trigger output signals • Clock mode (up to 675 MHz).
• Sequence mode Output impedance 50 Ω typ. Output level TTL (frequency < 180 MHz), 50 Ω to GND ECL 50 Ω to GND/-2 V, PECL 50 Ω +3 V Trigger advance 30 ns typ. between trigger output and data output /sampling point (delay set to zero in both cases) Maximum ext voltage –2 V to +3.3 V Jitter (int. reference/int. clock) < 10 ps rms (5 ps typ.) Technical specifications All specifications describe the instrument’s warranted performance. Non-warranted values are described as typical. All specifications are valid from 10 ° to 40 ° ambient temperature after a 30 minute warm-up phase, with outputs and inputs terminated with 50 Ohms to ground at ECL levels unless specified otherwise. E4805B E4808A Zin/termination voltage 50 Ω /-2.10 V to 3.30 V 50 Ω /-2.10 V to 3.30 V Sensitivity/max levels 400 mVpp/-3 V to + 6 V 200 mVpp/-3 V to + 6V for < 9.5 Gbit/s 300 mVpp/-3 V to+ 6 V for > 9.5 Gb/s Coupling dc dc Ext. clock/ext. ref: ac ac Input transitions/slope < 20 ns. ext. input active edge is selectable < 20 ns. ext. input active edge is selectable Clock input multiplier(m)/divider (n) m*n < = 1024 m/n * input frequency must fit data range input frequency/n > = 1.3 MHz PLL lock time 100 ms 100 ms Input frequency/period Ext. clock 170 kHz - 2.7 GHz 170 kHz - 10.8 GHz Ext. ref 1(1), 2(1), 5, or 10 MHz 1(1), 2(1), 5, or 10 MHz Required duty cycle 50 ±10 % 50 ±10 % Latency (typical): to trigger output to channel output to trigger output to trigger output Ext. input 16ns ±1 clock 46ns ±1 clock 16 ns ±1 clock 46 ns ±1 clock(2) Ext. clock 15 ns 45 ns 15 ns 45 ns Add 3 ns if an expander frame is used Add 3 ns if an expander frame is used (1) Jitter performance may be degraded (2) If frequency = 667 MHz Page 54/64 ParBERT 81250 Main Overview

Table 70. Programming times Table 71. Cooling requirements for modules with front-ends installed depends on the amount of data. On-line help: Context-sensitive. in the ParBERT 81250 software. (including front-ends) Net: 2kg. Re-calibration period: 1 year. For one E4805B with one E4832A. Increases with the number of modules. Change of period (1) 60 ms typ. Not applicable in run mode. (1) valid for a system consisting of one E4805A and one E4832A.

Table 72. Power Requirements of Modules and Front-Ends

Table 73. General mainframe characteristics

1000 W for 110 - 264 Vac supplies

Table 74. Ordering guide

• 10 channels at 13.5 Gb/s and

7 Gb/s

• 22 channels at 3.35 Gb/s
• 44 channels at 675 Mb/s. In some circumstances these maximum numbers cannot be achieved due to power restric- tions. Before finalizing a configu- ration, it is necessary to calcu- late the power budget. The 675 Mb/s Analyzer E4835A always comes as a pair and need to be configured side by side, providing two fully independent analyzer channels. Quick ordering guide - overview Data module/front-ends Generator Analyzer Clock module

13.5 Gb/s data module

7 Gb/s data module

3.35 Gb/s data module

3.35 Gb/s front-end

675 MHz data module

675 MHz front-end

More than 3 frames require more than one clock group. Table 75. Entry system

ParBERT 81250 Main Overview Page 59/64 Multi-mainframe/master-slave If the number of desired channels exceeds the number of available slots in the “entry” frame, it is possible to add expander frames. To add channels within one clock group, there is the limit of a maximum of two expander frames. If data modules are housed in an expander frame they need an additional clock module. This clock module must be connected to the clock module in the entry frame (master frame) with the help of the master-slave connection. This connection car- ries the clock and data flow syn- chronization between the frames. The master-slave connection hardware is delivered with the expander frames. The master- slave connection is only possible between clock modules of the same type. Aside from the master-slave con- nection between the clock mod- ules, the controller interface also needs an extension into the expander frames: The FireWire interface, can be “daisy-chained” from frame to frame. This would allow the configuration of a ParBERT 81250 system with a virtually unlimited number of channels. However, as mentioned above, a clock group can only be constructed of up to three VXI-frames, such that ParBERT systems larger than three frames must consist of more than one- clock group. Different clock groups A clock group consists of a clock module and one or more data modules. It is possible to have data modules from different speed classes combined in one clock group. The configuration of more than one clock group is possible. Several clock groups may be housed in one frame. Using expander frames is also possible. Each clock group will be operated from an independent instance of the graphical user interface, which will actually be assigned to this set of hardware defined as a clock group. In such a case the different GUIs may run from separate PCs, connect- ed via LAN. A configuration of more than one clock group is recommended for the following purposes:

• To run different speeds (non binary ratio) between generators and/or analyzers
• To make flexible use of data rate range when combining different speed classes
• To use custom (memory) based data and use of bit synchronization for the analyzer(s). The additional clock modules necessary for the different clock groups reduce the maximum number of possible channels listed in table 85 on the previous page. A master-slave connection must not be installed between the clock modules if different clock groups are desired.

Order information entry system 1 x 81250A 1 x 81250-149 1 x E4805B-ATO/E4808A-ATO/ E4809A-ATO System reference Mainframe 1st clock module Decide on controller: 1 x 81250A-013 1 x 81250A-014 or 1 x 81250A-015 FireWire (IEEE 1394) PC Link to VXI Ext. PC Laptop including PCMCIA IEEE 1394 card Decide on controller accessories: 1 x 15444A 1 x 15445A Monitor Ext. CD-ROM Order information multi mainframe: 1 x 81250-152 1 x E4805B/E4808A/ FireWire (IEEE 1394) expander frame Clock module Order information master-slave/different clock groups E4805B-ATO: Clock module (usable with 675Mb/s and 2.7 Gb/s module) E4808A-ATO: Clock module (usable with 675 Mb/s, 1.65 Gb/s, 2.7 Gb/s, 3.35 Gb/s, 10.8 Gb/s and 45 Gb/s modules) E4809A-ATO: Clock module (usable with 675 Mb/s, 3.35 Gb/s, 7 Gb/s and 13.5 Gb/s modules) Specific rules: Do not mix E4809A, E4808A and E4805B:

• Slave connection is possible only between clock modules of the same type
• One system must be configured with one type of clock module Add data modules/front-ends P/N Cable kit

description

No. of cables Connectors To be used with Bandwidth Matching Length Addl. parts included 15441A SMA to SCI 10 SMA (m) - SCI (f) 675 Mb/s tt ≥ 500 ps No 1.5 m 4 SCI adapt- ers 15442A SMA 4 SMA (m) - SMA (m) 675 Mb/s/ (3.35*) Gb/s tt ≥ 100 ps No 1 m –

15443 SMA

2 SMA (m) - SMA (m) 675 Mb/s/

(3.35*) Gb/s tt ≥ 100 ps Yes 1 m – N4869A SMA & phase shifter

3 SMA (m) - SMA (m) E4866A out to

tt ≥ 50 ps Adjustable 0.4 m Mech. phase Shifter ± 50 ps N4870A 1.85 mm matched 2 1.85/2.4 mm 1.85/2.4 mm N4868A out E4868A/B out E4869A/B in tt ≥ 15 ps ± 1.5 ps 0.63 m – N4871A SMA matched 2 SMA (m) - SMA (m) 3.35 Gb/s front-ends tt ≥ 50 ps ± 1.5 ps 1 m – N4910A 2.4 mm matched pair 2 2.4 mm - 2.4 mm 7 Gb/s, 13.5 Gb/s 0.60 m – Page 60/64 ParBERT 81250 Main Overview Table 76. Cable kit accessories

ParBERT 81250 Main Overview Page 61/64 Part #/Option Description 81250A ParBERT 81250 81250A-013 IEEE 1394 PC link to VXI 81250A-015 Laptop including PCMCIA IEEE 1394 card 81250A-148 13-slot VXI Mainframe 81250A-149 Mainframe 81250A-152 IEEE 1394 'FireWire' expander frame 81250A-0B0 Do not include tutorial CD ROM 81250A-AX4 Rack flange kit Software E4875A-ATO One licence and software CD ROM for ParBERT 81250 Clock modules E4805B 675 MHz central clock module E4808A High performance central clock module E4809A 13.5 GHz central clock module Data modules & front ends E4832A-ATO 675 Mb/s generator/analyzer module E4835A-FG Two differential analyzer front-ends, 675 Mb/s E4838A-FG Differential generator front-end, 675 Mb/s E4861B-ATO 3.35 Gb/s generator/analyzer module E4862B-ATO Generator front-end 3.35 Gb/s E4863B-ATO Analyzer front-end 3.35 Gb/s N4874A-ATO Generator module 7 Gb/s N4875A-ATO Analyzer module 7 Gb/s N4872A-ATO Generator module 13.5 Gb/s N4873A-ATO Analyzer module 13.5 Gb/s HDMI bundles and accessories E4887A-003 Economic HDMI Signal Generator up to 3.4 Gb/s E4887A-007 HDMI TMDS Signal Generator up to 7 Gb/s E4887A-037 HDMI TMDS Signal Generator up to 3.4 Gb/s E4887A-101 CTS 1.3 compliant low-speed cable emulator (< 75MHz) E4887A-102 CTS 1.3 compliant high-speed cable emulator (> 75MHz) E4887A-104 CTS 1.3 compliant passive EQ type cable emulator (set of 8 units) E4887A-207 HDMI Frame Generator Software for E4887A platform E4887A-303 Accessory and Cable Kit for E4887A-003 HDMI Signal Generator E4887A-307 Accessory and Cable Kit for E4887A-007 TMDS Signal Generator 7 Gb/s E4887A-308 Accessory and Cable Kit for E4887A-007 HDMI TMDS Signal Generator E4887A-310 Accessory and Cable Kit for E4887A-037 HDMI TMDS Signal Generator E4887A-S01 CTS 1.3 compliant passice EQ type cable emulator prototype (5mm chip) Product structure - ParBERT 81250

Page 62/64 ParBERT 81250 Main Overview Accessories 15440A Adapter kit: 4* SMA (M) I/O adapters 15442A Cable kit: 4*SMA (m) to SMA (m) 15443A Matched cable pair 15446A 8-line trigger input pod 15447A Deskew probe N4871A Cable kit: SMA matched pair, 50 ps N4910A Cable kit: matched cable pair for 13.5 G N4911A-002 Adapter 3.5 mm female to 2.4 mm male N4912A 2.4 mm 50Ω termination, male connector N4913A 4 GHz deskew probe Test automation software platform N5990 (Excerpt) N5990A-010 Test automation software platform, required for all other options N5990A-001 Interfaces to databases (Microsoft SQL and MySQL) and web browsers N5990A-500 User programming (API including templates) For test interfaces pls see www.agilent.com/find/automation Warranty & services All systems and modules have 1 year on-site warranty. Start up assistance for first time users is included. Product structure - ParBERT 81250 (continued)

This statement is to certify that none of Agilent Technologies’ ParBERT 81250 clock modules, data generator/analyzer modules or front ends store customer specifi c data in any non-volatile memory. As a general rule it can be said that after electrical power has been turned off, the modules will not store any data or settings. Data storage across power down/power up cycles will only appear in the ParBERT’s PC Controller where access to the data can be controlled via generic Microsoft ® Windows ® security mechanisms. Storage of Customer Specifi c Data in ParBERT 81250 Modules and Front Ends Related literature

• Agilent ParBERT 81250, Mux/Demux Application, Application Note, Literature Number 5968-9695E
• Advanced Memory Buffer, Product Note, Literature Number 5989-3481EN
• Jitter Fundamentals: Jitter Tolerance Testing with Agilent 81250 ParBERT, Application Note, Literature Number 5989-0223EN
• HDMI Compliant Jitter Tolerance Test Solution for cable and RX Test with ParBERT 81250, Application Note, Literature Number 5989-4959EN
• How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY), Application Note Literature Number, 5989-7184EN
• Next Generation I/O Bus PCI-Express BER Test Solution Application Note, Literature Number 5989-2690EN
• Automated PCI Express Receiver Compliance Test and Characterization with the Agilent N5990A Software Platform, Application Note, Literature Number 5989-5500EN
• Agilent N5990A Test Automation Software Platform (Version 1.0), Product Overview, Literature Number 5989-3797EN
• Test Automation Software Platform N5990A, Data Sheet, Literature Number 5989-5483EN
• Total Jitter Measurement at Low Probability Levels Using Optimized BERT Scan Method, White Paper, Literature Number 5989-2933EN
• Fast Total Jitter Test Solution, Application Note, Literature Number 5989-3151EN
• BERT Family brochure - applications focused, Brochure, Literature Number 5988-9514EN
• Physical Layer Testing of Passive Optical Network (PON) Modules, Application note, Literature number 5989-3298EN ParBERT 81250 Main Overview Page 63/64

www.agilent.com/fi nd/emailupdates Get the latest information on the products and applications you select. www.agilent.com/fi nd/agilentdirect Quickly choose and use your test equipment solutions with confi dence. www.agilent.com www.agilent.com/fi nd/ParBERT- For more information on Agilent Technologies’ products, applications or services, please contact your local Agilent offi ce. The complete list is available at: www.agilent.com/fi nd/contactus Americas Canada (877) 894-4414 Latin America 305 269 7500 United States (800) 829-4444 Asia Pacifi c Australia 1 800 629 485 China 800 810 0189 Hong Kong 800 938 693 India 1 800 112 929 Japan 0120 (421) 345 Korea 080 769 0800 Malaysia 1 800 888 848 Singapore 1 800 375 8100 Taiwan 0800 047 866 Thailand 1 800 226 008 Europe & Middle East Austria 01 36027 71571 Belgium 32 (0) 2 404 93 40 Denmark 45 70 13 15 15 Finland 358 (0) 10 855 2100 France 0825 010 700* *0.125 €/minute Germany 07031 464 6333 0.14€/minute Ireland 1890 924 204 Israel 972-3-9288-504/544 Italy 39 02 92 60 8484 Netherlands 31 (0) 20 547 2111 Spain 34 (91) 631 3300 Sweden 0200-88 22 55 Switzerland 0800 80 53 53 United Kingdom 44 (0) 118 9276201 Other European Countries: www.agilent.com/fi nd/contactus Revised: July 17, 2008 Product specifi cations and descriptions in this document subject to change without notice. © Agilent Technologies, Inc. 2003, 2004, 2008 Printed in USA, December 4, 2008 5968-9188E Remove all doubt Our repair and calibration services will get your equipment back to you, performing like new, when prom- ised. You will get full value out of your Agilent equipment through- out its lifetime. Your equipment will be serviced by Agilent-trained technicians using the latest factory calibration procedures, automated repair diagnostics and genuine parts. You will always have the utmost confi dence in your measurements. Agilent offers a wide range of ad- ditional expert test and measure- ment services for your equipment, including initial start-up assistance, onsite education and training, as well as design, system integration, and project management. For more information on repair and calibration services, go to: www.agilent.com/fi nd/open Agilent Open simplifi es the process of connecting and programming test systems to help engineers design, validate and manufacture electronic products. Agilent offers open connectivity for a broad range of system-ready instruments, open industry software, PC-standard I/O and global support, which are combined to more easily integrate test system development. www.lxistandard.org LXI is the LAN-based successor to GPIB, providing faster, more effi cient connectivity. Agilent is a founding member of the LXI consortium. www.agilent.com/fi nd/removealldoubt Microsoft is a U.S. registered trademark of Microsoft Corporation. “MIPI™ word marks and logos are trademarks owned by the MIPI Alliance, Inc. and any use of such marks by Agilent is under license. Other trademarks and trade names are those of their respective owners.