TNY177D

TNY174_V01 POWERINT | Alldatasheet

Document overview

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Technical content

www.power.com September 2020 Energy Efficient, Offline Switcher with Enhanced Flexibility and Extended Power Range Product Highlights Lowest System Cost with Enhanced Flexibility

• 650 V rated integrated MOSFET
• Simple ON/OFF control, no loop compensation needed
• Selectable curr ent limit through BP/M capacitor value
• Higher current limi t extends peak power or, in open frame applications, maximum continuous power
• Lower current limi t improves efficiency in enclosed adapters/ chargers
• Allows optimum Tin ySwitch-LT choice by swapping devices with no other circuit redesign
• Tight I2f parameter tolerance reduces system cost
• Maximizes MOSFET and magnetics power del ivery
• Minimizes max o verload power, reducing cost of transformer, primary clamp & secondary components
• ON-time extension – extends low-l ine regulation range/hold-up time to reduce input bulk capaci tance
• Sel f-biased: no bias winding or bias components
• Frequency ji ttering reduces EMI filter costs
• Pin-out simplifies heat sinking to the PCB
• SOURCE pins are electrical ly quiet for low EMI Enhanced Safety and Reliability Features
• Accurate hysteretic thermal shutdown protection with automatic r ecovery eliminates need for manual reset
• Auto-r estart delivers <3% of maximum power in short-circuit and open loop fault conditions
• Output ov ervoltage shutdown with optional Zener
• Very low component count enhances r eliability and enables single- sided printed circuit board layout
• High bandwidth pro vides fast turn on with no overshoot and excellent transient load response
• Extended creepage between DRAIN and al l other pins improves field
• rel iability EcoSmart™– Extremely Energy Efficient
• Easily meets all global energy efficiency regulations
• No-load <150 mW at 265 VAC without bias winding,
• <50 mW with bias winding
• ON/OFF control pr ovides constant efficiency down to very light loads – ideal for mandatory standby consumption regulations

Applications

• Supplies for appliances, home bui lding automation, PC standby and other auxiliary power supplies.

Description

TinySwitch™-LT incorporates a 650 V power MOSFET, oscillator, high-voltage switched current source, current limit (user selectable) and thermal shutdown circuitry. The IC family uses an ON/OFF control scheme and offers a design flexible solution with a low system cost and extended power capability. PI-4770-111918 D S EN BP/M DC Output TinySwitch-LT AC Input Figure 1. Typical Application.

230 VAC ± 15% 85 ‒ 265 VAC

Table 1. Output Power Table.

1. Minimum continuous power in a typical non-

in an open frame design (see Key Applications Considerations).

1. Packages: P: DIP-8C, D: SO-8C. S

ee Part Ordering Information. ey Application Considerations.

1.0 V + V

Figure 2. Functional Block Diagram. operating current for both start-up and steady-state operation. nternally generated 5.85 V supply. connected from the BP/M pin to a bias winding supply. threshold current is between 75 mA and 115 mA. high-voltage power return and control circuit common. Figure 3. Pin Configur ation.

to regulate the output voltage. tional block diagram with the most important features. to optimize EMI reduction for both average and quasi-peak emissions. in Figure 4 illustrates the frequency jitter. Figure 4. Fr equency Jitter. ENABLE pin from going much below 1.2 V in the disabled state. for both high frequency decoupling and energy storage. winding to decrease the no-load consumption to well below 50 mW. must rise back to 5.85 V to enable (turn-on) the power MOSFET. The current limit circuit senses the current in the power MOSFET. amounts under medium and light loads. time will not cause premature termination of the switching pulse. presence of an output short-circuit.

Rev. J 10/20 TNY174-180 www.power.com Applications Example D S S BP/M EN 1 mH 1N4007 RV1

275 VAC

3.15 A 1N4007 6.8 µF 400 V 1 µF 60 V 22 µF 400 V C10 1000 µF 25 V 2.2 nF

250 VAC

100 µF 25 V +12 V, 1 A 85-265 VAC RTN 100 nF 50 V TNY178P 10 nF 1 kV VR1 P6KE150A NC 8 1N4007GP D6 UF4003 BYV28-200 PC817A VR2 1N5255B 28 V VR3 BZX79-C11 11 V C7 is configurable to adjust U1 current limit, see circuit *R5 is optional 47 Ω 1/8 W 2 kΩ 1/8 W 390 Ω 1/8 W 20 Ω R8* 21 kΩ 1 kΩ 100 Ω 1N4007 1N4007 Ferrite Bead 3.5 × 7.6 mm PI-4773-010709 TinySwitch-LT Figure 12. TNY178P, 12 V, 1 A Universal Input Power Supply. plished using a simple Zener reference and optocoupler feedback. effective switching frequency and scaling switching losses with load. ideal for meeting energy efficiency requirements. requirement for an auxiliary or bias winding on the transformer. pin voltage (28 V+5.85 V), current begins to flow into the BP/M pin. consumption of this design from 140 mW to 40 mW at 265 VAC. EN55022 Class B conducted EMI limits.

Rev. J 10/20 TNY174-180 www.power.com For design flexibility the value of C7 can be selected to pick one of the 3 current limits options in U1. This allows the designer to select the current limit appropriate for the application: Standar d current limit (ILIMIT) is selected with a 0.1 mF BP/M pin capacitor and is the normal choice for typical enclosed adapter applications. When a 1 mF BP/M pin capacitor is used, the curr ent limit is reduced (ILIMITred or ILIMIT-1) offering reduced RMS device currents and therefore improved efficiency, but at the expense of maximum power capability. This is ideal for thermally challenging designs where dissipation must be minimized. When a 10 mF BP/M pin capacitor is used, the curr ent limit is increased (ILIMITinc or ILIMIT+1), extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow. Further flexibility comes from the current limits between adjacent TinySwitch-LT family members being compatible. The reduced current limit of a given device is equal to the standard current limit of the next smaller device and the increased current limit is equal to the standard current limit of the next larger device. Key Application Considerations TinySwitch-LT Design Considerations Output Power Table The data sheet output power table (Table 1) represents the minimum practical continuous output power level that can be obtained under the following assumed conditions: T he minimum DC input voltage is 100 V or higher for 85 VAC input, or 220 V or higher for 230 VAC input or 115 VAC with a voltage doubler. The value of the input capacitance should be sized to meet these criteria for AC input designs. E fficiency of 75%. M inimum data sheet value of I2f. T ransformer primary inductance tolerance of ±10%. R eflected output voltage (V OR) of 135 V. V oltage only output of 12 V with a fast PN rectifier diode. C ontinuous conduction mode operation with transient K P * value of 0.25. 8. I ncreased current limit is selected for peak and open frame power c olumns and standard current limit for adapter columns. T he part is board mounted with SOURCE pins soldered to s ufficient area of copper and/or a heat sink is used to keep the S OURCE pin temperature at or below 110 °C for P and G package a nd 100 °C for D packaged devices. 10. A mbient temperature of 50 °C for open frame designs and 40 °C for sealed adapters. *Below a value of 1, KP is the ratio of ripple to peak primary current. To prevent reduced power capability due to premature termination of switching cycles a transient K P limit of ≥0.25 is recommended. This prevents the initial current limit (IINIT) from being exceeded at MOSFET turn-on. For reference, Table 2 provides the minimum practical power delivered from each family member at the three selectable current limit values. This assumes open frame operation (not thermally limited) and otherwise the same conditions as listed above. These numbers are useful to identify the correct current limit to select for a given device and output power requirement. Overvoltage Protection The output overvoltage protection provided by TinySwitch-LT uses an internal latch that is triggered by a threshold current of approximately 5.5 mA into the BP/M pin. In addition to an internal filter, the BP/M pin capacitor forms an external filter providing noise immunity from inadvertent triggering. For the bypass capacitor to be effective as a high frequency filter, the capacitor should be located as close as possible to the SOURCE and BP/M pins of the device. For best performance of the OVP function, it is recommended that a relatively high bias winding voltage is used, in the range of 15 V ‒ 30 V. This minimizes the error voltage on the bias winding due to leakage inductance and also ensures adequate voltage during no-load operation from which to supply the BP/M pin for reduced no-load consumption. Selecting the Zener diode voltage to be approximately 6 V above the bias winding voltage (28 V for 22 V bias winding) gives good OVP performance for most designs, but can be adjusted to compensate for variations in leakage inductance. Adding additional filtering can be achieved by inserting a low value (10 W to 47 W) resistor in series with the bias winding diode and/or the OVP Zener as shown by R7 and R3 in Figure 12. The resistor in series with the OVP Zener also limits the maximum current into the BP/M pin. Reducing No-load Consumption As TinySwitch-LT is self-powered from the BP/M pin capacitor, there is no need for an auxiliary or bias winding to be provided on the transformer for this purpose. Typical no-load consumption when self-powered is <150 mW at 265 VAC input. The addition of a bias winding can reduce this down to <50 mW by supplying the TinySwitch-LT from the lower bias voltage and inhibiting the internal high-voltage current source. To achieve this, select the value of the resistor (R8 in Figure 12) to provide the data sheet DRAIN supply current. In practice, due to the reduction of the bias voltage at low load, start with a value equal to 40% greater than the data sheet maximum current, and then increase the value of the resistor to give the lowest no-load consumption.

Table 2. Minimum Pr actical Power at Three Selectable Current Limit Levels. such that the peak core flux density is below 3000 Gauss (300 mT). tion technique of dip varnishing practically eliminates audible noise. samples before approving the design. construction, for example a film type. See Figure 13 for a recommended circuit board layout for TinySwitch-LT. the area of copper connected to the SOURCE pins. including, but not limited to, the BYPASS and DRAIN pins. A clamp is used to limit peak voltage on the DRAIN pin at turn off. components to the transformer and TinySwitch-LT. source node, this area should be maximized for good heat sinking. of the input filter capacitors. area can increase high frequency radiated EMI.

Figure 13. R ecommended Circuit Board Layout for TinySwitch-LT. currents into and out of the EN pin to levels below 1 mA. leakage current into the EN pin is low. are >>10 MW and do not cause this issue. LIMIT(MIN) at the end of the tLEB(MIN). the specified absolute maximum ratings.

Rev. J 10/20 TNY174-180 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Specified) Min Typ Max Units Control Functions Output Frequency in Standard Mode fOSC TJ = 25 °C See Figure 4 Average 124 132 140 kHz Peak-to-peak Jitter 8 Maximum Duty Cycle DCMAX S1 Open 62 65 % ENABLE Pin Upper Turn-Off Threshold Current I DIS -150 -115 -90 mA ENABLE Pin Voltage VEN IEN = 25 mA 1.8 2.2 2.6 V IEN = -25 mA 0.8 1.2 1.6 DRAIN Supply Current IS1 EN Current > IDIS (MOSFET Not Switching) See Note A 290 mA IS2 EN Open (MOSFET Switching at fOSC) See Note B TNY174P/D 275 370 mA TNY175P/D 295 410 TNY176P/D 310 440 TNY177P/D 365 480 TNY178P/D 445 605 TNY179P 510 700 TNY180P 630 850 Absolute Maximum Ratings (1,5) DRAIN Peak Current: T NY174 T 60 (1050) mA(2) TNY176 20 (1350) mA(2) T 80 (1650) mA(2) TNY178 040 (1950) mA(2) ENABLE Current BP/M Voltage Storage Temperature Notes: A ll voltages referenced to SOURCE, T A = 25 °C. T he higher peak DRAIN current is allowed while the D RAIN voltage is simultaneously less than 400 V. N ormally limited by internal circuitry. /16 in. from case for 5 seconds. M aximum ratings specified may be applied one at a time, w ithout causing permanent damage to the product. E xposure to Absolute Maximum Rating conditions for e xtended periods of time may affect product reliability. Thermal Resistance Thermal Resistance: P Package: D P ackage: Notes: M easured on the SOURCE pin close to plastic interface. 2. S 3. S oldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

Rev. J 10/20 TNY174-180 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Specified) Min Typ Max Units Control Functions (cont.) BP/M Pin Charge Current ICH1 VBP/M = 0 V, TJ = 25 °C See Note C, D mA ICH2 VBP/M = 4 V, TJ = 25 °C See Note C, D BP/M Pin Voltage VBP/M See Note C 5.6 5.85 6.15 V BP/M Pin Voltage Hysteresis V BP/MH 0.80 0.95 1.20 V BP/M Pin Shunt Voltage VSHUNT IBP = 2 mA 6.0 6.4 6.7 V Circuit Protection Standard Current Limit (BP/M Capacitor = 0.1 mF) See Note D I LIMIT di/dt = 50 mA/ms TJ = 25 °C See Note E TNY174P 233 250 267 mA TNY174D 233 250 273 di/dt = 55 mA/ms TJ = 25 °C See Note E TNY175P 256 275 294 TNY175D 256 275 300 di/dt = 70 mA/ms TJ = 25 °C See Note E TNY176P 326 350 374 TNY176D 326 350 382 di/dt = 90 mA/ms TJ = 25 °C See Note E TNY177P 419 450 481 TNY177D 419 450 491 di/dt = 110 mA/ms TJ = 25 °C See Note E TNY178P 512 550 588 TNY178D 512 550 599 di/dt = 130 mA/ms TJ = 25 °C See Note E TNY179P 605 650 695 di/dt = 150 mA/ms TJ = 25 °C See Note E TNY180P 698 750 802

Rev. J 10/20 TNY174-180 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Specified) Min Typ Max Units Circuit Protection (cont.) Reduced Current Limit (BP/M Capacitor = 1 mF) See Note D I LIMITred di/dt = 50 mA/ms TJ = 25 °C See Note E TNY174P 196 210 233 mA TNY174D 196 210 237 di/dt = 55 mA/ms TJ = 25 °C See Note E TNY175P 233 250 277 TNY175D 233 250 283 di/dt = 70 mA/ms TJ = 25 °C See Notes E TNY176P 256 275 305 TNY176D 256 275 311 di/dt = 90 mA/ms TJ = 25 °C See Notes E TNY177P 326 350 388 TNY177D 326 350 396 di/dt = 110 mA/ms TJ = 25 °C See Notes E TNY178P 419 450 499 TNY178D 419 450 508 di/dt = 130 mA/ms TJ = 25 °C See Notes E TNY179P 512 550 610 di/dt = 150 mA/ms TJ = 25 °C See Notes E TNY180P 605 650 721 Increased Current Limit (BP/M Capacitor = 10 mF) See Note D I LIMITinc di/dt = 50 mA/ms TJ = 25 °C See Notes E, F TNY174P 196 210 233 mA TNY174D 196 210 237 di/dt = 55 mA/ms TJ = 25 °C See Notes E TNY175P 326 350 388 TNY175D 326 350 396 di/dt = 70 mA/ms TJ = 25 °C See Notes E TNY176P 419 450 499 TNY176D 419 450 509 di/dt = 90 mA/ms TJ = 25 °C See Notes E TNY177P 512 550 610 TNY177D 512 550 622 di/dt = 110 mA/ms TJ = 25 °C See Notes E TNY178P 605 650 721 TNY178D 605 650 734 di/dt = 130 mA/ms TJ = 25 °C See Notes E TNY179P 698 750 833 di/dt = 150 mA/ms TJ = 25 °C See Notes E TNY180P 791 850 943

Rev. J 10/20 TNY174-180 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Specified) Min Typ Max Units Circuit Protection (cont.) Power Coefficient I2f Standard Current Limit, I2f = ILIMIT(TYP) × fOSC(TYP) TNY174-180P 0.9 × I2f I2f 1.12 × I2f A2Hz TNY174-178D 0.9 × I2f I2f 1.16 × I2f Reduced Current Limit, I2f = ILIMITred(TYP) × fOSC(TYP) TNY174-180P 0.9 × I2f I2f 1.16 × I2f TNY174-178D 0.9 × I2f I2f 1.20 × I2f Increased Current Limit, I2f = ILIMITinc(TYP) × fOSC(TYP) TNY174-180P 0.9 × I2f I2f 1.16 × I2f TNY174-178D 0.9 × I2f I2f 1.20 × I2f Initial Current Limit IINIT See Figure 19 TJ = 25 °C, See Note G 0.75 × ILIMIT(MIN) mA Leading Edge Blanking Time tLEB TJ = 25 °C See Note G 170 215 ns Current Limit Delay tILD TJ = 25 °C See Note G, H 150 ns Thermal Shutdown Temperature T SD 135 142 150 °C Thermal Shutdown Hysteresis T SDH 75 °C BP/M Pin Shutdown Threshold Current I SD 4 6.5 9 mA BP/M Pin Power-Up Reset Threshold Voltage V BP/M(RESET) 1.6 2.6 3.6 V Output ON-State Resistance RDS(ON) TNY174P/D ID = 25 mA TJ = 25 °C 28 32 W TJ = 100 °C 42 48 TNY175P/D ID = 28 mA TJ = 25 °C 19 22 TJ = 100 °C 29 33 TNY176P/D ID = 35 mA TJ = 25 °C 14 16 TJ = 100 °C 21 24

Rev. J 10/20 TNY174-180 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Specified) Min Typ Max Units Output (cont.) ON-State Resistance RDS(ON) TNY177P/D ID = 45 mA TJ = 25 °C 7.8 9.0 W TJ = 100 °C 11.7 13.5 TNY178P/D ID = 55 mA TJ = 25 °C 5.2 6.0 TJ = 100 °C 7.8 9.0 TNY179P ID = 65 mA TJ = 25 °C 3.9 4.5 TJ = 100 °C 5.8 6.7 TNY180P ID = 75 mA TJ = 25 °C 2.6 3.0 TJ = 100 °C 3.9 4.5 OFF-State Drain Leakage Current IDSS1 VBP/M = 6.2 V VEN = 0 V VDS = 520 V TJ = 125 °C See Note I TNY174-176 50 mATNY177-178 100 TNY179-180 200 IDSS2 VBP/M = 6.2 V VEN = 0 V VDS = 375 V, TJ = 50 °C See Note G, I Breakdown Voltage BVDSS VBP = 6.2 V, VEN = 0 V, See Note J, TJ = 25 °C 650 V DRAIN Supply Voltage 50 V Auto-Restart ON-Time at f OSC tAR TJ = 25 °C See Note K 64 ms Auto-Restart Duty Cycle DCAR TJ = 25 °C 3 %

Rev. J 10/20 TNY174-180 www.power.com NOTES: IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. Total device consumption at no-load is the sum of I S1 and IDSS2. S ince the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BP/M pin current at 6.1 V. B P/M pin is not intended for sourcing supply current to external circuitry. D T o ensure correct current limit it is recommended that nominal 0.1 mF / 1 mF / 10 mF capacitors are used. In addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Nominal BP/M Pin Cap Value Tolerance Relative to Nominal Capacitor Value Min Max 0.1 mF -60% +100% 1 mF -50% +100% 10 mF -50% NA F or current limit at other di/dt values, refer to Figure 21. T NY174 does not set an increased current limit value, but with a 10 mF BP/M pin capacitor the current limit is the same as with a 1 mF BP/M pin capacitor (reduced current limit value). G. T his parameter is derived from characterization. T his parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I LIMIT specification. IDSS1 is the worst-case OFF-state leakage specification at 80% of BV DSS and maximum operating junction temperature. I DSS2 is a typical s pecification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations. B reakdown voltage may be checked against minimum BV DSS specification by ramping the DRAIN pin voltage up to but not exceeding mi nimum BVDSS. Au to-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).

5 W S2

NOTE: This test circuit is not applicable for current limit or output characteristic measurements. Figure 14. General Test Circuit. Figure 15. Duty Cycle Measurement. Figure 16. Output Enable Timing. Figure 17. Current Limit Envelope.

Figure 24. Dr ain Capacitance Power.

Rev. J 10/20 TNY174-180 www.power.com Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 4. Pin locations start with Pin 1, and continue counter-clock-wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. P08C PI-3933b-092920 .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .356 (9.05) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .118 (3.00) .140 (3.56) .015 (.38) MINIMUM .048 (1.22) .068 (1.73) .100 (2.54) BSC .014 (.36) .022 (.56) -E- Pin 1 SEATING PLANE -D- -T- D S .004 (.10)⊕ T E D S .010 (.25) M⊕ (NOTE 6) .137 (3.48) MINIMUM PDIP-8C (P Package) .30 in [7.62 mm] .30 in [7.62 mm] 0.200 in [5.08 mm] ∅.03 in [0.86 mm] .06 in [1.41 mm] .10 in [2.54 mm] Typ ∅.06 in [1.41 mm]

Rev. J 10/20 TNY174-180 www.power.com PI-4526-012315D07C 3.90 (0.154) BSC Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. 0.20 (0.008) C 1 4 2 6.00 (0.236) BSC D 4.90 (0.193) BSC 0.10 (0.004) C D 0.10 (0.004) C 2X A-B 1.27 (0.050) BSC 0.25 (0.010) M C A-B D 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) C C H o 1.27 (0.050) 0.40 (0.016) GAUGE PLANE 0 - 8 BSC SEATING PLANE 0.25 (0.010) 0.17 (0.007) DETAIL A DETAIL A C SEATING PLANE Pin 1 ID + + 4.90 (0.193) 2.00 (0.079) Reference Solder Pad Dimensions SO-8C (D Package) Part Ordering Information

• TinySwitch Product Family
• Series Number
• Package Identifier P Plastic DIP-8C D Plastic Surface Mount SO-8C
• Lead Finish N Pure Matte Tin (Pb-Free) (Not available in D Package) G RoHS Compliant and Halogen Free (D Package only)
• Tape & Reel and Other Options Blank Standard Configuration TL Tape & Reel, 2.5 k pcs for D Package. Not available for P Package.TNY 178 P N - TL

A Initial release. 08/07 B Minor text change. 08/10/07 C Updated Part Ordering Information section with Halogen Free and added D package part. Corrected electrical symbol mF in three locations under Circuit Protection in Parameter Table. D Added TNY177D. 08/12 E Added TNY178D. 09/13 F Updated with new PI Brand Style. 12/15 G Updated PDIP-8C (P Package) per PCN-16232. 08/16 H Initial web release. 11/18 I Updated per DSC-20391. 09/20 J Updated PDIP-8C package. 10/20 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: A Lif e support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. A cri tical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2020, Power Integrations, Inc. World Headquarters

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