7708

TFS7701 POWERINT | Alldatasheet

Document overview

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Technical content

This Product is Covered by Patents and/or Pending Patent Applications. Figure 1. Schematic of Two-Switch Forward and Flyback Converter.

• Selectable 132 kHz main switching frequency for lower cost and smaller magnetics
• Increased main peak power vs. HiperTFS-1
• Self-biased high-side driver eliminates high-side bias winding and diode
• Package lead form and pinout modified for easier insertion and PC-board layout
• Tighter UV(ON) standby threshold tolerance
• Improved standby no-load performance Key Benefits
• Single IC solution for two-switch forward main (66 kHz/132 kHz) and flyback (132 kHz) standby
• High integration allows smaller form factor and higher power density designs, with reduced component count
• Incorporates control, gate drivers, and three power MOSFETs
• Level shift technology eliminates need for pulse transformer
• Protection features include: UV, OV, OTP , OVP , standby OPC, SCP , and ILIMIT
• Transformer reset control, prevents saturation under all conditions
• Main duty cycle operation above 50% for reduced rms currents and lower output diode voltage rating
• Less than 10% variation in standby overload power over input voltage range
• Up to 586 W peak output power in a highly compact package
• >90% efficiency at full load
• Simple clip mounting to heat sink without need for insulation pad
• Halogen free and RoHS compliant Typical Applications
• PC (80 PLUS® Bronze and 80 PLUS Silver)
• Printer
• LCD TV
• Video game consoles
• High-power adapters
• Industrial and appliance Output Power Table Product3 Two-Switch Forward 380 V Flyback

100 V - 400 V

Table 1. Output Power Table.

1. Maximum practical continuous power in an open frame design with adequate

Considerations for more information) measured at specified ambient temperature.

2 Peak load less than 10 seconds and average power less than maximum

1. Package: eSIP-16F. (Note: Direct attach to heat sink, does not require insulation

Figure 2. Package Option.

Rev. B 04/15 TFS7701-7708 www.power.com Section List

Rev. B 04/15 TFS7701-7708 www.power.com

Description

The HiperTFS-2 device family members incorporate both a high-power two-switch-forward converter and a mid-power flyback (standby) converter into a single, low-profile eSIP™ power package. The single chip solution provides the controllers for the two-switch-forward and flyback converters, high- and low-side drivers, all three of the high-voltage power MOSFETs, and eliminates the converter’s need for costly external pulse transformers. The device is ideal for high power applications that require both a main power converter (two-switch forward) up to 586 W peak, and standby converter (flyback) up to 20 W. HiperTFS-2 includes Power Integrations’ standard set of comprehensive protection features, such as integrated soft- start, fault and overload protection, and hysteretic thermal shutdown. HiperTFS-2 utilizes advanced power packaging technology that simplifies the complexity of two-switch forward layout, mounting and thermal management, while providing very high power capabilities in a single compact package. The devices operate over a wide input voltage range, and can be used following a power-factor correction stage such as HiperPFS. Two-switch-forward power converters are often selected for applications demanding cost-effective converters that have high efficiency, fast transient response, and high rejection to line voltage variation. The two-switch-forward controller incorporated into HiperTFS-2 devices improves on the classic topology by allowing operation considerably above 50% duty cycle. This improvement reduces RMS current conduction losses, minimizes the size and cost of the bulk capacitor, and minimizes output diode voltage ratings. The advanced design also includes transformer flux reset control (saturation protection) and charge-recovery switching of the high-side MOSFET, which reduces switching losses. This combination of innovations yields an extremely efficient power supply with smaller MOSFETs, fewer passives and discrete components, and a lower-cost smaller transformer. HiperTFS-2’s flyback standby controller and MOSFET solution is based on the highly popular TinySwitch™ technology used in billions of power converter ICs due to its simplicity of operation, light load efficiency, and rugged, reliable, performance. This flyback converter can provide up to 20 W of output power and the built-in overload power compensation reduces component design margin. Product Highlights Protected Two-Switch Forward and Flyback Combination Solution

• Incorporates three high-voltage power MOSFETs, main and standby controllers, and gate drivers
• Level shift technology eliminates need for pulse transformer
• Programmable line undervoltage (UV) detection prevents turn-off glitches
• Programmable line overvoltage (OV) detection; latching and non-latching
• Accurate hysteretic thermal shutdown (OTP)
• Accurate selectable cycle-by-cycle current limit (main and standby)
• Line compensated standby MOSFET current limit for standby over power compensation (OPC)
• Fully integrated soft-start to minimize start-up stress
• Simple fast AC reset
• Reduced EMI
• Synchronized 66/132 kHz forward and 132 kHz flyback converters
• Frequency jitter
• Eliminates up to 30 discrete components for higher reliability and lower cost Asymmetrical Two-Switch Forward Reduces Losses
• Allows >50% duty cycle operation
• Reduces primary-side RMS currents and conduction losses
• Minimizes the size and cost of the bulk capacitor
• Allows reduced capacitance or longer hold-up time
• Allows lower voltage output diodes for higher efficiency
• Transformer reset control
• Prevents transformer saturation under all conditions
• Extends duty cycle to satisfy AC cycle drop out ride through
• Duty cycle soft-start
• Satisfies 2 ms ~ 20 ms start-up with large capacitance at output
• Self-biased high-side driver eliminates high-side bias winding (66 kHz)
• Remote-on/off function
• Voltage-mode controller with current limit

20 W Flyback with Selectable Power Limit

• TinySwitch-III based converter
• Selectable power limit (10 W, 12.5 W, 15 W, 20 W)
• Built-in overload power compensation (OPC)
• Flat overload power vs. input voltage
• Reduces component stress during overload conditions
• Reduces required design margin for transformer and output diode
• Output overvoltage (OVP) protection with fast AC reset
• Latching, non-latching, or auto-restart
• Output short-circuit protection (SCP) with auto-restart Advanced Package for High Power Applications
• Up to 586 W peak output power capability in a highly compact package
• Simple clip mounting to heat sink
• Can be directly connected to heat sink without insulation pad
• Provides lower thermal resistance than a TO-220
• Heat slug connected to ground potential for low EMI
• Two row lead form for easy insertion into PC-board
• Single power package for two power converters reduces assembly costs and layout size

Table 2. Summary of Differences Between HiperTFS-2 and Other Typical High Power Supplies. Wider duty cycle reduces RMS switch currents by 17%. Component Count Higher Lower Saves up to 30 components, depending on specification.

1 Package No SIL (insulation) pad required

Drain of the low-side MOSFET transistor forward converter. Drain of the MOSFET of standby power supply. of several internal standby current limit values. a function of input voltage. also used to implement remote-on/off for the main controller. 66 kHz (1 mF) or 132 kHz (10 mF) main switching frequency. SOURCE pin of the high-side MOSFET. with respect to low-side source and ground. Figure 2. Pin Configuration.

3 V+VT

Figure 3. Functional Block Diagram for Two-Switch Forward Converter.

Figure 4. Functional Block Diagram for Flyback/Standby Converter.

3 V + VT

regulation before the main applies a load to the bulk-capacitor. MOSFET turns on, while the main high-side MOSFET is held off. substantial capacitive load on the output. pin is used to provide duty cycle control for the main converter. 12 kHz, in order to facilitate optimal control loop response. LINE-SENSE pin and RESET pin. low-side main and high-side main MOSFET’s switch simultaneously. when driving the high-side MOSFET. supplied by a bootstrap diode or internal current source. converts the reset voltage into an RESET pin current signal. duty cycle limit is trimmed during production. (see Applications section layout guidelines for details). Figure 7. PWM Duty Cycle vs. Control Current.

current limit according to the following table. provide sufficient margin to meet hold-up time requirements. when the input voltage drops below approximately 40 V (IL(SB-UVON)). Figure 9. Current Limit Selection. Table 3. FEEDBACK Pin Main Current Limit Selection.

6.0 V after

Figure 8. Duty Cycle Limit vs. Ratio of R Pin Current Over L Pin Current.

leaving the standby in operation. typically a PFC boost converter).

1. There are 4 current limits that are selected via the ENABLE
2. Secondary OVP latching shutdown. This is triggered via a

threshold (IBP(SD) = 15 mA).

1. Dedicated LINE-SENSE pin for line-voltage detection providing

accuracy for UV(ON) threshold.

1. Current limit is compensated as a function of input voltage

to maintain a flat overload characteristic versus input voltage. and thus the standby is always the last power supply to shutdown.

4.7 V is achieved), and before the main or standby MOSFETs

start switching. This is done to minimize noise interference. Figure 10. Main and Standby Start-Up. Table 4. ENABLE Pin Standby Current Limit Selection. Figure 11. L and R Pin Duty Limit Mode.

float to it’s nominal voltage of 3.5 V. power capability of the device is more tightly managed. feature provides a much safer design. shutdown if regulation is lost when input voltage is below 100 V. voltage drops below approximately 40 V (as defined by IL(SB-UVOFF)). The standby converter operates at a frequency of 132 kHz. reduce quasi-peak and average EMI emissions. not required when both standby and main run at 132 kHz. safety feature to protect against abnormal or fault conditions. selection (FEEDBACK pin and ENABLE pin resistors respectively). change the value of the BYPASS pin capacitor is determined. Figure 12. Shows Output Overload Power for Compensated (TFS-2) Standby and General Uncompensated Standby.

Rev. B 04/15 TFS7701-7708 www.power.com shunt regulator, which will be enabled if the BYPASS pin voltage is externally driven above 5.7 V. The BYPASS pin shunt current is used for two functions: 1. First, a 4 mA threshold (IBP(ON)) for main remote-on. When the BYPASS pin current exceeds this threshold, the main is enabled. 2. Second a 15 mA threshold (IBP(SD))for standby secondary OVP latch-off. When the BYPASS pin current exceeds this threshold, the standby and main converters are latched-off. This latch can be reset by pulling the LINE-SENSE pin below the line undervoltage threshold (IL(SB-UVOFF)), or by discharging the BYPASS pin below 4.7 V. Main and Standby Line Overvoltage Detection (OV) The overvoltage threshold is included in the device, and can be used to disable the device during overvoltage (with the use of an additional external signal Zener). The overvoltage threshold is set sufficiently high to prevent accidental triggering during boost PFC overshoot conditions. When the overvoltage condition is triggered, it will simultaneously shutdown both the main and standby. The overvoltage feature is intended for use with external components (circuitry), to program the overvoltage threshold independently of the undervoltage thresholds (see the Applications section for details). High-Power eSIP Package The HiperTFS-2 package is designed to minimize the physical size of the device, while maintaining a low thermal resistance and sufficient electrical spacing for the pins. The package has 12 functional pins with 4 pins removed for increased pin-to-pin spacing between high-voltage pins. The low-side two-switch forward and flyback MOSFETs have a thermal resistance of less than 1 °C/W to the exposed pad on the back of the package. Since this pad is referenced to the SOURCE pin (Source), it is at electrical ground potential and thus can be connected to the heat sink without need for electrical insulation. The high-side MOSFET is over-molded to achieve electrical isolation and thus also allows direct connection to the heat sink.

1. +12 V output PC main and +12 V standby.
2. A regulated DC input for main with a nominal voltage of

385 VDC and a minimum of 300 VDC.

1. HiperTFS-2 combined main and standby efficiency of 87%
2. Schottky high-efficiency output diodes.
3. DC input for Standby 115 VDC to 385 VDC.
4. Sufficient heat sinking and fan cooling to maintain heat sink
5. Transformer designed with nominal duty factor of 45%.

provide better voltage centering of the outputs. to guarantee the 12 V bias required for the high-side driver. Figure 13. Bootstrap Supply for VDDH and Component Calculations. Typical VAUX_MIN is 17 V. Typical Value is 1 kW for 132 kHz Operation, and 2 kW if the Bias Support

the VAUX during start-up and standby output load dump. main feedback loop to prevent output overshoot on start-up. HiperTFS-2 is still in the current limit startup phase.

250 Hz which is high enough to reduce EMI but low enough to

have minimal effect on output ripple (rejected by the control loop). recommended for outputs above 10 A. spreadsheet allows selection of either scheme.

150 V+VBUS

Figure 14. Two Primary Clamp Schemes, (a) Clamp-to-Rail (Higher Efficiency) and (b) Clamp-to-Ground (Enables Output to Stay in Regulation to a Lower Input Voltage).

Figure 15. Standard Values for Clamp-to-Rail Scheme. These Work Well for all Power Ranges and both 66 and 132 kHz. Using Standard Recovery Diodes for CR2 and Frequency Damping, and R3 Allows VZ1 to Work as a “Bleed” Instead of a Hard Clamp, to Improve Efficiency. AC ripple currents. Very-low ESR capacitors are not necessary. capacitance for loop stabilization and transient response. bias resistor should be connected from V AUX to the BYPASS pin. otherwise powers the BYPASS pin. for the low-side main MOSFET and standby power MOSFET. for optimal thermal performance.

Figure 16. LM431 Feedback Loop Components.

• Output LC filter double pole – typically at 800 Hz, slightly underdamped.
• Output capacitor ESR zero – typically at 3-5 kHz.
• Optocoupler and FEEDBACK pin system pole – typically at 8-12 kHz. (The HiperTFS-2 has a low impedance FEEDBACK pin to improve optocoupler bandwidth) See Figure 16, the compensator should have a:
• Pole at the origin (an integrator to minimize steady-state error). This is implemented by C9.
• A Zero near the LC double pole location. This is implemented by R21 in conjunction with C8.
• A phase-boost circuit, centered near the crossover frequency – implemented with R10 and C4. This will improve phase margin and increase the crossover frequency. With the above compensation, and with the use of low ESR electrolytic capacitors, a gain crossover frequency of 7-9 kHz with a gain margin of >55° is achievable. Resistor R11 and C5 are for soft-start. They do not contribute significantly to the gain-phase characteristic. Resistor R15 should be sized to conduct approximately 10 mA when the TL431 is fully “ON” or saturated ( 2.5 V on the cathode). It is also an overall gain-setting resistor, affecting the entire frequency range. It, along with the phase-boost network (R10 + C4), are the main high-frequency gain setting components. Resistor R38 is to provide the minimum bias current for the LM431. Capacitor C9 rolls off the LM431 gain at very high frequencies. Overvoltage Protection An overvoltage protection circuit can be implemented by sourcing >15 mA into the BYPASS pin to cause latching shut-off of both converters. Resetting requires the BYPASS pin voltage to fall below 4.8 V. PI-7013-050313 S G HiperTFS-2 Bad Bulk Capacitor High Current Trace with Large di/dt Optocoupler To Other Small Signal Parts Ok Good Good

Figure 17. The PCB Trace from the Bulk Capacitor to the SOURCE Pin Contains bypass capacitors, should be connected to the GROUND pin. must be very close to the SOURCE or GROUND pin. to the HIGH-SIDE SOURCE pin. capacitor should be closer to the PFC than to the HiperTFS-2. ground traces and creating ground bounce issues.

100 V RTN

Figure 23. LINE-SENSE and RESET Pin Resistor Chain. The Highlighted Resistors be SMD type and placed very close to their associated pins. LINSE-SENSE and RESET pins. See Figure 24. traces that act as Faraday shields, such as V AUX o r B P.

Rev. B 04/15 TFS7701-7708 www.power.com 2. Efficiency of 80% at full load, minimum nominal input. 3. Minimum data sheet value of I 2f. 4. Transformer primary inductance tolerance of ±10%. 5. Reflected output voltage (V OR) of 100 V. 6. Voltage only output of 5 V with a Schottky diode. 7. Continuous conduction mode operation with transient KP* value of 0.25. 8. Highest standby current limit selection. 9. Heat sink max temperature is 95 °C. *Below a value of 1, KP is the ratio of ripple to peak primary current. A transient KP limit of ≥0.25 is recommended to prevent reduced power capability due to premature termination of switching cycles. Due to the initial current limit (I INIT) being exceeded at MOSFET turn-on. Reducing No-Load Consumption The BYPASS pin can be powered from the internal high-voltage current source from the HIGH-SIDE DRAIN pin, but R16 (7.5 kW) in Figure 30 will reduce no-load consumption by providing the BYPASS pin current from a lower voltage and inhibiting the internal high-voltage current source. Audible Noise Standard dip varnishing on the standby transformer will prevent the possibility of audible noise in the standby converter. Additionally, the peak core flux density should be kept below 3000 Gauss (300 mT). Vacuum impregnation of the transformer is not recommended because it will increase standby no-load losses due to the increased primary capacitance. Higher flux densities are possible, however careful evaluation of the audible noise performance should be made using production transformer samples before approving the design. Ceramic capacitors that use dielectrics such as Z5U, when used in clamp circuits with high ripple voltage, may also generate audio noise. If this is the case, try replacing them with a capacitor having a different dielectric or construction, for example a film type. Recommended First-Time Power-Up Procedure Place a small, fast-blow low-capacity fuse between the bulk capacitor and the HiperTFS-2 circuitry. Use a current-limited bench power supply to power the HiperTFS-2 converter instead of using the PFC or the AC mains. Be careful using a programmable bench AC source in DC mode, because when they are loaded with a large bulk capacitor and their output is turned off, the output of the AC source can undershoot to a negative voltage and damage the HiperTFS-2. If a remote-on circuit is present, keep it OFF so that only the standby will run. Place a voltage and current probe on the STANDBY DRAIN pin. Raise the bulk capacitor voltage slowly until the standby turns on. Check for proper waveforms (peak voltage, and check for core saturation) and for output regulation. Check the VAUX voltage. Check for over-heating components. Slowly increase the load and the input voltage. Check for over-heating components again. Place voltage probes on DRAIN and HIGH-SIDE SOURCE pins. Place current probe in DRAIN pin. If a remote-on circuit is present turn remote to ON. Keep input voltage below UV start threshold (typically 330 V). Slowly increase input voltage until main converter starts. Check for proper waveforms and for output regulation. Check for over-heating components, especially the Drain clamp diode, and associated snubber components. Slowly increase input voltage and load. Check for over-heating components again. Quick Design Checklist Flyback 1. Maximum standby drain voltage – Verify that DSB voltage does not exceed 675 V at highest input voltage and peak (overload) output power. This 50 V margin to the 725 V BVDSS specification gives margin for unit-to-unit variation. 2. Maximum DSB current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify Standby Drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at start-up. Repeat under steady-state conditions and verify that the leading edge current spike event is below ILIMIT(N)(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum Standby Drain current should be below the specified absolute maximum ratings. 3. Thermal check – With main converter off (and any system fans are also off), at specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for the HiperTFS-2, transformer, output diode, and output capacitors. Main (Forward) Converter Examine the voltage and current at 20% load and nominal input voltage. Measure and check the following:

• Switching frequency
• Duty cycle
• Peak voltage Repeat the measurements at full load. Be cautious of over- heating the power supply and use a strong fan. Measure the source voltage (HS) of the high-side MOSFET at turn-on for each steady-state switch cycle (Figure 28). It should be < 40% of the bulk voltage. Calculate and verify the K P from the current waveform and verify with the spreadsheet. Also check the peak current at peak load – do not dwell at peak load for more than several seconds to prevent over-heating. Check for any oscillation visible in the Drain current envelope. Start-Up Examine the start-up voltage and current. The peak start-up current should be close to the I LIMIT of the device. Examine the output voltage monotonicity. Check for the high-side misfiring during start-up. If the bootstrap diode is omitted (66 kHz only), the VDDH capacitor should be ≥4.7 mF to prevent misfiring. Start-up should be acceptable with either the remote-on/off switch, or by bringing up the HVDC supply with remote-on already asserted. Check startup at maximum expected input voltage.

Rev. B 04/15 TFS7701-7708 www.power.com Brown-Out At full load, reduce input voltage until the output just falls out of regulation. Note the HVDC input voltage, measure the duty cycle, and check the waveforms for complete core reset. Reduce the input voltage further until the output just drops below regulation (it is now in “LR mode”) while checking for complete core reset further reduce input voltage to find the voltage at which the converter shuts off (main UVLO) Temperatures Use a thermal camera and check device hotspot temperature, and the temperatures of the snubber components, output diodes, and magnetics. Light Load Examine the high-side MOSFET Source waveform at very light load. As the load is reduced, the duty cycle will begin to reduce, and at light enough load the high-side Source voltage will not reach ground. Keep reducing the load and check for misfiring in the high-side MOSFET. At 132 kHz operation, some misfiring at very light load may occur, but it should occur at such low duty cycles that any audio noise in the main transformer will not be audible if the transformer is dip-varnished. Loop Stability As a first check, do a load step of 50% -> 100% load, and check for oscillation or excessive ringing. Also check from 100% to peak load (be careful to avoid over-heating when operating at peak load). Check for cross-talk between the forward and flyback outputs. When a load transient is applied to one output, the other output should only show a very small perturbation, well below the output ripple specification. Use a gain-phase analyzer and check gain and phase margin at full load. Also check the minimum phase at lower frequencies. Check minimum phase at reduced load (just enough for continuous mode operation).

Figure 30. Design Example: 12 V / 15 A Main Output, 12 V, 0.83 A Standby.

250 VAC

12 V Bias

high-voltage current source to reduce zero-load consumption. controlled by a computer start-up command. current to start the turn-on sequence for the main converter. provide very high-efficiency. demand high-efficiency and low no-load input power consumption. which covers the normal universal input of 90 VAC to 265 VAC.

brown-out and load transients. off the main converter when the input voltage is below 212 V. selected internal primary current limit of the main switch path. decoupling capacitors are placed close to the HiperTFS-2. traces that conduct large switching currents, are segregated. pins and traces, and low-voltage traces and components. capacitor (C10), is placed close to the main output connector. placed close to the standby output connector (J2). Figure 31. PCB Layout of Design Example Schematic in Figure 30.

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units Control Functions Switching Frequency – PC Main fS1(MA) TJ = 25 °C Average 62 66 70 kHzPeak-to-Peak Jitter 4 fS2(MA) TJ = 25 °C Average 124 132 140 Peak-to-Peak Jitter 8 Frequency Jitter Modulation Rate fM1(MA) 250 HzfM2(MA) 250 Remote-ON Main BYPASS Pin Remote-ON Current IBP(ON) VEN = Open 4.3 5.3 6.3 mA BYPASS Pin Remote-OFF Current Hysteresis IBP(HYST) 66 kHz TFS7701 3.8 mA TFS7702 3.7 TFS7703 3.6 TFS7704 3.6 TFS7705 3.5 TFS7706 3.4 TFS7707 3.4 TFS7708 3.4 IBP(HYST) 132 kHz TFS7701 3.6 TFS7702 3.5 TFS7703 3.3 TFS7704 3.2 TFS7705 3.1 TFS7706 2.9 TFS7707 2.8 TFS7708 2.7 Absolute Maximum Ratings(1,5) DRAIN Peak Current Low-Side Notes: 1. All voltages referenced to SOURCE, TJ = 25 °C. 2. Normally limited by internal circuitry. 3. 1/16 in. (1.59 mm) from case for 5 seconds. 4. The higher peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V. 5. Maximum ratings specified may be applied one at a time, without causing permanent damage to the product. Exposure to Absolute Rating conditions for extended periods of time may affect product reliability. Thermal Resistance Notes: 1. All voltages referenced to SOURCE, TA = 25 °C.

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units Remote-ON Main (cont.) BYPASS Pin Latching Shutdown Threshold IBP(SD) 17 mA Main/Standby Remote-ON Delay tR(ON) 2.5 ms Main/Standby Remote-OFF Delay tR(OFF) 2.5 ms Soft-Start High-Side Start-Up Charge Time tD(CH) 60 ms Soft-Start Period tSS See Note D 12 ms FEEDBACK Pin PWM Gain DCREG(MA) -1800 mA < IFB < -1500 mA, IL = 60 mA, IR = 160 mA -70 %/mA PWM Gain Temperature Drift TCDCREG 0.05 %/°C FEEDBACK Pin Feed- back Onset current IFB(ON) IL = 100 mA, IR = 170 mA TJ = 25 °C -1.2 mA FEEDBACK Pin Current at Zero Duty Cycle IFB(OFF) -2.1 mA FEEDBACK Pin Internal Filter Pole fP(FB) 12 kHz FEEDBACK Pin Voltage VFB IFB = IFB(ON) 2.9 V LINE-SENSE Pin (Line Voltage) Line Undervoltage Threshold – Standby IL(SB-UVON) TJ = 25 °C Threshold 23.75 25 26.25 mA IL(SB-UVOFF) Threshold 9.0 10.5 12 Line Undervoltage Threshold – Main IL(MA-UVON) TJ = 25 °C Threshold 80 84 88 mA IL(MA-UVOFF) Threshold 47 54 58 Line Overvoltage Threshold – Main and Standby IL(MA-OVON) TJ = 25 °C Threshold 119 130 146 mA IL(MA-OVOFF) Threshold 135 144 164 LINE-SENSE Pin LINE-SENSE Pin Short-Circuit IL(SC) VL = VBP 3900 mA RESET Pin (Duty Limit/Main Only Remote-OFF) Reset Overvoltage Threshold IR(MA-OVON) TJ = 25 °C Threshold 165 205 245 mA IR(MA-OVOFF) Threshold 175 215 255 RESET Pin Voltage VR IR = 155 mA 1.55 V RESET Pin Short-Circuit Current IR(SC) VR = VBP 3750 mA Duty Cycle – Programmable Limit DCLIMIT(MA) IL = 100 mA, IR = 110 mA 50.5 %IL = 115 mA, IR = 170 mA 48.2 DCMAX(MA) IL = 90 mA, IR = 170 mA 61

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units Current Limit Programming FEEDBACK Pin Current Limit Detection Range #1 ILIM(1)(MA) Start-up See Note B 0-5 mA FEEDBACK Pin Current Limit Detection Range #2 ILIM(2)(MA) Start-up See Note B 5-12 mA FEEDBACK Pin Current Limit Detection Range #3 ILIM(3)(MA) Start-up See Note B 12-24 mA Maximum Current Limit Current Limit ILIM(1)(MA) TFS7701 TJ = 25 °C FS = 66 kHz di/dt = 175 mA/ms 1.19 A ILIM(2)(MA) di/dt = 224 mA/ms 1.53 ILIM(3)(MA) di/dt = 249 mA/ms 1.58 1.70 1.82 ILIM(1)(MA) TFS7702 TJ = 25 °C FS = 66 kHz di/dt = 267 mA/ms 1.82 ILIM(2)(MA) di/dt = 343 mA/ms 2.34 ILIM(3)(MA) di/dt = 381 mA/ms 2.40 2.60 2.78 ILIM(1)(MA) TFS7703 TJ = 25 °C FS = 66 kHz di/dt = 333 mA/ms 2.26 ILIM(2)(MA) di/dt = 428 mA/ms 2.91 ILIM(3)(MA) di/dt = 475 mA/ms 2.99 3.24 3.46 ILIM(1)(MA) TFS7704 TJ = 25 °C FS = 66 kHz di/dt = 370 mA/ms 2.52 ILIM(2)(MA) di/dt = 475 mA/ms 3.24 ILIM(3)(MA) di/dt = 528 mA/ms 3.33 3.60 3.85 ILIM(1)(MA) TFS7705 TJ = 25 °C FS = 66 kHz di/dt = 409 mA/ms 2.78 ILIM(2)(MA) di/dt = 525 mA/ms 3.58 ILIM(3)(MA) di/dt = 584 mA/ms 3.68 3.98 4.26 ILIM(1)(MA) TFS7706 TJ = 25 °C FS = 66 kHz di/dt = 448 mA/ms 3.05 ILIM(2)(MA) di/dt = 576 mA/ms 3.92 ILIM(3)(MA) di/dt = 639 mA/ms 4.03 4.36 4.66 ILIM(1)(MA) TFS7707 TJ = 25 °C FS = 66 kHz di/dt = 482 mA/ms 3.28 ILIM(2)(MA) di/dt = 619 mA/ms 4.22 ILIM(3)(MA) di/dt = 688 mA/ms 4.33 4.69 5.01 ILIM(1)(MA) TFS7708 TJ = 25 °C FS = 66 kHz di/dt = 509 mA/ms 3.47 ILIM(2)(MA) di/dt = 655 mA/ms 4.46 ILIM(3)(MA) di/dt = 727 mA/ms 4.58 4.96 5.30 Low-Side Main MOSFET ON-State Resistance RDS(ON) TFS7701 ID = 10% ILIM(3)(MA) TJ = 25 °C 4.3 4.95 W TJ = 100 °C 6.5 7.48 TFS7702 ID = 10% ILIM(3)(MA) TJ = 25 °C 2.7 3.10 TJ = 100 °C 4.1 4.70 TFS7703 ID = 10% ILIM(3)(MA) TJ = 25 °C 2.0 2.30 TJ = 100 °C 3.0 3.45 TFS7704 ID = 10% ILIM(3)(MA) TJ = 25 °C 1.55 1.78 TJ = 100 °C 2.35 2.70

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units Low-Side Main MOSFET (cont.) ON-State Resistance RDS(ON) TFS7705 ID = 10% ILIM(3)(MA) TJ = 25 °C 1.3 1.49 W TJ = 100 °C 1.95 2.24 TFS7706 ID = 10% ILIM(3)(MA) TJ = 25 °C 1.1 1.26 TJ = 100 °C 1.65 1.90 TFS7707 ID = 10% ILIM(3)(MA) TJ = 25 °C 1.0 1.15 TJ = 100 °C 1.45 1.67 TFS7708 ID = 10% ILIM(3)(MA) TJ = 25 °C 0.9 1.03 TJ = 100 °C 1.3 1.50 OFF-State Drain Leakage Current IDSS(D) TFS7701 VL, VR = 0 V, IBP = 6 mA, VDS = 560 V, TJ = 100 °C 150 mA TFS7702 150 TFS7703 150 TFS7704 150 TFS7705 170 TFS7706 170 TFS7707 470 TFS7708 470 Breakdown Voltage BVDSS(D) VL, VR = 0 V, IBP = 6 mA, TJ = 25 °C 725 V Rise Time tR(D) 100 ns Fall Time tF(D) 50 ns High-Side Main MOSFET ON-State Resistance RDS(ON)(HD) TFS7701 (VHD - VHS) = 1 V TJ = 25 °C 1.90 W TJ = 100 °C 2.40 TFS7702 (VHD - VHS) = 1 V TJ = 25 °C 1.90 TJ = 100 °C 2.40 TFS7703 (VHD - VHS) = 1 V TJ = 25 °C 1.20 TJ = 100 °C 1.50 TFS7704 (VHD - VHS) = 1 V TJ = 25 °C 1.20 TJ = 100 °C 1.50 TFS7705 (VHD - VHS) = 1 V TJ = 25 °C 0.90 TJ = 100 °C 1.10 TFS7706 (VHD - VHS) = 1 V TJ = 25 °C 0.90 TJ = 100 °C 1.10 TFS7707 (VHD - VHS) = 1 V TJ = 25 °C 0.71 TJ = 100 °C 0.90 TFS7708 (VHD - VHS) = 1 V TJ = 25 °C 0.71 TJ = 100 °C 0.90 Effective Output Capacitance COSS(EFF)(HD) TFS7701 TJ = 25 °C, VGS = 0 V VDS = 0 V to 80% VDSS(HD) pF TFS7702 55 TFS7703 82 TFS7704 82 TFS7705 110 TFS7706 110 TFS7707 165 TFS7708 165

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units High-Side Main MOSFET (cont.) Breakdown Voltage BVDSS(HD) TJ = 25 °C 530 530 OFF-State Drain Current Leakage IDSS(HD) TFS7701 VD = 424 V, TJ = 100 °C mA TFS7702 60 TFS7703 60 TFS7704 60 TFS7705 80 TFS7706 80 TFS7707 110 TFS7708 110 Turn-On Voltage Rise Time tR(HD) 30 ns Turn-Off Voltage Fall Time tF(HD) 25 ns High-Side Bias Shunt Voltage VDDH(SHUNT) IDDH = 5 mA See Note A 12.2 V High-Side Undervoltage ON-Threshold VDDH(UVON) See Note A 11.5 V High-Side Undervoltage OFF-Threshold VDDH(UVOFF) See Note A 10.3 V High-Side Shunt Hysteresis Voltage VDDH(HYST) See Note A 1.1 V Standby MOSFET ON-State Resistance RDS(ON)(DS) IDSB = 10% ILIM(4)(DSB) TJ = 25 °C 8.5 9.7 W TJ = 100 °C 12.8 14.6 OFF-State Drain Leakage Current IDSS1(DS) VBP = 6.2 V VEN = 0 V VDS = 560 V TJ = 100 °C 200 mA IDSS2(DS) VBP = 6.2 V VEN = 0 V VDS = 375 V, TJ = 50 °C 15 Breakdown Voltage BVDSS(DS) VBP = 6.2 V, VEN = 0 V, TJ = 25 °C 725 V DRAIN Supply Voltage VDSB(START) 50 V Standby Controller Output Frequency in Standard Mode fS(SB) TJ = 25 °C Average 124 132 140 kHz Peak-to-Peak Jitter 8 Maximum Duty Cycle DCMAX(DSB) IL = 40 mA 66 69 72 % ENABLE Pin Upper Turnoff Threshold Current IDIS -150 -105 -80 mA ENABLE Pin Voltage VEN IEN = -25 mA 2.7 3.6 4.5 V

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units Standby Controller (cont.) BYPASS Pin Charge Current ICH1 VBP = 0 V, mA ICH2 VBP = 4 V, TJ = 25 °C -4 -2.1 0 BYPASS Pin Voltage VBP VDS = 50 V 5.60 5.80 6.00 V BYPASS Pin Voltage Hysteresis VBP(HYST) 0.80 1.1 1.3 V BYPASS Pin Shunt Voltage VBP(SHUNT) IBP = 2 mA 5.8 6.15 6.4 V Standby Circuit Protection ENABLE Pin Current Limit Selection Range #1 ILIM(1)(DSB) Start-up 0-5 mA ENABLE Pin Current Limit Selection Range #2 ILIM(2)(DSB) Start-up 5-12 mA ENABLE Pin Current Limit Selection Range #3 ILIM(3)(DSB) Start-up 12-24 mA ENABLE Pin Current Limit Selection Range #4 ILIM(4)(DSB) Start-up 24-48 mA Standby Current Limit ILIM(1)(DSB) IL = 20 mA, di/dt = 95 mA/ms, TJ = 25 °C 450 500 540 mA ILIM(2)(DSB) IL = 20 mA, di/dt = 105 mA/ms, TJ = 25 °C 500 550 600 ILIM(3)(DSB) IL = 20 mA, di/dt = 123 mA/ms, TJ = 25 °C 610 650 690 ILIM(4)(DSB) IL = 20 mA, di/dt = 143 mA/ms, TJ = 25 °C 690 750 810 Δ ILIM ILIM (IL = 100 mA) / ILIM (IL = 20 mA) di/dt = 125 mA/ms 84 % General Circuit Protection Power Coefficient I2f I2f = ILIM(3)(DSB)(TYP)× fS(SB)(OSC)(TYP) TJ = 25 °C 0.9 × I2f I2f 1.12 × I2f A2Hz Initial Current Limit IINIT TJ = 25 °C See Note D 0.75 × ILIM(MIN) Leading Edge Blanking Time (Main) tLEB(D) TJ = 25 °C 150 ns Leading Edge Blanking Time (Standby) tLEB(DSB) TJ = 25 °C See Note D 170 215 ns Current Limit Delay (Main) tILD(D) TJ = 25 °C 150 ns

Rev. B 04/15 TFS7701-7708 www.power.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 °C to 100 °C (Unless Otherwise Specified) Min Typ Max Units General Circuit Protection (cont.) Current Limit Delay (Standby) tILD(DSB) TJ = 25 °C 150 ns Thermal Shutdown Temperature TSD See Note D 118 °C Thermal Shutdown Hysteresis TSD(HYST) 55 °C Auto-Restart ON-Time at fOSC Standby tAR TJ = 25 °C 64 ms Auto-Restart Duty Cycle Standby DCAR TJ = 25 °C 2.2 % Supply Current DRAIN Supply Current IS1 EN Current > IDIS (No MOSFETs Switching) 200 550 800 mA IS2 EN Open (Standby MOSFET Switching at fOSC) 360 710 960 NOTES: A. VDDH(SHUNT) minus VDDH(UV_ON) is equal to 250 mV minimum. B. Level 1 RFB = open, Level 2 RFB = 511 kW, Level 3 RFB = 232 kW. C. Level 1 REN = open, Level 2 REN = 511 kW, Level 3 REN = 232 kW, Level 4 REN = 107 kW. D. Guaranteed by characterization. Not tested in production.

Figure 56. High-Side MOSFET (HD-HS) Power vs. Drain Voltage.

Figure 57. Heat Sink Assembly – using Thermally Conductive Silicone Grease.

Rev. B 04/15 TFS7701-7708 www.power.com PI-7080-070813 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). 6. 7. Tied to SOURCE (Pin 6). 8. Tied to HS (Pin 14). 9. 10. Tied to HD (Pin 16). 0.628 (15.95) Ref. 0.019 (0.48) Ref. 0.060 (1.52) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) 0.016 (0.41) Ref. Detail A Pin 1 0.118 (3.00) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 13×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 6 7 0.290 (7.37) Ref. 0.047 (1.19) C 0.012 (0.30) Typ. 0.101 (2.57) Ref. 0.167 (4.24) Ref. 0.235 (5.96) Ref. 0.035 (0.89) Ref. 0.010 (0.25) Typ. 0.041 (1.04) Ref. 0.020 (0.51) Ref. 1 3 5 6 7 8 9 10 11 13 14 16 0.653 (16.59) 0.647 (16.43) 0.325 (8.25) 0.320 (8.13) A B Pin 1 I.D. 0.381 (9.68) Ref. 0.076 (1.93) 0.012 (0.30) Ref. 0.201 (5.11) Ref. 0.207 (5.26) 0.187 (4.75) 13×0.024 (0.61) 0.019 (0.48) 0.010 M 0.25 M C A B 0.519 (13.18) Ref. FRONT VIEW SIDE VIEW BACK VIEW Detail A (Scale = 9×)END VIEW eSIP-16F (H Package) MOUNTING HOLE PATTERN (N.T.S) All dimensions in inches (mm) 0.152 (3.88) 5 1 0.114 (2.91) 791114 0.114 (2.91) 0.114 (2.91)0.076 (1.94) 0.076 (1.94) 0.076 (1.94) 0.114 (2.91) 381016 13 TOP END VIEW B-B Location of exposed metal tie-bars

Rev. B 04/15 TFS7701-7708 www.power.com Part Marking Information

• HiperTFS-2 Product Family
• TFS Series Number
• Package Identifier H Plastic eSIP-16F. Halogen Free and RoHS Compliant TFS 7705 H Part Ordering Information Part Number Option Quantity TFS7701H Tube 30 TFS7702H Tube 30 TFS7703H Tube 30 TFS7704H Tube 30 TFS7705H Tube 30 TFS7706H Tube 30 TFS7707H Tube 30 TFS7708H Tube 30

A Code A. 11/13 B Moved location of “output short-circuit protection (SCP)” bullet point on page 3. 04/15 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2014, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters

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