TNY174

TNY174 POWERINT | Alldatasheet

Document overview

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Technical content

Energy Efﬁ cient, Ofﬂ ine Switcher with Enhanced Flexibility and Extended Power Range Figure 1. Typical Application.

650 V rating optimized for non-active PFC applications
Simple ON/OFF control, no loop compensation needed
Selectable current limit through BP/M capacitor value - Higher current limit extends peak power or, in open frame applications, maximum continuous power - Lower current limit improves ef ﬁ ciency in enclosed adapters/chargers - Allows optimum TinySwitch-LT choice by swapping devices with no other circuit redesign
Tight I 2f parameter tolerance reduces system cost - Maximizes MOSFET and magnetics power delivery - Minimizes max overload power, reducing cost of transformer, primary clamp & secondary components
ON-time extension – extends low line regulation range/ hold-up time to reduce input bulk capacitance
Self-biased: no bias winding or bias components
Frequency jittering reduces EMI ﬁ lter costs
Pin-out simpli ﬁ es heatsinking to the PCB
SOURCE pins are electrically quiet for low EMI Enhanced Safety and Reliability Features
Accurate hysteretic thermal shutdown protection with automatic recovery eliminates need for manual reset
Auto-restart delivers <3% of maximum power in short circuit and open loop fault conditions
Output overvoltage shutdown with optional Zener
Very low component count enhances reliability and enables single-sided printed circuit board layout
High bandwidth provides fast turn on with no overshoot and excellent transient load response
Extended creepage between DRAIN and all other pins improves ﬁ eld reliability EcoSmart – Extremely Energy Efﬁ cient
Easily meets all global energy ef ﬁ ciency regulations
No-load <150 mW at 265 V AC without bias winding, <50 mW with bias winding
ON/OFF control provides constant ef ﬁ ciency down to very light loads – ideal for mandatory CEC regulations

Applications

Chargers/adapters for cell/cordless phones, PDAs, digital cameras, MP3/portable audio, shavers, etc.
DVD/PVR and other low power set top decoders
Supplies for appliances, industrial systems, metering, etc. August 2007

Table 1. Notes: 1. Minimum continuous power in a typical non- P: DIP-8C, G: SMD-8C. See Part Ordering Information.

Description

TinySwitch-LT incorporates a 650 V power MOSFET, oscillator, high voltage switched current source, current limit (user selectable) and thermal shutdown circuitry. The IC family uses an ON/OFF control scheme and offers a design ﬂ exible solution with a low system cost and extended power capability. OUTPUT POWER TABLE PRODUCT3

230 VAC ±15% 85-265 VAC

TNY174PN 6 W 11 W 5 W 8.5 W TNY175PN 8.5 W 15 W 6 W 11.5 W TNY176PN 10 W 19 W 7 W 15 W TNY177PN 13 W 23.5 W 8 W 18 W TNY178PN 16 W 28 W 10 W 21.5 W TNY179PN 18 W 32 W 12 W 25 W TNY180PN 20 W 36.5 W 14 W 28.5 W PI-4770-073107 D S EN BP/M DC Output TinySwitch-LT AC Input

Figure 2. Functional Block Diagram. Figure 3. Pin Conﬁ guration.

It is the connection point for an external bypass capacitor

for the internally generated 5.85 V supply.

It is a mode selector for the current limit value, depending

larger device size for TNY175-180.

It provides a shutdown function. When the current into

BP/M voltage drops below 4.9 V , during a power down. The switching of the power MOSFET is controlled by this pin.

1.0 V + VT

A Figure 4. Frequency Jitter. for high voltage power return and control circuit common. TinySwitch-LT combines a high voltage power MOSFET switch with a power supply controller in one device. Unlike conventional PWM (pulse width modulator) controllers, it uses a simple ON/OFF control to regulate the output voltage. The controller consists of an oscillator, enable circuit (sense and logic), current limit state machine, 5.85 V regulator, BYPASS/ MULTI-FUNCTION pin undervoltage, overvoltage circuit, and current limit selection circuitry, over- temperature protection, current limit circuit, leading edge blanking, and a 700 V power MOSFET. TinySwitch-LT incorporates additional circuitry for auto-restart, adaptive switching cycle on-time extension, and frequency jitter. Figure 2 shows the functional block diagram with the most important features. Oscillator The typical oscillator frequency is internally set to an average of 132 kHz. Two signals are generated from the oscillator: the maximum duty cycle signal (DC MAX) and the clock signal that indicates the beginning of each cycle. The oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 8 kHz peak-to-peak, to minimize EMI emission. The modulation rate of the frequency jitter is set to 1 kHz to optimize EMI reduction for both average and quasi-peak emissions. The frequency jitter should be measured with the oscilloscope triggered at the falling edge of the DRAIN waveform. The waveform in Figure 4 illustrates the frequency jitter. Enable Input and Current Limit State Machine The enable input circuit at the EN pin consists of a low impedance source follower output set at 1.2 V . The current through the source follower is limited to 115 μA. When the current out of this pin exceeds the threshold current, a low logic level (disable) is generated at the output of the enable circuit, until the current out of this pin is reduced to less than the threshold current. This enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled). If low, the power MOSFET remains off (disabled). Since the sampling is done only at the beginning of each cycle, subsequent changes in the EN pin voltage or current during the remainder of the cycle are ignored. The current limit state machine reduces the current limit by discrete amounts at light loads when TinySwitch-LT is likely to switch in the audible frequency range. The lower current limit raises the effective switching frequency above the audio range and reduces the transformer ﬂ ux density, including the associated audible noise. The state machine monitors the sequence of enable events to determine the load condition and adjusts the current limit level accordingly in discrete amounts. Under most operating conditions (except when close to no-load), the low impedance of the source follower keeps the voltage on the EN pin from going much below 1.2 V in the disabled state. This improves the response time of the optocoupler that is usually connected to this pin. 5.85 V Regulator and 6.4 V Shunt Voltage Clamp The 5.85 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.85 V by drawing a current from the voltage on the DRAIN pin whenever the MOSFET is off. The BYPASS/MULTI-FUNCTION pin is the internal supply voltage node. When the MOSFET is on, the device operates from the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows TinySwitch-LT to operate continuously from current it takes from the DRAIN pin. A bypass capacitor value of 0.1 μF is sufﬁ cient for both high frequency decoupling and energy storage. In addition, there is a 6.4 V shunt regulator clamping the BYPASS/MULTI-FUNCTION pin at 6.4 V when current is provided to the BYPASS/MULTI-FUNCTION pin through an external resistor. This facilitates powering of TinySwitch-LT externally through a bias winding to decrease the no-load consumption to well below 50 mW. 600 05 1 0 136 kHz 128 kHz VDRAIN Time (μs) PI-2741-041901 500 400 300 200 100

Figure 5. Auto-Restart Operation. to 5.85 V to enable (turn-on) the power MOSFET. board due to a continuous fault condition. The current limit circuit senses the current in the power MOSFET. by discrete amounts under medium and light loads. circuit operation in the presence of an output short circuit. less than the reference voltage. a Zener diode across the DC output voltage to be regulated. optocoupler LED will start to conduct, pulling the EN pin low.

A Applications Example The circuit shown in Figure 12 is a low cost, high ef ﬁ ciency, ﬂ yback power supply designed for 12 V , 1 A output from universal input using the TNY178. The supply features primary sensed output overvoltage latching shutdown protection, high efﬁ ciency (>80%), and very low no- load consumption (<50 mW at 265 VAC). Output regulation is accomplished using a simple zener reference and optocoupler feedback. The rectiﬁ ed and ﬁ ltered input voltage is applied to the primary winding of T1. The other side of the transformer primary is driven by the integrated MOSFET in U1. Diode D5, C2, R1, R2, and VR1 comprise the clamp circuit, limiting the leakage inductance turn-off voltage spike on the DRAIN pin to a safe value. The use of a combination a Zener clamp and parallel RC optimizes both EMI and energy ef ﬁ ciency. Resistor R2 allows the use of a slow recovery, low cost, rectiﬁ er diode by limiting the reverse current through D5. The selection of a slow diode also improves ef ﬁ ciency and conducted EMI but should be a glass passivated type, with a speci ﬁ ed recovery time of ≤2 μs. The output voltage is regulated by the Zener diode VR3. When the output voltage exceeds the sum of the Zener and optocoupler LED forward drop, current will ﬂ ow in the optocoupler LED. This will cause the transistor of the optocoupler to sink current. When this current exceeds the ENABLE pin threshold current the next switching cycle is inhibited. When the output voltage falls below the feedback threshold, a conduction cycle is allowed to occur and, by adjusting the number of enabled cycles, output regulation is maintained. As the load reduces, the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. This provides almost constant efﬁ ciency down to very light loads, ideal for meeting energy efﬁ ciency requirements. As the TinySwitch-LT devices are completely self-powered, there is no requirement for an auxiliary or bias winding on the transformer. However by adding a bias winding, the output overvoltage protection feature can be con ﬁ gured, protecting the load against open feedback loop faults. When an overvoltage condition occurs, such that bias voltage exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION (BP/M) pin voltage (28 V+5.85 V), current begins to ﬂ ow into the BP/M pin. When this current exceeds I SD the internal latching shutdown circuit in TinySwitch-LT is activated. This condition is reset when the BP/M pin voltage drops below 2.6 V after removal of the AC input. In the example shown, on opening the loop, the OVP trips at an output of 17 V . D S S BP/M EN 1 mH 1N4007 RV1

275 VAC

3.15 A 1N4007 6.8 μF 400 V 1 μF 60 V 22 μF 400 V C10 1000 μF 25 V 2.2 nF

250 VAC

100 μF 25 V +12 V, 1 A 85-265 VAC RTN 100 nF 50 V TNY178P 10 nF 1 kV VR1 P6KE150A NC 8 1N4007GP D6 UF4003 BYV28-200 PC817A VR2 1N5255B 28 V VR3 BZX79-C11 11 V C7 is configurable to adjust U1 current limit, see circuit *R5 is optional 47 Ω 1/8 W 2 kΩ 1/8 W 390 Ω 1/8 W 20 Ω R8* 21 kΩ 1 kΩ 100 Ω 1N4007 1N4007 Ferrite Bead 3.5 × 7.6 mm PI-4773-073107 †TinySwitch-LT Figure 12. TNY178P , 12 V , 1 A Universal Input Power Supply.

A TNY174-180 For lower no-load input power consumption, the bias winding may also be used to supply the TinySwitch-LT device. Resistor R8 feeds current into the BP/M pin, inhibiting the internal high voltage current source that normally maintains the BP/M pin capacitor voltage (C7) during the internal MOSFET off time. This reduces the no-load consumption of this design from 140 mW to 40 mW at 265 V AC. In addition to the simple input pi ﬁ lter (C1, L1, C2) for differential mode EMI, this design makes use of E-Shield™ shielding techniques in the transformer to reduce common mode EMI displacement currents, and R2 and C4 as a damping network to reduce high frequency transformer ringing. These techniques, combined with the frequency jitter of TNY178, give excellent conducted and radiated EMI performance with this design achieving >12 dBμV of margin to EN55022 Class B conducted EMI limits. For design ﬂ exibility the value of C7 can be selected to pick one of the 3 current limits options in U1. This allows the designer to select the current limit appropriate for the application.

Standard current limit (I LIMIT) is selected with a 0.1 μF BP/M pin capacitor and is the normal choice for typical enclosed adapter applications.
When a 1 μF BP/M pin capacitor is used, the current limit is reduced (I LIMITred or ILIMIT-1) offering reduced RMS device currents and therefore improved ef ﬁ ciency, but at the expense of maximum power capability. This is ideal for thermally challenging designs where dissipation must be minimized.
When a 10 μF BP/M pin capacitor is used, the current limit is increased (I LIMITinc or ILIMIT+1), extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow. Further ﬂ exibility comes from the current limits between adjacent TinySwitch-LT family members being compatible. The reduced current limit of a given device is equal to the standard current limit of the next smaller device and the increased current limit is equal to the standard current limit of the next larger device. Key Application Considerations TinySwitch-LT Design Considerations Output Power Table The data sheet output power table (Table 1) represents the minimum practical continuous output power level that can be obtained under the following assumed conditions: 1. The minimum DC input voltage is 100 V or higher for

85 V AC input, or 220 V or higher for 230 V AC input or

115 V AC with a voltage doubler. The value of the input capacitance should be sized to meet these criteria for AC input designs. 2. Ef ﬁ ciency of 75%. 3. Minimum data sheet value of I 2f. 4. Transformer primary inductance tolerance of ±10%. 5. Re ﬂ ected output voltage (V OR) of 135 V . 6. V oltage only output of 12 V with a fast PN rectiﬁ er diode. 7. Continuous conduction mode operation with transient KP* value of 0.25. 8. Increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns. 9. The part is board mounted with SOURCE pins soldered to a sufﬁ cient area of copper and/or a heatsink is used to keep the SOURCE pin temperature at or below 110 °C. 10. Ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters. *Below a value of 1, K P is the ratio of ripple to peak primary current. To prevent reduced power capability due to premature termination of switching cycles a transient K P limit of ≥0.25 is recommended. This prevents the initial current limit (I INIT) from being exceeded at MOSFET turn on. For reference, Table 2 provides the minimum practical power delivered from each family member at the three selectable current limit values. This assumes open frame operation (not thermally limited) and otherwise the same conditions as listed above. These numbers are useful to identify the correct current limit to select for a given device and output power requirement. Overvoltage Protection The output overvoltage protection provided by TinySwitch-LT uses an internal latch that is triggered by a threshold current of approximately 5.5 mA into the BP/M pin. In addition to an internal ﬁ lter, the BP/M pin capacitor forms an external ﬁ lter providing noise immunity from inadvertent triggering. For the bypass capacitor to be effective as a high frequency ﬁ lter, the capacitor should be located as close as possible to the SOURCE and BP/M pins of the device. For best performance of the OVP function, it is recommended that a relatively high bias winding voltage is used, in the range of 15 V-30 V . This minimizes the error voltage on the bias winding due to leakage inductance and also ensures adequate voltage during no-load operation from which to supply the BP/M pin for reduced no-load consumption. Selecting the Zener diode voltage to be approximately 6 V above the bias winding voltage (28 V for 22 V bias winding)

adjusted to compensate for variations in leakage inductance. Figure 12. The resistor in series with the OVP Zener also limits the maximum current into the BP/M pin. of the resistor to give the lowest no-load consumption. can generate audio frequency components in the transformer. samples before approving the design. dielectric or construction, for example a ﬁ lm type. to the area of copper connected to the SOURCE pins. to the BP/M and SOURCE pins. should be kept as small as possible. Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.

frame and provide the main path to remove heat from the device. the PCB area connected to the cathode. between the negative terminals of the input ﬁ lter capacitors. optocoupler to prevent noise pick up. the power range and particularly in standby/no-load conditions. pads close to the EN pin such as the BP/M pin solder pad. Figure 13. Recommended Circuit Board Layout for TinySwitch-LT with Undervoltage Lock Out Resistor.

A pollution degree environment, then an optional 390 kΩ resistor should be added from EN pin to SOURCE pin to ensure that the parasitic leakage current into the EN pin is low. Note that typical values for surface insulation resistance (SIR) where no-clean ﬂ ux has been applied according to the suppliers’ guidelines are >>10 MΩ and do not cause this issue. Quick Design Checklist As with any power supply design, all TinySwitch-LT designs should be veriﬁ ed on the bench to make sure that component speciﬁ cations are not exceeded under worst case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that the worst case V DS does not exceed 650 V at highest input voltage and peak (overload) output power. 2. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at startup. Repeat under steady state conditions and verify that the leading edge current spike event is below I LIMIT(Min) at the end of the tLEB(Min). Under all conditions, the maximum drain current should be below the speci ﬁ ed absolute maximum ratings. 3. Thermal Check – At speci ﬁ ed maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature speciﬁ cations are not exceeded for TinySwitch-LT, transformer, output diode, and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the R DS(ON) of TinySwitch-LT as speciﬁ ed in the data sheet. Under low line, maximum power, a maximum TinySwitch-LT SOURCE pin temperature of 110 °C is recommended to allow for these variations.

A TNY174-180 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Speciﬁ ed) Min Typ Max Units CONTROL FUNCTIONS Output Frequency in Standard Mode fOSC TJ = 25 °C See Figure 4 Average 124 132 140 kHz Peak-to-peak Jitter 8 Maximum Duty Cycle DCMAX S1 Open 62 65 % EN Pin Upper Turnoff Threshold Current IDIS -150 -115 -90 μA EN Pin Voltage VEN IEN = 25 μA 1.8 2.2 2.6 V IEN = -25 μA 0.8 1.2 1.6 DRAIN Supply Current IS1 EN Current > IDIS (MOSFET Not Switching) See Note A 290 μA IS2 EN Open (MOS- FET Switching at fOSC) See Note B TNY174PN 275 360 μA TNY175PN 295 400 TNY176PN 310 430 TNY177PN 365 460 TNY178PN 445 540 TNY179PN 510 640 TNY180PN 630 760 ABSOLUTE MAXIMUM RATINGS(1,5) Operating Junction Temperature Notes: 1. All voltages referenced to SOURCE, T A = 25 °C. 2. The higher peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V . 3. Normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. Maximum ratings speci ﬁ ed may be applied one at a time, without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. THERMAL IMPEDANCE Thermal Impedance: P Package: ( θ Notes: 1. Measured on the SOURCE pin close to plastic interface. 2. Soldered to 0.36 sq. in. (232 mm 2), 2 oz. (610 g/m2) copper clad.

A Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Speciﬁ ed) Min Typ Max Units CONTROL FUNCTIONS (cont.) BP/M Pin Charge Current ICH1 VBP/M = 0 V, TJ = 25 °C See Note C, D mA ICH2 VBP/M = 4 V, TJ = 25 °C See Note C, D BP/M Pin Voltage VBP/M See Note C 5.6 5.85 6.15 V BP/M Pin Voltage Hysteresis VBP/MH 0.80 0.95 1.20 V BP/M Pin Shunt Voltage VSHUNT IBP = 2 mA 6.0 6.4 6.7 V CIRCUIT PROTECTION Standard Current Limit (BP/M Capacitor = 0.1 μF) See Note D ILIMIT di/dt = 50 mA/μs TJ = 25 °C See Note E TNY174PN 233 250 267 mA di/dt = 55 mA/μs TJ = 25 °C See Note E TNY175PN 256 275 294 di/dt = 70 mA/μs TJ = 25 °C See Note E TNY176PN 326 350 374 di/dt = 90 mA/μs TJ = 25 °C See Note E TNY177PN 419 450 481 di/dt = 110 mA/μs TJ = 25 °C See Note E TNY178PN 512 550 588 di/dt = 130 mA/μs TJ = 25 °C See Note E TNY179PN 605 650 695 di/dt = 150 mA/μs TJ = 25 °C See Note E TNY180PN 698 750 802

A TNY174-180 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Speciﬁ ed) Min Typ Max Units CIRCUIT PROTECTION (cont.) Reduced Current Limit (BP/M Capacitor = 1 μF) See Note D ILIMITred di/dt = 50 mA/μs TJ = 25 °C See Note E TNY174PN 196 210 233 mA di/dt = 55 mA/μs TJ = 25 °C See Note E TNY175PN 233 250 277 di/dt = 70 mA/μs TJ = 25 °C See Notes E TNY176PN 256 275 305 di/dt = 90 mA/μs TJ = 25 °C TNY177PN 326 350 388 di/dt = 110 mA/μs TJ = 25 °C See Notes E TNY178PN 419 450 499 di/dt = 130 mA/μs TJ = 25 °C See Notes E TNY179PN 512 550 610 di/dt = 150 mA/μs TJ = 25 °C See Notes E TNY180P 605 650 721 Increased Current Limit (BP/M Capacitor = 10 μF) See Note D ILIMITinc di/dt = 50 mA/μs TJ = 25 °C See Notes E, F TNY174PN 196 210 233 mA di/dt = 55 mA/μs TJ = 25 °C See Notes E TNY175PN 326 350 388 di/dt = 70 mA/μs TJ = 25 °C See Notes E TNY176PN 419 450 499 di/dt = 90 mA/μs TJ = 25 °C See Notes E TNY177PN 512 550 610 di/dt = 110 mA/μs TJ = 25 °C See Notes E TNY178PN 605 650 721 di/dt = 130 mA/μs TJ = 25 °C See Notes E TNY179PN 698 750 833 di/dt = 150 mA/μs TJ = 25 °C See Notes E TNY180PN 791 850 943

A Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Speciﬁ ed) Min Typ Max Units CIRCUIT PROTECTION (cont.) Power Coefﬁ cient I2f Standard Current Limit, I2f = ILIMIT(TYP) × fOSC(TYP) TNY174-180PN 0.9 × I2f I2f 1.12 × I2f A2Hz Reduced Current Limit, I2f = ILIMITred(TYP) × fOSC(TYP) TNY174-180PN 0.9 × I2f I2f 1.16 × I2f Increased Current Limit, I2f = ILIMITinc(TYP) × fOSC(TYP) TNY174-180PN 0.9 × I2f I2f 1.16 × I2f Initial Current Limit IINIT See Figure 19 TJ = 25 °C, See Note G 0.75 × ILIMIT(MIN) mA Leading Edge Blanking Time tLEB TJ = 25 °C See Note G 170 215 ns Current Limit Delay tILD TJ = 25 °C See Note G, H 150 ns Thermal Shut- down Temperature TSD 135 142 150 °C Thermal Shut- down Hysteresis TSDH 75 °C BP/M Pin Shut- down Threshold Current ISD 4 6.5 9 mA BP/M Pin Power up Reset Thresh- old Voltage VBP/M(RESET) 1.6 2.6 3.6 V OUTPUT ON-State Resistance RDS(ON) TNY174PN ID = 25 mA TJ = 25 °C2 8 3 2 Ω TJ = 100 °C4 2 4 8 TNY175PN ID = 28 mA TJ = 25 °C1 9 2 2 TJ = 100 °C2 9 3 3 TNY176PN ID = 35 mA TJ = 25 °C1 4 1 6 TJ = 100 °C2 1 2 4

A TNY174-180 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 14 (Unless Otherwise Speciﬁ ed) Min Typ Max Units OUTPUT (cont.) ON-State Resistance RDS(ON) TNY177PN ID = 45 mA TJ = 25 °C 7.8 9.0 Ω TJ = 100 °C 11.7 13.5 TNY178PN ID = 55 mA TJ = 25 °C 5.2 6.0 TJ = 100 °C 7.8 9.0 TNY179PN ID = 65 mA TJ = 25 °C 3.9 4.5 TJ = 100 °C 5.8 6.7 TNY180PN ID = 75 mA TJ = 25 °C 2.6 3.0 TJ = 100 °C 3.9 4.5 OFF-State Drain Leakage Current IDSS1 VBP/M = 6.2 V VEN = 0 V VDS = 520 V TJ = 125 °C See Note I TNY174-176 50 μATNY177-178 100 TNY179-180 200 IDSS2 VBP/M = 6.2 V VEN = 0 V VDS = 375 V, TJ = 50 °C See Note G, I Breakdown Voltage BVDSS VBP = 6.2 V, VEN = 0 V, See Note J, TJ = 25 °C 650 V DRAIN Supply Voltage 50 V Auto-Restart ON-Time at f OSC tAR TJ = 25 °C See Note K 64 ms Auto-Restart Duty Cycle DCAR TJ = 25 °C3 %

A NOTES: A. I S1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2. B Since the output MOSFET is switching, it is difﬁ cult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BP/M pin current at 6.1 V. C. BP/M pin is not intended for sourcing supply current to external circuitry. D. To ensure correct current limit it is recommended that nominal 0.1 μF / 1 μF / 10 μF capacitors are used. In addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. E. For current limit at other di/dt values, refer to Figure 21. F. TNY174 does not set an increased current limit value, but with a 10 μF BP/M pin capacitor the current limit is the same as with a 1 μF BP/M pin capacitor (reduced current limit value). G. This parameter is derived from characterization. H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I LIMIT speciﬁ cation. I. IDSS1 is the worst case OFF state leakage speciﬁ cation at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical speciﬁ cation under worst case application conditions (rectiﬁ ed 265 VAC) for no-load consumption calculations. J. Breakdown voltage may be checked against minimum BVDSS speciﬁ cation by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). Nominal BP/M Pin Cap Value Tolerance Relative to Nominal Capacitor Value Min MAX 0.1 μF -60% +100% 1 μF -50% +100% 10 μF -50% NA

Figure 15. Duty Cycle Measurement. Figure 16. Output Enable Timing. Figure 14. General Test Circuit. Figure 17. Current Limit Envelope.

5 W S2

NOTE: This test circuit is not applicable for current limit or output characteristic measurements.

Figure 24. Drain Capacitance Power.

A Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clock- wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) MINIMUM .048 (1.22) .053 (1.35) .100 (2.54) BSC .014 (.36) .022 (.56) -E- Pin 1 SEATING PLANE -D- -T- P08C DIP-8C PI-3933-100504 D S .004 (.10)⊕ T E D S .010 (.25) M⊕ (NOTE 6) .137 (3.48) MINIMUM PART ORDERING INFORMATION TinySwitch-LT Product Family Series Number Package Identiﬁ er P Plastic DIP-8C Lead Finish N Pure Matte Tin (Pb-Free) TNY 178 P N

A TNY174-180 Revision Notes Date A Initial Release 08/07 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY , FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents LIFE SUPPORT POLICY POWER INTEGRATIONS’ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signi ﬁ cant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, Clampless, EcoSmart, E-Shield, Filterfuse, StackFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2006, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations WORLD HEADQUARTERS

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20091 Bresso MI – Italy

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51 Newton Road

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Summary

Energy Effi cient, Offl ine Switcher with Enhanced Flexibility and Extended Power Range

Description

Energy Effi cient, Offl ine Switcher with Enhanced Flexibility and Extended Power Range

Source title TNY174 Datasheet(PDF) - Power Integrations, Inc.

Read TNY174 online.

TNY174 POWERINT | Alldatasheet

Document overview

Technical content

Applications

Description

230 VAC ±15% 85-265 VAC

1.0 V + VT

275 VAC

250 VAC

85 V AC input, or 220 V or higher for 230 V AC input or

5 W S2

5245 Hellyer Avenue

20091 Bresso MI – Italy

51 Newton Road

TNY174 specifications and overview.

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