TMD4903

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[v1-12] 2015-May-14 Document Feedback TMD4903 Color and Proximity Sensor Module with mobeam™ Barcode Emulation and IR Remote Control The TMD4903 features ambient light and color (RGB) sensing, proximity detection and IRBeam optical pattern generator capable of mobeam™ barcode emul ation and IR remote control. In addition, the device integrates an IR LED and advanced LED driver, all within a low-profile and small footprint, 2.0mm x 5.0mm x 1.0mm package. The Proximity sensing function synchronizes IR emission and detection to sense proximity events. The architecture of the engine features self-maximizing dynamic range, ambient light subtraction, advanced crosstalk cancelation, 14-bit data output, 32-dataset FIFO, and interrupt-driven I²C communication. Sensitivity, powe r consumption, and noise can be optimized with adjustable IR LED timing and power. The proximity engine recognizes detect/release events and produces a configurable interru pt whenever proximity result crosses upper or lower threshold settings. The Ambient Light and Color Sensing function provides Red, Green, and Blue (RGB) ambien t light sensing with a Clear reference (C). The color diode array has a UV/IR blocking filter and parallel ADCs to produce simultaneous 16-bit results. This architecture accurately measures ambient light and enables the calculation of illuminance, chromaticity, and color temperature to manage display appearance. The IRBeam pattern generato r supports mobeam™ barcode emulation and IR remote control. The engine features RAM for pattern storage and specialized control logic that is tailored to repetitively broadcast a barcode pattern using the integrated LED or an external LED with a low side driver. The IRBeam engine features adjustable timing, looping, and IR intensity to maximize successful transmission. IRBeam is designed to support all requirements for 1-D barcode transmission over IR to point-of-sale (POS) terminals as well as IR remote control. Ordering Information and Content Guide appear at end of datasheet. General Description

Document Feedback [v1-12] 2015-May-14 TMD4903 − General Description Key Benefits & Features The benefits and features of TMD4903, Color and Proximity Sensor Module with mobeam™ Barcode Emulation and IR Remote Control are listed below: Figure 1: Added Value of Using TMD4903

Applications

The TMD4903 applic ations include:

• Color sensing
• Ambient light sensing
• Cell phone touch screen disable
• Mechanical switch replacement
• 1D barcode emulation
• Universal remote control Benefit Feature Proximity detection
• Selectable direction sensitivity
• Ambient light rejection
• Advanced crosstalk compensation
• AFE saturation flag
• Programmable LED driver
• Interrupt-Driven I²C communication Ambient light and color sensing
• Variable sensitivity
• Designed to operate behind inked glass
• UV/IR blocking filter
• Programmable gain and integration time
• 6.7M:1 dynamic range by gain adjustment only
• Interrupt-driven I²C communication IRBeam pattern generator
• mobeam™ support
• Universal remote control support
• Interrupt-driven I²C communication Integrated LED and driver • Calibrated emission and response
• Invisible 950nm emission Low supply voltage • 1.8V operation

[v1-12] 2015-May-14 Document Feedback TMD4903 − General Description Block Diagram The functional blocks of this device for reference are shown below: Figure 2: TMD4903 Block Diagram TMD4903 /g115/g24/g24 /g115/g24/g24 /g39/g69/g24 I2C/g94/g24/g4 /g94/g18/g62 /g75/g94/g18/g47/g62/g62/g4/g100/g75/g90 /g47/g90/g17/g286/g258/g373/g3 /g87/g258/g410/g410/g286/g396/g374/g3 /g39/g286/g374/g286/g396/g258/g410/g381/g396 /g18/g381/g367/g381/g396 /g4/g62/g94 /g90/g286/g282 /g39/g396/g286/g286/g374 /g17/g367/g437/g286 /g18/g367/g286/g258/g396 /g69/g381/g396/g410/g346 /g94/g381/g437/g410/g346 /g116/g286/g400/g410 /g28/g258/g400/g410 /g87/g396/g381/g454/g349/g373/g349/g410/g455/g3 /g28/g374/g336/g349/g374/g286 /g87/g437/g367/g400/g286/g3/g18/g381/g374/g410/g396/g381/g367 /g62/g28/g24/g4 /g62/g24/g90

256 Byte FIFO

(2048 Bit Pattern RAM) /g90/g286/g336/g349/g400/g410/g286/g396/g400 /g24/g349/g336/g349/g410/g258/g367/g3/g18/g381/g396/g286 /g47/g69/g100/g3/g38/g367/g258/g336/g400 /g1085/g62/g349/g373/g349/g410 /g882/g62/g349/g373/g349/g410 /g87/g90/g75/g121 /g1085/g62/g349/g373/g349/g410 /g882/g62/g349/g373/g349/g410 /g18/g62/g28/g4/g90 /g39/g87/g47/g75 /g47/g69/g100

Document Feedback [v1-12] 2015-May-14 TMD4903 − Pin Assignment The device pin assignments are described below. Figure 3: Pin Diagram Pin Description Figure 4: Pin Description Pin Number Pin Name Description 1 VDD Supply voltage (1.8V)

2 SCL I²C serial clock terminal

3 GND Ground. All voltages are referenced to GND

4 LEDA LED anode

5 LDR LED driver (sinks current) and LED cathode (for direct access to LED)

6 GPIO Open drain IRBeam output or alternate interrupt

7I N T Interrupt. Open drain output and logic level output for external IR LED circuit

8 SDA I²C serial data I/O terminal

R

[v1-12] 2015-May-14 Document Feedback TMD4903 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Note(s) and/or Footnote(s): 1. All voltages with respect to GND 2. Measured with LDR = OFF or LDR = ON and LDRIVE = 310mA. Symbol Parameter Min Max Units Comments VDD Supply voltage -0.3 2.2 V VLEDA LED anode supply -0.3 3.6 V VIO Digital I/O terminal voltage -0.3 3.6 V VLDR Terminal voltage -0.3 3.6 V see note (2) IIO Output terminal current -1 20 mA Tstg Storage temperature range -40 85 ºC ESDHBM ESD tolerance, human body model ±2000 V Absolute Maximum Ratings

[v1-12] 2015-May-14 Document Feedback TMD4903 − Electrical Characteristics Figure 8: ALS/Color Operating Characteristics, VDD = 1.8 V, TA = 25ºC, AGAIN = 16x, ATIME = 0xF6 (unless otherwise noted) Note(s) and/or Footnote(s): 1. Integration time is configured from 1 step (0xFF) to 256 st eps (0x00) for a typical range of 2.78ms to 711.11ms. An ATIME se tting of 0xFF results in a full-scale count value of 1024. Each additional integration step adds 1024 counts to full scale. To enable 16 -bit ADC range, 64 or more integration steps (177.8ms or more) are required (ATIME <= 0xC0). 2. The typical 3-sigma distribution is between 0 and 1 count for an AGAIN setting of 16x. 3. Lux accuracy is function of red, green, blue and clear channels, and not 100% production tested. 4. ADC noise is calculated as the standard deviation of 1000 data samples. Parameter Conditions Min Typ Max Units Integration time step size(1), (2) 2.68 2.78 2.90 ms Dark ADC count value (2) Ee = 0 μW/ cm2 AGAIN: 64x ATIME: 100ms (0xDC) 01 3 c o u n t s Gain scaling, relative to 16x gain setting AGAIN: 1/4x 0.0135 0.0175 x AGAIN: 1x 0.058 0.067 AGAIN: 4x 0.237 0.263 AGAIN: 64x 3.75 4.37 Clear channel irradiance responsivity White LED, 2700K 8.94 10.28 11.62 counts/ (μW/ cm Lux accuracy (3) White LED, 2700K 90 100 110 % ADC Noise (4) AGAIN: 16x 0.005 % Full Scale

Document Feedback [v1-12] 2015-May-14 TMD4903 − Electrical Characteristics Figure 9: Color Ratio Characteristics, VDD = 1.8V, TA = 25ºC Note(s) and/or Footnote(s): 1. The 465 nm input irradiance is supplied by an InGaN light-em itting diode with the following characteristics: dominant wavele ngth λD = 465 nm, spectral halfwidth Δλ½ = 22 nm. 2. The 525 nm input irradiance is supplied by an InGaN light-em itting diode with the following characteristics: dominant wavele ngth λD = 525 nm, spectral halfwidth Δλ½ = 35 nm. 3. The 615 nm input irradiance is supplied by an AlInGaP light- emitting diode with the following characteristics: dominant wave length λD = 615 nm, spectral halfwidth Δλ½ = 15 nm. Parameter Test Conditions Ratio of Color to Clear Channel Red Channel Green Channel Blue Channel Min Max Min Max Min Max Color ADC count value ratio: Color/Clear White LED, 2700 K 45% 65% 19% 39% 15% 40% λD = 465 nm (1) 0% 15% 10% 42% 70% 90% λD = 525 nm (2) 4% 25% 60% 85% 10% 45% λD = 615 nm (3) 80% 110% 0% 14% 5% 24%

[v1-12] 2015-May-14 Document Feedback TMD4903 − Electrical Characteristics Figure 10: Proximity Operating Characteristics, VDD = 1.8 V, TA = 25ºC (unless otherwise noted) Note(s) and/or Footnote(s): 1. Offset varies with power supply characteristics and system noise. 2. Production tested result is the average of 5 readings expressed relative to a calibrated response. 3. Representative result by characterization . Device settings can vary from 1 to 64 pulse count, 4μs to 32μs pulse width, 10mA to 310mA current setting, and 1x to 8x electrical gain. Refer to Figure 22 for device performance with different settings. 4. Production tested result is the range of 20 readings divided by the average response. Parameter Conditions Min Typ Max Unit ADC conversion time step size 20 μs Offset (no target response) (1) PGAIN = 2 (4x) PGLDRIVE = 7 (150mA) PGPULSE_LEN = 1 (8us) No target present After electrical calibration 16 36 counts Part to part variation (2) PGAIN = 2 (4x) PGLDRIVE = 1 (30mA) PGPULSE_LEN = 1 (8us) d=23mm round target 30mm target distance After electrical calibration 75 100 125 % Response, absolute (3) PGAIN = 2 (4x) PGLDRIVE = 7 (150mA) PGPULSE_LEN = 1 (8us) 100x100mm, 90% reflective Kodak gray card 100mm target distance After electrical calibration 790 990 1190 counts Noise/Signal (4) PGAIN = 2 (4x) PGLDRIVE = 2 (50mA) PGPULSE_LEN = 1 (8us) PGPULSE = 7 (8 pulses)

[v1-12] 2015-May-14 Document Feedback TMD4903 − Typical Operating Characteristics Figure 22: Proximity Response vs. Target Distance Counts Distance - cm 2000 4000 6000 8000 10000 12000 14000 16000 18000 0 5 10 15 20 TMD4903 Proximity Response by Pulse Width 4µs 8µs 16µs 32µs PGAIN =2 (4x), PGLDRIVE = 7 (150mA), 100x100mm, 90% Reflective Kodak gray card

Document Feedback [v1-12] 2015-May-14 TMD4903 − I²C Protocol The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and both standard and full-speed cl ock frequency modes. Read and Write transactions comply with th e standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (I.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general it is recommended to use I²C bursts whenever possible, especially in this ca se when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors. I²C Write Transaction A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP . Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP . I²C Read Transaction A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP . The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification. I²C Protocol

[v1-12] 2015-May-14 Document Feedback TMD4903 − I²C Protocol Figure 23: Simplified State Diagram /g87/g4/g90/g4/g62/g62/g28/g62 /g38/g104/g69/g18/g100/g47/g75/g69/g94 /g87/g28/g69 /g4/g28/g69 /g47/g17/g28/g69/g3/g894/g1005/g895 /g47/g17/g28/g69/g3/g894/g1005/g895 /g47/g24/g62/g28 /g4/g62/g94/g876 /g18/g75/g62/g75/g90 /g87/g90/g75/g121/g47/g68/g47/g100/g122/g3 /g18/g4/g62/g47/g17/g90/g4/g100/g47/g75/g69 /g47/g90/g17/g28/g4/g68 /g87/g90/g75/g121/g47/g68/g47/g100/g122 /g47/g1006/g18 /g47/g17/g28/g69/g3/g894/g1005/g895 /g94/g62/g28/g28/g87 /g87/g75/g69 /g47/g1006/g18 /g373/g381/g271/g286/g258/g373/g929/g3 /g100/g90/g4/g69/g94/g68/g47/g94/g94/g47/g75/g69 /g90/g28/g68/g18/g75/g69/g3 /g100/g90/g4/g69/g94/g68/g47/g94/g94/g47/g75/g69 /g1004 /g1004 /g1004 /g1005 /g1005 /g1005 /g1005 /g1005 /g1004 /g1004

Document Feedback [v1-12] 2015-May-14 TMD4903 − I²C Protocol Figure 24: Detailed State Diagram Note(s) and/or Footnote(s): 1. While IRBeam is enabled (IBEN = 1) , PROXIMITY is disabled automatically. /g4/g62/g94/g876/g18/g75/g62/g75/g90/g18/g4/g62/g47/g17/g90/g4/g100/g47/g75/g69/g87/g90/g75/g121/g47/g68/g47/g100/g122 /g47/g69/g100/g28/g90/g90/g104/g87/g100/g47/g90/g17/g28/g4/g68 /g87/g75/g90 /g47/g69/g47/g100/g47/g4/g62/g47/g127/g28 /g894/g1006/g1004/g1004/g1106/g400/g895/g3 /g87/g75/g69/g3/g1089/g3/g1005/g845/g94/g62/g28/g28/g87SAI = 1? /g28/g121/g47/g100/g3/g94/g62/g28/g28/g87/g122 /g47/g24/g62/g28 /g4/g28/g69/g3/g1089/g3/g1005/g4/g28/g69/g3/g1089/g3/g1004 /g4/g104/g100/g75/g127/g28/g90/g75 /g894/g286/g448/g286/g396/g455/g3/g374/g410/g346/g3/g410/g349/g373/g286/g895 /g47/g69/g100/g28/g39/g90/g4/g100/g28 /g894/g4/g100/g47/g68/g28/g895/g18/g90/g39/g17/g3/g24/g4/g100/g4 /g116/g4/g47/g100 /g894/g116/g100/g47/g68/g28/g895 /g47/g17/g28/g69/g3/g1089/g3/g1005 /g47/g1006/g18 /g47/g17/g28/g69/g3/g1089/g3/g1004 /g18/g75/g69/g38/g47/g39/g104/g90/g28 /g68/g75/g17/g28/g4/g68 /g75/g90 /g90/g28/g68/g18/g75/g69 /g94/g100/g4/g69/g24/g17/g122 /g100/g90/g4/g69/g94/g68/g47/g94/g94/g47/g75/g69/g3 /g18/g75/g68/g87/g62/g28/g100/g28/g39/g28/g69/g28/g90/g4/g100/g28/g3 /g47/g69/g100/g28/g90/g90/g104/g87/g100 /g47/g1006/g18 /g104/g87/g24/g4/g100/g28 /g94/g100/g4/g100/g104/g94 EVALUATE: INTERRUPT? /g69 /g122 /g69 /g122 /g69 /g39/g28/g69/g28/g90/g4/g100/g28/g3/g87/g4/g100/g100/g28/g90/g69 /g24/g75/g69/g28 /g18/g4/g62/g47/g17/g90/g4/g100/g28/g3/g75/g38/g38/g94/g28/g100/g94 /g94/g28/g100/g3/g100/g44/g90/g28/g94/g44/g75/g62/g24/g94 /g87/g28/g69/g3/g1089/g3/g1005/g3/g87/g28/g69/g3/g1089/g3/g1004/g3 /g4/g18/g18/g104/g68/g104/g62/g4/g100/g28 /g87/g24/g4/g100/g4 /g116/g4/g47/g100 /g894/g87 /g100 /g47 /g68 /g28/g895 /g18/g62/g28/g4/g90/g3/g47/g69/g100/g28/g90/g90/g104/g87/g100/g94/g94/g100/g4/g90/g100 /g100/g68/g24/g1008/g1013/g1004/g1007/g3/g75/g393/g286/g396/g258/g410/g349/g381/g374/g258/g367/g3/g94/g410/g258/g410/g286/g400/g3

[v1-12] 2015-May-14 Document Feedback TMD4903 − Detailed Description Upon power-up, POR, the device init ializes. During initialization (typically 200μs), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed, and all outputs from the device must be ignored including interr upts. After initialization, the device enters the SLEEP state. In this operational state the internal oscillator and other circ uitry are not active, resulting in ultra-low power consumption. If I²C transaction occurs during this state, the I²C core wake up temporarily to service the communication. Once the Power ON bit, PON, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. The first time the SLEEP state is exited and any functions are enabled (PEN | AEN | IBEN = 1) an EXIT SLEEP pause occurs followed by an immediate entry into the selected engines. If all functions are disabled (PEN = 0 & AEN = 0 & IBEN = 0), the device returns to the IDLE state. As depicted in Figure 23 and Figure 24 , the proximity and CRGB color sensing functions operate in parallel when enabled (PEN | AEN = 1). The IRBeam pattern generator takes priority when enabled (IBEN = 1).Proximity will not function, and ALS integration only occurs while IRBeam is in standby. In addition, when proximity or calibration is requested, it will temporarily disable the proximity function. A simplified state diagram for each function is depicted in Figure 24 . Each function is individually configured (e.g. Gain, ADC integration time, wait time, persistence, thresholds, etc.). Sleep After Interrupt Operation If Sleep After Interrupt is enabled (SAI = 1), the state machine will enter SLEEP when non-gesture interrupts occur. However for IRBeam, the state machine remains active to continue to support this function. Entering SLEEP does not automatically change any of the register setting s (E.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP state is terminated when the SAI bit is cleared. Detailed Description

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description 0x97 RDATAH R Red ADC high data register 0x00 0x98 GDATAL R Green ADC low data register 0x00 0x99 GDATAH R Green ADC high data register 0x00 0x9A BDATAL R Blue ADC low data register 0x00 0x9B BDATAH R Blue ADC high data register 0x00 0x9C PDATAL R Proximity ADC low data register 0x00 0x9D PDATAH R Proximity ADC high data register 0x00 0x9E STATUS2 R Additional device status 0x00 0x9F CFG2 R/W Configuration register two 0x04 0xA0 ICONFIG R/W IRBeam config uration register one 0x00 0xA1 ICONFIG2 R/W IRBeam configuration register two 0x00 0xA2 ISNL R/W IRBeam symbol loops 0x00 0xA3 ISOFF R/W IRBeam delay between symbol loops 0x00 0xA4 IPNL R/W IRbeam packet loops 0x00 0xA5 IPOFF R/W IRBeam delay between packet loops 0x00 0xA6 IBT R/W IRBeam time period 0x00 0xA7 ISLEN R/W IRBeam symbol length 0x00 0xA8 ISTATUS R IRBeam status 0x00 0xA9 ISTART R/W IRBeam start transmission 0x00 0xAB CFG3 R/W Configuration register three 0x00 0xAC CFG4 R/W Configuration register four 0x07 0xAD CFG5 R/W Configuration register five 0x08 0xB3 STATUS3 R Status register three 0x00 0xBC CONTROL R/W Control register 0x00 0xBD AUXID R Auxiliary ID 0x00 0xC0 OFFSETNL R/W North channel offset low byte 0x00 0xC1 OFFSETNH R/W North channel offset high byte 0x00 0xC2 OFFSETSL R/W South channel offset low byte 0x00 0xC3 OFFSETSH R/W South channel offset high byte 0x00 0xC4 OFFSETWL R/W West channel offset low byte 0x00 Address Register Name R/W Register Function Reset Value

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description 0xC5 OFFSETWH R/W West channel offset high byte 0x00 0xC6 OFFSETEL R/W East channel offset low byte 0x00 0xC7 OFFSETEH R/W East channel offset high byte 0x00 0xD6 AZ_CONFIG R/W Configure CRGB autozero frequency 0xFF 0xD7 CALIB R/W Start offset calibration 0x00 0xD8 CALIBCFG0 R/W Calibration configuration register zero 0x44 0xD9 CALIBCFG1 R/W Calibration configuration register one 0x0C 0xDD INTENAB R/W Interrupt enable 0x00 0xDE INCLEAR R/W Interrupt clear 0x00 Address Register Name R/W Register Function Reset Value

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Enable Register (ENABLE 0x80) Enable has fields that power on the device and enable the functions. Before enabling any functions, all of the bits associated with each function mu st be set. Changing control register values while operating may result in invalid results. Figure 26: Enable Register 76543210 IBEN Reserved PIEN AIEN WEN PEN AEN PON Field Bits Description IBEN 7 IRBeam Enable. When asserted, the LED driver pin (LDR) is controlled by the IRBeam state machine. Proximity is suppressed. ALS continues in the background except when IBUSY = 1 (ISTATUS register). Reserved 6 Reserved. Bit must be set to 0. PIEN 5 Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter. AIEN 4 ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. WEN 3 Wait Enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the wait timer. PEN 2 Proximity Enable. This bit activates the proximity function. Writing a 1 enables proximity. Writing a 0 disables proximity. AEN 1 ALS Enable. This bit activates the ALS/Color functionality. Writing a 1 enables ALS/Color. Writing a 0 disables ALS/Color. PON 0 Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator and clears IBEN, PEN, and AEN. Only set this bit after all other registers have been initialized by the host.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description ALS Integration Time Register (ATIME 0x81) Figure 27: ALS Integration Time Register 76 5 4 3 2 10 ATIME Field Bits Description ATIME 7:0 ALS Integration Time. Sets the internal integration time of ALS/Color analog to digital converters in increments of 2.78ms. The power on reset value is 0xFF. The ADC maximum count (or saturation) value depends on the integration time. It is the lesser of either: 65535 (16-bit saturation) or The result of equation: Count MAX = 1024 X CYCLES VALUE INTEGRATION TIME MAX COUNTS 0xFF 2.78ms 1024 0xF6 27.8ms 10240 0xDC 100ms 36864 … 2.78ms X (256 - ATIME) … 0xC0 178ms 65535 0x00 711ms 65535

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Proximity Sample Time Register (PTIME 0x82) Figure 28: Proximity Sample Time Register 76 5 4 3 2 10 PTIME Field Bits Description PTIME 7:0 Proximity Sample Time. Sets the proximity sample rate. The power on reset value is 0x00. Proximity is executed once for each sample time. VALUE SAMPLE TIME FREQUENCY 0x00 2.78ms 360Hz 0x01 5.56ms 180Hz 0x03 11.1ms 90Hz 0x23 100ms 10Hz … 2.78ms X (PTIME +1) 1/Proximity Sample Time 0xFF 711ms 1.41Hz

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Wait Time Register (WTIME 0x83) Figure 29: Wait Time Register 76 5 4 3 2 10 WTIME Field Bits Description WTIME 7:0 Wait Time. Sets the wait time between ALS cycles. Wait mode reduces current consumption. It is set in 2.78ms increments unless the WLONG bit is asserted in which case the wait times are 12x longer. The power on reset value is 0xFF. Wait time should be configured before AEN is asserted. VALUE WAIT TIME (WLONG=0) WAIT TIME (WLONG=1) 0xFF 2.78ms 0.03sec 0xDC 100ms 1.20sec … 2.78ms X (256 - WTIME) 33.3ms X (256 - WTIME) 0x6A 417ms 5.00sec 0x00 711ms 8.53sec

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Interrupt Persistence Register (PERS 0x8C) Figure 32: Interrupt Persistence Register 7 6 543 21 0 PPERS APERS Field Bits Description PPERS 7:4 Proximity Interrupt Persistence. Defines a filter for the number of consecutive occurrences that PDATA must remain outside the threshold range between PILT and PIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE CONSECUTIVE OCCURENCES OUT OF RANGE

0 Every proximity cycle generates an interrupt

1 Generate interrupt after every occurrence. 2 Generate interrupt after 2 occurrences. ... Generate interrupt after PPERS occurrences. 15 Generate interrupt after 15 occurrences. APERS 3:0 ALS Interrupt Persistence. Defines a filter for the number of consecutive occurrences that CDATA must remain outside the threshold range between AILT and AIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE CONSECUTIVE OCCURENCES OUT OF RANGE

0 Every ALS cycle generates an interrupt

1 Generate interrupt after every occurrence. 2 Generate interrupt after 2 occurrences. 3 Generate interrupt after 3 occurrences. 4 Generate interrupt after 5 occurrences. 5 Generate interrupt after 10 occurrences. … Generate interrupt after 5 X (APERS -3) occurrences. 14 Generate interrupt after 55 occurrences. 15 Generate interrupt after 60 occurrences.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Configuration Register Zero (CFG0 0x8D) Figure 33: Configuration Register Zero 76 5 4 3 2 1 0 Reserved LOWPOWER_IDLE Reserved WLONG RAM_BANK Field Bits Description Reserved 7:6 Reserved LOWPOWER_IDLE 5 Low Power Idle. When asserted, the device will run in a low power mode if all functions are in wait states or disabled. Reserved 4:3 Reserved WLONG 2 Wait Long Enable. When asserted, the wait cycles are increased by a factor 12x. RAM_BANK 1:0 RAM Bank Selection. Specifies the RAM bank to access for IRBeam. VALUE RAM BANK ACCESS

0 Ram Bank 0 (lower 128 bytes)

1 Ram Bank 1 (upper 128 bytes)

Access is given to the 16 words at 0xB0…0xBF.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Proximity Configuration Register Zero (PGCFG0 0x8E) PGCFG0 has fields that set the am ount of time the LDR driver is sinking current during a proximity pulse and set the maximum number of pulses for each proximity sample. Figure 34: Proximity Configuration Register Zero 7 6 5 4 3 2 1 0 PGPULSE_LEN PPULSE Field Bits Description PGPULSE_LEN 7:6 Proximity Pulse Length. Sets the LED-ON pulse width during a Proximity Pulse. VALUE LED ON 04 μ s 18 μ s 21 6 μ s 33 2 μ s PPULSE 5:0 Proximity Pulse Count. Specifies the maximum number of Proximity pulses to be generated on LDR. The pulse count can be set between 1 and 64 pulses. The number of pulses is equal to the PPULSE value plus 1.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Proximity Configuration Register One (PGCFG1 0x8F) PGCFG1 has fields that set the el ectrical gain of the proximity response and set the LED drive current during pulses. Figure 35: Proximity Configuration Register One 7 6 5 4 3 210 PGGAIN Reserved PGLDRIVE Reserved Field Bits Description PGGAIN 7:6 Proximity Gain Control. VALUE GAIN VALUE 0 1x Gain 1 2x Gain 2 4x Gain 3 8x Gain Reserved 5 Reserved. Bit must be set to 0. PGLDRIVE 4:1 Proximity LED Drive Strength. Configures nominal LED current linearly in steps of 20mA (actual current depends on factory-configuration of LED drive strength). VALUE LED STRENGTH 01 0 m A 13 0 m A 25 0 m A … 10mA + (20mA * PGLDRIVE) 14 290mA 15 310mA Reserved 0 Reserved. Bit must be set to 0.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description CRGB Data Registers (0x94 − 0x9B) Red, green, blue, and clear data are stored as 16-bit values. The read sequence must read byte pairs (low followed by high) starting on an even address boundary (0x94, 0x96, 0x98, or 0x9A) inside the CRGB Data Register block. In addition, reading the Clear channel data low byte (0x94) latches all 8 data bytes. Reading these 8 bytes consecutively (0x94 - 0x9A) ensures that the data is concurrent. Figure 40: CRGB Data Registers Field Register Bits Description CDATA 0x94 7:0 Clear channel data low byte 0x95 15:8 Clear channel data high byte RDATA 0x96 7:0 Red channel data low byte 0x97 15:8 Red channel data high byte GDATA 0x98 7:0 Green channel data low byte 0x99 15:8 Green channel data high byte BDATA 0x9A 7:0 Blue channel data low byte 0x9B 15:8 Blue channel data high byte

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Proximity Data Registers (0x9C – 0x9D) Proximity data is stored as a 14 -bit value (two bytes). PDATA has a two-byte latch like 16-bit fields. Reading the low byte first latches the high byte. Proximity detection uses an Automatic Pulse Control (APC) mechanism that adjusts the number of pulses per measurement based on the magnitude of the reflected IR signal. As the magnitude of the signal increases, the number of pulses decreases. Proximity detection uses a 10-bit ADC that is extended to a 14-bit dynamic range for PDATA using the following formula: PDATA = ADC value x (16 / proximity pulses) PDATA is the average response of the non-masked proximity photodiodes. If one or more photodiodes are masked (CFG2 register 0x9F), the proximity response will remain the same since it is an average of the active photodiodes. PDATA is therefore proportional to the reflected energy per pulse, independent of the number of pulses used. Figure 41: Proximity Data Register Field Register Bits Description PDATA 0x9C 7:0 Proximity data low byte 0x9D 13:8 Proximity data high byte

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Status Register Two (STATUS2 0x9E) Figure 42: Status Register Two 7 6 5432 1 0 PVALID AVALID Reserved ASAT_ DIGITAL ASAT_ ANALOG PGSAT_ ADC PGSAT_ REFLECTIVE PGSAT_ AMBIENT Field Bits Description PVALID 7 Proximity Valid. Indicates that the proximity state has completed a cycle since either an assertion of PEN or the last readout of PDATA. AVALID 6 ALS Valid. Indicates that the ALS state has completed a cycle since either an assertion of AEN or the last readout of at least one the CDATAL register. Reserved 5 Reserved. ASAT_DIGITAL 4 ALS Digital Saturation. Indicates that the maximum counter value has been reached. Maximum counter value depends on integration time set in the ATIME register. ASAT_ANALOG 3 ALS Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit. PGSAT_ADC 2 Proximity ADC Saturation. Indicates that the maximum ADC value has occurred. PGSAT_REFLECTIVE 1 Proximity Reflective Saturation. Indicates that the intensity of reflected light has exceeded the maximum integration level for the proximity analog circuit. PGSAT_AMBIENT 0 Proximity Ambient Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the proximity analog circuit.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Configuration Register Two (CFG2 0x9F) Figure 43: Configuration Register Two 7 6543210 PMASK_E PMASK_W PMASK_S PMASK_N AMASK Reserved Field Bits Description PMASK_E 7 Proximity Mask East. Writing a 1 disables the East photodiode. PMASK_W 6 Proximity Mask West. Writing a 1 disables the West photodiode. PMASK_S 5 Proximity Mask South. Writing a 1 disables the South photodiode. PMASK_N 4 Proximity Mask North. Writing a 1 disables the North photodiode. AMASK 3 ALS Mask. Writing a 1 reduces the ALS gain by a factor of the ALS photodiode pixels. Only the center 2x2 array of pixels remains enabled out of the 4x4 array. Reduces ALS sensitivity for measurement of maximum ambient light levels. Reserved 2:0 Reserved.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description IRBeam Configuration Register (ICONFIG 0xA0) Figure 44: IRBeam Configuration Register 76543210 Reserved IIEN SLEW Reserved ISQZT Field Bits Description Reserved 7:6 Reserved IIEN 5 IRBeam Interrupt Enable. When asserted permits IRBeam interrupts to be generated. SLEW 4 Slew Rate Control. Must be set to 1. Slew rate is used to maintain LED pulse symmetry. Reserved 3 Reserved ISQZT 2:0 IRBeam Symbol Quiet Zone Time. Defines the delay between symbols as a multiple of fundamental bit-times (IBT), calculated as follows: tISQZT = nISQZT X tIBT VALUE QUIET ZONE DURATION 0 0 bit-times (Not activated) 1 5 bit-times 2 9 bit-times … n ISQZT = 2ISQZT + 1 + 1 6 129 bit-times 7 257 bit-times

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description IRBeam Configuration Register Two (ICONFIG2 0xA1) Figure 45: IRBeam Configuration Register Two 76 5 43 2 1 0 Reserved IINVERT IOUTPUT IRCDCMODE IDUTY Field Bits Description Reserved 7:6 Reserved. IINVERT 5 IRBeam Invert. If asserted, the IRBeam output is inverted. IOUTPUT 4:3 IRBeam Output Pin. Define which output pin used for IRBeam. VALUE IRBEAM OUTPUT PIN 0L D R

1 LDR (digital mode)

IRBeam Remote Control DC Mode. If asserted, the pattern is transmitted in DC mode without carrier modulation. Timing is still defined by the IBT register. IDUTY 1:0 IRBeam Duty Cycle. Define the IRBeam duty cycle. VALUE IRBEAM DUTY CYCLE 05 0 % 1 37.5% 22 5 % 3 12.5%

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Configuration Register Three (CFG3 0xAB) Figure 54: Configuration Register Three 76 5 4 3 2 1 0 Reserved LTF_USEPROX Reserved SAI Reserved Field Bits Description Reserved 7 Reserved. LTF_USEPROX 6 Use Proximity Photodiodes for ALS Measurement. Connects the IR-sensitive proximity photodiodes to the ALS engine in order to collect ALS data in the IR band. The data registers contain the following channel data depending on the LTF_USEPROX setting. 16-bit Output Registers L TF_USEPROX High Low 0 1 0x95 0x94 Clear North 0x97 0x96 Red South 0x99 0x98 Green West 0x9B 0x9A Blue East Reserved 5 Reserved. SAI 4 Sleep After Interrupt. Powers down the device at the end of a proximity/ALS cycle if an interrupt has been generated. Note that SAI does not modify any register bits directly, it rather uses the interrupt signal to turn off the oscillator. The only way to "wake up" the device from SAI-sleep is by clearing the SAI_ACTIVE flag. PON SAI INT (Low Active) Oscillator 0O f f

10 O n

1 1 0 Off (sleep after interrupt) Reserved 3:0 Reserved.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Configuration Register Four (CFG4 0xAC) Figure 55: Configuration Register Four 76 5 4 3 2 1 0 ALS_INT_ DIRECT ALS_INT_ DIRECT_GPIO PROX_INT_ DIRECT PROX_INT_ DIRECT_GPIO Reserved Field Bits Description ALS_INT_DIRECT 7 ALS Interrupt Direct. If asserted, then the INT pin shows the ALS state directly and it is not necessary to clear the interrupt. If the CLEAR data exits the threshold range from within, the INT pin is asserted. The interrupt pin is de-asserted when the CLEAR data re-enters the threshold range. As long as the CLEAR data is within the thresholds, the INT pin is not asserted. ALS_INT_DIRECT_GPIO 6 ALS Interrupt Direct on GPIO Pin. If asserted, the GPIO pin shows the ALS interrupt state directly instead of the INT pin. This function operates in the same manner otherwise as ALS_INT_DIRECT. PROX_INT_DIRECT 5 Proximity Interrupt Direct. If asserted, then the INT pin shows the proximity state directly and it is not necessary to clear the interrupt. If PDATA crosses the upper threshold from below, the INT pin is asserted. The interrupt pin is only de-asserted when PDATA crosses the lower threshold from above. As long as PDATA is below the lower threshold, the INT pin is not asserted. PROX_INT_DIRECT_GPIO 4 Proximity Interrupt Direct on GPIO Pin. If asserted, the GPIO pin shows the proximity interrupt state directly instead of the INT pin. This function operates in the same manner otherwise as PROX_INT_DIRECT. Reserved 3:0 Reserved.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Configuration Register Five (CFG5 0xAD) Figure 56: Configuration Register Five 76 5 4 3 2 1 0 Reserved LONG_LTFSTOP_ DISCARD_ALS Reserved DISABLE_IR_ CORRECTION PROX_FILTER_ DOWNSAMPLE PROX_FILTER_ SIZE PROX_ FILTER Field Bits Description Reserved 7:6 Reserved. LONG_LTFSTOP_DISCARD_ ALS 5 Long Disruption Discard ALS. Aborts ALS integration that is disrupted if the proximity state is entered (sensor field of view is obstructed) or an IRBeam transmission is executed (long disruption while LED is pulsed for an extended duration). Immediately after proximity mode is exited or IRBeam transmission is complete, a new ALS integration is started. When restarting ALS, this function ignores wait configuration, which may cause more ALS measurements to occur than expected. Reserved 4 Reserved. DISABLE_IR_CORRECTION 3 Disable IR Correction. Default is 1. If bit is 0, then calculate IR=(R+G+B-C)/2 and store R'=R-IR, G' , B' , and C' in the color DATA registers. PROX_FILTER_ DOWNSAMPLE 2 Proximity Filter Downsample. If PROX_FILTER = 1, then, if asserted, PDATA and proximity interrupt check are performed only every n proximity samples. If not asserted, then proximity filtering uses a moving window: PDATA is updated every cycle and proximity interrupt is checked every cycle. PROX_FILTER_SIZE 1 Proximity Filter Size. Determines the number of consecutive proximity samples to average to filter out noise. VALUE FILTER 02 s a m p l e s PROX_FILTER 0 Proximity Filter. If asserted, enables proximity filter functionality. Depending on PROX_FILTER_SIZE, 2 or 4 consecutive proximity samples are averaged.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Autozero Configuration Register (AZ_CONFIG 0xD6) Figure 61: Autozero Configuration Register Calibration Register (CALIB 0xD7) Figure 62: Calibration Register 76 5 4 3 2 10 AZ_NTH_ITERATION Field Bits Description AZ_NTH_ITERATION 7:0 ALS Autozero Frequency. Sets the frequency at which the device performs autozero of the ALS pulse counter. VALUE AUTOZERO FREQUENCY

0 Never

…E v e r y (AZ_NTH_ITERATION) cycles

253 Every 253 cycles

254 Every 254 cycles

255 Only once (before 1

st cycle) 765 4 32 1 0 Reserved START_OFFSET _CALIB Field Bits Description Reserved 7:1 Reserved. START_OFFSET_ CALIB 0 Start Offset Calibration. Starts the proximity offset register calibration routine. Results are stored in the Proximity Offset Registers (0xC0 – 0xC7). The CALIB_FINISHED flag is asserted when calibration is complete and an interrupt (CINT) is asserted if CIEN is set. Calibration can be stopped by writing a 0 to this field.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Calibration Configuration Register Zero (CALIBCFG0 0xD8) Figure 63: Calibration Configuration Register Zero 76 5 43 2 1 0 Reserved DCAVG_ AUTO_OFFSET_ ADJUST Reserved ELECTRICAL_ CALIBRATION BINSRCH_ SKIP DCAVG_ITERATIONS Field Bits Description Reserved 7 Reserved. DCAVG_AUTO_OFFSET_ADJUST 6 DC Averaging Auto Offset Adjust. If set, then during DC averaging, whenever an ADC measurement is zero, the appropriate offset register will be decreased and the OFFSET_ADJUSTED flag is set. Note also that DC averaging is not automatically restarted when this happens, so the calculated baseline might be wrong. Software could restart averaging in this case. Reserved 5 Reserved. ELECTRICAL_CALIBRATION 4 Enable Electrical Calibration. When asserted the calibration routine will perform an internal electrical calibration to adjust the proximity offset registers to remove electrical crosstalk – there is no optical response at all for this routine. When not asserted, calibration will measure both optical and electrical crosstalk during calibration. BINSRCH_SKIP 3 Binary Search Skip. When asserted the calibration routine will skip the binary search step. It is useful if zeroes are detected during the DC averaging process to manually reset the baseline and reduce the likelihood of zero counts.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description DCAVG_ITERATIONS 2:0 DC Averaging Iterations. Sets the number of proximity results during calibration that are averaged after the binary search is complete. During this period, whenever a result is zero, the appropriate offset register is automatically decremented. The default value is 4 (16 iterations). VALUE SAMPLES 0S k i p … n Iterations = 2DCAVG_ITERATIONS 66 4 71 2 8 Field Bits Description

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Calibration Configuration Register One (CALIBCFG1 0xD9) Figure 64: Calibration Configuration Register One 7 6 5 4 3 210 PXDCAVG_ AUTO_ GTHR PROX_ AUTO_OFFSET_ ADJUST Reserved PXDCAVG_ AUTO_ BASELINE PXDCAVG_BASELINE_WINDOW Field Bits Description PXDCAVG_AUTO_GTHR 7 Proximity Automatic Thresholds. When asserted, GTHR_IN and GTHR_OUT are automatically written with a multiple of the PBSLN every time PBSLN changes. The multiplication factor is set in AUTO_GTHR_IN_MULT. PBSLN can only change if PXDCAVG_AUTO_BASELINE is asserted and PBSLN_MEAS is less than PBSLN. PROX_AUTO_OFFSET_ADJUST 6 Proximity Auto Offset Adjust. If set, then during proximity/gesture mode, whenever an ADC measurement is zero, the appropriate offset register will be decreased. Will set the OFFSET_ADJUSTED flag if it happens. Reserved 5:4 Reserved. PXDCAVG_AUTO_BASELINE 3 Proximity Automatic Baseline. When asserted, PBSLN_MEAS is written to PBSLN whenever PBSLN_MEAS is less than PBSLN. When this happens, the BASELINE_ADJUSTED flag is raised. The default value is 1. PXDCAVG_BASELINE_WINDOW 2:0 Prox Baseline Averaging Window. Sets the number of proximity samples averaged to calculate PBSLN_MEAS, which is updated at the end of each window. The default value is 16 samples. VALUE SAMPLES 0S k i p … n Iterations = 2PXDCAVG_BASELINE_WINDOW 66 4 71 2 8

[v1-12] 2015-May-14 Document Feedback TMD4903 − Register Description Interrupt Enable Regi ster (INTENAB 0xDD) Figure 65: Interrupt Enable Register 7654321 0 ASIEN PGSIEN PIEN AIEN IIEN Reserved CIEN Reserved Field Bits Description ASIEN 7 ALS Saturation Interrupt Enable. When asserted permits ALS saturation interrupts to be generated. Bit is mirrored in the CFG1 register. PGSIEN 6 Proximity Saturation Interrupt Enable. When asserted permits proximity saturation interrupts to be generated. Bit is mirrored in the CFG1 register. PIEN 5 Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter. Bit is mirrored in the ENABLE register. AIEN 4 ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. Bit is mirrored in the ENABLE register. IIEN 3 IRBeam Interrupt Enable. When asserted permits IRBeam interrupts to be generated. Bit is mirrored in the ICONFIG register. Reserved 2 Reserved. Bit must be set to 0. CIEN 1 Calibration Interrupt Enable. When asserted permits calibration interrupts to be generated. Reserved 0 Reserved.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Register Description Interrupt Clear Register (INTCLEAR 0xDE) Figure 66: Interrupt Clear Register 7654 3 2 1 0 INTCLEAR_ ASAT INTCLEAR_ PGSAT INTCLEAR_ PINT INTCLEAR_ AINT INTCLEAR_ IINT Reserved INTCLEAR_ CINT Reserved Field Bits Description INTCLEAR_ASAT 7 Clear Interrupt: Analog Saturation. Clears the analog saturation interrupt. INTCLEAR_PGSAT 6 Clear Interrupt: Proximity Saturation. Clears the proximity saturation interrupt. INTCLEAR_PINT 5 Clear Interrupt: Proximity. Clears the proximity interrupt. INTCLEAR_AINT 4 Clear Interrupt: ALS. Clears the ALS interrupt. INTCLEAR_IINT 3 Clear Interrupt: IRBeam. Clears the IRBeam interrupt. Reserved 2 Reserved. Bit must be set to 0. INTCLEAR_CINT 1 Clear Interrupt: Calibration. Clears the calibration interrupt. Reserved 0 Reserved.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Figure 67: TMD4903 Typical Application Circuit

Application Information

/g100/g68/g24/g1008/g1013/g454/g454 /g1005 /g1006 /g1007 /g1008 /g1009 VDD GND LEDA INT SCL SDA /g1011 /g1012 LDR4.7µF 1µF >4.7µF 22/g525 VDDVBUS /g1010GPIO VDD VLED VLED

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Figure 68: TMD4903 Recommended Circuit Layout Note(s) and/or Footnote(s): 1. For best performance, all comp onents should be positioned as close as possibl e to the TMD4903. Traces and vias should be as large as possible. The proximity of the capacitors is most important.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Remote Control General Description of RC Functionality The TMD4903 is equipped with Remote Control functionality which is used to generate and transmit patterns over IR for electronic equipment (E.g. television, DVD, or audio receiver). Virtually all protocols can be accommodated by the specialized architecture of the Remote Control engine. The engine contains 256 bytes of pattern RAM and controls for carrier frequency, duty cycle and pattern repetition to easily create and broadcast a complete command waveform. The command waveform is output on a device pin allowing direct control of an external transistor and LED (pull-up resistor required). The integrated LED may also be used to output the IR waveform. Detailed Description of RC Functionality Remote Control functionality uses a digital core that is independent of the analog sensor operation. The logic internal to the digital core is activated when IBEN=1. In this operational mode the LDR pin is exclusively acquired; during this time sensor functionality will not operate. Most of the functional engines are controlled by dedicated registers; however, some devices use a “shared register” scheme. For example, this device uses address space: 0xA0 to 0xAF to also control mobeam operation. Because each functional block serves a different purpose and utilizes common on-chip resources, only one may be activated at a time.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Block Diagram of Remote Control Functionality Figure 69: Block Diagram of RC Functionality Block Diagram of RC Functionality: Resources associated with Remote Control. There are many different remote control protocols currently in use; and to meet the multitude of requirements the remote control engine has been designed to be flexible. The remote control engine consists of four major components: Pattern RAM, Timeword RAM, control registers, and pattern output pin (or integrated LED). TMD4903 I2CSDA SCL INT OSCILLATOR Remote Control Engine LEDA

256 X 8-bit

16 X 16-bit

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Pattern RAM The Pattern RAM is 256 bytes in length and is divided into two banks with 128 bytes each. Both banks must be used to enable all Pattern RAM. To access the Pattern RAM, write 0 or 1 to RAM_BANK (0x8D<0>). Functionally, the RAM is split into the MSB and LSB nibbles; each of which are used to index the Timeword RAM table. The MSB is used for “pulses” , and the LSB is used for “gaps” . Figure 70: Terminology of Pattern RAM Terminology of Pattern RAM: Pulses/Gaps, and Single/Repeated/Complete Patterns are shown. The pulse-gap pair defines when the LED is modulating or deactivated, respectively. The control logic processes the RAM locations sequentially until special operator values are encountered. “Single” sub-pattern “Repeated” sub-pattern LED Modulation First of Repeat part Second of Repeat part “Complete” Pattern Terminology Pulse Gap

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Figure 71: Pattern RAM Table Pattern RAM: Volatile memory used for storing pattern data. Note(s) and/or Footnote(s): 1. T_DATA = 0xFE is a special instruct ion. The following value in RAM becomes the start address of any repeated sub-pattern. 2. T_DATA = 0xFF is a special instruction. It identifies the end of the pattern. There are two special values that control the flow of the pattern: Stop and Repeat-destination. A Stop is signified by the value of 0xFF loaded into a pattern ram location. The value is analogous to a null character at the end of a text file. Any remaining RAM after the 0xFF operator is encountered is not executed and the pattern is finished. The Repeat-destination operator is signified by a value of 0xFE followed by the start address of any repeated sub-pattern. This value is analog ous to a “goto” statement. Once this value is encountered instruction pointer to the pattern RAM is changed to the address stored in the next pattern RAM location. These data values will not be decoded by the logic as a reference/pointer to the timeword table, that is, 0xFF will not index timeword location 15 for pulse and gap. Pattern RAM Address (Bank 0) Data (Pulse-Gap) 00 x 0 t o 0 x F F 10 x 0 t o 0 x F F 20 x 0 t o 0 x F F 30 x 0 t o 0 x F F 255 0x0 to 0xFF

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Timeword RAM The Timeword RAM is a dedicated table that contains sixteen, 16-bit words which are used to set pulse and gap widths. The pulse and gap widths are described as a multiple of carrier periods, T CAR. For example, if the LED must modulate for 8 carrier periods, then be off for 15 carrier periods, index 0 could be loaded with 0x0008 and index 1 could be loaded with 0x000F. A pattern RAM value of 0x01 would result in LED activation for 8 T CARs, as stored in index 0, and a LED deactivation for 15 T CARs. Similarly to pattern RAM, the Timeword table also has a special operator. If the timeword value is zero, then whatever state the LED was in last (I.e. modulating or deactivated) will be continued into the next pulse or gap defined in pattern RAM. For example, if the RAM Pulse nibble (MSB) indexes a timeword set to 5, and the gap (LSB) nibbl e indexes a timeword set to 0, the LED will modulate for 5T CARs then instead of deactivating, the modulation is continued into the next pulse in pattern RAM. In this way pulses or gaps longer than 65535 T CARs can be generated. Figure 72: Timeword RAM Table Timeword RAM: Volatile memory used for storing 16-bit timing data. The Timeword table is located in RAM bank two. Each 16-bit word is accessible using two byte locations: MSB bytes are stored in even addresses and LSBs are stored in odd addresses. For example, if 0x2953 is to be stored at index 0, then 0x29 is written to: bank 2, I²C address of 0x00, and 0x53 is written to bank 2, I²C address of 0x01. Timeword RAM T_INDEX T_DATA I2C Address (Bank 1) 0 0 to 65535 0x01 8-bit MSB 0x00 8-bit LSB 1 0 to 65535 0x03 8-bit MSB 0x02 8-bit LSB 2 0 to 65535 0x05 8-bit MSB 0x04 8-bit LSB 3 0 to 65535 0x07 8-bit MSB 0x06 8-bit LSB ~~ ~ ~ 15 0 to 65535 0x0F 8-bit MSB 0x1E 8-bit LSB

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Control Registers The remote control engine has 19 fields that govern pattern timing and flow, output selection, and report status. All pertinent fields are listed in the figure below. Figure 73: Remote Control Registers and Fields Pertinent Control Registers: Resources associated with Remote Control. Register / Bit Address Description ENABLE<PON> 0x80<0> Power On ENABLE<IBEN> 0x80<7> IRBeam Enable CFG0 <RAM_BANK> 0x8D<0> RAM Bank Select PGCFG1 <PGLDRIVE> 0x8F<4:0> LED Drive Strength STATUS <IINT> 0x93<3> IRBeam Interrupt (mirrors ISTATUS<IINT>) ICONFIG <IIEN> 0xA0<5> IRBe am Interrupt Enable ICONFIG2 <IINVERT> 0xA1<5> IRBeam Polarity Inversion ICONFIG2 <IOUTPUT> 0xA1<4:3> Output Select ICONFIG2 <IRCDCMODE> 0xA 1<2> DC Carrier Select ICONFIG2 <IDUTY> 0xA1<1:0> Duty Cycle Select ISNL <ISNL> 0xA2<7:0> Number of Repeated Sub-pattern Loops ISOFF <ISOFF> 0xA3<7:0> Pause between Sub-pattern Bursts IPNL <IPNL> 0xA4<7:0> Number of Complete Pattern Loops IPOFF <IPOFF> 0xA5<7:0> Pause between Pattern Bursts IBT <IBT> 0xA6<5:0> Carrier Selection Time ISTATUS <IINT> 0xA8<1> IRBeam Interrupt ISTATUS <IBUSY> 0xA8<0> IRBeam Busy ISTART <ISTARTREMCON> 0xA9<1> Remote Control Start Pattern Burst INTCLEAR <INTCLEAR_IINT> 0xD E<3> IRBeam Interrupt Clear

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Carrier frequency, Duty cycle, and Pause (the delay between complete patterns) comprise the registers associated with timing. Carrier periods are selectable in 250ns increments in with register settings in the range of 8 to 255. Carrier frequencies are in the range of 16 kHz to 460 kHz. Typical carrier frequencies are listed in the table below. Protocols that do not use carriers can also be accommodated by enabling the DC Carrier Selection bit. The duty cycle of the carrier is selectable as: 50%, 37%, 25%, and 12%. Note that these duty cycles do not translate exactly to the actual LED duty cycle, depending on the external circuit. Finally, if desired, complete pattern rebursts are separated by a selectable delay of 0us to 2.55s, in 10us increments. Figure 74: Carrier Frequencies Carrier Frequencies: Typical carrier frequencies can be reproduced to closely match the desired value. Controls associated with the output are: Output select, Output Polarity Inversion, and LED Drive Strength. Output Select is used to choose output on the integrated LED or the GPIO pin. The polarity inversion control inverts the waveform on both the LED and the GPIO pin if enabled. The LED Drive Strength controls the current through the integrated LED which effectively sets its intensity. Controls associated with interrupts are: Pattern Burst Interrupt Enable, Pattern Burst Interrupt flag, Pattern Burst Interrupt Clear, Pattern Burst Interrupt Force, and Pattern Burst Busy. Following an entire pattern burst, including all repeats, loops, and delays, a pa ttern burst interrupt bit is set. This bit is readable from two locations: STATUS register and ISTATUS register. If the interrupt enable bit is set, then the INT pin will also activate when the burst is finished. To clear the interrupt, the host must write a zero to IRBeam Interrupt Clear (0xDE<3>). For debugging purpos es the interrupt bits and pin can be forced to activate by setting the Pattern Burst Interrupt Force bit. The Pattern Burst Bu sy bit is automatically set whenever a pattern is actively being transmitted; it is reset once the remote control engine returns to the IDLE state. Desired Frequency (kHz) Generated Frequency (kHz) IBT 36 36.04 111 38 38.10 105 40 40.00 100 56 56.34 71 450 444.44 9

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Controls associated to define the number of complete pattern loops and sub-pattern repeats are: Number of Repeated Sub-pattern Loops and Number of Complete Pattern Loops. As depicted below, the number of “run-once” pattern loops sets the amount of additional iterations, up to 254. If the register is set to 0xFF then the sub-pattern is continuously repeated until the value is changed or IBEN bit is reset. Figure 75: Complete Pattern Loops Complete Pattern Loops: The red box represents a “run-once” pattern. The pattern begins at pattern ram address 0x00 and bursts until the end of the pattern is encountered. The complete pattern can be reiterated 1 to 254 times, or continuously. As depicted below, the number of repeated sub-pattern loops sets the amount of additional “repeated part” burst iterations, up to 254. If the register is set to 0xFF then the sub-pattern is continuously repeated until the value is changed or IBEN bit is reset. Pause Loop IPNL Times IDLE START IDLE Protocols with No Repeated Sub-Patterns “Run-once” Sub- pattern

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Figure 76: Number of Repeated Sub-Pattern Loops Protocols with “Repeated” Sub-Patterns: The blue box represents a repeated part of a pattern. These sub-patterns begin at an address within the red box and burst until the end of the pattern is encountered. The repeated sub-pattern can be reiterated 1 to 254 times, or continuously. Digital Logic The Simplified Flow Diagram depicts the basic premise of how an entire waveform is generated. Protocols of the form described in Figure 75 and Figure 76 can be generated using the mechanism depicted below. Any functionality show in the red, blue, or green boxes can be activated or omitted via control register settings or special oper ators in pattern RAM to produce virtually any waveform. Typically, patterns are built by assembling pulses and gaps in a particular order. To this end the length of time for each pulse and gap, measured in multiples of carrier periods, as well as the order of each pulse/gap pair are specified in the equipment/button data. The remote control engine can directly accept the data in this format. Pulse/Gap order is stored in pattern RAM and pulse/gap time durations are stored in the Timewords table. Pause Loop ISNL Times Loop IPNL Times IDLE START IDLE Protocols with Repeated Sub-Patterns Repeat Sub- pattern “Run-once” Sub- pattern

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Figure 77: Simplified Flow Diagram Simplified Flow Diagram: The digital logic in the remote control engine has been tailored to fit the data format and protocol specifications for IR remote control. “Press and Release” type buttons (E.g. Power) are generated using the logic in the red box (logic in the blue box is not needed). “Press and Hold” type buttons (E.g. Volume+) are generated using logic in both the red and blue boxes. START N Y IDLE Done Looping At the END of Pattern Burst “Pulse” for x Carrier Periods (LED ON) Go to next RAM location N Burst “Gap” for y Carrier Periods (LED ON) Decrement Loop Counter N Set RAM Address to 0x00 IDLE Y Set RAM Address to “Repeated” Start Location Y At the END of Pattern Burst “Pulse” for x Carrier Periods (LED ON) Go to next RAM location N Burst “Gap” for y Carrier Periods (LED ON) Done Repeating Decrement Repeat Counter Y N Y Interrupt Simplified Flow Diagram for Remote Control (With Repeated Sub-Pattern) Delay (0ms to 2.55s)

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information The digital logic in the remote control engine has been tailored to fit the data format and protocol specifications for IR remote control. “Press and Release” type buttons (E.g. Power) are generated using the logic in the red box. “Press and Hold” type buttons (E.g. Volume+) are gene rated using logic in both the red and blue boxes. Figure 78 depicts how a command pattern with a repeated sub-pattern is created using the logic shown in the Simplified Flow Diagram. All of the “run-once” sub-pattern and the “first” instance of the “repeated” sub-pattern is actually run by the logic in the red box. The second instance of the “repeated” sub-pattern is run by the logic in the blue box. Figure 78: Pattern Generation by Logical Block Pattern Generation: All of the “one-time” sub-pattern and the “first” instance of the “repeated” sub-pattern is actually run by the logic in the red box. The second instance of the “repeated” sub-pattern is run by the logic in the blue box. LED Modulation First of Repeat part Second of Repeat part “Complete” Pattern Generated by “red box logic” Generated by “blue box logic” Pattern Generation by Digital Logic Block

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Complete patterns can also be automatically reburst from 1 to 254 times or continuously. Complete patterns can also be separated by a pause, or time delay, as generated by the logic in the green block. The entire pattern consists of a multiple of complete patterns and pause delays. During this length of time the entire pattern is bursting the IBUSY bit is set. Upon completion the IBUSY bit is cleared and the interrupts are set. Figure 79: Entire Pattern Waveform Entire Pattern: Complete patterns can also be separated by a pause, or time delay, as generated by the logic in the green block. The entire pattern consists of a multiple of complete patterns and pause delays. During the length of time the entire pattern is bursting, the PBUSY bit is set. Refer to the Remote Control Engine diagram which depicts the how the engine functions in great detail. Pause Pause Pause “Entire” Pattern Entire Pattern Waveform

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Figure 80: Detailed Flow Diagram of the Remote Control Engine Remote Control Engine: Complete guide to the inner workings and use of the remote control functionality. Remote Control Engine IBUSY = 1 PBEN = 1 START START Y IDLE RAM_ADDRESS = 0 Get MSB Nibble from RAM Data (RDATA-MSBn) Get RAM Data Byte (RDATAn) RDATAn == 0xFE COUNTERR >=0 RDATAn == 0xFF RAM_ADDRESS = START LOCATION OF REPEATED PATTERN Y TIME_INDEX = MSB NIBBLE TDATAMSB == Activate Modulated Output Have TDATAMSB carrier periods been output N Y N Get LSB Nibble from RAM Data (RDATA-LSBn) TIME_INDEX = LSB NIBBLE TDATALSB == Deactivate Modulated Output Have TDATALSB carrier periods been output N Y N Y Y N N Start Exit Output Pattern COUNTERR = ISNL COUNTERR-- COUNTERR < 255 Y RAM_ADDRESS++ N Output Pattern Pause (if any) COUNTERW > 0 COUNTERW = IPNL Y COUNTERW-- Y Start TIMERP = IPOFF TIMERP > 0 Delay 10us TIMERP-- Y Exit N Repeated Sub-Pattern Complete Waveform IBUSY = 0 IINT = 1 IIEN == 1 ASSERT INT PIN Y N Done N Pause (if any)

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Electrical and Optical Output The electrical or optical output of the remote control engine can be realized in three ways: use of the integrated top-facing LED, use of the LDR pin to directly drive an external LED, or use of the GPIO pin to drive an external FET and IR LED. The LDR pin has a regulated current sink with selectable drive value. This is an attractive way to use an external LED without having an additional LED drive FET. If this method is to be used, then LEDA must be disconnected from the circuit. Since the cathode of the integrated LED is connected to the LDR pin internal to the module any current that is sourced through LEDA will reduce the current available on the external remote control LED. When the remote control functionality is not used the external LED must be electrically disconnected from the LDR pin to prevent it from illuminating. Figure 81: External IR LED Using the LDR Pin Recommended Connection: Option number one. If the LDR pin is not used as the pattern output, the GPIO pin can be used. With this method both the LEDA and external remote control IR LED may remain connected to the LED power supply, but an additional FET is needed to drive the remote control LED. TMD4903 VDD GND LEDA INT SCL SDA LDR 1µF 1µF >4.7µF 22Ω µP VDDVBUS Remote Control Circuit Option #1 GPIO VDD VLED µP VLED

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Figure 82: External IR LED Using the GPIO Pin Recommended Connection: Option number two. Example Waveform and Device Setup A practical example is included to describe how each register is used and how to setup the device to burst a real waveform. The physical waveform, as seen on an oscilloscope, is described by the depiction in Figure 80 . The Figure 83 depicts the mechanics to precondition the remote control engine for proper operation. TMD4903 VDD GND LEDA INT SCL SDA LDR 1µF 1µF >4.7µF 22Ω VDDVBUS Remote Control Circuit Option #2 GPIO VDD VLED VLED

Document Feedback [v1-12] 2015-May-14 TMD4903 − Application Information Figure 83: Practical Example Practical Example: Device registers and RAM are loaded with values to generate a real remote control waveform. ADDRESS T_DATA 0 0x01 0x22 0x23 0x32 0x24 0x05 Pattern Table Example 1. Carrier Frequency: 38kHz (T CAR = 26us) 2. Duty Cycle = 25% 3. Non-repeat count=5 (LED ON-LEDOFF) 334-177, 22-22, 22-60, 60-22, 22-1541 4. Repeat count=2 (LED ON-LEDOFF) 334-88 22-3694 Run 2 times 5. Repeat compete pattern 3 times. 6. Delay 100us between complete patterns. 6 0x26 7 0xFE 8 0x05 9 0xFF T_INDEX T_DATA 0 334 177 1541 Time Words Table 0x01, 0x01 I2C Address, Data 0x00, 0x4E 0x03, 0x00 0x02, 0xB1 0x05, 0x00 0x04, 0x16 0x07, 0x00 0x06, 0x3C 0x09, 0x06 0x08, 0x05 0x0B, 0x00 0x0A, 0x58 6 3694 0x0D, 0x0E 0x0C, 0x6E START LED ON for 344 TCAR LED OFF for 177 TCAR LED ON for 22 TCAR LED OFF for 22 TCAR LED ON for 22 TCAR LED OFF for 60 TCAR LED OFF for 22 TCAR LED ON for 60 TCAR LED OFF for 1541 TCAR LED ON for 22 TCAR LED OFF for 88 TCAR LED ON for 334 TCAR LED OFF for 3694 TCAR LED ON for 22 TCAR LED OFF for 88 TCAR LED ON for 334 TCAR LED OFF for 3694 TCAR LED ON for 22 TCAR LED OFF for 88 TCAR LED ON for 334 TCAR LED OFF for 3694 TCAR LED ON for 22 TCAR x01 MSB points to index 0. Index 0 data is 334. LED will be on for 334 X TCAR LSB points to index 2. Index 2 data is 22. LED will be off for 22 X TCAR Byte following “0xFE” becomes the starting address of the repeated pattern. STOP x05 To run two times, must repeat once. IDLE Delay 100us Pattern Delay 100us Pattern Delay 100us IDLE To run complete pattern three times, must repeat twice. Carrier Frequency: IBT = 0x68 (26us/250ns) Duty Cycle: ICONFIG2 = 0x02 “Repeated sub -pattern” Repeat count =2: ISNL = 0x01 “Complete sub -pattern” Repeat count =3: IPNL = 0x02 Delay 100us between complete patterns: IPOFF = 0x0A (100us/10us) START: Write a 0x02 to ISTART. LEDON for 572us LEDOFF for 96ms Pause Pause PauseOutput:

[v1-12] 2015-May-14 Document Feedback TMD4903 − Application Information Protocol Accommodation Checklist The Remote Control pattern generation/transmission feature can be configured to broadcast virtually all IR communication protocols used for commanding consumer electronic devices. There are many different remote control protocols currently in use; and to meet the multitude of requirements the remote control engine has been designed to be flexible. In general, a protocol functions within the following transmission specifications can be accommodated:

• Carrier periods are selectable in 250ns increments. Carrier frequencies are in the range of 15.625 kHz to 460 kHz. Protocols that do not use carriers can also be accommodated.
• Duty cycle of the carrier is selectable: 50%, 37%, 25%, and 12%. Exact LED duty cycle depe nds on the external circuit.
• Pulse (LED on) and Gap (LED off) widths are a multiple of carrier periods (T CAR). Pulse and Gap length is selectable from 0 to 65535 carrier periods. Patterns with exceptionally long pulses or gaps (I.e. longer than 65535 carrier periods) may be ac commodated. This requires setting contiguous pattern ram locations, but results in a glitch-free long pulse/gap.
• A dedicated “time word” RAM table contains sixteen, 16-bit words which are used to set pulse and gap widths. Simply stated, a pattern must contain sixteen or fewer unique pulse/gap widths. Note : patterns containing more than 16 unique pulse/gap widths may be accommodated by using the 16-bit timewords as “building blocks” to form longer pulse/gaps. For example, if a pattern has a pulse/gap of both 3T CAR and 6T CAR, then only the 3T CAR need be represented in the Time Word table; then the 6TCAR can be generated by indexing into the 3T CAR twice (This requires the use of additional pattern RAM).
• A dedicated “pattern” RAM co ntains 256 bytes of data. Each byte indexes into the Timeword table to form a complete pulse and gap pair. A pattern that does not contain a “repeated” sub-pattern must have 255 or fewer pulse/gap pairs. A pattern that contains a “repeated” sub-pattern must have 254 or fewer pulse/gap pairs, not including the additional repetitions of the “repeated” sub-pattern.
• Entire patterns can be reburst up to an additional 255 times and are separated by a selectable delay of 0us to 2.55s, in 10us increments.

Document Feedback [v1-12] 2015-May-14 TMD4903 − Package Drawings & Markings Figure 84: TMD4903 Module Dimensions Note(s) and/or Footnote(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. Contacts are copper with NiPdAu plating. 4. This package contains no lead (Pb). 5. This drawing is subject to change without notice. 6. Measurement guarantee by lot a cceptance testing using 20 units. Package Drawings & Markings Green RoHS '(7(&725 /(' 7239,(: 3,1 6,'(9,(: ; ; %277209,(:

[v1-12] 2015-May-14 Document Feedback TMD4903 − PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 85: Recommended PCB Pad Layout Note(s) and/or Footnote(s): 1. All linear dimensio ns are in millimeters. 2. Dimension tolerances are ±0 .05mm unless otherwise noted. 3. This drawing is subject to change without notice. PCB Pad Layout

Document Feedback [v1-12] 2015-May-14 TMD4903 − Mechanical Data Figure 86: Tape and Reel Mechanical Drawing Note(s) and/or Footnote(s): 1. All linear dimensions are in millimeters. Dime nsion tolerance is ± 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. 4. Each reel is 330 millimeters in diameter and contains 5000 parts. 5. ams packaging tape and reel conform to th e requirements of EIA Standard 481−B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Mechanical Data

Document Feedback [v1-12] 2015-May-14 TMD4903 − Soldering & Storage Information Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:

• Shelf Life: 12 months
• Ambient Temperature: <40°C
• Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
• Floor Life: 168 hours
• Ambient Temperature: <30°C
• Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.

[v1-12] 2015-May-14 Document Feedback TMD4903 − Ordering & Contact Information Figure 89:

Ordering Information

Note(s) and/or Footnote(s): 1. Contact ams for availability. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Address Interface Delivery Form TMD49033 0x39 I²C bus = 1.8V Interface Tape & Reel TMD49037 (1) 0x29 I²C bus = 1.8V Interface Tape & Reel Ordering & Contact Information

Document Feedback [v1-12] 2015-May-14 TMD4903 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

[v1-12] 2015-May-14 Document Feedback TMD4903 − Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer

Document Feedback [v1-12] 2015-May-14 TMD4903 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status

[v1-12] 2015-May-14 Document Feedback TMD4903 − Revision Information Changes from 1-11 (2015-Apr-23) to current revision 1-12 (2015-May-14) Page Updated Section title Updated text under General Description 1 Updated Figure 1 2 Updated Applications 2 Updated Figure 2 3 Updated Figure 4 4 Updated Figure 5 5 Updated Figure 10 9 Updated title of Figure 20 14 Updated text under I2C Protocol section 16 Updated Figure 23 17 Updated Figure 24 and added a note under it 18 Updated text under Detailed Description 19 Updated Figure 25 20 Updated Figure 26 23 Updated text under ALS Interrupt Threshold Registers 27 Updated text under Proximity Interrupt Threshold Registers 27 Updated Figure 32 28 Updated FIgure 33 29 Updated Proximity Configuration Register Zero section 30 Updated text under Proximity Configuration Register One 31 Updated Figure 37 32 Updated Figure 38 33 Updated Figure 39 33 Updated text under CRGB Data Registers 34 Updated text under Proximity Data Registers 35 Revision Information

Document Feedback [v1-12] 2015-May-14 TMD4903 − Revision Information Note(s) and/or Footnote(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Updated Figure 47 40 Updated Figure 49 41 Updated Figure 54 44 Updated text under Proximity Offset Registers 48 Added Autozero Configuration Register 49 Updated Figure 63 50 Added Calibration Configuration Register One 52 Updated Figure 67 55 Updated Figure 89 79 Changes from 1-11 (2015-Apr-23) to current revision 1-12 (2015-May-14) Page

[v1-12] 2015-May-14 Document Feedback TMD4903 − Content Guide

1 General Description

2 Key Benefits & Features

2 Applications

3 Block Diagram

4 Pin Assignment

4 Pin Description

5A b s o l u t e M a x i m u m R a t i n g s

6 Electrical Characteristics

11 Timing Characteristics

11 Timing Diagram

12 Typical Operating Characteristics

16 I²C Protocol

16 I²C Write Transaction

16 I²C Read Transaction

19 Detailed Description

19 Sleep After Interrupt Operation

20 Register Description

23 Enable Register (ENABLE 0x80)

24 ALS Integration Time Register (ATIME 0x81)

25 Proximity Sample Time Register (PTIME 0x82)

26 Wait Time Register (WTIME 0x83)

27 ALS Interrupt Threshold Registers (0x84 – 0x87)

27 Proximity Interrupt Threshold Registers

(0x88 – 0x8B)

28 Interrupt Persistence Register (PERS 0x8C)

29 Configuration Register Zero (CFG0 0x8D)

30 Proximity Configuration Register Zero

(PGCFG0 0x8E)

31 Proximity Configuration Register One

(PGCFG1 0x8F)

32 Configuration Register One (CFG1 0x90)

33 ID Register (ID 0x92)

33 Status Register (STATUS 0x93)

34 CRGB Data Registers (0x94 − 0x9B)

35 Proximity Data Registers (0x9C – 0x9D)

36 Status Register Two (STATUS2 0x9E)

37 Configuration Register Two (CFG2 0x9F)

38 IRBeam Configuration Register (ICONFIG 0xA0)

39 IRBeam Configuration Register Two

(ICONFIG2 0xA1)

40 IRBeam Symbol Looping Register (ISNL 0xA2)

40 IRBeam Inter-Symbol OFF Register

(ISOFF 0xA3)

41 IRBeam Packet Looping Register (IPNL 0xA4)

41 IRBeam Inter-Packet OFF Register (IPOFF 0xA5)

42 IRBeam Bit Time Register (IBT 0xA6)

Document Feedback [v1-12] 2015-May-14 TMD4903 − Content Guide

42 IRBeam Symbol Length Register (ISLEN 0xA7)

43 IRBeam Status Register (ISTATUS 0xA8)

43 IRBeam Start Register (ISTART 0xA9)

44 Configuration Register Three (CFG3 0xAB)

45 Configuration Register Four (CFG4 0xAC)

46 Configuration Register Five (CFG5 0xAD)

47 Status Register Three (STATUS3 0xB3)

47 Control Register (CONTROL 0xBC)

48 Auxiliary ID Register (AUXID 0xBD)

48 Proximity Offset Registers

(0xC0 − 0xC7)

49 Autozero Configuration Register

(AZ_CONFIG 0xD6)

49 Calibration Register (CALIB 0xD7)

50 Calibration Configuration Register Zero

(CALIBCFG0 0xD8)

52 Calibration Configuration Register One

(CALIBCFG1 0xD9)

53 Interrupt Enable Register (INTENAB 0xDD)

54 Interrupt Clear Register (INTCLEAR 0xDE)

57 Remote Control

57 General Description of RC Functionality

57 Detailed Description of RC Functionality

58 Block Diagram of Remote Control Functionality

59 Pattern RAM

61 Timeword RAM

62 Control Registers

65 Digital Logic

71 Example Waveform and Device Setup

73 Protocol Accommodation Checklist

75 PCB Pad Layout

76 Mechanical Data

77 Soldering & Storage Information

77 Soldering Information

78 Storage Information

78 Moisture Sensitivity

78 Shelf Life

78 Floor Life

78 Rebaking Instructions

80 RoHS Compliant & ams Green Statement

81 Copyrights & Disclaimer

82 Document Status