TCS3530 AMSCO | Alldatasheet
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Technical content
Datasheet, Public Page 1 [v3-00] 2023-Jun-23 Document Feedback TCS3530 Fully Embedded, True Color Ambient Light Sensor with Selective Flicker Detection The TCS3530 features true color XYZ ambient light detection, as well as flicker detection up to 7kHz. The device comes in a small footprint 8-pin optical module with a dimension of L2.50mm x W1.80mm x H1.50mm. The optical module is fully embedded offering an integrated aperture and integrated diffuser. This unparalleled scale of integration, containing the photodiodes, aperture and diffuser, as well as precise distances between these key optical elements, allows accurate pre-calibration in final optical device test. The ambient light detection function provides eight concurrent ambient light sensing channe ls with independent gain configuration. These channels can be arbitrarily connected to the 27 photodiodes. A built-in sequencer enables automated measurements without the need to reprogram the device after every measurement cycle. All photodiodes are covered with an UV/IR blocking filter. This architecture accurately measures ambient light and calculates illuminance, chromaticity, and correlated color temperature (CCT) to manage display appearance. The device also integrates direct detection of ambient light flicker up to 7kHz. This extended sampling range enables flicker detection from either conventional mains powered 50Hz/60Hz AC light sources as well as modern PDM controlled LED lighting systems. Flicker detection is executed in parallel with ambient light sensing and has independ ent gain configuration. The flicker detection engine will sample and buffer data for calculating flicker frequencie s externally on a host CPU. Ordering Information and Content Guide appear at end of datasheet. General Description
Page 2 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − General Description Key Benefits & Features The benefits and features of TCS3530 are listed below: Figure 1: Added Value of Using TCS3530
Applications
TCS3530 integrates multiple appl ications within one device. The applications for TCS3530 include:
- CCT and chromaticity calculation
- Auxiliary auto white balancing
- Light type identification
- Flicker-immune camera operation Benefits Features
- Invisible ambient light and color sensing under glass
- Configurable, high sensitivity
- Programmable gain and integration time
- 8192x dynamic range by gain adjustment only
- 1mlux minimum detectable illuminance (100ms)
- Tailored ALS and color response
- UV/IR blocking filter for all channels
- Clear reference channel
- ALS/color interrupt with thresholds
- Unique fast ALS integration mode • Flicker-immune ambient light sensing with programmable integration time
- Integrated ambient light flicker detection on chip
- Independently configurable timing and gain
- Concurrent flicker and ALS measurement with new simplified readout methodology
- Up to 7kHz flicker detection (14kHz sampling)
- FIFO buffer interrupt
- Low power consumption and minimum I²C traffic (optional I3C mode)
- 1.8VBUS and 1.2VBUS operation
- Configurable sleep mode
- Interrupt-driven device
- I²C interface up to 1 MHz (Fast-Mode Plus)
- On-chip data compression decreases serial bus traffic
- Integrated status checking for all functions • Digital and analog ALS saturation flags
Datasheet, Public Page 3 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − General Description Block Diagram The functional blocks of this device are shown below: Figure 2: Functional Blocks of TCS3530
Page 4 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Pin Assignments Figure 3: Pin Diagram of TCS3530 Figure 4: Pin Description of TCS3530 Pin Number Pin Name Description 1 INT Interrupt. Open-drain output. 2P G N D Ground. All voltages are referenced to VSS/PGND, and both ground pins must be connected to ground. 3 VDD Supply voltage (1.8V) 4V S S Ground. All voltages are referenced to VSS/PGND, and both ground pins must be connected to ground.
5 VBUS I²C (I3C) bus supply voltage
6 SDA I²C (I3C) serial data I/O terminal
7 SCL I²C (I3C) serial bus clock terminal
8 VSYNC/GPIO Synchronization input or General Purpose open-drain Input/Output
Datasheet, Public Page 5 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages with respect to VSS/PGND. Device parameters are guaranteed at V DD = 1.8 V and TA = 25°C unless otherwise noted. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply Voltage -0.3 1.98 VVBUS I²C (I3C) Bus Supply Voltage -0.3 1.98 VIO VSYNC/GPIO, VINT Terminal Voltage -0.3 3.6 IIO Output Terminal Current -3 20 mA Stress Parameters ESDHBM HBM Electrostatic Discharge ± 2000 V JEDEC JS-001-2017 ESDCDM CDM Electrostatic Discharge ± 500 V JEDEC JS-002-2018 ISCR Input Current (latch-up immunity) ± 100 mA Class II JEDEC JESD78E Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range -40 85 °C Absolute Maximum Ratings
Page 6 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Absolute Maximum Ratings Figure 6: Recommended Operating Conditions 1. While the device is operational across the temperat ure range, functionality will vary with temperature. Symbol Parameter Conditions Min Typ Max Units VDD Supply voltage 1.7 1.8 1.98 V VIO I/O supply voltage 1.62 1.8 3.3 V VIL-INT/GPIO INT, GPIO input low voltage 0.54 V VIH-INT/GPIO INT, GPIO input high voltage 0.84 V VIL-SCL/SDA SCL, SDA -0.1*VBUS 0.3*VBUS V VIH1.2-SCL/SDA SCL, SDA VBUS=1.2V 0.7*V BUS 1.1*VBUS V VIH1.8-SCL/SDA SCL, SDA VBUS=1.8V 0.7*V BUS 1.98 V I²C Bus Operation VOL-SDA-I2C SDA output low voltage VBUS=1.2V/1.8V@ 20mA 0.4 V I3C Bus Operation VOL-SDA1.2-I3C SDA output low voltage VBUS=1.2V@2mA 0.18 V VOL-SDA1.8-I3C SDA output low voltage VBUS=1.8V@3mA 0.27 V VOH-SDA1.2-I3C SDA output high voltage VBUS=1.2V@-2mA V BUS-0.18 V VOH-SDA1.8-I3C SDA output high voltage VBUS=1.8V@-3mA V BUS-0.27 V Temperature Ranges and Storage Conditions TA Operating free-air temperature (1) -30 25 85 °C Other Conditions CI Input pin capacitance 4 pF
Datasheet, Public Page 7 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Optical Characteristics Parameters listed under Test Level 4 are guaranteed with production tests and SQC (Statistical Quality Control). Parameters listed under Test Level 3 are measured in-line with transparent monitor glasses. Pa rameters listed under Test Level 2 are measured in lab bench characterization. Parameters listed under Test Level 1 are guaranteed by design. All Test Levels are measured with V DD = 1.8V and T A = 25°C unless otherwise noted. Figure 7: ALS/Color Characteristics of TCS3530, ALS Gain = 128x , Integration Time = 11ms (unless otherwise noted) Note(s): 1. The typical 3-sigma distribution shows less than 1 count for an ATIME setting of less than 98 ms. Residual counts are not con sidered for dark count measurement. 2. The gain ratios are calculated relative to the response with ALS gain = 128x. 3. The White LED is an InGaN light-emitting diode with integrat ed phosphor and the following characteristic: correlated color temperature = 2700K. 4. ADC noise is calculated as the standard deviation relative to full scale. Parameter Conditions Min Typ Max Unit Test Level Dark ADC count value (1) Ee = 0μW/cm2 ALS gain: 512x Integration time: 100ms 00 3 c o u n t s 4 ALS gain ratios (2) 0.5x 1/261.10 1x 1/126.90 2x 1/63.69 4x 1/31.85 8x 1/15.53 16x 1/8 32x 1/4 64x 1/2 256x 1.92 512x 3.79 1024x 7.44 2048x 14.40 4096x 27.90 ADC noise (4) White LED, 2700K (3) Integration time: 100ms 0.05 2 Optical Characteristics
Datasheet, Public Page 9 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Optical Characteristics Note(s): 1. Light source not native in XRITE light box. dLUX LED 2800K (1) 1.6 LED 4000K 0.1 Fluorescent (CFL) 6500K (1) -1.3 Fluorescent (CWF) 4000K 0.1 D65 1.3 Halogen (A) 2900K 0.4 Halogen (HZ) 2300K 2.0 Incandescent (A) 2600K (1) -0.9 dCCT LED 2800K (1) 0.2 LED 4000K -0.6 Fluorescent (CFL) 6500K (1) -1.7 Fluorescent (CWF) 4000K -1.9 D65 -0.9 Halogen (A) 2900K 0.6 Halogen (HZ) 2300K 1.6 Incandescent (A) 2600K (1) 0.6 Parameter Conditions Min Typ Max Unit Test Level
Datasheet, Public Page 11 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Electrical Characteristics Parameters listed under Test Level 4 are guaranteed with production tests and SQC (Statistical Quality Control). Parameters listed under Test Level 3 are measured in-line with transparent monitor glasses. Parameters listed under Test Level 2 are measured in lab bench characterization. Parameters listed under Test Level 1 are guaranteed by design. All Test Levels are measured with V DD = 1.8V and TA = 25°C unless otherwise noted. Figure 12: Note(s): 1. This parameter indicates the supply curr ent during periods of ALS integration. The ALS gain setting will have an effect on t he active supply current. The ALS gain setting used for this parameter is 128x. 2. Idle state occurs when PON=1 and all functions are disabled. 3. Sleep state occurs when PON = 0 and I²C/I3C bus is idle. If Sleep state has been entered as the result of operational flow, SAI = 1, PON will remain high. Symbol Parameter Conditions Min Typ Max Unit Test Level IDD;ALS ALS supply current Active ALS state (1) (PON=AEN=1) 485 560 μA 4 IDD;IDLE Idle current Idle state (2) (PON=1, AEN=0) 98 130 IDD;SLEEP Sleep current Sleep state (3) 0.7 5.0 ILEAK Leakage current Measured on SDA, SCL, INT, GPIO -5 5
Electrical Characteristics
Page 12 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Timing Characteristics Parameters listed under Test Level 4 are guaranteed with production tests and SQC (Statistical Quality Control). Parameters listed under Test Level 3 are measured in-line with transparent monitor glasses. Parameters listed under Test Level 2 are measured in lab bench characterization. Parameters listed under Test Level 1 are guaranteed by design. All Test Levels are measured with V DD = 1.8V and TA = 25°C unless otherwise noted. Figure 13: I²C Timing Characteristics of TCS3530 Symbol Parameter Min Typ Max Unit Test Level fSCL I²C clock frequency 0 400 kHz 1 tBUF Bus free time between start and stop condition 1.3 μs 1 tHD;STA Hold time after (repeated) start condition. After this period, the first clock is generated 0.6 tSU;STA Repeated start condition setup time 0.6 tSU;STO Stop condition setup time 0.6 tLOW SCL clock low period 1.3 tHIGH SCL clock high period 0.6 tHD;DAT Data hold time 0 ns 1 tSU;DAT Data setup time 100 tF Clock/data fall time 300 tR Clock/data rise time 300 Timing Characteristics
Datasheet, Public Page 15 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Detailed Description Upon power-up, POR, the device init ializes. During initialization (typically 200μs), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed, and all outputs from the device must be ignored including interr upts. After initialization, the device enters the SLEEP state. In this operational state the internal oscillator and other circ uitry are not active, resulting in ultra-low power consumption. If an I²C transaction occurs during this state, the I²C core wakes up temporarily to service the communication. Once the Powe r ON bit, PON, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. Whenever a function is enabled (AEN = 1), the device exits the IDLE state. If all functions are disabled (AEN = 0), the device returns to the IDLE state. As depicted in Figure 18 and Figure 19 , the color sensing functions operate in parallel when enabled. Each function is individually configured (e.g. gain, ADC integration time, wait time, persistence, thresholds, etc.). If Sleep after Interrupt is enabled the state machine will enter SLEEP when an interrupt occu rs. Entering SLEEP does not automatically change any of the register settings (e.g. PON bit is still high, but the normal oper ational state is over-ridden by SLEEP state). SLEEP state is terminated when the SAI_ACTIVE bit is cleared (the status bit is in register 0xA7 and the clear status bit is in register 0xFA). State Machine Diagrams Figure 18: Simplified State Diagram Detailed Description AEN IDLE ALS/ COLOR/WIDEBAND/ FLICKER SLEEP PON
Page 16 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Detailed Description Figure 19: Detailed State Diagram ALS/COLOR/WIDEBAND/FLICKER/IR INTERRUPT I2C POR INITIALIZE (200μs) PON = 1?SLEEPSAI = 1? EXIT SLEEPY AEN = 1AEN = 0 AUTOZERO (every nth time) INTEGRATE (ATIME) WA IT (WTIME) N Y N GENERATE INTERRUPT UPDATE STATUS EVALUAT E: INTER RUPT?Y N CLEAR INTE RRUP TS IDLE TCS3440 OperationalStates CHANNEL DATA TCS3530 Operational States
Datasheet, Public Page 17 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Detailed Description I²C Protocol The device uses I²C serial communication protocol for communication. The device support s 7-bit chip addressing and both standard and full-speed cl ock frequency modes. Read and Write transactions comply with th e standard set by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification. Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general it is recommended to use I²C bursts whenever possible, especially in this ca se when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors. A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP . Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the sl ave, the master may issue a STOP . A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP .
Page 18 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview The device is controlled and monitored by registers accessed through the I²C serial interface. These registers provide device control functions and are read to determine device status and acquire device data. Register Map The register set is summarized in Figure 20 . The values of all registers and fields that are listed as reserved or are not listed must not be changed at any time. The power-on reset values of each bit are indicated in these columns. Two-byte fields are always latched with the low byte followed by the high byte. Figure 20: Register Map Addr Name Description Reset 0x24 CONTROL_SCL Initialize the device 0x00 0x40 MOD_OFFSET0[7:0] Modulator Offset Register 0x00 0x41 MOD_OFFSET0[9:8] Modulator Offset Register 0x00 0x42 MOD_OFFSET1[7:0] Modulator Offset Register 0x00 0x43 MOD_OFFSET1[9:8] Modulator Offset Register 0x00 0x44 MOD_OFFSET2[7:0] Modulator Offset Register 0x00 0x45 MOD_OFFSET2[9:8] Modulator Offset Register 0x00 0x46 MOD_OFFSET3[7:0] Modulator Offset Register 0x00 0x47 MOD_OFFSET4[9:8] Modulator Offset Register 0x00 0x48 MOD_OFFSET4[7:0] Modulator Offset Register 0x00 0x49 MOD_OFFSET4[9:8] Modulator Offset Register 0x00 0x4A MOD_OFFSET5[7:0] Modulator Offset Register 0x00 0x4B MOD_OFFSET5[9:8] Modulator Offset Register 0x00 0x4C MOD_OFFSET6[7:0] Modulator Offset Register 0x00 0x4D MOD_OFFSET6[9:8] Modulator Offset Register 0x00 0x4E MOD_OFFSET7[7:0] Modulator Offset Register 0x00 0x4F MOD_OFFSET7[9:8] Modulator Offset Register 0x00 0x7F OSCEN Power on polling 0x00 0x80 ENABLE Enables device states 0x00 0x81 MEAS_MODE0 Measurement mode settings 0 0x04 0x82 MEAS_MODE1 Measurement mode settings 1 0x0C Register Overview
Datasheet, Public Page 19 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview 0x83 SAMPLE_TIME0 Flicker and ALS sample time settings 0 0x60 0x84 SAMPLE_TIME1 Flicker and ALS sample time settings 1 0x16 0x85 SAMPLE_TIME_ ALTERNATIVE0 Alternative sample time setting 0 0x60 0x86 SAMPLE_TIME_ ALTERNATIVE1 Alternative sample time setting 1 0x16 0x87 ALS_NR_SAMPLES0 ALS number of samples setting 0 0x00 0x88 ALS_NR_SAMPLES1 ALS number of samples setting 1 0x00 0x89 ALS_NR_SAMPLES_ ALTERNATIVE0 Alternative ALS number of samples setting 0 0x00 0x8A ALS_NR_SAMPLES_ ALTERNATIVE1 Alternative ALS number of samples setting 1 0x00 0x8B FD_NR_SAMPLES0 ALS Interrupt Low Threshold [15:8] 0x00 0x8C FD_NR_SAMPLES1 ALS Interrupt Low Threshold [23:16] 0x00 0x8D FD_NR_SAMPLES_ ALTERNATIVE0 ALS Interrupt High Threshold [7:0] 0x00 0x8E FD_NR_SAMPLES_ ALTERNATIVE1 ALS Interrupt High Threshold [15:8] 0x00 0x8F WTIME Wait Time 0x00 0x90 AUX_ID Auxiliary Identification 0x00 0x91 REV_ID Revision Identification 0x14 0x92 ID Device Identification 0x68 0x93 AILT0 ALS Interrupt Low Threshold 0 0x00 0x94 AILT1 ALS Interrupt Low Threshold 1 0x00 0x95 AILT2 ALS Interrupt Low Threshold 2 0x00 0x96 AIHT0 ALS Interrupt High Threshold 0 0x00 0x97 AIHT1 ALS Interrupt High Threshold 1 0x00 0x98 AIHT2 ALS Interrupt High Threshold 2 0x00 0x99 AGC_NR_ SAMPLES[7:0] AGC Number of Samples 0x00 0x9A AGC_NR_ SAMPLES[10:8] AGC Number of Samples 0x00 0x9B STATUS Device Status Information 0x00 0x9C STATUS2 Device Status Information 2 0x00 Addr Name Description Reset
Page 20 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview 0x9D STATUS3 Device Status Information 3 0x08 0x9E STATUS4 Device Status Information 4 0x00 0x9F STATUS5 Device Status Information 5 0x00 0xA0 STATUS6 Device Status Information 6 0x00 0xA1 CFG0 Configuration 0 0x00 0xA2 CFG1 Configuration 1 0x00 0xA3 CFG2 Configuration 2 0x00 0xA4 CFG3 Configuration 3 0x00 0xA5 CFG4 Configuration 4 0x00 0xA6 CFG5 Configuration 5 0x00 0xA7 CFG6 Configuration 6 0x03 0xA8 CFG7 Configuration 7 0x01 0xA9 CFG8 Configuration 8 0xC3 0xAA CFG9 Configuration 9 0x00 0xAB MOD_CHANNEL_ CTRL Modulator Channel Control 0x00 0xAD TRIGGER_MODE Repetition time of modulator or sequencer measurement 0x00 0xAE OSC_TUNE Oscillator tuning settings 0x00 0xB0 VSYNC_GPIO_INT Control of VSYNC/GPIO pin 0x02 0xBA INTENAB Enable interrupts 0x00 0xBB SIEN Enable saturation interrupts 0x00 0xBC CONTROL Device control settings 0x00 0xBD ALS_DATA_STATUS ALS measurement data status 0x00 0xBE ALS_DATA_FIRST ALS data read and update control 0x00 0xBF ALS_DATA ALS data read and update control 0x00 0xC0 MEAS_SEQR_STEP0_ MOD_GAINX_0 Defines the gain of modulator for the measurement sequencer step 0x88 0xC1 MEAS_SEQR_STEP0_ MOD_GAINX_1 Defines the gain of modulator for the measurement sequencer step 0x88 0xC2 MEAS_SEQR_STEP0_ MOD_GAINX_2 Defines the gain of modulator for the measurement sequencer step 0x88 Addr Name Description Reset
Datasheet, Public Page 21 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview 0xC3 MEAS_SEQR_STEP0_ MOD_GAINX_3 Defines the gain of modulator for the measurement sequencer step 0x88 0xC4 MEAS_SEQR_STEP1_ MOD_GAINX_0 Defines the gain of modulator for the measurement sequencer step 0x88 0xC5 MEAS_SEQR_STEP1_ MOD_GAINX_1 Defines the gain of modulator for the measurement sequencer step 0x88 0xC6 MEAS_SEQR_STEP1_ MOD_GAINX_2 Defines the gain of modulator for the measurement sequencer step 0x88 0xC7 MEAS_SEQR_STEP1_ MOD_GAINX_3 Defines the gain of modulator for the measurement sequencer step 0x88 0xC8 MEAS_SEQR_STEP2_ MOD_GAINX_0 Defines the gain of modulator for the measurement sequencer step 0x88 0xC9 MEAS_SEQR_STEP2_ MOD_GAINX_1 Defines the gain of modulator for the measurement sequencer step 0x88 0xCA MEAS_SEQR_STEP2_ MOD_GAINX_2 Defines the gain of modulator for the measurement sequencer step 0x88 0xCB MEAS_SEQR_STEP2_ MOD_GAINX_3 Defines the gain of modulator for the measurement sequencer step 0x88 0xCC MEAS_SEQR_STEP3_ MOD_GAINX_0 Defines the gain of modulator for the measurement sequencer step 0x88 0xCD MEAS_SEQR_STEP3_ MOD_GAINX_1 Defines the gain of modulator for the measurement sequencer step 0x88 0xCE MEAS_SEQR_STEP3_ MOD_GAINX_2 Defines the gain of modulator for the measurement sequencer step 0x88 0xCF MEAS_SEQR_STEP3_ MOD_GAINX_3 Defines the gain of modulator for the measurement sequencer step 0x88 0xD0 MEAS_SEQR_STEP0_ FD Defines whether or not a flicker measurement shall be executed with respective modulator 0x00 0xD1 MEAS_SEQR_STEP1_ FD Defines whether or not a flicker measurement shall be executed with respective modulator 0x00 0xD2 MEAS_SEQR_STEP2_ FD Defines whether or not a flicker measurement shall be executed with respective modulator 0x00 0xD3 MEAS_SEQR_STEP3_ FD Defines whether or not a flicker measurement shall be executed with respective modulator 0x00 0xD4 MEAS_SEQR_STEP0_ RESIDUAL Defines whether or not a residual measurement shall be executed with respective modulator 0xFF 0xD5 MEAS_SEQR_STEP1_ RESIDUAL Defines whether or not a residual measurement shall be executed with respective modulator 0xFF Addr Name Description Reset
Page 22 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview 0xD6 MEAS_SEQR_STEP2_ RESIDUAL Defines whether or not a residual measurement shall be executed with respective modulator 0xFF 0xD7 MEAS_SEQR_STEP3_ RESIDUAL Defines whether or not a residual measurement shall be executed with respective modulator 0xFF 0xD8 MEAS_SEQR_STEP0_ ALS Defines whether or not an ALS measurement shall be executed with respective modulator 0xFF 0xD9 MEAS_SEQR_STEP1_ ALS Defines whether or not an ALS measurement shall be executed with respective modulator 0x00 0xDA MEAS_SEQR_STEP2_ ALS Defines whether or not an ALS measurement shall be executed with respective modulator 0x00 0xDB MEAS_SEQR_STEP3_ ALS Defines whether or not an ALS measurement shall be executed with respective modulator 0x00 0xDC MEAS_SEQR_APERS_ AND_VSYNC_WAIT Defines the measurement sequencer pattern 0x01 0xDD MEAS_SEQR_AGC Defines the measurement sequencer pattern 0xFF 0xDE MEAS_SEQR_SMUX_ AND_SAMPLE_TIME Defines the measurement sequencer pattern 0x00 0xDF MEAS_SEQR_WAIT_ AND_TS_ENABLE Defines the measurement sequencer pattern 0x01 0xE0 MOD_CALIB_CFG0 Defines the modulator calibration repetition rate 0xFF 0xE2 MOD_CALIB_CFG2 Defines the modulator calibration settings 0x69 0xE3 MOD_CALIB_CFG3 Defines the modulator autozero settings 0x6A 0xE7 MOD_COMP_CFG2 Allows to change the modulator IDAC range 0xBF 0xE8 MOD_RESIDUAL_ CFG0 Defines modulator clock cycles for residual measurements 0x00 0xE9 MOD_RESIDUAL_ CFG1 Defines relative steps for residual measurements 0x00 0xEA MOD_RESIDUAL_ CFG2 Defines relative steps for residual measurements 0x00 0xEB VSYNC_DELAY_CFG0 Defines the delay time relative to VSYNC 0x00 0xEC VSYNC_DELAY_CFG1 Defines the delay time relative to VSYNC 0x00 0xED VSYNC_PERIOD0 Allows to measure the period of a VSYNC input signal 0x00 0xEE VSYNC_PERIOD1 Allows to measure the period of a VSYNC input signal 0x00 0xEF VSYNC_PERIOD_ TARGET0 Allows to set a target period depending on the VSYNC input signal 0x00 Addr Name Description Reset
Datasheet, Public Page 23 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview 0xF0 VSYNC_PERIOD_ TARGET1 Allows to set a target period depending on the VSYNC input signal 0x00 0xF1 VSYNC_CONTROL Allows to sets various oscillator synchronization modes 0x00 0xF2 VSYNC_CFG Defines the oscillator calibration and synchronization mode 0x00 0xF3 FIFO_THR Configuration of FIFO threshold interrupt 0x7F 0xF4 MOD_FIFO_DATA_ CFG0 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xF5 MOD_FIFO_DATA_ CFG1 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xF6 MOD_FIFO_DATA_ CFG2 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xF7 MOD_FIFO_DATA_ CFG3 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xF8 MOD_FIFO_DATA_ CFG4 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xF9 MOD_FIFO_DATA_ CFG5 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xFA MOD_FIFO_DATA_ CFG6 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xFB MOD_FIFO_DATA_ CFG7 Defines conditions and data format for corresponding modulator to write to FIFO 0x8F 0xFC FIFO_STATUS0 Contains number of FIFO entries 0x00 0xFD FIFO_STATUS0 Contains number of FIFO entries 0x00 0xFD FIFO_STATUS1 Contains FIFO overflow and underflow status 0x00 0xFE FIFO_DATA_ PROTOCOL Register to read out FIFO with FIFO protocol mechanism 0x00 0xFF FIFO_DATA Register contains FIFO data for read-out 0x00 Addr Name Description Reset
Datasheet, Public Page 25 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview Note(s): 1. Return to the Register Map ( 0x40 , 0x41 , 0x42 , 0x43 , 0x44 , 0x45 , 0x46 , 0x47 , 0x48 , 0x49 , 0x4A , 0x4B , 0x4C , 0x4D , 0x4E , 0x4F ). 0x45 7:2 Reserved 0 Modulator Offset Registers These registers hold the 8 LSB or the 2 MSB bits of the modulator offset value for the related modulator channel. It can be overwritten, and it gets overwritten by the auto-zero mechanism. The value is 10-bit wide and 2's complement encoded. -512 gets saturated to -511, thus the range is from ±511. Do not write -512. 0x45 1:0 MOD_ OFFSET2[9:8] 0R / W 0x46 7:0 MOD_ OFFSET3[7:0] 0R / W 0x47 7:2 Reserved 0 0x47 1:0 MOD_ OFFSET4[9:8] 0R / W 0x48 7:0 MOD_ OFFSET4[7:0] 0R / W 0x49 7:2 Reserved 0 0x49 1:0 MOD_ OFFSET4[9:8] 0R / W 0x4A 7:2 MOD_ OFFSET5[7:0] 0R / W 0x4B 1:0 Reserved 0 0x4B 7:0 MOD_ OFFSET5[9:8] 0R / W 0x4C 7:2 MOD_ OFFSET6[7:0] 0R / W 0x4D 1:0 Reserved 0 0x4D 7:0 MOD_ OFFSET6[9:8] 0R / W 0x4E 7:2 MOD_ OFFSET7[7:0] 0R / W 0x4F 1:0 Reserved 0 0x4F 7:0 MOD_ OFFSET7[9:8] 0R / W Addr Bit Field Reset Type Description
Datasheet, Public Page 27 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MEAS_MODE0 Register Figure 25: MEAS_MODE0 Note(s): 1. Return to the Register Map ( 0x81 ). Addr: 0x81 MEAS_MODE0 Bit Field Reset Type Bit Description
7 STOP_AFTER_NTH_
Stops a manual calibration after nth iterations by setting FDEN and AEN to “0” . PON will stay at “1” . Per default it stops after one calibration. ENABLE_AGC_ ASAT_DOUBLE_ STEP_DOWN 0R / W Enables two gain steps down at once in case of an analogue AGC saturation and at a gain step still >0. This will allow a faster reach of 25% full-scale range and a more prompt reaction if analogue saturations occurs. MEASUREMENT_ SEQUENCER_ SINGLE_SHOT_ MODE 0R / W Start one measurement cycle with sequencer settings and stop it by asserting Sleep After Interrupt (SAI) MOD_FIFO_ALS_ STATUS_WRITE_ ENABLE 0R / W Enables writing of ALS status to the FIFO RAM in case ALS data scaling is used as well as 16-bit ALS data writing. It is needed to be able to correctly interpret the ALS data. 3:0 ALS_SCALE 4 R/W ALS_SCALE is used to avoid that redundant ALS MSBs are transmitted and are reducing possible resolution, since the ALS data register is only 16 bits wide (internally the result can be 26 bits wide = 11 bits samples + 11 bits sampling time + 4 bits residuals - ALS_MSB_POSITION). The ALS_ SCALE register defines the number of MSBs which must be "0" so that the scaled representation is used in the ALS data registers instead of the unscaled representation.
Page 28 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview MEAS_MODE1 Register Figure 26: MEAS_MODE1 Note(s): 1. Return to the Register Map ( 0x82 ). Addr: 0x82 MEAS_MODE1 Bit Field Reset Type Bit Description MOD_FIFO_FD_ END_ MARKER_WRITE_ ENABLE 0R / W Enables writing of end marker to FIFO after each complete flicker measurement. MOD_FIFO_FD_ CHECKSUM_ WRITE_ENABLE 0R / W Enables writing of flicker checksum to FIFO after each complete flicker measurement. MOD_FIFO_FD_ GAIN_WRITE_ ENABLE 0R / W Enables writing of gain to FIFO after each complete flicker measurement. This is required in case AGC is enabled. 4:0 ALS_MSB_ POSITION 12 R/W Internally the result can be 26 bits wide = 11-bit samples + 11-bit sampling time + 4-bit residuals and is stored in a 32-bit register. ALS_MSB_POSITION defines the MSB in this 32-bit register.
Page 38 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview Note(s): 1. Return to the Register Map ( 0x9B ). STATUS2 Register Figure 45: STATUS2 Note(s): 1. Return to the Register Map ( 0x9C ). 1R e s e r v e d 0 0S I N T 0 0 System Interrupt. If SIEN is set, indicates that one or more of several events has occurred or is complete. The events related to this interrupt are indicated in the STATUS5 register. Addr: 0x9C STATUS2 Bit Field Reset Type Bit Description 7:5 Reserved 0 R
4 ALS_DIGITAL_
ALS Digital Saturation. Indicates that a counter value has been reached that cannot be expressed with the selected data format defined with ALS_MSB_POSITION. Maximum counter value also depends on integration time set in the ATIME register.
3 FD_DIGITAL_
Flicker Detect Digital Saturation. Indicates that the maximum counter value has been reached during flicker detection. 2:1 Reserved 0 R
0 MOD_ANALOG_
SATURATION_ANY 0R ALS Analog Saturation of any Modulator. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit. Addr: 0x9B STATUS Bit Field Reset Type Bit Description
Datasheet, Public Page 39 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview STATUS3 Register Figure 46: STATUS3 Note(s): 1. Return to the Register Map ( 0x9D ). Addr: 0x9D STATUS3 Bit Field Reset Type Bit Description 7:6 Reserved 0 5A I N T _ A I H T 0 R / W ALS Interrupt High. Indicates that an ALS interrupt occurred because the ALS data exceeded the high threshold. Writing “1” to this bit clears this interrupt. 4A I N T _ A I L T 0 R / W ALS Interrupt Low. Indicates that an ALS interrupt occurred because the ALS data is below the low threshold. Writing “1” to this bit clears this interrupt.
3 VSYNC_LOST 1 R
Indicates that synchronization is out of sync with clock provided at vsync pin. Default value is “1” since device always starts unsynchronized. The detected vsync clock is not within the expected range. Please see VSYNC_PERIOD_TARGET for more details. 2R e s e r v e d 0
1 OSC_CALIB_
Indicates that oscillator calibration with the current values of TRIM_OSC and OSC_TUNE is out of range abs(TRIM_ OSC+OSC_TUNE) > 32 .
0 OSC_CALIB_
FINISHED 0 R Indicates that oscillator calibration is finished.
Page 40 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview STATUS4 Register Figure 47: STATUS4 Note(s): 1. Return to the Register Map ( 0x9E ). Addr: 0x9E STATUS4 Bit Field Reset Type Bit Description 7:4 Reserved 0
3 MOD_SAMPLE_
TRIGGER_ERROR 0R Indicates that Measured Data is Corrupted. For a valid measurement, this bit must not be asserted. This error condition does not trigger an interrupt, however AEN and FDEN will be cleared and SINT_MEASURMENT_ SEQUENCER will be set. Writing “1” clears this bit.
2 MOD_TRIGGER_
Indicates that WTIME is too short for the programmed configuration (SAMPLE_TIME, ALS_NR_SAMPLES, FD_NR_ SMAPLES). This error condition does not trigger an interrupt. Writing “1” clears this bit.
1 SAI_ACTIVE 0 R
Sleep After Interrupt Active. Indicates that the device is in sleep due to an interrupt. To exit sleep mode, clear this bit by writing “1” to CLEAR_SAI_ACTIVE. 0I N I T _ B U S Y 0 R Initialization Busy. Indicates that the device is initializing. This bit will remain 1 for about 300μs after power on. Do not interact with the device until initialization is complete (e.g. via I²C/I3C).
Datasheet, Public Page 41 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview STATUS5 Register Figure 48: STATUS5 Note(s): 1. Return to the Register Map ( 0x9F ). Addr: 0x9F STATUS5 Bit Field Reset Type Bit Description 7:3 Reserved 0 2S I N T _ A U X 0 R / W Auxiliary System Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as an auxiliary interrupt occurs. SINT_ MEASUREMENT_ SEQUENCER 0R / W Measurement Sequencer Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as invoked by a measurement sequencer event. 0S I N T _ V S Y N C 0R / W Vsync Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as soon as a vysnc interrupt occurs.
Page 42 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview STATUS6 Register Figure 49: STATUS6 Note(s): 1. Return to the Register Map ( 0xA0 ). Addr: 0xA0 STATUS6 Bit Field Reset Type Bit Description
7 MOD_ANALOG_
ALS Analog Saturation of Modulator7. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
6 MOD_ANALOG_
ALS Analog Saturation of Modulator6. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
5 MOD_ANALOG_
ALS Analog Saturation of Modulator5. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
4 MOD_ANALOG_
ALS Analog Saturation of Modulator4. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
3 MOD_ANALOG_
ALS Analog Saturation of Modulator3. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
2 MOD_ANALOG_
ALS Analog Saturation of Modulator2. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
1 MOD_ANALOG_
ALS Analog Saturation of Modulator1. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit. ALS Analog Saturation of Modulator0. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit.
Datasheet, Public Page 43 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview CFG0 Register Figure 50: CFG0 Note(s): 1. Return to the Register Map ( 0xA1 ). CFG1 Register Figure 51: CFG1 Note(s): 1. Return to the Register Map ( 0xA2 ). Addr: 0xA1 CFG0 Bit Field Reset Type Bit Description 7R e s e r v e d 0 6S A I 0 R / W Sleep After Interrupt. If asserted, the oscillator is turned off whenever interrupt is active (low). SAI_ ACTIVE is set in this event. To activate the oscillator again, service and clear all interrupts plus clear the SAI_ACTIVE bit by writing “1” to CLEAR_SAI_ACTIVE. Sleep after interrupt is asserted only in combination with MEASUREMENT_ SEQUENCER_SINT_PER_STEP or SIEN or SIEN_ MEASUREMENT_SEQUENCER. 5:0 Reserved 0 Do not overwrite default. Addr: 0xA2 CFG1 Bit Field Reset Type Bit Description 7:3 Reserved 0
2 DO_ALS_FINAL_
If this bit is set to “1” and flicker measurement takes longer than ALS measurement, ALS measurement writings are postponed until flicker measurement is finished. Otherwise ALS data is not written to FIFO. 1:0 Reserved 0 Do not overwrite default.
Datasheet, Public Page 45 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview CFG4 Register Figure 54: CFG4 Note(s): 1. Return to the Register Map ( 0xA5 ). Addr: 0xA5 CFG4 Bit Field Reset Type Bit Description 7R e s e r v e d 0 MOD_ CALIBRATION_ NTH_ITERATION_ STEP_ENABLE 0R / W Enable a modulator calibration with nth iterations per sequencer step instead of waiting for a full round for all sequencers to be finished. In case of AGC enabled (MOD_ CALIB_NTH_ITERATION_AGC_ENABLE) this bit must be set “0” , otherwise AGC will not properly work. MEASUREMENT_ SEQUENCER_AGC_ PREDICT_TARGET_ LEVEL 0R / W Sets the target measurement levels for AGC prediction. 0b: 50% of max value 1b: 25% of max value MEASURMENT_ SEQUENCER_ SINT_PER_STEP 0R / W Invokes the system interrupt SINT_MEASUREMENT_ SEQUENCER per sequencer step instead of after a full sequencer round.
3 OSC_TUNE_NO_
RESET 0R If set to 0, OSC_TUNE gets reset to 0 if PON is set to 1. If set to 1, OSC_TUNE keeps its value if PON is set to 1. 2R e s e r v e d 0 1:0 MOD_ALS_FIFO_ DATA_FORMAT 0R / W Sets the format for ALS data written to FIFO. Please observe readout pattern if digital or analog saturation has occurred. 00b: 16-bit (FFFF analog sat, FFFE digital sat) 01b: 24-bit (FFFFFF analog sat, FFFFFE digital sat) 10b: Reserved 11b: 32-bit (FFFFFFFF analog sat)
Page 46 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview CFG5 Register Figure 55: CFG5 Note(s): 1. Return to the Register Map ( 0xA6 ). Addr: 0xA6 CFG5 Bit Field Reset Type Bit Description 7R e s e r v e d 0 6:4 ALS_THRESHOLD_ CHANNEL 0R / W Selects the modulator channel used for the ALS threshold metering and subsequent interrupt. 000b default, Modulator 0 001b: Modulator 1 010b: Modulator 2 011b: Modulator 3 111b: Modulator7 3:0 APERS 0 R/W ALS Interrupt Persistence. Defines a filter for the number of consecutive occurrences that ALS measurement data must remain outside the threshold range between AILT and AIHT before an interrupt is generated. The ALS data channel used for the persistence filter is set by ALS_THRESHOLD_CHANNEL. Any sample that is inside the threshold range resets the counter to 0. Interrupts are generated at 0x0: Every ALS cycle 0x1: Any ALS value outside the threshold range 0x2: 2 consecutive ALS values outside the range 0x3: 3 consecutive ALS values outside the range 0x4: 5 … 0x5: 10 … …… continued in increments of 5 values 0xE: 55 … 0xF: 60 consecutive ALS values outside the range
Datasheet, Public Page 47 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview CFG6 Register Figure 56: CFG6 Note(s): 1. Return to the Register Map ( 0xA7 ). Addr: 0xA7 CFG6 Bit Field Reset Type Bit Description 7:6 Reserved 0 MOD_ MEASUREMENT_ COMPLETE_ STARTUP 0R / W Activated complete start procedure in for each measurement sample. This reduces measurement time per sample by 9 modulator clock cycles. 4R e s e r v e d 0 3:2 MOD_MINIMUM_ RESIDUAL_BITS 0R / W Limits the number of residual bits to a minimum within this value. ATTENTION: When this function is used, the default settings for the gains are not correct anymore. Thus a residual calibration is mandatory (use MOD_CALIB_ RESIDUAL_ENABLE_AUTO_CALIB_ON_GAIN_ CHANGE or MOD_CALIB_NTH_ITERATION_RC_ ENABLE to enforce residual calibration) 00b: 0 residual bits at minimum (default, turned off ) 01b: 1 residual bits at minimum 10b: 2 residual bits at minimum 11b: 3 residual bits at minimum 1:0 MOD_MAXIMUM_ RESIDUAL_BITS 10b R/W Limits the number of residual bits to a maximum within this value. ATTENTION: When this function is used, the default settings for the gains are not correct anymore. Thus a residual calibration is mandatory (use MOD_CALIB_ RESIDUAL_ENABLE_AUTO_CALIB_ON_GAIN_ CHANGE or MOD_CALIB_NTH_ITERATION_RC_ ENABLE to enforce residual calibration). 00b: 1 residual bits at maximum 01b: 2 residual bits at maximum 10b: 3 residual bits at maximum (default) 11b: 4 residual bits at maximum
Datasheet, Public Page 49 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview CFG9 Register Figure 59: CFG9 Note(s): 1. Return to the Register Map ( 0xAA ). Addr: 0xAA CFG9 Bit Field Reset Type Bit Description 7:2 Reserved 0 1:0 MOD_RESIDUAL_ BITS_IGNORE 0R / W Sets the number of residual bits ignored and shifted in flicker data. Please observe to set MOD_FD_FIFO_DATAx_ WIDTH accordingly.
Page 50 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview MOD_CHANNEL_CTRL Register Figure 60: MOD_CHANNEL_CTRL Note(s): 1. Return to the Register Map ( 0xAB ). Addr: 0xAB MOD_CHANNEL_CTRL Bit Field Reset Type Bit Description
7 MOD7_DISABLE 0 R/W When asserted modulator 7 is disabled
6 MOD6_DISABLE 0 R/W When asserted modulator 6 is disabled
5 MOD5_DISABLE 0 R/W When asserted modulator 5 is disabled
4 MOD4_DISABLE 0 R/W When asserted modulator 4 is disabled
3 MOD3_DISABLE 0 R/W When asserted modulator 3 is disabled
2 MOD2_DISABLE 0 R/W When asserted modulator 2 is disabled
1 MOD1_DISABLE 0 R/W When asserted modulator 1 is disabled
0 MOD0_DISABLE 0 R/W When asserted modulator 0 is disabled
Page 52 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview VSYNC_GPIO_INT Register Figure 63: VSYNC_GPIO_INT Note(s): 1. Return to the Register Map ( 0xB0 ). Addr: 0xB0 VSYNC_GPIO_INT Bit Field Reset Type Bit Description 7R e s e r v e d 0 6 INT_INVERT 0 R/W If set to “1” the INT pin output is inverted. This applies to all output signals as selected in INT_PINMAP . 5I N T _ I N _ E N 0 R / W If programmed to “1” the INT pin is set as input. Please observe that the connected net must not be floating since INT is an open drain input. 4 INT_IN 0 R External HIGH or LO value applied to INT pin.
3 VSYNC_GPIO_
If set to “1” the VSYNC/GPIO pin output is inverted. This applies to all output signals as selected in VSYNC_GPIO_ PINMAP .
2 VSYNC_GPIO_
IN_EN 0R / W If programmed to “1” the VSYNC/GPIO pin is set as in-put. Please observe that the connected net must not be floating since VSYNC/GPIO is an open drain input.
1 VSYNC_GPIO_OUT 1 R/W
Programs the VSYNC/GPIO pin HI or LOW. Since the pin is an open drain I/O pin, the default value is HIGH to avoid any unintended power consumption through pull-up resistor. The routed internal signal is selected in VSYNC_ GPIO_PINMAP . 0 VSYNC_GPIO_IN 0 R External HIGH or LO value applied to VSYNC/GPIO pin.
Datasheet, Public Page 53 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview INTENAB Register Figure 64: INTENAB Note(s): 1. Return to the Register Map ( 0xBA ). Addr: 0xBA INTENAB Bit Field Reset Type Bit Description 7M I E N 0 R / W Modulator Interrupt Enable. Setting this bit will allow a modulator interrupt on the external INT pin. Please check in STATUS2 for the reason of the interrupt. 6:4 Reserved 0 3A I E N 0 R / W ALS Interrupt Enable. Setting this bit will allow an ALS interrupt on the external INT pin. Please check in STATUS3 for the reason of the interrupt.
2 FIEN 0 R/W
FIFO Interrupt Enable. Setting this bit will allow a fifo interrupt on the external INT pin. Please observe that this interrupt indicates that data in the FIFO is available for readout. Check FINT for further information. 1R e s e r v e d 0
0 SIEN 0 R/W
System Interrupt Enable. Setting this bit will allow a system interrupt on the external INT pin. Please check in STATUS5 for the reason of the interrupt.
Page 54 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview SIEN Register Figure 65: SIEN Note(s): 1. Return to the Register Map ( 0xBB ). CONTROL Register Figure 66: CONTROL Note(s): 1. Return to the Register Map ( 0xBC ). Addr: 0xBB SIEN Bit Field Reset Type Bit Description 7:3 Reserved 0
2 SIEN_AUX 0 R/W
Auxiliary System Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as an auxiliary interrupt occurs. Please see SINT_AUX for further information. SIEN_ MEASUREMENT_ SEQUENCER 0R / W Measurement Sequencer Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as invoked by a measurement sequencer event. Please see SINT_ MEASUREMENT_SEQUENCER for further information
0 SIEN_VSYNC 0 R/W
Vsync Interrupt Enable. Setting this bit will allow a system interrupt SINT as soon as soon as a vysnc interrupt occurs. Please see SINT_VSYNC for further information. Addr: 0xBC CONTROL Bit Field Reset Type Bit Description 7:2 Reserved 0 1F I F O _ C L R 0 R / W Setting this bit will clear the FIFO, as well as FINT, FIFO_ FULL, FIFO_OVERFLOW, FIFO_UNDERFLOW and FIFO_LVL.
0 CLEAR_SAI_
ACTIVE 0R / W Setting this bit will clear the Sleep After Interrupt Active SAI_ACTIVE and start measurements if enabled.
Datasheet, Public Page 55 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview ALS_DATA_STATUS Register Figure 67: ALS_DATA_STATUS Note(s): 1. Return to the Register Map ( 0xBD ). ALS_DATA_FIRST Register Figure 68: ALS_DATA_FIRST Note(s): 1. Return to the Register Map ( 0xBE ). ALS_DATA Register Figure 69: ALS_DATA Addr: 0xBD ALS_DATA_STATUS Bit Field Reset Type Bit Description
7 ALS_DATA_VALID 0 R
ALS Data Valid. Indicates that the ALS state has completed a cycle since either an assertion of AEN or the last readout of the ALS_DATA_FIRST register. 6:0 Reserved 0 Addr: 0xBE ALS_DATA_FIRST Bit Field Reset Type Bit Description
7 ALS_DATA_FIRST 0 R
ALS Data First. ALS_CB_ENABLE needs to be set in order to read and update to the latest ALS data. A part of the FIFO is used for this function. In such case the FIFO size will be reduced from 1280 to 896 bytes. 6:0 Reserved 0 Addr: 0xBF ALS_DATA Bit Field Reset Type Bit Description 7:0 ALS_DATA 0 R Continue Reading ALS data. ALS_CB_ENABLE needs to be set in order to read and update to the latest ALS data. A part of the FIFO is used for this function. In such case the FIFO size will be reduced from 1280 to 896 bytes. ATTENTION: Automatic address wrap from to this address. In this case the wrap is done from ALS_DATA_H to ALS_ DATA_H.
Page 70 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview MEAS_SEQR_APERS_AND_VSYNC_WAIT Register Figure 98: MEAS_SEQR_APERS_AND_VSYNC_WAIT Note(s): 1. Return to the Register Map ( 0xDC ). Addr: 0xDC MEAS_SEQR_APERS_AND_VSYNC_WAIT Bit Field Reset Type Bit Description 7:4 MEASUREMENT_ SEQUENCER_ VSYNC_WAIT_ PAT TERN 0000b R/W Defines if a measurement sequence shall wait for a vsync before starting the measurement. The bit pattern does not represent a value but controls bitwise which sequencer step shall be used. The leftmost position of “0000” refers to sequencer step 3, the rightmost refers to sequencer step 0. 3:0 MEASUREMENT_ SEQUENCER_ APERS_ PAT TERN 0001b R/W Defines the sequencer steps where an ALS persistence evaluation shall be performed on modulator data selected by ALS_THRESHOLD_CHANNEL. The bit pattern does not represent a value but controls bitwise which sequencer step shall be used. The leftmost position of “0000” refers to sequencer step 3, the rightmost refers to sequencer step 0. By default step 0 is used on all modulators.
Datasheet, Public Page 73 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MOD_CALIB_CFG2 Register Figure 103: MOD_CALIB_CFG2 Note(s): 1. Return to the Register Map ( 0xE2 ). Addr: 0xE2 MOD_CALIB_CFG2 Bit Field Reset Type Bit Description MOD_CALIB_NTH_ ITERATION_RC_ ENABLE 1R / W Enables a residual calibration during the nth iteration. Please observe that this residual calibration feature only makes sense for modulators which are enabled in the first sequences step, since a gain calibration only happens in the first sequencer step. MOD_CALIB_NTH_ ITERATION_AZ_ ENABLE 1 R/W Enables auto-zero calibration during the nth iteration. MOD_CALIB_NTH_ ITERATION_AGC_ ENABLE 0R / W Enables AGC calibration during the nth iteration. Please observe in this case, that MOD_CALIB_NTH_ ITERATION_STEP_ENABLE must be “0” otherwise AGC will not be properly executed. MOD_CALIB_ RESIDUAL_ENABLE_ AUTO_CALIB_ON_ GAIN_CHANGE 1R / W Enables an automatic re-calibration in case of a change in gain. This recalibration is executed at the beginning of each sequencer step. 3:0 MOD_CALIB_ RESIDUAL_AVERAGE_ ROUNDS
0011 R/W
Defines the number of averaging rounds during residual calibrations. 0000b: No averaging 0001b: 2 averaging rounds 0010b: 3 averaging rounds 1111b: 16 averaging rounds
Page 78 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview VSYNC_PERIOD_TARGET0 Register Figure 113: VSYNC_PERIOD_TARGET0 Note(s): 1. Return to the Register Map ( 0xEF ). VSYNC_PERIOD_TARGET1 Register Figure 114: VSYNC_PERIOD_TARGET1 Note(s): 1. Return to the Register Map ( 0xF0 ). Addr: 0xEF VSYNC_PERIOD_TARGET0 Bit Field Reset Type Bit Description 7:0 VSYNC_PERIOD_ TARGET[7:0] 0R / W It sets the target vsync period. The value can be calculated as VSYNC_PERIOD_TARGET = ((1/target_ frequency_in_Hz) * 1.3888888 * 10-6). Addr: 0xF0 VSYNC_PERIOD_TARGET1 Bit Field Reset Type Bit Description
7 VSYNC_PERIOD_USE_
FAST_TIMING_EVAL 0R / W If set to “0” it selects VSYNC_PERIOD[15:1] (range 15Hz to 500Hz) and if set to “1” it selects VSYNC_ PERIOD[14:0] (range 30Hz to 1kHz). 6:0 VSYNC_PERIOD_ TARGET[14:8] 0R / W S e e VSYNC_PERIOD_TARGET0 .
Datasheet, Public Page 79 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview VSYNC_CONTROL Register Figure 115: VSYNC_CONTROL Note(s): 1. Return to the Register Map ( 0xF1 ). VSYNC_CFG Register Figure 116: VSYNC_CFG Addr: 0xF1 VSYNC_CONTROL Bit Field Reset Type Bit Description 7:1 Reserved 0
0 SW_VSYNC_TRIGGER 0 R/W
Trigger Software vsync Pulse. In case if vsync_mode is 1, this register can be written to 1 to trigger a vsync from I²C/I3C side. If one knows the exact time between two such I²C/I3C writings, the oscillator offset can be calculated by using the resulting value in vsync_ trigger. Addr: 0xF2 VSYNC_CFG Bit Field Default Access Bit Description 7:6 OSC_CALIB_MODE 0 R/W Oscillator calibration mode register Value ID Meaning 0 osccal_ disable no autmatic oscillator calibration is done 1 osccal_ after_pon if pon goes to 1 or after each vsync_lost goes 0 an oscillator calibration is done once not during measurement 2 osccal_ always_on oscillator calibration is done always if possible, not during measurement and not if vsync_lost is detected 3 osccal_ reserved if set to 3, osccal is also not starting
Page 80 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview Note(s): 1. Return to the Register Map ( 0xF2 ). FIFO_THR Register Figure 117: FIFO_THR Note(s): 1. Return to the Register Map ( 0xF3 ).
2 VSYNC_MODE 0 R/W
Select which input to use for vsync Value ID Meaning pad_ vsync_ trigger Use VSYNC/GPIO/INT input as vsync start trigger 1 sw_vsync_ trigger Use VSYNC_ CONTROL.sw_vsync_ trigger as vsync trigger
1 VSYNC_SELECT 0 R/W
Select which input to use for vsync Value ID Meaning 0 vsync_gpio Use VSYNC/GPIO input 1i n t U s e I N T i n p u t
0 VSYNC_INVERT 0 R/W
If enabled then the selected vsync input is inverted. Value ID Meaning 0 do_not_ invert Do not invert 1i n v e r t D o i n v e r t Addr: 0xF3 FIFO_THR Bit Field Default Access Bit Description 7:0 FIFO_THR[10:3] 127 R/W If FIFO_LVL > FIFO_THR, an FIFO interrupt FINT is raised. See CFG2 and FIFO_LVL[2:0] for lsbs. Addr: 0xF2 VSYNC_CFG Bit Field Default Access Bit Description
Datasheet, Public Page 81 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MOD_FIFO_DATA_CFG0 Register Figure 118: MOD_FIFO_DATA_CFG0 Note(s): 1. Return to the Register Map ( 0xF4 ). Addr: 0xF4 MOD_FIFO_DATA_CFG0 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA0_WRITE_ ENABLE 1R A M = 0 x 1 0 L Enable ALS data write to fifo of modulator 0, if flicker measurement is not enabled in this sequencer step or ficker measurement has already finished (select als_ nr_samples >= fd_nr_samples) or in case of do_als_ final_processing_after_flicker. MOD_FD_FIFO_ DATA0_ COMPRESSION_ ENABLE 0R A M = 0 x 1 0 L Enables data compression in case of flicker detection mode. MOD_FD_FIFO_ DATA0_ DIFFERENCE_ ENABLE 0R A M = 0 x 1 0 L Enables that only the difference between previous and actual data is used for data writing instead of actual data value. This makes only sense in case of MOD_FD_FIFO_DATA0_COMPRESSION_ENABLE=1. 3:0 MOD_FD_FIFO_ DATA0_WIDTH 15 RAM=0x10L Select data width to use for FIFO writing of flicker data0. Or in case of compression select the width of the data parts. See MOD_ALS_FIFO_DATA0_WRITE_ ENABLE for more details. In case of no compression the user must specify the mod_fd_fifo_dataX_width's so that the full possible data is written to the fifo (log2(sample_time)+4). ATTENTION: There is no digital saturation implemented that show's a range overflow. There was not enough resources left to implement this.
Page 82 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview MOD_FIFO_DATA_CFG1 Register Figure 119: MOD_FIFO_DATA_CFG1 Note(s): 1. Return to the Register Map ( 0xF5 ). Addr: 0xF5 MOD_FIFO_DATA_CFG1 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA1_WRITE_ ENABLE 1R A M = 0 x 1 1 L S e e MOD_ALS_FIFO_DATA0_WRITE_ENABLE . MOD_FD_FIFO_ DATA1_ COMPRESSION_ ENABLE 0R A M = 0 x 1 1 L See MOD_FD_FIFO_DATA0_COMPRESSION_ ENABLE and MOD_FD_FIFO_DATA0_WIDTH for more details. MOD_FD_FIFO_ DATA1_ DIFFERENCE_ ENABLE 0R A M = 0 x 1 1 L S e e MOD_FD_FIFO_DATA0_DIFFERENCE_ENABLE . 3:0 MOD_FD_FIFO_ DATA1_WIDTH 15 RAM=0x11L See MOD_FD_FIFO_DATA0_WIDTH .
Datasheet, Public Page 83 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MOD_FIFO_DATA_CFG2 Register Figure 120: MOD_FIFO_DATA_CFG2 Note(s): 1. Return to the Register Map ( 0xF6 ). Addr: 0xF6 MOD_FIFO_DATA_CFG2 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA2_WRITE_ ENABLE 1 RAM=0x12L See MOD_ALS_FIFO_DATA0_WRITE_ENABLE . MOD_FD_FIFO_ DATA2_ COMPRESSION_ ENABLE 0R A M = 0 x 1 2 L See MOD_FD_FIFO_DATA0_COMPRESSION_ ENABLE and MOD_FD_FIFO_DATA0_WIDTH for more details. MOD_FD_FIFO_ DATA2_ DIFFERENCE_ ENABLE 0R A M = 0 x 1 2 L See MOD_FD_FIFO_DATA0_DIFFERENCE_ ENABLE . 3:0 MOD_FD_FIFO_ DATA2_WIDTH 15 RAM=0x12L See MOD_FD_FIFO_DATA0_WIDTH .
Page 84 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview MOD_FIFO_DATA_CFG3 Register Figure 121: MOD_FIFO_DATA_CFG3 Note(s): 1. Return to the Register Map ( 0xF7 ). Addr: 0xF7 MOD_FIFO_DATA_CFG3 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA3_WRITE_ ENABLE 1R A M = 0 x 1 3 L S e e MOD_ALS_FIFO_DATA0_WRITE_ENABLE . MOD_FD_FIFO_ DATA3_ COMPRESSION_ ENABLE 0R A M = 0 x 1 3 L See MOD_FD_FIFO_DATA0_COMPRESSION_ ENABLE and MOD_FD_FIFO_DATA0_WIDTH for more details. MOD_FD_FIFO_ DATA3_DIFFERENCE_ ENABLE 0R A M = 0 x 1 3 L See MOD_FD_FIFO_DATA0_DIFFERENCE_ ENABLE 3:0 MOD_FD_FIFO_ DATA3_WIDTH 15 RAM=0x13L See MOD_FD_FIFO_DATA0_WIDTH .
Datasheet, Public Page 85 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MOD_FIFO_DATA_CFG4 Register Figure 122: MOD_FIFO_DATA_CFG4 Note(s): 1. Return to the Register Map ( 0xF8 ). Addr: 0xF8 MOD_FIFO_DATA_CFG4 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA4_WRITE_ ENABLE 1 RAM=0x14L See MOD_ALS_FIFO_DATA0_WRITE_ENABLE . MOD_FD_FIFO_ DATA4_ COMPRESSION_ ENABLE 0R A M = 0 x 1 4 L See MOD_FD_FIFO_DATA0_COMPRESSION_ ENABLE and MOD_FD_FIFO_DATA0_WIDTH for more details. MOD_FD_FIFO_ DATA4_ DIFFERENCE_ ENABLE 0R A M = 0 x 1 4 L See MOD_FD_FIFO_DATA0_DIFFERENCE_ ENABLE . 3:0 MOD_FD_FIFO_ DATA4_WIDTH 15 RAM=0x14L See MOD_FD_FIFO_DATA0_WIDTH .
Page 86 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview MOD_FIFO_DATA_CFG5 Register Figure 123: MOD_FIFO_DATA_CFG5 Note(s): 1. Return to the Register Map ( 0xF9 ). Addr: 0xF9 MOD_FIFO_DATA_CFG5 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA5_WRITE_ ENABLE 1 RAM=0x15L See MOD_ALS_FIFO_DATA0_WRITE_ENABLE . MOD_FD_FIFO_ DATA5_ COMPRESSION_ ENABLE 0R A M = 0 x 1 5 L See MOD_FD_FIFO_DATA0_COMPRESSION_ ENABLE and MOD_FD_FIFO_DATA0_WIDTH for more details. MOD_FD_FIFO_ DATA5_ DIFFERENCE_ ENABLE 0 RAM=0x15L See MOD_FD_FIFO_DATA0_DIFFERENCE_ENABLE . 3:0 MOD_FD_FIFO_ DATA5_WIDTH 15 RAM=0x15L See MOD_FD_FIFO_DATA0_WIDTH .
Datasheet, Public Page 87 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview MOD_FIFO_DATA_CFG6 Register Figure 124: MOD_FIFO_DATA_CFG6 Note(s): 1. Return to the Register Map ( 0xFA). Addr: 0xFA MOD_FIFO_DATA_CFG6 Bit Field Default Access Bit Description MOD_ALS_FIFO_ DATA6_WRITE_ ENABLE 1R A M = 0 x 1 6 L S e e MOD_ALS_FIFO_DATA0_WRITE_ENABLE . MOD_FD_FIFO_ DATA6_ COMPRESSION_ ENABLE 0R A M = 0 x 1 6 L See MOD_FD_FIFO_DATA0_COMPRESSION_ ENABLE and MOD_FD_FIFO_DATA0_WIDTH for more details. MOD_FD_FIFO_ DATA6_ DIFFERENCE_ ENABLE 0R A M = 0 x 1 6 L S e e MOD_FD_FIFO_DATA0_DIFFERENCE_ENABLE . 3:0 MOD_FD_FIFO_ DATA6_WIDTH 15 RAM=0x16L See MOD_FD_FIFO_DATA0_WIDTH .
Datasheet, Public Page 89 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview FIFO_STATUS1 Register Figure 127: FIFO_STATUS1 Note(s): 1. Return to the Register Map ( 0xFD ). FIFO_DATA_PROTOCOL Register Figure 128: FIFO_DATA_PROTOCOL Note(s): 1. Return to the Register Map ( 0xFE ). Addr: 0xFD FIFO_STATUS1 Bit Field Reset Type Bit Description
7 FIFO_OVERFLOW 0 R
If set to “1” a FIFO overflow has occurred and data for the FIFO was lost (e.g. reading from FIFO was too slow). This flag is cleared by PON and FIFO_CLR. Always check this flag before and after reading the FIFO. Read FIFO_STATUS0 and then FIFO_STATUS1 to get consistent values for both registers. 6F I F O _ U N D E R F L O W 0 R If set to “1” the FIFO was read out too often and has returned 0 at least once. In such case the read-out data may not consistent anymore. This flag is cleared by PON and FIFO_CLR. Always check this flag before and after reading the FIFO. Read FIFO_STATUS0 and then FIFO_STATUS1 to get consistent values for both registers. 5:3 Reserved 0 2:0 FIFO_LVL[2:0] 0 R See FIFO Status 0 for description. Read FIFO_STATUS0 and then FIFO_STATUS1 to get consistent values for both registers. Addr: 0xFE FIFO_DATA_PROTOCOL Bit Field Reset Type Bit Description 7:0 FIFO_DATA_ PROTOCOL 0R The register FIFO_DATA_PROTOCOL can used to read-out FIFO data using the protocol mechanism. It can be read out with single reads or with a block-read.
Page 90 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Register Overview FIFO_DATA Registers Figure 129: FIFO_DATA Note(s): 1. Return to the Register Map ( 0xFF ). Addr: 0xFF FIFO_DATA Bit Field Reset Type Bit Description 7:0 FIFO_DATA 0 R The register FIFO_DATA can be read-out with single reads or with a block-read. Upon reading out FIFO_DATA, the internal FIFO read pointer is advanced and FIFO_LVL is decreased. A false reading upon the FIFO_LVL will return 0 and set the FIFO_UNDERFLOW flag.
Page 92 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Package Drawings & Markings Figure 132: TCS3530 Module Dimensions Note(s): 1. All linear dimensions are in millimeters. 2. Contacts are copper with NiPdAu plating (ENEPIG). 3. This package contains no lead (Pb). 4. This drawing is subject to change without notice. Package Drawings & Markings
Datasheet, Public Page 93 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 133: TCS3530 PCB Pad Layout Note(s): 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. PCB Pad Layout
Page 94 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Tape & Reel Information Figure 134: Tape and Reel Mechanical Drawing Note(s): 1. All linear dimensions are in millimeters. Dime nsion tolerance is ± 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. 4. Each reel is generally 330 millimeters in diameter and contains 5000 parts. Please reconfirm for actual orders. 5. ams OSRAM packaging tape and reel confor m to the requirements of EIA Standard 481−B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Tape & Reel Information
Datasheet, Public Page 95 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Soldering & Storage Information Soldering Information The module has been tested an d has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Please observe that re-soldering the module will influence color measurement accuracy. Please consult with application team in such case. Figure 135: Solder Reflow Profile Note(s): 1. Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum. Profile Feature Preheat/Soak Sn-Pb Eutectic Assembly Pb-Free Assembly Temperature Min ( Tsmin) 100°C 150°C Temperature Max ( Tsmax) 150°C 200°C Time (ts) from (Tsmin to Tsmax) 60-120 s 60-120 s Ramp-up rate (TL to TP) 3°C/s max. 3°C/s max. Liquidous temperature (TL) Time (tL) maintained above TL 183°C 60-150 s 217°C 60-150 s Peak package body temperature (TP) For users TP must not exceed the Classification temp of 235°C For suppliers TP must equal or exceed the Classification temp of 235°C For users TP must not exceed the Classification temp of 260°C For suppliers TP must equal or exceed the Classification temp of 260°C Time (tP)(1) within 5°C of the specified classification temperature (Tc) 20(1)s3 0 (1)s Ramp-down rate (TP to TL) 6°C/s max. 6°C/s max. Time 25°C to peak temperature 6 minutes max. 8 minutes max. Soldering & Storage Information
Page 96 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Soldering & Storage Information Figure 136: Solder Reflow Profile Graph Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 24 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 24 months
- Ambient Temperature: <40°C
- Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 24 months shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Not to Scale – For Reference Only TP Temperature (°C) Time (seconds) tL TL TC - 5°C tP Tsmin Tsmax Preheat Area Max Ramp Up Rate = 3°C/s Max Ramp Down Rate = 6°C/s
Datasheet, Public Page 97 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Soldering & Storage Information Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: <30°C
- Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
Page 98 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Ordering & Contact Information Figure 137:
Ordering Information
Note(s): 1. TCS35303-3 on request with I3C mode enabled. Buy our products or get free samples online at: www.ams.com/Products Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/Contact Headquarters ams-OSRAM AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Address Interface Delivery Form Delivery Quantity TCS35303-2 0x39 1.8V/1.2V I²C Tape & Reel 5000 pcs/reel TCS35303-2M 0x39 1.8V/1.2V I²C Tape & Reel 500 pcs/reel Ordering & Contact Information
Datasheet, Public Page 99 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
Page 100 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Copyrights & Disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provis ions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by desc ription regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications re quiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but no t limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. Copyrights & Disclaimer
Datasheet, Public Page 101 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
Page 102 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 2-00 (2022-Jun-24) to current revision 3-00 (2023-Jun-23) Page Updated document security class from “Confidential” to “Public” Updated Shelf Life from 12 months to 24 months 96 Revision Information
Datasheet, Public Page 103 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Content Guide
1 General Description
2 Key Benefits & Features
2 Applications
3 Block Diagram
4 Pin Assignments
5A b s o l u t e M a x i m u m R a t i n g s
7 Optical Characteristics
8 Color and Lux Measurement Accuracy
10 Wavelength Accuracy
12 Timing Characteristics
14 Typical Operating Characteristics
15 Detailed Description
15 State Machine Diagrams
17 I²C Protocol
18 Register Overview
18 Register Map
24 Register Description
24 CONTROL_SCL Register
24 Modulator Offset Register
26 OSCEN Register
26 ENABLE Register
27 MEAS_MODE0 Register
28 MEAS_MODE1 Register
29 SAMPLE_TIME0 Register
29 SAMPLE_TIME1 Register
30 SAMPLE_TIME_ALTERNATIVE0 Register
30 SAMPLE_TIME_ALTERNATIVE1 Register
31 ALS_NR_SAMPLES0 Register
31 ALS_NR_SAMPLES1 Register
32 ALS_NR_SAMPLES_ALT ERNATIVE0 Register
32 ALS_NR_SAMPLES_ALT ERNATIVE1 Register
33 FD_NR_SAMPLES0 Register
33 FD_NR_SAMPLES1 Register
34 FD_NR_SAMPLES_ALTERNATIVE0 Register
34 FD_NR_SAMPLES_ALTERNATIVE1 Register
35 WTIME Register
35 Identification Registers
36 ALS Interrupt Low Threshold Register
36 ALS Interrupt High Threshold Register
37 AGC Number of Samples Register
37 STATUS Register
38 STATUS2 Register
39 STATUS3 Register
40 STATUS4 Register
41 STATUS5 Register
42 STATUS6 Register
43 CFG0 Register
43 CFG1 Register
Page 104 Datasheet, Public Document Feedback [v3-00] 2023-Jun-23 TCS3530 − Content Guide
44 CFG2 Register
44 CFG3 Register
45 CFG4 Register
46 CFG5 Register
47 CFG6 Register
48 CFG7 Register
48 CFG8 Register
49 CFG9 Register
50 MOD_CHANNEL_CTRL Register
51 TRIGGER_MODE Register
51 OSC_TUNE Register
52 VSYNC_GPIO_INT Register
53 INTENAB Register
54 SIEN Register
54 CONTROL Register
55 ALS_DATA_STATUS Register
55 ALS_DATA_FIRST Register
55 ALS_DATA Register
56 MEAS_SEQR_STEP0_MOD_GAINX_0 Register
56 MEAS_SEQR_STEP0_MOD_GAINX_1 Register
57 MEAS_SEQR_STEP0_MOD_GAINX_2 Register
57 MEAS_SEQR_STEP0_MOD_GAINX_3 Register
58 MEAS_SEQR_STEP1_MOD_GAINX_0 Register
58 MEAS_SEQR_STEP1_MOD_GAINX_1 Register
59 MEAS_SEQR_STEP1_MOD_GAINX_2 Register
59 MEAS_SEQR_STEP1_MOD_GAINX_3 Register
60 MEAS_SEQR_STEP2_MOD_GAINX_0 Register
60 MEAS_SEQR_STEP2_MOD_GAINX_1 Register
61 MEAS_SEQR_STEP2_MOD_GAINX_2 Register
61 MEAS_SEQR_STEP2_MOD_GAINX_3 Register
62 MEAS_SEQR_STEP3_MOD_GAINX_0 Register
62 MEAS_SEQR_STEP3_MOD_GAINX_1 Register
63 MEAS_SEQR_STEP3_MOD_GAINX_2 Register
63 MEAS_SEQR_STEP3_MOD_GAINX_3 Register
64 MEAS_SEQR_STEP0_FD Register
64 MEAS_SEQR_STEP1_FD Register
65 MEAS_SEQR_STEP2_FD Register
65 MEAS_SEQR_STEP3_FD Register
66 MEAS_SEQR_STEP0_RESIDUAL Register
66 MEAS_SEQR_STEP1_RESIDUAL Register
67 MEAS_SEQR_STEP2_RESIDUAL Register
67 MEAS_SEQR_STEP3_RESIDUAL Register
68 MEAS_SEQR_STEP0_ALS Register
68 MEAS_SEQR_STEP1_ALS Register
69 MEAS_SEQR_STEP2_ALS Register
69 MEAS_SEQR_STEP3_ALS Register
70 MEAS_SEQR_APERS_AND_ VSYNC_WAIT Register
71 MEAS_SEQR_AGC Register
71 MEAS_SEQR_SMUX_AND_SAMPLE_TIME Register
72 MEAS_SEQR_WAIT_AND_TS_ENABLE Register
72 MOD_CALIB_CFG0 Register
73 MOD_CALIB_CFG2 Register
74 MOD_CALIB_CFG3 Register
74 MOD_COMP_CFG2 Register
Datasheet, Public Page 105 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Content Guide