TMD3725 AMSCO | Alldatasheet
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[v1-05] 2018-Mar-08 Document Feedback TMD3725 ALS, Color and Proximity Sensor Module The device features advanced proximity measurement, color sense (RGBC+IR), and digital ambient light sensing (ALS). The package has been designed to accommodate a “single hole” aperture approach. The slim module incorporates an IR LED and factory calibrated LED driver. The proximity detection feature provides object detection (e.g. mobile device screen to user’s ear) by photodiode detection of reflected IR energy (sourced by the integrated LED). Detect/release events are interrupt driven, and occur when proximity result crosses upper and/or lower threshold settings. The proximity engine features offset adjustment registers to compensate for unwanted IR energy reflection at the sensor. Proximity results are further improved by automatic ambient light subtraction. The ALS detection feature provides photopic light intensity data. The color photodiodes have UV and IR blocking filters and a dedicated data converters producing 16-bit data. This architecture allows applications to accurately measure ambient light which enables devices to calculate illuminance and color temperature to control display backlight and chromaticity. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TM D3725, ALS, Color and Proximity Sensor Module are listed below: Figure 1: Added Value of Using TMD3725 Benefits Features
- Single glass aperture solution • 1.0mm spacing between proximity IR LED and sensor
- Reduced board space requirements and enables low-profile system design
- Small footprint and low-profile package (3.65 mm x 2.00 mm x 1.00 mm)
- Accurate color temperature and ambient light sensing
- UV / IR blocking filters
- 460 Average FOV
- Photopic ambient light sensing (ALS)
- Programmable gain and integration time
- Compact integrated optical module • Color (RGB), Ambient Light and Proximity Sensing with integrated IR LED
- Reduced power consumption
- Power management features (active, idle and sleep states)
- 1.8V power supply with 1.8V I²C bus General Description
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − General Description
Applications
The TMD3725 applic ations include:
- Ambient light sensing
- Single hole proximity sensing
- Mobile phone touc h screen disable
- Color temperature sensing to assist backlight, camera, and flash control Block Diagram The functional blocks of this device are shown below: Figure 2: Functional Blocks of TMD3725 Wa it Control Pr ox im ity LED Current Sink I²C Interface Red - Ch 1 Green - Ch 2 Lower Upper Prox DataProx ADC Prox Integration Prox Control INT SCL SDA VDD Optically Isolated IR LE D GND ALS Thresholds CH0 ADC CH1 ADC CH0 Data ALS Control CH1 Data Interrupt Out / Threshol d Status LEDA IR - Ch 4 Lower Upper Prox Thresholds CH2 ADC CH3 ADC CH2 Data CH3 Data Clear - Ch 0 Blue - Ch 3 PGND TMD37253S LEDK/LDR
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Pin Assignment Figure 3: Pin Diagram of TMD3725 Figure 4: Pin Description of TMD3725 (8-Pin Module) Pin Number Pin Name Description
1 VDD Supply voltage
2 SDA I²C serial data I/O terminal
3 SCL I²C serial clock input terminal
4 LEDA LED anode
5L E D K / L D R LED driver (sinks current) and LED cathode (for direct access to LED)
6 PGND Ground for LED current sink and pins with open drain
7 INT Interrupt. Open drain output (active low) 8 VSS Ground. All voltages are referenced to GND Pin Assignment 9'' 6'$ 6&/ /('$ 966 ,17 3*1' /('./'5
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply Voltage to Ground -0.3 2.2 V LEDA LED Voltage to PGND -0.3 3.6 V VIO Digital I/O Terminal Voltage -0.3 3.6 V IIO SDA, INT Output Terminal Current -1 20 mA Electrostatic Discharge ISCR Input Current (latch up immunity) JEDEC JESD78D ±100 mA Class II ESD HBM Electrostatic Discharge HBM JS-001-2014 ± 2000 V ESD CDM Electrostatic Discharge CDM JEDEC JESD22-C101F ± 500 V Absolute Maximum Ratings
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Absolute Maximum Ratings Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range -40 85 °C IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices. ” RH NC Relative Humidity (non-condensing) 58 5% MSL Moisture Sensitivity Level 3 Maxi mum floor life time 168 hours Symbol Parameter Min Max Units Comments
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Typical Operating Characteristics Figure 8: Optical Characteristics, VDD = 1.8V, T A = 25°C (unless otherwise noted) Figure 9: ALS Optical Characteristics, VDD = 1.8V, T A = 25°C (unless otherwise noted) Note(s): 1. The typical value based on 3-sigma distribution. An AGAIN setti ng of 16x correlates to a typically dark ADC count value less than or equal to 1. Parameter Conditions Clear Channel Unit Min Typ Max Re Irradiance responsivity Settings: AGAIN = 16x ATIME = 400ms λ D = 465 nm LED, 53.8 μW/cm2 128 Count/ (μW/cm2) λD = 530 nm LED, 43.9 μW/cm2 161 λD = 620 nm LED, 37.5 μW/cm2 191 Warm White LED, 45.6 μW/cm2 161 Warm White LED, 45.6 μW/cm2 5950 7000 8050 Counts λD = 950 nm LED, 21.1 μW/cm2 1.5 Count/ (μW/cm2) Parameter Conditions Min Typ Max Unit Integration time step size 2.68 2.78 2.90 ms Dark ADC count value Ee = 0 μW/ cm2 AGAIN: 64x ATIME = 100ms (0x23)
012 Counts (1)
Gain scaling, relative to 1x gain setting AGAIN = 4x 4 x AGAIN = 16x 16 AGAIN = 64x 67 AGAIN = 128x 140 ADC noise AGAIN = 16x 0.005 % full scale Typical Operating Characteristics
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Typical Operating Characteristics Figure 10: Proximity Optical Characteristics, VDD = 1.8V, T A = 25°C (unless otherwise noted) Note(s): 1. Production tested result is the average of 5 readings expressed relative to a calibrated response. 2. Representative result by characterization. 3. Production tested result is the average of 20 readings divided by the maximum proximity value 255. Parameter Conditions Min Typ Max Unit Part to part variation (1) Conditions: PGAIN = 2 (4x) PLDRIVE = 8 (54mA) PPULSE = 15 (16 pulses) PPULSE_LEN = 1 (8μs) d=23mm round target 30mm target distance 75 100 125 % Response, absolute Basic proximity measurement (2) Conditions: PGAIN = 2 (4x), PLDRIVE = 16 (102mA) PPULSE = 15 (16 pulses) PPULSE_LEN = 2 (16μs) Target material: 90% reflective surface of Kodak gray card Target Size: 100mm x 100mm Target Distance: 100mm 128 160 192 Counts Response, no target after optical calibration PGAIN = 2 (4x) ILEDDRIVE = 16 (102mA) PPULSE = 16 (17 pulses) Pulse Length = 2 (16μs) 01 2 Noise/Signal (3) PGAIN = 2 (4x) IRLEDDRIVE = 8 (54mA) PPULSE = 15 (16 pulses) PPULSE_LEN = 1 (8μs) d=23mm round target 30mm target distance
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Typical Operating Characteristics Figure 15: Proximity Operation Proximity Operation: By varying Gain, LED drive current, number of LED pulses and LED pulse duration the proximity detection range can be adjusted. 100 150 200 250 1 2 3 4 5 10 15 20 25 30 35 40 50 60 70 80 90 100 110 120 130 140 150 Proximity Count (0 - 255 Range) Distance to Target in mm Proximity Operating Range using six 90mA pulses, while varying Gain and Pulse Length 4uS, 1X Gain 8uS, 2X Gain 16uS, 4X Gain 32uS, 8X Gain
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Detailed Description Proximity Proximity results are affected by three fundamental factors: the integrated IR LED emission, IR reception, and environmental factors, including target distance and surface reflectivity. The IR reception signal path be gins with IR detection from a photodiode and ends with the 8- bit proximity result in PDATA register. Signal from the photodiode is amplified, and offset adjusted to optimize performance. Offset correction or cross-talk compensation is accomplished by adjustment to the POFFSET register. The analog circuitry of the device applies the offset value as a subtraction to the signal accumulation; therefore a positive offset value has the effect of decreasing the results. Color and Ambient Light Sense The color and ALS reception signal path begins as photodiodes receive filtered light and ends with 16-bit results. The IR photodiode primarily used for proximity sense, is multiplexed with the green channel’s ADC to measure the IR content of ambient light. The color photodiodes are filtered with a UV and IR filters. The IR photodiode is filtered to receive only IR. Signal from the RGBC photodiodes simultaneously accumulate for a period of time set by the value in ATIME before the results are available. Measurement of IR must be done in a separate integration because it shares the ADC with the green photodiode. Gain is adjustable fr om 1x to 128 x to facilitate operation over a wide range of lighting conditions. Custom LUX equations are used to calculate the amount of ambient light, color temperature, as well as, determine the light type (e.g. LED, fluorescent, incandescent, etc.) using the ALS results. I²C Characteristics The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and both standard and fast clock frequency modes with a chip address of 0x39. Read and Write transactions comply with the standard set by Ph ilips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address + 1. Detailed Description
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Detailed Description I²C Write Transaction A Write transaction consists of a START, CHIP-ADDRESS WRITE , REGISTER-ADDRESS, DATA BYTE(S ), and STOP . Following each byte (9 th clock pulse) the slave places an ACKNOWLEDGE/ NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP . I²C Read Transaction A Read transaction consists of a START, CHIP-ADDRESS WRITE , REGISTER-ADDRESS, START, CHIP-ADDRESS READ, DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9 th clock pulse). Termination of the Read transaction is indicated by a NA CK being placed on the bus by the master, followed by STOP . Alternately, if the previous I²C transaction was a Read, the internal register address buffer is still valid, allowing the transaction to proceed without “re”-specifying the register address. In this case the transaction consists of a START, CHIP-ADDRESS READ, DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9 th clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP . The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at: www.i2c-bus.org/references/ Timing Diagrams Figure 16: I²C Timing
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Principles of Operation System State Machine An internal state machine provides system control of the ALS, proximity detection, and power management features of the device. At power up, an internal power-on-reset initializes the device and puts it in a lowpower Sleep state. When a write on I²C bus to the Enable register (0x80) PON bit is set, the device transitions to the Idle state. If PON is disabled, the device will return to the Sleep state to save power. Otherwise, the device will remain in the Idle state unti l a Proximity or ALS function is enabled. Once enabled, the device will execute the ALS, Proximity and Wait states in sequence as indicated in Figure 17 and Figure 18 . Upon completion, the device will automatically begin a new ALS-Prox-Wait cycle as long as PON and either PEN or AEN remain enabled. If the Prox or ALS function generates an interrupt and the Sleep-After-Interrupt (SAI) feature is enabled, the device will transition to the Sleep state and remain in a low-power mode until an I²C command is received clearing the interrupts in the STATUS register. See Interrupts for additional information. Principles of Operation
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Principles of Operation Figure 17: Detailed State Diagram aen Run ALS Integration pen Run Proximity Offset Calibration Run Proximity Integration yes yes Run Autozero Calibration no no ~aen Oscillator On (IDLE) Oscillator Off (SLEEP) pon no yes az-done yes az-done = 1 aen | pen yes start-offset-calibno yes no no aen | pen wen yes aen==1 && az-done==0 no yes az-done = 1 yes no Run Autozero Calibration Run WTIME timer no az-done & wtime-done yes yes ~wen | (~aen & ~pen) wtime-done = 0 wtime-done = 1 autozero calibration is executed in parallel to running WTIME timer wen==0 | (aen==0 & pen==0) aborts WTIME timer aen==0 aborts ALS An I2C Write to az-nth-iteration register, except of the value 00h(disable-az), resets az-done independent of actual cntrl-state. In consequence, a new autozero calibration will be started in advance to the next ALS integration cycle. az-done = 0 (reset) az-done = 0, if az-nth iterations passed since last AZ calibration. (refer to note 1 for exceptions) aen no
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Principles of Operation Figure 18: Simplified State Diagram aen=1 Run ALS Integration Run Proximity Offset Calibration Run Autozero Calibration yes Oscillator On (IDLE) Oscillator Off (SLEEP) pon=1no 1st ALS iteration yes aen=0 & pen=0 no start-offset-calibyes yes no no no wen=0 | (aen=0 & pen=0) aborts WTIME timer aen=0 aborts ALS Az_nth_iteration is assumed 0x7f – Run Autozero once before 1st ALS integration This makes the flow chart simpler, and this is the more usual case pen=1 Run Proximity Integration yes wen=1 Run WTIME timer no yes aen=0 & pen=1yes aen=1 & pen=x no yes no
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description Register Overview Figure 19: Register Overview Address Register Name R/W Register Function Reset Value 0x80 ENABLE R/W Enables states and functions 0x00 0x81 ATIME R/W ALS integration time 0x00 0x82 PRATE R/W Proximity sampling time 0x1F 0x83 WTIME R/W Wait time 0x00 0x84 AILTL R/W ALS interrupt low threshold low byte 0x00 0x85 AILTH R/W ALS interrupt low threshold high byte 0x00 0x86 AIHTL R/W ALS interrupt high threshold low byte 0x00 0x87 AIHTH R/W ALS interrupt hi gh threshold high byte 0x00 0x88 PILT R/W Proximity interrupt low threshold 0x00 0x8A PIHT R/W Proximity interrupt high threshold 0x00 0x8C PERS R/W Interrupt persistence filters 0x00 0x8D CFG0 R/W Configuration register zero 0x80 0x8E PCFG0 R/W Proximity configuration register zero 0x4F 0x8F PCFG1 R/W Proximity configuration register one 0x80 0x90 CFG1 R/W Configuration register one 0x00 0x91 REVID R Revision ID 0x00 0x92 ID R Device ID 0xE4 0x93 STATUS R Device status register 0x00 0x94 CDATAL R Clear channel data low byte 0x00 0x95 CDATAH R Clear channel data high byte 0x00 0x96 RDATAL R Red channel data low byte 0x00 0x97 RDATAH R Red channel data high byte 0x00 0x98 GDATAL (1) R Green channel data low byte 0x00 0x99 GDATAH (1) R Green channel data high byte 0x00 0x9A BDATAL R Blue channel data low byte 0x00 0x9B BDATAH R Blue channel data high byte 0x00 Register Description
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description Note(s): 1. Address 0x98 and 0x99 will contain the results fo r the IR photodiode when controlled by the Green/IR MUX. 2. Register Access: R = Read Only W = Write Only R/W = Read or Write SC = Self Clearing after access 0x9C PDATA R Proximity channel data 0x00 0x9E REVID2 R Auxiliary ID 0x00 0x9F CFG2 R/W Configuration register two 0x04 0xAB CFG3 R/W Configuration register three 0x0C 0xC0 POFFSETL R/W Proximity Offset Magnitude 0x00 0xC1 POFFSETH R/W Proximity Offset Sign 0x00 0xD6 AZ_CONFIG R/W Autozero configuration 0x7F 0xD7 CALIB R/W Calibration start 0x00 0xD9 CALIBCFG R/W Calibration configuration 0x50 0xDC CALIBSTAT R/W Calibration status 0x00 0xDD INTENAB R/W Interrupt enables 0x00 Address Register Name R/W Register Function Reset Value
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description Detailed Register Description Enable Register (Address 0x80) Figure 20: Enable Register Before activating AEN or PEN, preset each applicable operating mode registers and bits. Addr: 0x80 Enable Bit Bit Name Default Access Bit Description 7:4 RESERVED 0000 RW Reserved. 3 WEN 0 RW This bit activates the wait feature. Active high. 2 PEN 0 RW This bit activates the proximity detection. Active high. 1A E N 0 R W This bit actives the ALS function. Active high. *Set AEN=1 and PON=1 in the same command to ensure auto-zero function is run prior to the first measurement. 0P O N 0 R W This field activates the internal oscillator and ADC channels. Active high.
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description PIHT Register (Address 0x8A) Figure 29: PIHT Register The proximity channel is compared against high-going 8-bit threshold value set by PIHT. If the value generated by the proximity channel is above the PIHT threshold and the PPERS value is reached, the PINT bit is asserted. If PIEN is set, then the INT pin will also assert. PERS Register (Address 0x8C) Figure 30: PERS Register Addr: 0x8A PIHT Bit Bit Name Default Access Bit Description 7:0 PIHT 0x00 RW This register sets the proximity ADC channel high threshold. Addr: 0x8C PERS Bit Bit Name Default Access Bit Description 7:4 PPERS 0000 RW This register sets the proximity persistence filter. Value Interrupt
0 Every proximity cycle
1 Any value outside PILT/PIHT thresholds
2 2 consecutive proximity values out of range 3 3 consecutive proximity values out of range …… . 15 15 consecutive proximity values out of range
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description The frequency of consecutive proximity channel results outside of threshold limits are counted; this count value is compared against the PPEARS value. If the counter is equal to the PPERS value an interrupt is asserted . Any time a pr oximity channel result is inside the threshold values the counter is cleared. The frequency of consecutive clear channel results outside of threshold limits are counted; this count value is compared against the APEARS value. If the counter is equal to the APERS setting an interrupt is asserted. Any time a clear channel result is inside the threshold values the counter is cleared. 3:0 APERS 0000 RW This register sets the ALS persistence filter. 0E v e r y A L S c y c l e
1 Any value outside ALS thresholds
2 2 consecutive ALS values out of range 3 3 consecutive ALS values out of range 4 5 consecutive ALS values out of range 5 10 consecutive ALS values out of range 6 15 consecutive ALS values out of range 7 20 consecutive ALS values out of range 13 50 consecutive ALS values out of range 14 55 consecutive ALS values out of range 15 60 consecutive ALS values out of range Addr: 0x8C PERS Bit Bit Name Default Access Bit Description
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description CFG0 Register (Address 0x8D) Figure 31: CFG0 Register The wait timer is implemented using a down counter. Wait time = (value +1) x 2.8ms. If WLONG is enabled then Wait time = (value +1) x 2.8ms x 12. Addr: 0x8D CFG0 Bit Bit Name Default Access Bit Description 7:3 Reserved 10000 RW This field must be set to the default value. 2W L O N G 0 R W When Wait Long is asserted the wait period as set by WTIME is increased by a factor of 12. 1:0 Reserved 00 RW This field must be set to the default value.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description PCFG0 Register (Address 0x8E) Figure 32: PCFG0 Register The PPULSE_LEN field sets the width of all IR LED pulses within the proximity cycle. Longer pulses result in increased proximity range and typically result in less electrical noise generated in the analog front end. However, a setting of 8μs is recommended because less cumulative noise is generated during a proximity cycle. The PPULSE field sets the maximum number of IR LED pulses that may occur in a proximity cycle. The proximity engine will automatically continue to add IR LED pulses, up to the value set in PPULSE or if a near-s aturation condition occurs. The dynamic range of the sensor is automatically adjusted to detect distant targets as well as prevent saturation from close targets. This operation also reduces power consumption because proximity integration period is automatically shortened when a target is either to close or far from the sensor. Addr: 0x8E PCFG0 Bit Bit Name Default Access Bit Description 7:6 PPULSE_LEN 01 RW Proximity pulse length Value Pulse Length 04 μ s 18 μ s 21 6 μ s 33 2 μ s 5:0 PPULSE 001111 RW Maximum number of pulses in a single proximity cycle. Value Maximum Number of Pulses 63 64
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description PCFG1 Register (Address 0x8F) Figure 33: PCFG1 Register Addr: 0x8F PCFG1 Bit Bit Name Default Access Bit Description 7:6 PGAIN 10 RW This field sets the gain of the proximity IR sensor. Value Gain 01 x 12 x 24 x 38 x
5 Reserved 0 RW Reserved
4:0 PLDRIVE 0000 RW This field sets the drive strength of the IR LED current. Values are approximate; actual current through LED is factory trimmed to normalize IR intensity. Value LED Current 06 m A 11 2 m A i LED = 6(PLDRIVE +1) mA 30 186mA 31 192mA
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description CFG1 Register (Address 0x90) Figure 34: CFG1 Register REVID Register (Address 0x91) Figure 35: REVID Register Addr: 0x90 CFG1 Bit Bit Name Default Access Bit Description 7:4 Reserved 0000 RW Reserved
3 IR_TO_GREEN 0 RW
If set high, the IR (Proximity) photodiode is switched into the Green channel’s data converter. GDATAL/H register will report IR content. Green photodiode is not connected.
2 Reserved 0 RW Reserved
1:0 AGAIN 00 RW This field sets the gain of the ALS/Color sensor. Value LED Current 01 x 14 x 21 6 x 36 4 x Addr: 0x91 REVID Bit Bit Name Default Access Bit Description 7:3 Reserved 00000 RO Reserved 2:0 REV_ID Rev RO Device revision number
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description ID Register (Address 0x92) Figure 36: ID Register Status Register (Address 0x93) Figure 37: Status Register All flags in this register can be cleared by setting the bit high. Alternatively, if the CFG3.int_read_clear bit is set, then simply reading this register automatically clears all eight flags. Addr: 0x92 ID Bit Bit Name Default Access Bit Description 7:2 ID 111001 RO Device type identification. 1:0 Reserved 00 RO Reserved Addr: 0x93 Status Register Bit Bit Name Default Access Bit Description
7 ASAT 0 R, SC The Analog Saturation flag signals that the ALS/Color
results may be unreliable due to saturation of the AFE.
6 PSAT 0 R, SC
The Proximity Saturation flag indicates that an ambient- or reflective-saturation event occurred during a previous proximity cycle. 5P I N T 0 R , S C The Proximity Interrupt flag indicates that proximity results have exceeded thresholds and persistence settings. 4A I N T 0 R , S C The ALS Interrupt flag indicates that ALS/Color results (clear channel) have exceeded thresholds and persistence settings. 3C I N T 0 R , S C The Calibration Interrupt flag indicates that calibration has completed.
2 Reserved 0 R, SC Reserved
1 PSAT_REFLECTIVE 0 R, SC
The Reflective Proximity Saturation Interrupt flag signals that the AFE has saturated during the IR LED active portion of proximity integration.
0 PSAT_AMBIENT 0 R, SC
The Ambient Proximity Saturation Interrupt flag signals that the AFE has saturated during the IR LED inactive portion of proximity integration.
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description Figure 49: AGAIN Range AGAIN[1] AGAIN[0] AGAINMAX AGAINL Overall ALS Gain 00 0 0 ½ 00 0 1 1 01 0 1 4 10 0 1 1 6 11 0 1 6 4 11 1 1 1 2 8
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description CFG3 Register (Address 0xAB) Figure 50: CFG3 Register The SAI bit sets the device operational mode following the completion of an ALS or proximity cycle. If AINT and AIEN are both set or if PINT and PIEN ar e both set, causing an interrupt on the INT pin, and the SAI bit is set, then the oscillator will deactivate. The Device will appear as if PON = 0, however, PON will read as 1. The device can only be reactivated (oscillator enabled) by clearing the interrupts in the STATUS register. Addr: 0xAB CFG3 Bit Bit Name Default Access Bit Description
7 INT_READ_CLEAR 0 RW
If the Interrupt-Clear-by-Read bit is set, then all flag bits in the STATUS register will be reset whenever the STATUS register is read over I²C. 6:5 Reserved 00 RW Reserved. 4S A I 0 R W The Sleep After Interrupt bit is used to place the device into a low power mode upon an interrupt pin assertion. PON SAI INT Oscillator 0XX O F F 10X O N
111 O N
110 O F F
3:0 Reserved 1100 RW Reserved.
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description POFFSETL Register (Address 0xC0) Figure 51: POFFSETL Register Typically, optical and/or electrical crosstalk negatively influence proximity operation and results. The POFFSETL/POFFSETH registers provide a mechanism to remove system crosstalk from the proximity data. POFFSETL and POFFSETH contains the magnitud e and sign of a value which adjusts PDATA is generated in the AFE. An offset value in the range of ± 255 is possible. POFFSETH Register (Address 0xC1) Figure 52: POFFSETH Register Typically, optical and/or electrical crosstalk negatively influence proximity operation and results. The POFFSETL/POFFSETH registers provide a mechanism to remove system crosstalk from the proximity data. POFFSETL and POFFSETH contains the magnitud e and sign of a value which adjusts PDATA is generated in the AFE. An offset value in the range of ± 255 is possible. Addr: 0xC0 POFFSETL Bit Bit Name Default Access Bit Description 7:0 POFFSETL 0x00 RW This register contains the magnitude portion of proximity offset adjust value. Addr: 0xC1 POFFSETH Bit Bit Name Default Access Bit Description 7:1 Reserved 0000000 RW Reserved.
0 POFFSET_SIGN 0 RW This register contains the sign portion of
proximity offset adjust value.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description AZ_CONFIG Register (Address 0xD6) Figure 53: AZ_CONFIG Register Addr: 0xD6 AZ_CONFIG Bit Bit Name Default Access Description 7 Reserved 0 RW Reserved. 6:0 AZ_NTH_ITERATION 1111111 RW Run autozero automatically before every nth ALS cycle (00h = never, n = every nth ALS cycle, and 7Fh = only before the first ALS cycle).
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description CALIB Register (Address 0xD7) Figure 54: CALIB Register Proximity response in systems with electrical and optical crosstalk may be improved by using the calibration feature. Optical crosstalk is caused when the photodiode receives a small portion of the LED IR whic h was unintentionally reflected by a surface other than the target. Electrical offset is caused by electrical disturbance in the sensor AFE, and also influences the proximity result. The calibration routine adjusts the value in registers C0 and C1 until the proximity result is as close to BINSRCH_TARGET as possible without becoming zero. Optical and electrical calibration function identically, except that during an electrical cali bration the proximity photodiode is disconnected from the AFE. An electrical only calibration can be initiated by setting the ELECTRICAL_CALIBRATION an d START_OFFSET_CALB bits. To perform an optical (and electr ical) calibration do not set the ELECTRICAL_CALIBRATION bi t when setting the START_ OFFSET_CALIB. The CINT flag will assert after calibration has finished. Upon completion proximity offset registers are automatically loaded with calibration result. Addr: 0xD7 CALIB Bit Bit Name Default Access Bit Description 7:6 Reserved 00 RO Reserved.
5 ELECTRICAL_
Selects proximity calibration type. 1=Electrical offset only. 0= Calibration compensates for electrical and optical crosstalk. 4:1 Reserved 0000 RW Reserved.
0 START_OFFSET_
CALIB 0 RW Set to 1 to start a calibration sequence.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Register Description CALIBCFG Register (Address 0xD9) Figure 55: CALIBCFG Register The binary search target field is used by the calibration feature to set the baseline value for PDATA when no target is present. For example, calibration of a device in open air, with no target, Addr: 0xD9 CALIBCFG Bit Bit Name Default Access Bit Description 7:5 BINSRCH_ TARGET 010 RW Proximity Result Target. Value PDATA Target 41 5 53 1 66 3 71 2 7 4 Reserved 0 RW Reserved.
3 AUTO_
OFFSET_ADJ 0R W The Proximity Auto Offset Adjust bit causes the value in POFFSETL register to decrement when PDATA equals zero at the completion of the proximity cycle. 2:0 PROX_AVG 000 RW The Proximity Averaging field defines the number of ADC samples collected and averaged during a cycle which become the proximity result. Value Sample Size 0D i s a b l e 41 6 53 2 66 4 71 2 8
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Register Description and BINSEARCH_TARGET setting of 4 causes the PDATA value will be approximately 15 counts. This feature is useful because it forces PDATA result to always be above zero. The PROX_AVG field sets the number of ADC samples that are averaged to calculate the PDATA result. CALIBSTAT Register (Address 0xDC) Figure 56: CALIBSTA T Register INTENAB Register (Address 0xDD) Figure 57: INTENAB Register Addr: 0xDC CALIBSTAT Bit Bit Name Default Access Bit Description 7:1 Reserved 0000000 RW Reserved.
0 CALIB_FINISHED 0 RW
This flag indicates that calibration has finished. It can only be cleared by setting this bit high.Addr: 0xDD INTENAB Bit Bit Name Default Access Bit Description 7 ASIEN 0 RW ALS Saturation Interrupt Enable. 6 PSIEN 0 RW Proximity Saturation Interrupt Enable. PIEN 0 RW Proximity Interrupt Enable. 4 AIEN 0 RW ALS/Color Interrupt Enable. 3 CIEN 0 RW Calibration Interrupt Enable. 2:0 Reserved 000 RW Reserved.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Application Information Schematic Figure 58: Typical Applications Circuit Typical Applications Circuit: It is important to place the 4.7μF (VDD) and 10μF (LEDA) capacitors at the package pins. Note(s): 1. Place the 4.7μF and 10μF LEDA capacitors within 5mm of the module. 2. The value of the I²C pull up resistors RPU should be based on the 1.8V bus voltage, system bus speed and trace capacitance. 3. The bulk capacitor can affect the stability of a regulated supply output and should be chos en with the regulator characteri stics in mind. 4. VSS and PGND should be connected to the same so lid ground plane as close to the device as possible.
Application Information
1.8V 3.0V RPU 10μF 4.7μF VBUS INT SCL SDA Bulk System Capacitance R = 22Ω TMD37253S LEDA VSS VDD PGND INT SCL SDA LEDK/LDR RINT = 10KΩ
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Application Information PCB Layout Figure 59: PCB Layout The dominant factor governing device performance is the component placement, not necessarily component value. The placement of the decoupling capacitor, C1, is the most critical. Place the component on the same side of PCB as device as shown in the figure above. Make connection as close as possible to minimize series inductance an d resistance. This is critical.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Package Drawings & Markings Figure 60: Package Drawings Note(s): 1. All linear dimensions are in millimeters. 2. Contact finish is Au. 3. This package contains no lead (Pb). 4. This drawing is subject to change without notice. Package Drawings & Markings 3$57&/ 72352;&/ 3,1,1',&$725 /('$3(5785( /('&/ 72352;&/ 3$57&/ 72$/6&/ 5&/ 0 & $% 0 & $% GreenRoHS
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Package Drawings & Markings Figure 61: Recommended PCB Pad Layout Note(s): 1. All dimensions are in millimeters. 2. Dimension tolerances are 0.05mm unless otherwise noted. 3. This drawing is subject to change without notice.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Tape & Reel Information Figure 62: Tape and Reel Information Note(s): 1. All linear dimensions are in millimeters. 2. For missing tolerances and dimensions, refer to EIA-481. 3. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. Tape & Reel Information /g36/g16/g36 /g3/g46/g19/g32/g20/g17/g21/g3 /g3/g20/g19/g131/g80/g68/g91/g17/g3 /g147/g19/g17/g19/g24/g3/g3/g36/g19/g32/g21/g17/g21/g24/g3/g147/g19/g17/g19/g24/g3 /g11/g21/g29/g20/g12 /g3/g21/g3/g147/g19/g17/g19/g24/g3 /g3/g20/g21/g3 /g3/g23/g91/g20/g19/g32/g23/g19/g3 /g3/g23/g3 /g147/g19/g17/g21 /g20/g17/g24/g3/g19 /g147/g19/g17/g20/g3 /g19/g17/g20 /g3/g19/g17/g20 /g3 /g19/g17/g22 /g3 /g14 /g147/g19/g17/g19/g24/g3/g24/g17/g24/g3 /g16 /g3 /g147/g19/g17/g20/g3/g20/g17/g26/g24/g3 /g14 /g3 /g3/g147/g19/g17/g20/g3/g23/g3 /g3 /g3 /g3/g20/g17/g20/g3/g147/g19/g17/g20/g3 /g36 /g36 /g37 /g37 /g74 /g88/g81/g90/g76/g81/g71/g76/g81/g74/g3/g71/g76/g85/g72/g70/g87/g76/g82/g81/g3/g72/g80/g83/g87/g92 /g37/g16/g37 /g3 /g3/g147/g19/g17/g19/g24/g3/g19/g17/g21/g27/g3 /g3/g37/g19/g32/g22/g17/g28/g3/g147/g19/g17/g19/g24 /g3/g20/g19/g131/g80/g68/g91/g17/g3 Cover Tape: Surface Resistance (Top Side) - 10^10 Ohms Surface Resistance (Adhesive Side) - 10^8 Ohms Carrier Tape: Surface Resistance - 10^4 - 10^10 Ohms
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Soldering & Storage Information The module has been tested an d has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 63: Solder Reflow Profile Note(s): 1. Tolerance for peak profile temperature (TP) is defined as a supplier mi nimum and a user maximum. Profile Feature Preheat/ Soak Sn-Pb Eutectic Assembly Pb-Free Assembly Temperature Min ( Tsmin) 100 °C 150 °C Temperature Max ( Tsmax) 150 °C 200 °C Time (ts) from (Tsmin to Tsmax) 60-120 seconds 60-120 seconds Ramp-up rate (TL to TP) 3 °C/second max. 3 °C/second max. Liquidous temperature (TL) Time (tL) maintained above TL 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body temperature (TP) For users TP must not exceed the Classification temp of 235 °C For suppliers TP must equal or exceed the Classification temp of 235 °C For users TP must not exceed the Classification temp of 260 °C For suppliers TP must equal or exceed the Classification temp of 260 °C Time (tP) (1) within 5 °C of the specified classification temperature (Tc) 20 (1)seconds 30 (1)seconds Ramp-down rate (TP to TL) 6 °C/second max. 6 °C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Soldering & Storage Information
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Soldering & Storage Information Figure 64: Solder Reflow Profile Graph Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed mois ture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with sili ca gel to protect them from ambient moisture during shipping, handling, and storage before use. Not to Scale – For Reference Only TP Temperature (°C) Time (seconds) tL TL TC - 5°C tP Tsmin Tsmax Preheat Area Max Ramp Up Rate = 3°C/s Max Ramp Down Rate = 6°C/s
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Soldering & Storage Information Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 12 months
- Ambient Temperature: <40°C
- Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: <30°C
- Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Ordering & Contact Information Figure 65:
Ordering Information
Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code I2C Bus I2C Address Delivery Form Delivery Quantity TMD37253 1.8V 39h Tape & Reel (13”) 10000 pcs/reel Ordering & Contact Information
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Copyrights & Disclaimer Copyright ams AG, Tobelbader St rasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-03 (2017-Oct-26) to current revision 1-05 (2018-Mar-08) Page 1-03 (2017-Oct-26) to 1-04 (2018-Feb-23) Updated ATIME Register (Address 0x81) 20 Updated WTIME Register (Address 0x83) 21 Updated CALIB Register (Address 0xD7) 38 1-04 (2018-Feb-23) to 1-05 (2018-Mar-08) Updated Figure 65 49 Revision Information
Document Feedback [v1-05] 2018-Mar-08 TMD3725 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignment
4A b s o l u t e M a x i m u m R a t i n g s
6 Electrical Characteristics
7 Typical Operating Characteristics
12 Detailed Description
12 Proximity
12 Color and Ambient Light Sense
12 I²C Characteristics
13 I²C Write Transaction
13 I²C Read Transaction
13 Timing Diagrams
14 Principles of Operation
14 System State Machine
17 Register Description
17 Register Overview
19 Detailed Register Description
19 Enable Register (Address 0x80)
20 ATIME Register (Address 0x81)
20 PTIME Register (Address 0x82)
21 WTIME Register (Address 0x83)
21 AILTL Register (Address 0x84)
22 AILTH Register (Address 0x85)
22 AIHTL Register (Address 0x86)
23 AIHTH Register (Address 0x87)
23 PILT Register (Address 0x88)
24 PIHT Register (Address 0x8A)
24 PERS Register (Address 0x8C)
26 CFG0 Register (Address 0x8D)
27 PCFG0 Register (Address 0x8E)
28 PCFG1 Register (Address 0x8F)
29 CFG1 Register (Address 0x90)
29 REVID Register (Address 0x91)
30 ID Register (Address 0x92)
30 Status Register (Address 0x93)
31 CDATAL Register (Address 0x94)
31 CDATAH Register (Address 0x95)
31 RDATAL Register (Address 0x96)
31 RDATAH Register (Address 0x97)
32 GDATAL Register (Address 0x98)
32 GDATAH Register (Address 0x99)
32 BDATAL Register (Address 0x9A)
32 BDATAH Register (Address 0x9B)
33 PDATA Register (Address 0x9C)
33 REVID2 Register (Address 0x9E)
33 CFG2 Register (Address 0x9F)
35 CFG3 Register (Address 0xAB)
[v1-05] 2018-Mar-08 Document Feedback TMD3725 − Content Guide