TMD3719

TMD3719 AMSCO | Alldatasheet

Document overview

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Technical content

Datasheet, Public Page 1 [v2-00] 2023-Jan-12 Document Feedback TMD3719 ALS/Color and Proximity Sensor The TMD3719 features ambient light and color (RGB) sensing, flicker detection and proximity detection. The device integrates three IR VCSELs and an adva nced VCSEL driver within a low-profile 6.35mm x 3.00mm x 1.00mm package. The ambient light and color sensing function provides six concurrent ambient light sensing channels: Red, Green, Blue, Clear, Leakage and Wideband. The RGBL and Clear channels have a UV/IR blocking filter. This architecture accurately measures ambient light and enables the calculation of illuminance, chromaticity, and color temperature to manage display appearance. The device integrates direct detection of ambient light flicker for 4 selectable frequency bins. Flicker detection is executed in parallel with ambient light and color sensing. The flicker detection engine can also buffer data for calculating other flicker frequencies externally. The proximity function synchroniz es IR emission and detection to sense nearby objects. The architecture of the engine features self-maximizing dynamic range, ambient light subtraction, advanced crosstalk cancelation, and interrupt-driven I²C communication. Sensitivity, powe r consumption, and noise can be optimized with adjustable IR VCSEL timing and power. The proximity engine recognizes detect/release events and produces a configurable interrupt whenever the proximity result crosses upper or lower threshold settings. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TMD3719 are listed below: Figure 1: Added Value of Using TMD3719 Benefits Features

• Improved Lux Accuracy for ALS Behind OLED • High Sensitivity
• Leakage Channel
• Minimized Display Distortion for Proximity Behind OLED
• Proximity Function Synchronized with Display
• Multiple VCSEL Emitters to Lower the Optical Powe r Densit y General Description

Page 2 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − General Description

Applications

TMD3719 integrates multiple ap plications within one device. The applications fo r TMD3719 include:

• Brightness management for displays
• Color management for displays
• Camera image processing
• Flicker-immune camera operation
• Touch screen disable Block Diagram The functional blocks of this device are shown below: Figure 2: Functional Blocks of TMD3719 Digital Core INPUT TMD3719 I2C OSCILLATOR GPIO GND PGND VDD SDA SCL Proximity Engines

2 Prox

++ Limit - Limit Mux PWM Registers Interrupt Flags GPIO2 VSYNC

8 ADCs

C VDD3 Eye Safety Circuit High Side Switch ALS/Flicker Engine Color (CRGBL) Wideband (W)

Datasheet, Public Page 3 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Pin Assignments Device pinout is described below. Figure 3: Pin Diagram of TMD3719 Figure 4: Pin Description of TMD3719 Pin Number Pin Name Description

1 SDA I²C serial data I/O terminal

2 SCL I²C serial clock terminal

3 INT Interrupt. Open-drain output plus supports additional output options. 4G N D Ground. All voltages are referenced to GND/PGND, and both ground pins must be connected to ground. 5P G N D Ground. All voltages are referenced to GND/PGND, and both ground pins must be connected to ground. 6 VDD3 Supply voltage (3.3V) 7 VDD Supply voltage (1.8V)

8 GPIO2 General purpose input

9V S Y N C V S Y N C i n p u t

10 GPIO Open-drain general purpose input/output

*3,2 96<1&;5(69''9'' - VDD3 - GPIO2 - VDD

Page 4 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Ex posure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages with respect to GND/PGND. Device parameters are guaranteed at V DD = 1.8 V and TA = 25°C unless otherwise noted. Figure 5: Absolute Maximum Ratings Note(s): 1. This ensures the maximum optical power is <12mW at 940nm ±10nm. 2. While the device is operational across the temperat ure range, functionality will vary with temperature. Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply Voltage to GND -0.3 1.98 VVDD3 Emitter Supply Voltage to GND -0.3 3.6 VIO Digital I/O Terminal Voltage -0.3 3.6 IIO Digital Output Terminal Current -1 20 mA ISINK VCSEL Current (1) 01 0 The VCSEL current setting should not exceed 10mA for any of the VCSELs to maintain Class 1 laser safety. Electrostatic Discharge ISCR Input Current (latch-up immunity) ± 100 mA Class II JEDEC JESD78D ESD HBM HBM Electrostatic Discharge ±2000 V JEDEC/ESDA JS-001-2017 ESDCDM CDM Electrostatic Discharge ± 500 V JEDEC JESD22-C101F Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range -40 85 TA Operating Temperature Range (2) -30 85 Absolute Maximum Ratings

Datasheet, Public Page 5 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Absolute Maximum Ratings Figure 6: Recommended Operating Conditions Symbol Parameter Min Typ Max Units VDD Supply Voltage 1.7 1.8 1.98 V VDD3 Emitter Supply Voltage 2.9 3.3 3.6 V ISINK VCSEL Current 10 10 10 mA

Page 6 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 7: Note(s): 1. Values are shown at the VDD pin and do not include current through the VDD3 pin. 2. This parameter indicates the supply curr ent during periods of ALS integration. The ALS gain setting will have an effect on t he active supply current. The ALS gain setting for this parameter is 2x. 3. Idle state occurs when PON=1 and all functions are not enabled. 4. Sleep state occurs when PON = 0 and I²C bus is idle. If Slee p state has been entered as the result of operational flow, SAI = 1, PON will remain high. 5. Not production tested. Specifie d by design and characterization. Symbol Parameter Conditions Min Typ Max Unit IDD Supply current (1) Active ALS State (2) (PON=AEN=1, WEN=PEN=0) 380 460 μA Active Proximity State (PON=PEN=1, AEN=0) 600 700 Idle State (3) (PON=1, AEN=PEN=0) 125 150 Sleep State (4) (PON = 0) 0.7 5.0 VOL INT, SDA, GPIO output low voltage 3mA sink current 0.36 V ILEAK Leakage current, SDA, SCL, INT -5 5 μA VIH SCL, SDA, VSYNC input high voltage 1.26 V VIL SCL, SDA, VSYNC input low voltage 0.54 V TWAKEUP Time from sleep state exit to proximity engine ready(5) 0.5 ms TACTIVE Time from power-on to ready for receiving I²C commands(5) 1.5 ms

Electrical Characteristics

Datasheet, Public Page 7 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Optical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Device parameters are guaranteed with V DD = 1.8V, V DD3 = 3.3V and T A = 25°C unless otherwise noted. Figure 8: ALS/Color Characteristics of TMD3719, ALS Gain = 512x, Integration Time = 10.8ms (unless otherwise noted) Parameter Conditions Min Typ Max Unit Dark ADC count value(1) Ee = 0μW/cm2 ALS gain: 4096x Integration time: 22ms 0 0 3 counts ALS gain ratios 2x 0.0032 0.0041 0.0049 4x 0.0068 0.0083 0.0095 8x 0.0138 0.0164 0.0176 16x 0.0270 0.0317 0.0345 32x 0.050 0.061 0.067 64x 0.105 0.124 0.134 128x 0.217 0.249 0.267 256x 0.454 0.498 0.526 1024x 1.85 2.02 2.50 2048x 3.2 4.1 10.0 4096x 5.0 9.0 18.0 Clear channel irradiance responsivity (1) White LED, 3000K(2) 559 657 756 counts/ μW/cm2 Wideband channel irradiance responsivity(1) 332 Lux accuracy(3) White LED, 3000K Integration time: 100ms 85 100 115 % ADC noise(4) White LED, 3000K ALS gain: 1024x Integration time: 355ms 0.025 % Optical Characteristics

Page 8 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Optical Characteristics Note(s): 1. ALS output values (ADATAX) are divided by 4 to account for the output having 2 sub-LSBs. 2. The White LED is an InGaN light-emitting diode with integr ated phosphor that has a correlated color temperature = 3000K. 3. Lux accuracy is an illuminance estimated using the red, green , blue, and clear channels and is not 100% production tested. 4. ADC noise is calculated as the standard deviation of 1000 da ta samples divided by full scal e and is not 100% production. 5. The Blue LED is an InGaN light-emitting diode with the following characteristics: dominant wavelength λ D = 465nm, spectral halfwidth Δλ½ = 22nm. 6. The Red LED is an AlInGaP light-emitting diode with the following characteristics: dominant wavelength λ D = 615nm, spectral halfwidth Δλ½ = 15nm. 7. The Green LED is an InGaN light-emitting diode with the following characteristics: dominant wavelength λ D = 525nm, spectral halfwidth Δλ½ = 35nm. 8. The IR LED is an AlGaAs light-emitting diode wi th the following characteristics: peak wavelength λ P = 940nm, spectral halfwidth Δλ½ = 42nm. Red/Clear channel ratios White LED, 3000K 52 62 72 Blue LED, λD = 465nm(5) 17 1 3 Red LED, λD= 615nm(6) 80 97 113 Green/Clear channel ratios White LED, 3000K 21 31 41 Green LED, λD = 525nm(7) 63 76 88 Red LED, λD = 615nm 58 1 2 Blue/Clear channel ratios White LED, 3000K 7 18 30 Blue LED, λD = 465nm 74 88 103 Red LED, λD = 615nm 05 1 2 Leakage/Clear channel ratio White LED, 3000K 0 1 5 Wideband/Clear channel ratio White LED, 3000K 36 48 60 Wideband/IR channel ratio IR LED = 940nm(8) 71 3 1 8 Parameter Conditions Min Typ Max Unit

Datasheet, Public Page 9 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Optical Characteristics Figure 9: Proximity Characteristics of TMD3719 Parameter Conditions Min Typ Max Unit Near Response, Relative Variation(1), (4) PGAIN = 0 (1x) All 3 ISINKs set to 10mA(5) PPULSE_LEN = 4 (64μs) PPULSE = 2 (3pulses) d= 50mm round target 84mm target distance After electrical calibration 75 100 125 % Far Response, Relative Variation (1), (4) PGAIN = 0 (1x) All 3 ISINKs set to 10mA(5) PPULSE_LEN = 4 (64μs) PPULSE = 2 (3pulses) d= 50mm round target 84mm target distance After electrical calibration 80 100 120 % Near/Far Ratio Response, Relative Variation (1) PGAIN = 0 (1x) All 3 ISINKs set to 10mA(5) PPULSE_LEN = 4 (64μs) PPULSE = 2 (3pulses) d= 50mm round target 84mm target distance After electrical calibration 87.5 100 112.5 % Near Response, Absolute (2) PGAIN = 0 (1x) All 3 ISINKs set to 10mA (5) PPULSE_LEN = 3 (32μs) PPULSE = 0 (1pulse) POFFSET = 0 100mm x 100mm, 90% reflective Kodak gray card 100mm target distance 5338 7117 8897 counts Far Response, Absolute (2) PGAIN = 0 (1x) All 3 ISINKs set to 10mA(5) PPULSE_LEN = 3 (32μs) PPULSE = 0 (1pulse) POFFSET = 0 100mm x 100mm, 90% reflective Kodak gray card 100mm target distance 5419 6774 8129 counts

Page 10 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Optical Characteristics Note(s): 1. Production tested result is the average of 5 readings expressed relative to a calibrated response. 2. Representative result by characterizati on. This characterization result does not include the VCSEL output power drift over t he life of the product. 3. Production tested result is the range of 10 readings divided by the average response. 4. Production test does not include the VCSEL output power drift over the life of the product. The VCSEL output power drift wil l stay within ±1dB of the initial output power for standard device operation using all 3 VCSELs. 5. Use ISINK_RELEASE = ISINK_DETECT = 3 (2x), ISINK0 = 4 (5mA) an d ISINK1 =ISINK2 = 5 (5mA) to set all 3 VCSELs with 10mA drive current. Noise/Signal(3) PGAIN = 0 (1x) All 3 ISINKs set to 10mA(5) PPULSE_LEN = 2 (16μs) PPULSE = 7 (8pulses) POFFSET = 0 Parameter Conditions Min Typ Max Unit

Page 12 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Timing Characteristics Figure 12: Functional Timing Characteristics of TMD3719 Note(s): 1. 100% production tested. Symbol Parameter Min Typ Max Unit fOSC Oscillator clock frequency (1) 357 369 380 kHz tOSL Oscillator clock cycle (1) 2.63 2.71 2.80 μs t(PROX ADC) Proximity ADC conversion time 20 μs

Page 14 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Typical Operating Characteristics Figure 15: Illuminance (Lux) vs. Counts (Clear Channel) 0.00001 0.0001 0.001 0.01 0.1 100 1000 10000 1 10 100 1000 10000 100000 1000000 Illuminance (lux) Clear Channel (counts) Dynamic Range (ATIME = 100ms) 32x 512x 4096x

Datasheet, Public Page 15 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Detailed Description Upon power-up, POR, the device init ializes. During initialization (maximum of 1.5ms), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed, and all outputs from the device must be ignored including interrupts. After initialization, the device enters the SLEEP state. In this operational state the internal oscillator and other circ uitry are not active, resulting in ultra-low power consumption. If an I²C transaction occurs during this state, the I²C core wakes up temporarily to service the communication. Once the Powe r ON bit, PON, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. Whenever a function is enabled (PEN | AEN = 1) the device exits the IDLE state. If all functions are disabled (PEN = 0 & AEN = 0), the device returns to the IDLE state. As depicted in Figure 16 the proximity and CRGBLW color sensing functions operate in parallel when enabled (PEN | AEN = 1). In addition, when proximity calibration is requested, it will temporarily disable the proximity function. Each function is individually configured (e.g. gain, ADC integration time, wait time, persistence, thresholds, etc.). If Sleep after Interrupt is enabled (SAI = 1 in register 0x96), the state machine will enter SLEEP when an interrupt occurs. Entering SLEEP does not auto matically change any of the register settings (e.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP state is terminated when the SAI_ACTIVE bit is cleared (the status bit is in register 0xBE and the clear status bit is in register 0xF6). Detailed Description

Page 16 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Detailed Description State Machine Diagrams Figure 16: Simplified State Diagram PARALLEL FUNCTIONS PEN AEN IDLE ALS CRGB/L/W/IR PROX CALIBRATION PROXIMITY I2C SLEEP PON I2C

Datasheet, Public Page 17 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Detailed Description I²C Protocol The device uses I²C serial communication protocol for communication. The device support s 7-bit chip addressing and both standard and full-speed cl ock frequency modes. Read and Write transactions comply with th e standard set by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification. Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (I.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general it is recommended to use I²C bursts whenever possible, especially in this ca se when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors. A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP . Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP . A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP .

Page 18 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview The device is controlled and monitored by registers accessed through the I²C serial interface. These registers provide device control functions and are read to determine device status and acquire device data. Register Map The register set is summarized in Figure 17 . The values of all registers and fields that are listed as reserved or are not listed must not be changed at any time. Bits 7 (MSB) through 0 (LSB) are shown in the last columns of the table. The power-on reset values of each bit are indicated in these columns. Two-byte fields are always latched with the low byte followed by the high byte. The functions column illustrates the purpose of each register by highlighting the function associated to each bit. The bits are shown from MSB (bit7) to LSB (bit0). GRA Y indicates fields apply independent of one function or apply to all functions, GREEN indicates fields that are pert inent to ALS/color sensing and flicker detection and BLUE indicates fields that are pertinent to proximity detection. WHITE fields are reserved and their values must not be changed at any time. Figure 17: Register Map Addr Name Type Description 7 6 5 4 3 2 1 0 Reset 0x2E AILT R/W ALS interrupt low threshold 00000000 00000000 00000000 0x00 0x2F 0x00 0x30 0x00 0x31 AIHT R/W ALS interrupt high threshold 00000000 00000000 00000000 0x00 0x32 0x00 0x33 0x00 0x34 PILT0 R/W Proximity interrupt low threshold zero 00000000 00000000 0x00 0x35 0x00 0x36 PIHT0 R/W Proximity interrupt high threshold zero 00000000 00000000 0x00 0x37 0x00 0x38 PILT1 R/W Proximity interrupt low threshold one 00000000 00000000 0x00 0x39 0x00 0x3A PIHT1 R/W Proximity interrupt high threshold one 00000000 00000000 0x00 0x3B 0x00 Register Overview

Datasheet, Public Page 19 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview 0x3C PILTR R/W Proximity interrupt low threshold ratio 00000000 00000000 0x00 0x3D 0x00 0x3E PIHTR R/W Proximity interrupt high threshold ratio 00000000 00000000 0x00 0x3F 0x00 0x40 FD_CFG0 R/W Flicker detection configuration zero 000 00 0 01 0x01 0x41 FD_CFG1 R/W Flicker detection configuration one 000 00000 0x00 0x42 FD_CFG2 R/W Flicker detection configuration two 000 00000 0x00 0x43 FD_CFG3 R/W Flicker detection configuration three 000 00000 0x00 0x44 FD_CFG4 R/W Flicker detection configuration four 000 00000 0x00 0x45 FD_CFG5 R/W Flicker detection configuration five 11111110 0xFE 0x47 FD_CFG7 R/W Flicker detection configuration seven 000000 01 0x01 0x48 FD_CFG8 R/W Flicker detection configuration eight 01100111 0x67 0x4F SYNC_DELAY R/W Synchronized delay 00000000 00000000 0x00 0x50 0x00 0x53 VSYNC_CFG0 R/W Vertical sync configuration zero 0001 00 00 0x10 0x54 VSYNC_CFG1 R/W Vertical sync configuration one 00 010000 0x10 0x56 VSYNC_CFG2 R/W Vertical sync configuration two 00000000 0x00 0x57 VSYNC_CFG3 R/W Vertical sync configuration three 00000000 0x00 0x69 CALIB R/W Calibration start 0000000 00 x 0 0 0x6A CALIBCFG0 R/W Calibration configuration zero 0 00 0 0 000 0x00 0x6B CALIBCFG1 R/W Calibration configuration one 0 0 0 0 1 100 0x0C 0x6C CALIBCFG2 R/W Calibration configuration two 000 00000 0x00 0x6D CALIBSTAT R/W Calibration status 00000 0 0 00 x 0 0 0x80 ENABLE R/W Enable device states 0 00 0 00 0 00 x 0 0 Addr Name Type Description 7 6 5 4 3 2 1 0 Reset

Page 20 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview 0x81 MEAS_MODE0 R/W Measurement mode zero 0 00 0 00 0 00 x 0 0 0x82 MEAS_MODE1 R/W Measurement mode one 0 00 0 0 000 0x00 0x83 TRIGGER_MODE R/W Trigger Mode 0 000 0 000 0x00 0x84 ATIME R/W ALS integration time 00000000 0x00 0x85 ASTEP R/W ALS integration step 11111111 00000011 0xFF 0x86 0x03 0x87 PTIME R/W Proximity time 00000000 0x00 0x88 WTIME R/W Wait time 00000000 0x00 0x89 MOD_GAIN_0_1 R/W Modulator zero and one gain 0000 0000 0x00 0x8A MOD_GAIN_2_3 R/W Modulator two and three gain 0000 0000 0x00 0x8B MOD_GAIN_4_5 R/W Modulator four and five gain 0000 0000 0x00 0x8C MOD_GAIN_6_7 R/W Modulator six and seven gain 0000 0000 0x00 0x8D AGC_ENABLE R/W AGC enable 0 0 0 0 0 0 0 00 x 0 0 0x90 AUXID R Auxiliary identification 00000011 0x03 0x91 REVID R Revision identification 00010011 0x13 0x92 ID R Device identification 01000000 0x40 0x93 CFG0 R/W Configuration zero 0 01 0 0 000 0x20 0x96 CFG3 R/W Configuration three 00 0 01 1 1 1 0 x 0 F 0x97 CFG4 R/W Configuration four 0000 0000 0x00 0x9A PERS R/W Persistence configuration 0001 0001 0x11 0x9B CFG8 R/W Configuration eight 10 000000 0x80 0x9C CFG9 R/W Configuration nine 0 0 000000 0x00 0x9D CFG10 R/W Configuration ten 11 11 0010 0xF2 0x9E CFG11 R/W Configuration eleven 0 1 000000 0x40 0x9F CFG12 R/W Configuration twelve 00000 000 0x00 0xA4 AZ_CONFIG R/W Autozero configuration 11111111 0xFF 0xA7 CFG20 R/W Configuration twenty 000 00 0 0 0 0 x 0 0 0xAA PCFG1 R/W Proximity configuration one 00 0 0 0 000 0x00 0xAB PCFG2 R/W Proximity configuration two 00 00 0000 0x00 0xAC PCFG3 R/W Proximity configuration three 0000 0000 0x00 Addr Name Type Description 7 6 5 4 3 2 1 0 Reset

Datasheet, Public Page 21 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview 0xAD PCFG4 R/W Proximity configuration four 0000 10 10 0x0A 0xAE PCFG5 R/W Proximity configuration five 00001111 0x0F 0xAF PCFG6 R/W Proximity configuration six 00 0 0 0 0 0 00 x 0 0 0xB0 PCFG7 R/W Proximity configuration seven 000 00 001 0x01 0xB1 POFFSET0 R/W Proximity offset zero 00000000 00000000 0x00 0xB2 0x00 0xB3 PXAVG R/W Proximity average 00000000 00000000 0x00 0xB4 0x00 0xB5 PBSLN R/W Proximity baseline 00000000 00000000 0x00 0xB6 0x00 0xB7 STATUS R/W Device status one 0 0 0 0 0 0 0 00 x 0 0 0xB8 STATUS2 R/W Device status two 0 0 0 0 0 0 0 00 x 0 0 0xB9 STATUS3 R/W Device status three 0 0 0 0 0 0 0 00 x 0 0 0xBA STATUS4 R/W Device status four 00 0 0 0 0 0 00 x 0 0 0xBB STATUS5 R/W Device status five 0000 00 0 00 x 0 0 0xBD STATUS7 R/W Device status seven 0 00 0 0 0 0 00 x 0 0 0xBE STATUS8 R/W Device status eight 00 00 00 0 00 x 0 0 0xBF STATUS9 R Device status nine 0000 00 0 0 0 x 0 0 0xC0 ASTATUS RA L S s t a t u s 0000000 00 x 0 0 0xC1 ADATA0 R ALS channel zero data 00000000 00000000 00000000 0x00 0xC2 0x00 0xC3 0x00 0xC4 ADATA1 R ALS channel one data 00000000 00000000 00000000 0x00 0xC5 0x00 0xC6 0x00 0xC7 ADATA2 R ALS channel two data 00000000 00000000 00000000 0x00 0xC8 0x00 0xC9 0x00 Addr Name Type Description 7 6 5 4 3 2 1 0 Reset

Page 22 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview 0xCA ADATA3 R ALS channel three data 00000000 00000000 00000000 0x00 0xCB 0x00 0xCC 0x00 0xCD ADATA4 R ALS channel four data 00000000 00000000 00000000 0x00 0xCE 0x00 0xCF 0x00 0xD0 ADATA5 R ALS channel five data 00000000 00000000 00000000 0x00 0xD1 0x00 0xD2 0x00 0xD3 ADATA6 R ALS channel six data 00000000 00000000 00000000 0x00 0xD4 0x00 0xD5 0x00 0xD6 ADATA7 R ALS channel seven data 00000000 00000000 00000000 0x00 0xD7 0x00 0xD8 0x00 0xD9 PSTATUS R Proximity status 0 0 000000 0x00 0xDA PDATA0 R Proximity channel zero data 00000000 00000000 0x00 0xDB 0x00 0xDC PDATA1 R Proximity channel one data 00000000 00000000 0x00 0xDD 0x00 0xDE PDATAR R Proximity channel ratio data 00000000 00000000 0x00 0xDF 0x00 0xF2 GPIO R/W GPIO configuration 00 0 0 0 0 1 00 x 0 2 0xF4 AGC_GAIN_MAX R/W Maximum AGC gain 00000 110 0x06 0xF5 INTENAB R/W Enable interrupts 0 0 0 0 0 0 0 00 x 0 0 0xF6 CONTROL R/W Control 00000 0 0 00 x 0 0 0xF7 POFFSET1 R/W Proximity offset one 00000000 00000000 0x00 0xF8 0x00 0xF9 FIFO_MAP R/W FIFO buffer map configuration 0 0 0 0 0 0 0 00 x 0 0 Addr Name Type Description 7 6 5 4 3 2 1 0 Reset

Datasheet, Public Page 23 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Detailed Register Descriptions ALS Interrupt Thresholds ALS level detection uses data ge nerated by the ADC Channel X. The channel can be selected via ALS_TH_CHANNEL (see CFG12 ). The ALS Interrupt Threshold registers provide 24-bit values to be used as the high and low thresholds for comparison to the 24-bit ADATAX values. If AIEN is enabled and ADATAX is not between AILT and AIHT for the number of consecutive samples specified in APERS an interrupt is asserted on the interrupt pin. These registers are read/write. Figure 18: ALS Interrupt Thresholds Note(s): 1. Return to the Register Map ( 0x2E , 0x2F , 0x30 , 0x31 , 0x32 , 0x33 ) 0xFA FIFO_MAP2 R/W FIFO buffer map configuration two 000 0 0 0 0 00 x 0 0 0xFB FIFO_STATUS R FIFO buffer status 0 0000000 0x00 0xFC FDATA R FIFO buffer data 00000000 00000000 00000000 00000000 0x00 0xFD 0x00 0xFE 0x00 0xFF 0x00 Bits Addr Field Reset Type Description 7:0 0x2E AILT 0x00 R/W ALS Interrupt Low Threshold15:8 0x2F 0x00 R/W 23:16 0x30 0x00 R/W 7:0 0x31 AIHT 0x00 R/W ALS Interrupt High Threshold15:8 0x32 0x00 R/W 23:16 0x33 0x00 R/W Addr Name Type Description 7 6 5 4 3 2 1 0 Reset

Page 24 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Proximity Interrupt Thresholds The Proximity Interrupt Threshol d Registers set the high and low trigger points for the comp arison function which generates an interrupt. Interrupt generation is subject to the value set in persistence filter (PPERS). These registers are read/write. Figure 19: Proximity Interrupt Thresholds Note(s): 1. Return to the Register Map ( 0x34 , 0x35 , 0x36 , 0x37 , 0x38 , 0x39 , 0x3A , 0x3B , 0x3C , 0x3D , 0x3E , 0x3F ) Bits Addr Field Reset Type Description 7:0 0x34 PILT0 0x00 R/W Proximity Interrupt Low Threshold Zero 15:8 0x35 0x00 R/W 7:0 0x36 PIHT0 0x00 R/W Proximity Interrupt High Threshold Zero 15:8 0x37 0x00 R/W 7:0 0x38 PILT1 0x00 R/W Proximity Interrupt Low Threshold One 15:8 0x39 0x00 R/W 7:0 0x3A PIHT1 0x00 R/W Proximity Interrupt High Threshold One 15:8 0x3B 0x00 R/W 7:0 0x3C PILTR 0x00 R/W Proximity Interrupt Low Threshold Ratio 15:8 0x3D 0x00 R/W 7:0 0x3E PIHTR 0x00 R/W Proximity Interrupt High Threshold Ratio 15:8 0x3F 0x00 R/W

Datasheet, Public Page 25 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 20: FD_CFG0 Note(s): 1. Return to the Register Map ( 0x40 ) 2. If FD_MODE = 1 then number of sa mples changes from 1024 to unlimited. Figure 21: FD_CFG1 Note(s): 1. Return to the Register Map ( 0x41 ) Addr: 0x40 FD_CFG0 Bit Field Reset Type Bit Description 7:5 Reserved 000 4:3 FD_SAMPLES 00 R/W Flicker Detection Number of Samples. VALUE SAMPLES 0 (default) 128 12 5 6 25 1 2 3 1024(2) 2R e s e r v e d 0 1:0 FD_TIME 01 R/W Flicker Detection Time. VALUE TIME 05 0 m s 1 (default) 100ms 22 0 0 m s

3 User defined by FD_SAMPLE_TIME

and FD_SAMPLES Addr: 0x41 FD_CFG1 Bit Field Reset Type Bit Description 7:5 Reserved 000 4:0 FD_BIN0 00000 R/W Flicker Detection Bin Zero. Coefficient to use for Bin 0.

Page 28 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 28: SYNC_DELAY Note(s): 1. Return to the Register Map ( 0x4F , 0x50 ) Figure 29: VSYNC_CFG0 Note(s): 1. Return to the Register Map ( 0x53 ) Bits Addr Field Reset Type Description 7:0 0x4F SYNC_DELAY 0x00 R/W Synchronized Delay 14:8 0x50 [6:0] 0000000 R/W Addr: 0x53 VSYNC_CFG0 Bit Field Reset Type Bit Description 7:4 Reserved 0001 3 VSYNC_FREQ_LL_IGNORE 0 R/W VSYNC Frequency Low Limit Ignore. 2R e s e r v e d 0 1:0 OSC_CAL_MODE 00 R/W Oscillator Calibration Mode. VALUE MODE 0 (default) No oscillator calibration

1 Single oscillator calibration after

PON is set to 1.

2 Oscillator calibration is

performed whenever possible 3R e s e r v e d

Page 30 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 33: CALIB Note(s): 1. Return to the Register Map ( 0x69 ) Addr: 0x69 CALIB Bit Field Reset Type Bit Description 7:1 Reserved 0000000

0 START_OFFSET_CALIB 0 PUSH

Start Offset Calibration. Starts the proximity offset register calibration routine. Results are stored in the Proximity Offset Registers (0xC7 – 0xC8). The CALIB_FINISHED flag is asserted when calibration is complete and an interrupt (CINT) is asserted if CIEN is set. Calibration can be stopped immediately by writing a 0 to this field.

Datasheet, Public Page 31 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 34: CALIBCFG0 Note(s): 1. Return to the Register Map ( 0x6A ) Addr: 0x6A CALIBCFG0 Bit Field Reset Type Bit Description 7D C A V G _ A U T O _ B S L N 0 R / W DC Averaging Automatic Baseline. Load the DC average calculated during offset calibration into the PBSLN registers at the end of calibration. Note that if the offset is adjusted (by zero detection) during the DC averaging, the average may be incorrect.

6 DCAVG_AUTO_OFFSET_

DC Averaging Auto Offset Adjust. If set, then during DC averaging, whenever an ADC measurement is zero, the appropriate offset register will be decreased and the OFFSET_ADJUSTED flag is set. Note also that DC averaging is not automatically restarted when this happens, so the calculated baseline might be wrong. Software could restart averaging in this case. 5:4 Reserved 00

3 BINSRCH_SKIP 0 R/W

Binary Search Skip. When asserted the calibration routine will skip the binary search step. It is useful if zeros are detected during the DC averaging process to manually reset the baseline and reduce the likelihood of zero counts. 2:0 DCAVG_ITERATIONS 000 R/W DC Averaging Iterations. Sets the number of proximity results during calibration that are averaged after the binary search is complete. During this period, whenever a result is zero, the appropriate offset register is automatically decremented. VALUE ITERATIONS 0S k i p ∙∙∙ 2 DCAVG_ITERATIONS 66 4 71 2 8

Page 32 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 35: CALIBCFG1 Note(s): 1. Return to the Register Map ( 0x6B ) Addr: 0x6B CALIBCFG1 Bit Field Reset Type Bit Description 7R e s e r v e d 0

6 PROX_AUTO_OFFSET_

Proximity Auto Offset Adjust. If set, then during proximity/gesture mode, whenever an ADC measurement is zero, the appropriate offset register will be decreased. If this happens, OFFSET_ADJUSTED will be set to 1 and CINT will occur if enabled. 5 PROX_SUBT_BSLN1 0 R/W Proximity Subtract Baseline One. 4 PROX_SUBT_BSLN0 0 R/W Proximity Subtract Baseline Zero. 3P X A V G _ A U T O _ B S L N 1 R / W Proximity Average Auto Baseline Adjust. If asserted, PBSLN is automatically updated with the value of PXAVG whenever PXAVG is less than previous PBSLN. If this happens, BASELINE_ADJUSTED will be set to 1 and CINT will occur if enabled. 2:0 PXAVG_ITERATIONS 100 R/W Proximity Average Iterations. Sets the number of proximity results that are averaged during normal proximity operation. The resulting proximity average is stored as a 14-bit value in the PXAVG registers after each set of iterations is complete. VALUE ITERATIONS 0S k i p ∙∙∙ 2 DCAVG_ITERATIONS 66 4 71 2 8

Datasheet, Public Page 33 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 36: CALIBCFG2 Note(s): 1. Return to the Register Map ( 0x6C ) Figure 37: CALIBSTA T Note(s): 1. Return to the Register Map ( 0x6D ) Addr: 0x6C CALIBCFG2 Bit Field Reset Type Bit Description 7:5 BINSRCH_TARGET 000 R/W Binary Search Target. Sets the target value for proximity used during calibration. The target value is 2(BINSRCH_TARGET + 2) − 1 counts. VALUE COUNTS 21 5 ∙∙∙ 2(BINSRCH_TARGET + 2)-1 62 5 5 75 1 1 4:0 Reserved 00000 Addr: 0x6D CALIBSTAT Bit Field Reset Type Bit Description 7:3 Reserved 00000

2 BASELINE_ADJUSTED 0 R/W

Baseline Adjusted Automatically. Indicates that PBSLN was reduced because PXAVG was smaller than PBSLN. Only occurs if PXAVG_AUTO_BSLN is set. Clear bit by writing 1 to it.

1 OFFSET_ADJUSTED 0 R/W

Offset Adjusted Automatically. Indicates that proximity offset has been adjusted automatically. Only occurs if PROX_AUTO_OFFSET_ADJUST is set. Clear bit by writing 1 to it. 0 CALIB_FINISHED 0 R/W Calibration Finished. Indicates that calibration is complete. Clear bit by writing 1 to it.

Page 34 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Power, Enable, and Operation The enable register has fields that power on the device and enable the functions. To operate the device, first set all configuration fields for all fun ctions, then set PON = 1, and finally enable functions. Changing configuration register values while functions are operating may result in invalid results. Figure 38: ENABLE Note(s): 1. Return to the Register Map ( 0x80 ) Addr: 0x80 ENABLE Bit Field Reset Type Bit Description 7R e s e r v e d 0 6F D E N 0 R / W Flicker Detection Enable. Writing a 1 activates flicker detection. Writing a 0 disables flicker detection. 5R e s e r v e d 0 4A E N 0 R / W ALS Enable. Writing a 1 enables ALS/Color. Writing a 0 disables ALS/Color. 3P E N 0 R / W Proximity Enable. Writing a 1 enables proximity. Writing a 0 disables proximity. 2:1 Reserved 00 0P O N 0 R / W Power ON. When asserted, the internal oscillator is activated, allowing timers and ADC channels to operate. Writing a 0 disables the oscillator and clears PEN and AEN. Only set this bit after all other registers have been initialized by the host.

Datasheet, Public Page 35 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 39: MEAS_MODE0 Note(s): 1. Return to the Register Map ( 0x81 ) Addr: 0x81 MEAS_MODE0 Bit Field Reset Type Bit Description 7R e s e r v e d 0 6C L _ A P F _ V S Y N C 0 R / W Classical ALS Proximity Flicker Detection with next VSYNC. 5:4 Reserved 00 3:2 PROX_DIODE_ENABLE 00 R/W Proximity Diode Enable. Write '11' to these two bits to enable the proximity diodes for measurement.

1 ALS DIODE SELECTION 0 R/W

ALS Diode Selection. Select which chain mode to use for ALS measurements. Writing a 0 will select ALS Set A and writing a 1 will select ALS Set B. 0 ALS_DIODE_ENABLE 0 R/W Enable ALS Diodes. Write 1 to enable the ALS diodes for measurement.

Page 36 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 40: MEAS_MODE1 Note(s): 1. Return to the Register Map ( 0x82 ) Addr: 0x82 MEAS_MODE1 Bit Field Reset Type Bit Description 7R e s e r v e d 0

6 FD_MODE 0 R/W

Flicker Detection Mode. Writing a 0 will set the FD to on-chip mode and writing a 1 will set the FD to data sampling mode. 5:3 Reserved 000 R/W 2:0 FIFO_MODE 0 R/W FIFO Mode. VALUE MODE 0O f f 13 2 - b i t 21 6 - b i t A L S 31 6 - b i t F D 4 8-bit FD 5 - 7 Reserved

Datasheet, Public Page 37 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 41: TRIGGER_MODE Note(s): 1. Return to the Register Map ( 0x83 ) Addr: 0x83 TRIGGER_MODE Bit Field Reset Type Bit Description 7 VSYNC_START_ALIGN 0 R/W VSYNC Start Alignment. Enables aligned start for ALS/Proximity/Flicker with VSYNC. 6:4 PROX_TRIGGER_TIMING 000 R/W Proximity Trigger Timing. Selects Proximity trigger timing step. VALUE TIMING 0O f f 1N o r m a l ( 2 . 7 8 m s )

2 Long (50ms)

3 Fast (86.61μs) 4F a s t / L o n g ( 1 . 5 6 m s ) 5V S Y N C 6, 7 Reserved 3R e s e r v e d 0 Modulator Trigger Timing. Selects Modulator trigger timing step. 2:0 MOD_TRIGGER_TIMING 0 R/W VALUE TIMING 0O f f 1N o r m a l ( 2 . 7 8 m s ) 3 Fast (86.61μs) 4F a s t / L o n g ( 1 . 5 6 m s ) 5V S Y N C 6, 7 Reserved

Page 40 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 46: MOD_GAIN_0_1 Addr: 0x89 MOD_GAIN_0_1 Bit Field Reset Type Bit Description 7:4 MOD_GAIN1 0000 R/W Modulator One Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 9 1024x 10 2048x 11 4096x 12 - 15 Reserved

Datasheet, Public Page 41 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Note(s): 1. Return to the Register Map ( 0x89 ) 3:0 MOD_GAIN0 0000 R/W Modulator Zero Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 9 1024x 10 2048x 11 4096x 12 - 15 Reserved Addr: 0x89 MOD_GAIN_0_1 Bit Field Reset Type Bit Description

Page 42 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 47: MOD_GAIN_2_3 Addr: 0x8A MOD_GAIN_2_3 Bit Field Reset Type Bit Description 7:4 MOD_GAIN3 0000 R/W Modulator Three Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 91 0 2 4 x 10 2048x 11 4096x 12 - 15 Reserved

Datasheet, Public Page 43 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Note(s): 1. Return to the Register Map ( 0x8A ) 3:0 MOD_GAIN2 0000 R/W Modulator Two Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 91 0 2 4 x 10 2048x 11 4096x 12 - 15 Reserved Addr: 0x8A MOD_GAIN_2_3 Bit Field Reset Type Bit Description

Page 44 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 48: MOD_GAIN_4_5 Addr: 0x8B MOD_GAIN_4_5 Bit Field Reset Type Bit Description 7:4 MOD_GAIN5 0000 R/W Modulator Five Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 9 1024x 10 2048x 11 4096x 12 - 15 Reserved

Datasheet, Public Page 45 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Note(s): 1. Return to the Register Map ( 0x8B ) 3:0 MOD_GAIN4 0000 R/W Modulator Four Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 9 1024x 10 2048x 11 4096x 12 - 15 Reserved Addr: 0x8B MOD_GAIN_4_5 Bit Field Reset Type Bit Description

Page 46 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 49: MOD_GAIN_6_7 Addr: 0x8C MOD_GAIN_6_7 Bit Field Reset Type Bit Description 7:4 MOD_GAIN7 0000 R/W Modulator Seven Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 9 1024x 10 2048x 11 4096x 12 - 15 Reserved

Datasheet, Public Page 47 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Note(s): 1. Return to the Register Map ( 0x8C ) 3:0 MOD_GAIN6 0000 R/W Modulator Six Gain. VALUE GAIN 02 x 14 x 28 x 31 6 x 43 2 x 56 4 x 61 2 8 x 72 5 6 x 85 1 2 x 9 1024x 10 2048x 11 4096x 12 - 15 Reserved Addr: 0x8C MOD_GAIN_6_7 Bit Field Reset Type Bit Description

Page 48 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 50: AGC_ENABLE Note(s): 1. Return to the Register Map ( 0x8D ) Addr: 0x8D AGC_ENABLE Bit Field Reset Type Bit Description 7A G C _ E N A B L E _ M O D _ 7 0 R / W AGC Enable Modulator Seven. If asserted, then device will use automatic gain control for the modulator seven to maximize ALS signal while avoiding saturation. 6A G C _ E N A B L E _ M O D _ 6 0 R / W AGC Enable Modulator Six. If asserted, then device will use automatic gain control for the modulator six to maximize ALS signal while avoiding saturation. 5A G C _ E N A B L E _ M O D _ 5 0 R / W AGC Enable Modulator Five. If asserted, then device will use automatic gain control for the modulator five to maximize ALS signal while avoiding saturation. 4A G C _ E N A B L E _ M O D _ 4 0 R / W AGC Enable Modulator Four. If asserted, then device will use automatic gain control for the modulator four to maximize ALS signal while avoiding saturation. 3A G C _ E N A B L E _ M O D _ 3 0 R / W AGC Enable Modulator Three. If asserted, then device will use automatic gain control for the modulator three to maximize ALS signal while avoiding saturation. 2A G C _ E N A B L E _ M O D _ 2 0 R / W AGC Enable Modulator Two. If asserted, then device will use automatic gain control for the modulator two to maximize ALS signal while avoiding saturation. 1A G C _ E N A B L E _ M O D _ 1 0 R / W AGC Enable Modulator One. If asserted, then device will use automatic gain control for the modulator one to maximize ALS signal while avoiding saturation. 0A G C _ E N A B L E _ M O D _ 0 0 R / W AGC Enable Modulator Zero. If asserted, then device will use automatic gain control for the modulator zero to maximize ALS signal while avoiding saturation.

Datasheet, Public Page 49 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Identification The identification registers provide auxiliary identification for special cases, wafer revision data, and device identification. All identification registers are read only. Figure 51: Identification Registers Note(s): 1. Return to the Register Map ( 0x90 , 0x91 , 0x92 ) Figure 52: CFG0 Note(s): 1. Return to the Register Map ( 0x93 ) Bits Addr Field Reset Type Description 7:0 0x90 AUXID 0x03 R Auxiliary Identification. 7:0 0x91 REVID 0x13 R Revision Identification. 7:0 0x92 ID 0x40 R Device Identification. Addr: 0x93 CFG0 Bit Field Reset Type Bit Description 7R e s e r v e d 0 6L O W P O W E R _ I D L E 0 R / W Low Power Idle. When asserted, the device will automatically run in a low power mode whenever all functions are in wait states or disabled. 5:3 Reserved 100 2:0 RAM_BANK 000 R/W RAM Bank Selection. Specifies the RAM bank to access in registers 0x00 to 0x7F. VALUE BANK 2, 4, 5, 6, 7 Remote Control

3 On-Chip Flicker

Page 50 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 53: CFG3 Note(s): 1. Return to the Register Map ( 0x96 ) Addr: 0x96 CFG3 Bit Field Reset Type Bit Description 7:6 Reserved 00 5H X T A L K _ M O D E 1 0 R / W High Crosstalk Mode. If asserted, the proximity engine uses a 10-bit output mode for no aperture proximity operation intended for extremely high optical crosstalk systems. HXTALK_MODE1 and HXTALK_MODE2 must both be asserted for this function to work. 4S A I 0 R / W Sleep After Interrupt. If asserted, the oscillator is turned off whenever interrupt is active (low). SAI_ ACTIVE is set in this event. To activate the oscillator again, service and clear all interrupts plus clear the SAI_ACTIVE bit. 3:0 Reserved 1111

Datasheet, Public Page 51 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 54: CFG4 Note(s): 1. Return to the Register Map ( 0x97 ) Persistence filters limit the rate of interrupts generated for proximity and ALS/color data. Addr: 0x97 CFG4 Bit Field Reset Type Bit Description 7:4 INT_PINMAP 0000 R/W Interrupt Pin Map. Selects the signal to output on the INT pin. VALUE INTERRUPT PIN 0N o r m a l 1R e s e r v e d 2A I N T D i r e c t 3P I N T D i r e c t 4, 5 Inverted 6V C S E L p u l s e 7 - 15 Reserved 3:0 GPIO_PINMAP 0000 R/W GPIO Pin Map. Selects the signal to output on the GPIO pin. VALUE GPIO PIN 0N o r m a l 1R e s e r v e d 2A I N T D i r e c t 3P I N T D i r e c t 4, 5 Inverted 6V C S E L p u l s e 7 - 15 Reserved

Page 52 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 55: PERS Note(s): 1. Return to the Register Map ( 0x9A ) Addr: 0x9A PERS Bit Field Reset Type Bit Description 7:4 PPERS 0001 R/W Proximity Interrupt Persistence. Defines a filter for the number of consecutive occurrences that PDATA must remain outside the threshold range between PILT and PIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE CONSECUTIVE PDATA OUT OF RANGE TO INTERRUPT

0 Every proximity cycle generates an interrupt

∙∙∙ PPERS 15 15 3:0 APERS 0001 R/W ALS Interrupt Persistence. Defines a filter for the number of consecutive occurrences that ALS/color data must remain outside the threshold range between AILT and AIHT before an interrupt is generated. The ALS data channel used for the persistence filter is set by ALS_TH_CHANNEL. Any sample that is inside the threshold range resets the counter to 0. VALUE CONSECUTIVE ADATA OUT OF RANGE TO INTERRUPT

0 Every ALS cycle generates an interrupt

Datasheet, Public Page 53 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 56: CFG8 Note(s): 1. Return to the Register Map ( 0x9B ) Figure 57: CFG9 Note(s): 1. Return to the Register Map ( 0x9C ) Addr: 0x9B CFG8 Bit Field Reset Type Bit Description 7:6 FIFO_THR 10 R/W FIFO Threshold. Sets a threshold on the FIFO level that triggers the first FIFO buffer interrupt (FINT). VALUE FIFO_LVL 21 6 33 2 5:0 Reserved 000000 Addr: 0x9C CGF9 Bit Field Reset Type Bit Description 7R e s e r v e d 0

6 SIEN_FD 0 R/W

System Interrupt Flicker Detection. Enables system interrupt when flicker detection status change has occurred. 5:0 Reserved 000000

Page 54 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 58: CFG10 Note(s): 1. Return to the Register Map ( 0x9D ) Addr: 0x9D CFG10 Bit Field Reset Type Bit Description 7:6 ALS_AGC_HIGH_HYST 11 R/W ALS AGC High Hysteresis. Sets the ALS data threshold at which AGAIN is reduced when ALS AGC mode is enabled. The threshold is automatically calculated internally as a percentage of full-scale. Note that full-scale is equal to (ATIME + 1) × (ASTEP + 1). VALUE SIGNAL 05 0 % 1 62.5% 27 5 % 3 87.5% 5:4 ALS_AGC_LOW_HYST 11 R/W ALS AGC Low Hysteresis. Sets the ALS data threshold at which AGAIN is increased when ALS AGC mode is enabled. The threshold is automatically calculated internally as a percentage of full-scale. Note that full-scale is equal to (ATIME + 1) × (ASTEP + 1). VALUE SIGNAL 0 12.5% 12 5 % 2 37.5% 35 0 % 3:0 Reserved 0010

Datasheet, Public Page 55 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 59: CFG11 Note(s): 1. Return to the Register Map ( 0x9E ) Addr: 0x9E CFG11 Bit Field Reset Type Bit Description 7A I N T _ D I R E C T 0 R / W ALS Interrupt Direct. Enables the direct mode of ALS interrupt. The status of the ALS interrupt is directly output on the INT pin if this mode is enabled and the pin is configured to do so according to the INT_PINMAP setting. 6P I N T _ D I R E C T 1 R / W Proximity Interrupt Direct. If asserted, the proximity interrupt has a hysteresis loop built into the interrupt. After setting PEN = 1, the device interrupts once PDATA is below PILT or above PIHT. After this initial interrupt, the device will then interrupt based on the direction that the PDATA changes relative to each threshold. An interrupt is generated when PDATA increases from below to above PIHT to indicate a Detect condition, and an interrupt is generated when PDATA decreases from above to below PILT to indicate a Release condition. With built-in hysteresis, it is no longer necessary to change the thresholds between Detect or Release interrupts. This bit applies to PINT0 and PINT1 by using PDATA0 and PDATA1 respectively, as well as the respective thresholds. 5:0 Reserved 000000

Page 56 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 60: CFG12 Note(s): 1. Return to the Register Map ( 0x9F ) Addr: 0x9F CFG12 Bit Field Reset Type Bit Description 7:3 Reserved 00000 2:0 ALS_TH_CHANNEL 000 R/W ALS Thresholds Channel. Sets the channel used for interrupts and persistence if enabled, to determine device status and ALS gain settings. VALUE CHANNEL DEFAUL T

00 C L E A R

11 R E D

33 B L U E

44 L E A K A G E

55 W I D E B A N D

66 I R 1

77 I R 2

Datasheet, Public Page 57 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview ALS autozero configuration is used to set how often the ALS engine offsets are reset to comp ensate for changes in device temperature. Figure 61: AZ_CONFIG Note(s): 1. Return to the Register Map ( 0xA4 ) Addr: 0xA4 AZ_CONFIG Bit Field Reset Type Bit Description 7:0 AZ_NTH_ITERATION 0xFF R/W ALS Autozero Frequency. Sets the frequency at which the device performs autozero of the ALS pulse counter. VALUE AUTOZERO FREQUENCY

0 Never

∙∙∙ Every (AZ_NTH_ITERATION) cycles

253 Every 253 cycles

254 Every 254 cycles

255 Only once (before 1st cycle)

Page 58 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 62: CFG20 Note(s): 1. Return to the Register Map ( 0xA7 ) Figure 63: PCFG1 Note(s): 1. Return to the Register Map ( 0xAA ) Addr: 0xA7 CFG20 Bit Field Reset Type Bit Description 7:5 Reserved 000 4 FLICKER_FIFO_MODE 0 R/W Flicker FIFO Mode. 3:0 Reserved 0000 Addr: 0xAA PCFG1 Bit Field Reset Type Bit Description 7H X T A L K _ M O D E 2 0 R / W High Crosstalk Mode. If asserted, the proximity engine uses a 10-bit output mode for no aperture proximity operation intended for extremely high optical crosstalk systems. HXTALK_MODE1 and HXTALK_MODE2 must both be asserted for this function to work. 6:4 Reserved 000

3 PROX_FILTER_DOWNSAMPLE 0 R/W

Proximity Filter Down Sample. Sets how often proximity results are checked for interrupts and persistence when PROX_FILTER is enabled. 2:0 PROX_FILTER 000 R/W Proximity Filter. Selects the filter size for proximity, n. The average is a moving window of length n, and the result is updated and used either every cycle (PROX_FILTER_DOWNSAMPLE = 0) or every n cycles (PROX_FIL TER_ DOWNSAMPLE = 1). VALUE FILTER LENGTH ∙∙∙ PROX_FILTER + 1

Datasheet, Public Page 59 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 64: PCFG2 Note(s): 1. Return to the Register Map ( 0xAB ) 2. The maximum value setting is limited to a maximum of 7. Addr: 0xAB PCFG2 Bit Field Reset Type Bit Description 7:6 ISINK_RELEASE 00 R/W Current Sink Release Scaler. Current sink scaler used during release setting. VALUE SCALER 00 . 5 21 . 5 5:4 ISINK_DETECT 00 R/W Current Sink Detect Scaler. Current sink scaler used during detect setting. VALUE SCALER 00 . 5 21 . 5 3:0 ILEDS2_SINK2 (2) 0000 R/W Current Sink Slave Two. VALUE CURRENT 00 m A ∙∙∙ n mA 77 m A

Page 60 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 65: PCFG3 Note(s): 1. Return to the Register Map ( 0xAC ) 2. The maximum value setting is limited to a maximum of 7. Addr: 0xAC PCFG3 Bit Field Reset Type Bit Description 7:4 ILEDS1_SINK1 (2) 0R / W Current Sink Slave One. VALUE CURRENT 00 m A ∙∙∙ n mA 77 m A 3:0 ILEDM0_SINK0 (2) 0R / W Current Sink Master Zero. VALUE CURRENT 01 m A ∙∙∙ n+1 mA 78 m A

Page 62 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 68: PCFG6 Note(s): 1. Return to the Register Map ( 0xAF ) Addr: 0xAF PCFG6 Bit Field Reset Type Bit Description 7P D A T A _ E V A L _ C H 0 R / W Proximity Evaluation Channel. This bit selects which channel is used for the proximity baseline calculation. If set to 0 then PDATA0 is used, if set to 1 then PDATA1 is used. 6:4 Reserved 000 3P D A T A 1 _ H _ A N D 0 R / W Proximity One High Threshold And. If set to 1 then the high threshold of PDATA1 is seen as an AND for the proximity interrupt. 2P D A T A 1 _ L _ A N D 0 R / W Proximity One Low Threshold And. If set to 1 then the low threshold of PDATA1 is seen as an AND for the proximity interrupt. 1P D A T A 0 _ H _ A N D 0 R / W Proximity Zero High Threshold And. If set to 1 then the high threshold of PDATA0 is seen as an AND for the proximity interrupt. 0P D A T A 0 _ L _ A N D 0 R / W Proximity Zero Low Threshold And. If set to 1 then the low threshold of PDATA0 is seen as an AND for the proximity interrupt.

Datasheet, Public Page 63 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 69: PCFG7 Note(s): 1. Return to the Register Map ( 0xB0 ) Figure 70: POFFSET0 Note(s): 1. Return to the Register Map ( 0xB1 , 0xB2 ) Addr: 0xB0 PCFG7 Bit Field Reset Type Bit Description 7:5 Reserved 000

4 PROX_PRE_FILTER 0 R/W

Proximity Pre-Filter. When this bit is set, the 2 most recent proximity integrations will be combined and PDATA will be ~2x the value of a single integration when this bit is not set. 3R e s e r v e d 0 2:0 PPULSE_LEN 001 R/W Proximity Pulse Length. Sets the proximity pulse length. VALUE PULSE LENGTH 04 μ s 18 μ s 21 6 μ s 33 2 μ s 46 4 μ s 51 2 8 μ s 62 5 6 μ s 75 1 2 μ s Bits Addr Field Reset Type Description 7:0 0xB1 POFFSET0 0x00 R/W Proximity Offset Zero 15:8 0xB2 0x00 R/W

Datasheet, Public Page 65 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Status Registers The primary status register for TMD3719 indicates if there are saturation or interrupt events th at need to be handled by the user. This register is self-clear ing, meaning that writing a 1 to any bit in the register clears that status bit. In this way, the user should read the STATUS register, handle all indicated event(s), then write the register value back to STATUS to clear the handled events. Writing 0 to these bits will not clear those bits if they have a value of 1, wh ich means that new events that occurred since the last read of the STATUS register will not be accidentally cleared. Figure 73: STATUS Note(s): 1. Return to the Register Map ( 0xB7 ) Addr: 0xB7 STATUS Bit Field Reset Type Bit Description 7A S A T 0 R ALS Saturation. If ASIEN is set, indicates ALS saturation. Check the STATUS3 register to differentiate between analog or digital saturation. 6F D S A T 0 R Flicker Detection Saturation. If FDSIEN is set, indicates Flicker Detection saturation. Check the STATUS4 register to differentiate between analog or digital saturation. 5P S A T 0 R Proximity Saturation. If PSIEN is set, indicates analog saturation during a previous proximity cycle. Check the STATUS2 register to differentiate between ambient or reflected light saturation. 4P I N T 0 R Proximity Interrupt One. If PIEN is set, indicates that a proximity detect or release event that met the programmed proximity thresholds and persistence occurred. 3A I N T 0 R ALS Interrupt. If AIEN is set, indicates that an ALS event that met the programmed ALS thresholds and persistence occurred. 2F I N T 0 R FIFO Buffer Interrupt. If FIEN is set, indicates that the FIFO_LVL fulfills the threshold condition. If cleared by writing 1, the interrupt will be asserted again as more data is collected. To fully clear this interrupt, all data must be read from the FIFO buffer. 1C I N T 0 R Calibration Interrupt. If CIEN is set, indicates that either calibration is finished or that one of certain events have occurred during normal operation. If each function is enabled, CINT will be asserted if too many zeros occur too often in a period of samples, if the proximity baseline has decreased, or if at least one offset register has been adjusted. Check the CALIBSTAT register to identify the triggering event(s). 0S I N T 0 R System Interrupt. If SIEN is set, indicates that one or more of several events has occurred or is complete. The events related to this interrupt are indicated in the STATUS5 register (0xBB): flicker detection register status has changed.

Page 66 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Additional status registers indi cate details about saturation, interrupts, and device execution. Figure 74: STATUS2 Note(s): 1. Return to the Register Map ( 0xB8 ) Addr: 0xB8 STATUS2 Bit Field Reset Type Bit Description 7P V A L I D 0 R Proximity Valid. Indicates that the proximity state has completed a cycle since either an assertion of PEN or the last readout of PDATA. 6A V A L I D 0 R ALS Valid. Indicates that the ALS state has completed a cycle since either an assertion of AEN or the last readout of the ASTATUS register. 5P S A T 1 _ A D C 0 R Proximity One ADC Saturation. Indicates that the maximum proximity ADC value has occurred for proximity channel one during proximity measurement.

4 PSAT1_

Proximity One Reflective Saturation. Indicates that the intensity of reflected light has exceeded the maximum integration level for the proximity analog circuit for channel one during proximity measurement.

3 PSAT1_

Proximity One Ambient Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the proximity analog circuit for channel one during proximity measurement. 2P S A T 0 _ A D C 0 R Proximity Zero ADC Saturation. Indicates that the maximum proximity ADC value has occurred for proximity channel zero during proximity measurement.

1 PSAT0_

Proximity Zero Reflective Saturation. Indicates that the intensity of reflected light has exceeded the maximum integration level for the proximity analog circuit for channel zero during proximity measurement.

0 PSAT0_

Proximity Zero Ambient Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the proximity analog circuit for channel zero during proximity measurement.

Datasheet, Public Page 67 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 75: STATUS3 Note(s): 1. Return to the Register Map ( 0xB9 ) Addr: 0xB9 STATUS3 Bit Field Reset Type Bit Description 7A S A T 7 _ A N A L O G 0 R ALS Channel Seven Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel seven analog circuit. 6A S A T 6 _ A N A L O G 0 R ALS Channel Six Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel six analog circuit. 5A S A T 5 _ A N A L O G 0 R ALS Channel Five Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel five analog circuit. 4A S A T 4 _ A N A L O G 0 R ALS Channel Four Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel four analog circuit. 3A S A T 3 _ A N A L O G 0 R ALS Channel Three Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel three analog circuit. 2A S A T 2 _ A N A L O G 0 R ALS Channel Two Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel two analog circuit. 1A S A T 1 _ A N A L O G 0 R ALS Channel One Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel one analog circuit. 0A S A T 0 _ A N A L O G 0 R ALS Channel Zero Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS channel zero analog circuit.

Page 68 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 76: STATUS4 Note(s): 1. Return to the Register Map ( 0xBA ) Addr: 0xBA STATUS4 Bit Field Reset Type Bit Description 7 OSCCAL_SAT 0 R Oscillator Calibration Saturation. 6R e s e r v e d 0 5 OSCCAL_FINISHED 0 R Oscillator Calibration Finished.

4 FD_SAT_DETECTED 0 R

Flicker Saturation Detected. Indicates that saturation occurred during the last flicker detection measurement, and the result may not be valid. Write 1 to this bit to clear this field. 3F D _ B U S Y 0 R Flicker Detection Busy. Indicates flicker detection is in progress.

2 FD_TRIG_ERROR 0 R

Flicker Detect Trigger Error. Indicates that there is a timing error that prevents flicker detect from functioning correctly.

1 PROX_TRIG_ERROR 0 R

Proximity Trigger Error. Indicates that there is a timing error that prevents proximity from functioning correctly. The number of pulses and/or pulse length are too long for the PTIME configured for the device.

0 MOD_TRIG_ERROR 0 R

Modulator Trigger Error. Indicates that there is a timing error that prevents ALS from functioning correctly. The WTIME is too short for the ATIME configured for the device.

Datasheet, Public Page 69 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 77: STATUS5 Note(s): 1. Return to the Register Map ( 0xBB ) Addr: 0xBB STATUS5 Bit Field Reset Type Bit Description 7:4 Reserved 0000 3S I N T _ F D 0 R Flicker Detect Interrupt. If SIEN_FD is set, indicates that the FD_STATUS register status has changed. 2:1 Reserved 00 0 SINT_SYNC_ERROR 0 R Synchronization Error Interrupt. If SINT_SYNC_ERROR is set, indicates there was a synchronization error.

Page 70 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 78: STATUS7 Note(s): 1. Return to the Register Map ( 0xBD ) Addr: 0xBD STATUS7 Bit Field Reset Type Bit Description 7A I N T _ A I H T 0 R ALS Interrupt High. Indicates that an ALS interrupt occurred because the ALS data exceeded the high threshold. 6A I N T _ A I L T 0 R ALS Interrupt Low. Indicates that an ALS interrupt occurred because the ALS data is below the low threshold. 5:4 Reserved 00

3 PINT1_PIHT 0 R

Proximity One Interrupt High. Indicates that a proximity one interrupt occurred because the proximity one data exceeded the high threshold.

2 PINT1_PILT 0 R

Proximity One Interrupt Low. Indicates that a proximity one interrupt occurred because the proximity one data is below the low threshold.

1 PINT0_PIHT 0 R

Proximity Zero Interrupt High. Indicates that a proximity zero interrupt occurred because the proximity zero data exceeded the high threshold.

0 PINT0_PILT 0 R

Proximity Zero Interrupt Low. Indicates that a proximity zero interrupt occurred because the proximity zero data is below the low threshold.

Datasheet, Public Page 71 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 79: STATUS8 Note(s): 1. Return to the Register Map ( 0xBE ) Figure 80: STATUS9 Note(s): 1. Return to the Register Map ( 0xBF ) Addr: 0xBE STATUS8 Bit Field Reset Type Bit Description 7:6 Reserved 00 5F V A L I D 0 R Flicker Data Valid. Indicates that the flicker detection has completed a cycle since assertion of FDEN or since the last readout of the FSTATUS register. 4R e s e r v e d 0 3S Y N C _ L O S T 0 R Synchronization Lost. Indicates when synchronization of VSYNC is lost. 2R e s e r v e d 0 1S A I _ A C T I V E 0 R Sleep After Interrupt Active. Indicates that the device is in SLEEP due to an interrupt. To exit SLEEP mode, clear this bit. 0I N I T _ B U S Y 0 R Initialization Busy. Indicates that the device is initializing. This bit will remain 1 for about 300μs after power on. Do not interact with the device until initialization is complete. Addr: 0xBF STATUS9 Bit Field Reset Type Bit Description 7:4 Reserved 0000

3 SYNC_ERROR 0 R Synchronization Error

2:0 Reserved 000

Page 72 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 81: ASTATUS Note(s): 1. Return to the Register Map ( 0xC0 ) Addr: 0xC0 ASTATUS Bit Field Reset Type Bit Description 7:1 Reserved 0000000 0A S A T _ S T A T U S 0 R ALS Saturation Status. Indicates if the latched ALS data is affected by analog or digital saturation.

Datasheet, Public Page 73 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 82: ALS Data Registers Note(s): 1. Return to the Register Map ( 0xC1 , 0xC2 , 0xC3 , 0xC4 , 0xC5 , 0xC6 , 0xC7 , 0xC8 , 0xC9 , 0xCA , 0xCB , 0xCC, 0xCD , 0xCE , 0xCF , 0xD0 , 0xD1 , 0xD2 , 0xD3 , 0xD4 , 0xD5 , 0xD6 , 0xD7 , 0xD8 ). Bits Addr Field Reset Type Description 7:0 0xC1 ADATA0 0x00 R ALS Channel Zero Data. CLEAR data15:8 0xC2 0x00 R 23:16 0xC3 0x00 R 7:0 0xC4 ADATA1 0x00 R ALS Channel One Data. RED data15:8 0xC5 0x00 R 23:16 0xC6 0x00 R 7:0 0xC7 ADATA2 0x00 R ALS Channel Two Data. GREEN data15:8 0xC8 0x00 R 23:16 0xC9 0x00 R 7:0 0xCA ADATA3 0x00 R ALS Channel Three Data. BLUE data15:8 0xCB 0x00 R 23:16 0xCC 0x00 R 7:0 0xCD ADATA4 0x00 R ALS Channel Four Data. LEAKAGE data15:8 0xCE 0x00 R 23:16 0xCF 0x00 R 7:0 0xD0 ADATA5 0x00 R ALS Channel Five Data. WIDEBAND data15:8 0xD1 0x00 R 23:16 0xD2 0x00 R 7:0 0xD3 ADATA6 0x00 R ALS Channel Six Data. IR1 data15:8 0xD4 0x00 R 23:16 0xD5 0x00 R 7:0 0xD6 ADATA7 0x00 R ALS Channel Seven Data. IR2 data15:8 0xD7 0x00 R 23:16 0xD8 0x00 R

Datasheet, Public Page 75 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 85: GPIO Note(s): 1. Return to the Register Map ( 0xF2 ) Figure 86: AGC_GAIN_MAX Note(s): 1. Return to the Register Map ( 0xF4 ) Addr: 0xF2 GPIO Bit Field Reset Type Bit Description 7:6 Reserved 00

5 INT_INVERT 0 R/W

Interrupt Invert. If asserted, the output on interrupt pin is inverted. This is useful for direct interrupt output if active = high. 4I N T _ I N _ E N 0 R / W Interrupt Input Enable. If asserted, the interrupt pin can be used as an input. 3G P I O _ I N V E R T 0 R / W GPIO Invert. If asserted, the output on GPIO is inverted. This is useful for direct interrupt output if active = high. 2 GPIO_IN_EN 0 R/W GPIO Input Enable. If asserted, the GPIO pin accepts a non-floating input. 1 GPIO_OUT 1 R/W GPIO Output. If asserted, the output state of the GPIO is active directly. 0G P I O _ I N 0 R / W GPIO Input. Indicates the status of the GPIO input if GPIO_IN_EN is asserted. Addr: 0xF4 AGC_GAIN_MAX Bit Field Reset Type Bit Description 7:3 Reserved 00000 2:0 AGC_MOD_GAIN_MAX 110 R/W AGC Modulator Gain Max. Sets the maximum modulator gain for the AGC engine.

Page 76 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 87: INTENAB Note(s): 1. Return to the Register Map ( 0xF5 ) Addr: 0xF5 INTENAB Bit Field Reset Type Bit Description 7A S I E N 0 R / W ALS Saturation Interrupt Enable. When asserted permits ALS saturation interrupts to be generated. 6F D S I E N 0 R / W Flicker Detect Saturation Interrupt Enable. When asserted permits flicker detection saturation interrupts to be generated.

5 PSIEN 0 R/W

Proximity Saturation Interrupt Enable. When asserted permits proximity saturation interrupts to be generated.

4 PIEN 0 R/W

Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter.

3 AIEN 0 R/W

ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. Bit is mirrored in the ENABLE register.

2 FIEN 0 R/W

FIFO Buffer Interrupt Enable. When asserted permits interrupt to be generated when FIFO_LVL exceeds the FIFO threshold condition. 1 CIEN 0 R/W Calibration Interrupt Enable. When asserted permits calibration interrupts to be generated. 0S I E N 0 R / W System Interrupt Enable. When asserted permits system interrupts to be generated. Indicates that flicker detection status has changed.

Datasheet, Public Page 77 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 88: CONTROL Note(s): 1. Return to the Register Map ( 0xF6 ) Figure 89: POFFSET1 Note(s): 1. Return to the Register Map ( 0xF7 , 0xF8 ) Addr: 0xF6 CONTROL Bit Field Reset Type Bit Description 7:3 Reserved 00000

2 ALS_MANUAL_AZ 0 R/W

ALS Manual Autozero. Starts a manual autozero of the ALS engines. Set AEN = 0 before starting a manual autozero for it to work. 1F I F O _ C L R 0 R / W FIFO Buffer Clear. Clears all FIFO data, FINT, FIFO_OV, and FIFO_LVL.

0 CLEAR_SAI_ACTIVE 0 R/W

Clear Sleep-After-Interrupt Active. Clears SAI_ACTIVE, ends sleep, and restarts device operation. Bits Addr Field Reset Type Description 7:0 0xF7 POFFSET1 0x00 R/W Proximity Offset One 15:8 0xF8 0x00 R/W

Page 78 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Register Overview Figure 90: FIFO_MAP Note(s): 1. Return to the Register Map ( 0xF9 ) Addr: 0xF9 FIFO_MAP Bit Field Reset Type Bit Description 7 FIFO_WRITE_ADATA7 0 R/W FIFO Write ALS Data Seven. If asserted, ADATA7 is written to the FIFO Buffer. 6 FIFO_WRITE_ADATA6 0 R/W FIFO Write ALS Data Six. If asserted, ADATA6 is written to the FIFO Buffer. 5 FIFO_WRITE_ADATA5 0 R/W FIFO Write ALS Data Five. If asserted, ADATA5 is written to the FIFO Buffer. 4 FIFO_WRITE_ADATA4 0 R/W FIFO Write ALS Data Four. If asserted, ADATA4 is written to the FIFO Buffer. 3 FIFO_WRITE_ADATA3 0 R/W FIFO Write ALS Data Three. If asserted, ADATA3 is written to the FIFO Buffer. 2 FIFO_WRITE_ADATA2 0 R/W FIFO Write ALS Data Two. If asserted, ADATA2 is written to the FIFO Buffer. 1 FIFO_WRITE_ADATA1 0 R/W FIFO Write ALS Data One. If asserted, ADATA1 is written to the FIFO Buffer. 0 FIFO_WRITE_ADATA0 0 R/W FIFO Write ALS Data Zero. If asserted, ADATA0 is written to the FIFO Buffer.

Datasheet, Public Page 79 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Register Overview Figure 91: FIFO_MAP2 Note(s): 1. Return to the Register Map ( 0xFA) Addr: 0xFA FIFO_MAP2 Bit Field Reset Type Bit Description 7:5 Reserved 000

4 FIFO_WRITE_FD_RESULT 0 R/W

FIFO Write Flicker Detection Result. If asserted, flicker detection on-chip calculation result is written to the FIFO Buffer.

3 FIFO_WRITE_FD_DATA 0 R/W

FIFO Write Flicker Detection Data. If asserted, flicker detection data is written to the FIFO Buffer. 2 FIFO_WRITE_PDATAR 0 R/W FIFO Write Proximity Ratio Data. If asserted, proximity ratio data is written to the FIFO Buffer. 1 FIFO_WRITE_PDATA1 0 R/W FIFO Write Proximity One Data. If asserted, proximity one data is written to the FIFO Buffer. 0 FIFO_WRITE_PDATA0 0 R/W FIFO Write Proximity Zero Data. If asserted, proximity zero data is written to the FIFO Buffer.

Page 82 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Package Drawings & Markings Figure 96: TMD3719 Module Dimensions Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. Contacts are copper with NiPdAu plating. 4. This package contains no lead (Pb). 5. This drawing is subject to change without notice. 6. Measurement guarantee by lot a cceptance testing using 20 units. Package Drawings & Markings ;758(5 $/6&/ 7<3 7[&/ 3,1&/ & $% ; ; 3,1 “7<3 0 & $% 0 & $% RoHS Green

Datasheet, Public Page 83 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 97: Recommended PCB Pad Layout Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. This drawing is subject to change without notice. PCB Pad Layout 3,1

Page 84 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Tape & Reel Information Figure 98: TMD3719 Tape and Reel Mechanical Drawing Note(s): 1. All linear dimensions are in millimeters. Dime nsion tolerance is ± 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. 4. Each reel is generally 330 millimeters in diameter and contains 10000 parts. Please reconfirm for actual orders. 5. ams OSRAM packaging tape and reel confor m to the requirements of EIA Standard 481−B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Tape & Reel Information

Datasheet, Public Page 85 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Soldering & Storage Information Soldering Information The module has been tested an d has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 99: Solder Reflow Profile Note(s): 1. Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum. Profile Feature Preheat/ Soak Sn-Pb Eutectic Assembly Pb-Free Assembly Temperature Min ( Tsmin) 100°C 150°C Temperature Max ( Tsmax) 150°C 200°C Time (ts) from (Tsmin to Tsmax) 60s - 120s 60s-120s Ramp-up rate (TL to TP) max. 3°C/s max. 3°C/s Liquidous temperature (TL) Time (tL) maintained above TL 183°C 60s - 150s 217°C 60s - 150s Peak package body temperature (TP) For users TP must not exceed the Classification temp of 235°C. For suppliers TP must equal or exceed the Classification temp of 235°C. For users TP must not exceed the Classification temp of 260°C. For suppliers TP must equal or exceed the Classification temp of 260°C. Time (tP)(1) within 5°C of the specified classification temperature (Tc) 20(1) seconds 30 (1) seconds Ramp-down rate (TP to TL) Max. 6°C/s Max. 6°C/s Time 25°C to peak temperature Max. 6 minutes Max. 8 minutes Soldering & Storage Information

Page 86 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Soldering & Storage Information Figure 100: Solder Reflow Profile Graph Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 24 months from the date code on the bag when stored under the following conditions:

• Shelf Life: 24 months
• Ambient Temperature: <40°C
• Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 24 months shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Not to Scale – For Reference Only TP Temperature (°C) Time (seconds) tL TL TC - 5°C tP Tsmin Tsmax Preheat Area Max Ramp Up Rate = 3°C/s Max Ramp Down Rate = 6°C/s

Datasheet, Public Page 87 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Soldering & Storage Information Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:

• Floor Life: 168 hours
• Ambient Temperature: <30°C
• Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.

Page 88 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Laser Eye Safety The TMD3719 is designed to meet the Class 1 laser safety limits including single faults in compliance with IEC 60825-1:2014. This applied to the stand-alone device. In an end application system environment, the system may need to be tested to ensure it remains compliant. Th e system must not include any additional lens to concentrate the laser light or parameters set outside of the recommended operating conditions. Use outside of the recommended condition or any physical modification to the module during development could result in hazardous levels of radiation exposure. Laser Eye Safety

Datasheet, Public Page 89 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Ordering & Contact Information Figure 101:

Ordering Information

Buy our products or get free samples online at: www.ams.com/Products Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/Contact Headquarters ams-OSRAM AG Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Address Interface Delivery Form Delivery Quantity TMD37193 0x39 1.8V I²C Tape & Reel 10000 pcs/reel Ordering & Contact Information

Page 90 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

Datasheet, Public Page 91 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Copyrights & Disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provis ions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by desc ription regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications re quiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but no t limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. Copyrights & Disclaimer

Page 92 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status

Datasheet, Public Page 93 [v2-00] 2023-Jan-12 Document Feedback TMD3719 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-03 (2020-Nov-20) to current revision 2-00 (2023-Jan-12) Page Updated “Shelf Life” to 24 months 86 Revision Information

Page 94 Datasheet, Public Document Feedback [v2-00] 2023-Jan-12 TMD3719 − Content Guide

1 General Description

1 Key Benefits & Features

2 Applications

2 Block Diagram

3 Pin Assignments

4A b s o l u t e M a x i m u m R a t i n g s

6 Electrical Characteristics

7 Optical Characteristics

11 Timing Characteristics

13 Typical Operating Characteristics

15 Detailed Description

16 State Machine Diagrams

17 I²C Protocol

18 Register Overview

18 Register Map

23 Detailed Register Descriptions

23 ALS Interrupt Thresholds

24 Proximity Interrupt Thresholds

34 Power, Enable, and Operation

49 Identification

65 Status Registers

80 FIFO Buffer Data and Status

83 PCB Pad Layout

84 Tape & Reel Information

85 Soldering & Storage Information

85 Soldering Information

86 Storage Information

86 Moisture Sensitivity

86 Shelf Life

87 Floor Life

87 Rebaking Instructions

88 Laser Eye Safety

90 RoHS Compliant & ams Green Statement

91 Copyrights & Disclaimer

92 Document Status