TMD3702VC AMSCO | Alldatasheet
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Datasheet, Public Page 1 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC Narrow ALS, Color and Proximity Sensor Module The TMD3702VC features proxim ity detection, color sense (RGBC+IR), and digital ambient light sensing (ALS). The extremely narrow 1.44mm module incorporates an IR VCSEL and factory calibrated VCSEL driver. The proximity detection feature provides object detection (e.g. mobile device screen to user’s ear) by photodiode detection of reflected IR energy (sourced by the integrated VCSEL). Detect/release events are interrupt driven, and occur when proximity result crosses upper and/or lower threshold settings. The proximity engine features a wide range offset adjustment to compensate for unwanted IR energy reflection at the sensor. Proximity results are further improved by automatic ambient light subtraction. The color photodiodes have UV and IR bloc king filters and dedicated data converters producing 16-bit data. This architecture allows applications to accurately measure ambient light which enables devices to calculate illuminance and color temperature to control display backlight and chromaticity. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TMD3702VC, Narrow ALS, Color and Proximity Sensor Module are listed below: Figure 1: Added Value of Using TMD3702VC Benefits Features
- Single device integrated optical solution
- ALS + color + proximity
- 1.44mm x 2.84mm x 0.65mm module
- ±48° field of view
- Integrated 940nm IR VCSEL
- Power management features
- I²C fast mode interface compatible
- Accurate ambient light sensing
- 5 channels (RGBC + IR)
- UV / IR blocking filters
- Programmable gain and integration time
- Reduced power consumption • 1.8V power supply with 1.8V I²C bus
- Sleep mode General Description
Page 2 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − General Description
Applications
The TMD3702VC applications include:
- Ambient light sensing
- Proximity sensing
- Mobile phone touc h screen disable
- Color temperature measurement to assist display, backlight, camera, and flash control Block Diagram The functional blocks of this device are shown below: Figure 2: TMD3702VC Block Diagram SCL SDA INT VDD IR CH3 Data CH2 ADC CH2 Data CH1 ADC CH1 Data CH3 ADC C R G B Proximity Integration Wait Control Proximity Control Prox Data Prox Thresholds Lower Upper Prox ADC ALS Thresholds Lower Upper I2C Interface Interrupt Open Drain Output Open Drain Current Sink PGND 940nm IR VCSEL Optically Isolated LEDA UV & IR Cut Filter AMUX VSS ALS Control CH0 ADC CH0 Data
Datasheet, Public Page 3 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Pin Assignment Figure 3: Pin Diagram Figure 4: Pin Description Pin Number Pin Name Description
1 SCL I²C serial clock input terminal
2V S S Ground. All voltages are referenced to VSS/PGND and both pins must be connected to ground.3P G N D
4 LEDA VCSEL anode
5N C No connect. No internal electrical connection. For improved device ESD protection, connect to ground. 6 VDD Supply voltage (1.8V) 7 INT Interrupt. Open drain output (active low)
8 SDA I²C serial data I/O terminal
6&/ 966 3*1' 9'' ,17 /('$ 6'$
Page 4 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condition beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments VDD Supply voltage to ground -0.3 2.0 V LEDA VCSEL voltage to PGND -0.3 3.6 V VIO Digital I/O terminal voltage -0.3 3.6 V IIO Digital output terminal current -1 20 mA IVCSEL VCSEL current 30 mA ISCR Input current (latch-up immunity) ± 100 mA Class II JEDEC JESD78D ESDHBM HBM electrostatic discharge ± 2000 V JS-001-2014 ESDCDM CDM electrostatic discharge ± 500 V JEDEC JESD22-C101F TSTRG Storage temperature range -40 85 °C IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.” RH NC Relative humidity (non-condensing) 58 5% PDISS Power dissipation 200 mW Average power dissipation over a 1 second period Absolute Maximum Ratings
Datasheet, Public Page 5 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Recommended Operating Conditions Note(s): 1. Power dissipation averaged over 1 second period. Symbol Parameter Min Typ Max Units VDD Supply voltage 1.7 1.8 2.0 V VLEDA Supply voltage to VCSEL anode (PLDRIVE = 19mA) 3.0 3.3 3.6 V Supply voltage to VCSEL anode (PLDRIVE = 14mA) 2.8 3.3 3.6 V PDISS Average power dissipation(1) 100 mW TA Operating ambient temperature -30 85 °C
Electrical Characteristics
Page 6 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Electrical Characteristics Figure 7: Operating Characteristics (V DD = 1.8V, T A = 25 °C unless otherwise noted) Note(s): 1. Values are shown at the VDD pin and do not include current through the IR VCSEL. 2. This parameter indicates the supply current during periods of ALS integration. If Wait is enabled (WEN=1), the supply curren t is lower during the Wait period. 3. Idle state occurs when PON=1 and all functions are not enabled. 4. Sleep state occurs when PON = 0 and I²C bus is idle. If Slee p state has been entered as the result of operational flow, SAI = 1, PON will remain high. 5. Digital pins: SDA, SCL, INT are tolera nt to a communication voltage up to 3.0V. Symbol Parameter Conditions Min Typ Max Unit fOSC Oscillator frequency 8.1 MHz IDD Supply current (1) Active ALS State (PON=AEN=1, PEN=0) (2) 50 105 150 μAIdle State (PON=1, AEN=PEN=0) (3) 35 Sleep State (4) 0.54 VOL INT, SDA output low voltage 6mA sink current 0.6 V ILEAK Leakage current, SDA,SCL,INT -5 5 μA VIH SCL, SDA input high voltage (5) 1.26 V VIL SCL, SDA input low voltage 0.54 V TActive Time from power-on to ready to receive I²C commands 1.5 ms
Page 8 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Electrical Characteristics Figure 10: Proximity Optical Characteristics (V DD = 1.8V, LEDA = 3.0V, T A = 25 °C, unless otherwise noted) Note(s): 1. Production tested result is the average of 5 readings expressed relative to a calibrated response. 2. Representative result by characterization. 3. Production tested result is the average of 20 readings divided by the average response. Parameter Conditions Min Typ Max Unit Part to Part Variation (1) Conditions: PGAIN = 2 (4x) PLDRIVE = 8 (19mA) PPULSE = 7 (8 pulses) PPULSE_LEN = 3 (32μs) d=23mm round target 30mm target distance 65 100 135 % Response, Absolute Basic proximity measurement (2) Conditions: PGAIN = 2 (4x), PLDRIVE = 8 (19mA) PPULSE = 7 (8 pulses) PPULSE_LEN = 3 (32μs) Target material: 90% reflective surface of Kodak gray card Target Size: 100mm x 100mm Target Distance: 100mm 250 312 374 counts Noise/Signal (3) PGAIN = 2 (4x) PLDRIVE = 8 (19mA) PPULSE = 7 (8 pulses) PPULSE_LEN = 3 (32μs) d=23mm round target 30mm target distance
Page 12 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Typical Operating Characteristics Figure 17: Proximity Operation Proximity Operation: By varying Gain, VCSEL drive current, number of VCSEL pulses and VCSEL pulse duration the proximity detection range can be adjusted. 200 400 600 800 1000 1200 02 0 4 0 60 80 100 120 140 Proximity Response (counts) Target Distance (in mm; 90% white card) Proximity Operating Range (@19mA) 8ʅs/2x/16 Pulses 16ʅs/4x/16 Pulses4ʅs/1x/16 Pulses 4ʅs/1x/32 Pulses 8ʅs/2x/32 Pulses 16ʅs/4x/32 Pulses 32ʅs/8x/16 Pulses 32ʅs/8x/32 Pulses
Datasheet, Public Page 13 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Detailed Description Proximity Proximity results are affected by three fundamental factors: the integrated IR VCSEL emission, IR reception, and environmental factors, including target distance and surface reflectivity. The IR reception signal path begins with IR detection from a photodiode and ends with the 10-b it or 14-bit proximity result in PDATA register. Signal from the photodiode is amplified, and offset adjusted to optimize performance. Offset correction or cross-talk compensation is accomplished by adjustment to the POFFSET register. The analog circuitry of the device applies the offset value as a subtraction to the signal accumulation; therefore a positive offset value has the effect of decreasing the results. Color and Ambient Light Sense The color and ALS reception signal path begins as photodiodes receive filtered light and ends with 16-bit results. The IR photodiode primarily used for proximity sense, is multiplexed with the green channel’s ADC to measure the IR content of ambient light. The color photodiodes are filtered with a UV and IR filters. The IR photodiode is filtered to receive only IR. Signal from the RGBC photodiodes simultaneously accumulate for a period of time set by the value in ATIME before the results are available. Measurement of IR must be done in a separate integration because it shares the ADC with the green photodiode. Gain is adjustable from 1x to 512x to facilitate operation over a wide range of lighting conditions. Based on the optical glass used on top of the device, custom equations are empirically derived to calculate the amount of ambient light, color temperature, as well as, determine the light type (e.g. LED, fluorescent, incandescent, etc.) using the ALS results. I²C Characteristics The device uses I²C serial communication protocol for communication. The device support s 7-bit chip addressing and both standard and fast clock frequency modes with a chip address of 0x49. Read and Write transactions comply with the standard set by Ph ilips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address + 1. Detailed Description
Page 14 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Detailed Description I²C Write Transaction A Write transaction consists of a START, CHIP-ADDRESS WRITE , REGISTER-ADDRESS, DATA BYTE(S ), and STOP . Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/ NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP . I²C Read Transaction A Read transaction consists of a START, CHIP-ADDRESS WRITE , REGISTER-ADDRESS, START, CHIP-ADDRESS READ , DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NA CK being placed on the bus by the master, followed by STOP . Alternately, if the previous I²C transaction was a Read, the internal register address buffer is still valid, allowing the transaction to proceed without “re”-specifying the register address. In this case the transaction consists of a START, CHIP-ADDRESS READ , DATA BYTE(S), and STOP . Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP . The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at: www.i2c-bus.org/references/ Figure 18: I²C Timing Diagrams STARTSTART STOPSTOP tBUF tLOW tHD; STA tR tF VIH VIL VIH VIL tSU; DAT tSU; STAtHD; DAT tHIGH tSU; STO SCL SDA
Datasheet, Public Page 15 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Detailed Description Figure 19: Simplified State Diagram SLEEP Averaging Loop N Times IDLE WAIT COLOR ALSPROX
Page 16 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description Figure 20: Register Overview Address Register Name R/W Register Function Reset Value 0x80 ENABLE R/W Enables states 0x00 0x81 ATIME R/W ADC integration time 0x00 0x82 PRATE R/W Proximity time 0x1F 0x83 WTIME R/W Wait time 0x00 0x84 AILTL R/W ALS interrupt low threshold low byte 0x00 0x85 AILTH R/W ALS interrupt low threshold high byte 0x00 0x86 AIHTL R/W ALS interrupt high threshold low byte 0x00 0x87 AIHTH R/W ALS interrupt high threshold high byte 0x00 0x88 PILTL R/W Proximity interrupt low threshold low byte 0x00 0x89 PILTH R/W Proximity interrupt low threshold high byte 0x00 0x8A PIHTL R/W Proximity interrupt high threshold low byte 0x00 0x8B PIHTH R/W Proximity interrupt high threshold high byte 0x00 0x8C PERS R/W ALS and proximity interrupt persistence filters 0x00 0x8D CFG0 R/W Configuration zero 0x40 0x8E PCFG0 R/W Proximity configuration zero 0x4F 0x8F PCFG1 R/W Proximity configuration one 0x80 0x90 CFG1 R/W Configuration one 0x09 0x91 REVID R Revision ID 0x01 0x92 ID R Device ID 0x10 0x93 STATUS R, SC Device status 0x00 0x94 CDATAL R Clear ADC low data 0x00 0x95 CDATAH R Clear ADC high data 0x00 0x96 RDATAL R Red ADC low data 0x00 0x97 RDATAH R Red ADC high data 0x00 0x98 GDATAL R Green (or IR) ADC low data 0x00 0x99 GDATAH R Green (or IR) ADC high data 0x00 0x9A BDATAL R Blue ADC low data 0x00 Register Description
Datasheet, Public Page 17 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Register Description 0x9B BDATAH R Blue ADC high data 0x00 0x9C PDATAL R Proximity ADC low data 0x00 0x9D PDATAH R Proximity ADC high data 0x00 0x9E REVID2 R Revision ID two 0x07 0x9F CFG2 R/W Configuration two 0x00 0xA0 SOFTRST R/W Soft reset 0x00 0xAB CFG3 R/W Configuration three 0x04 0xAC CFG4 R/W Configuration four (must be set to 0x3D) 0x3F 0xAE CFG6 R/W Configuration six 0x3F 0xC0 POFFSETL R/W Proximity offset low data 0x00 0xC1 POFFSETH R/W Proximity offset high data 0x00 0xD7 CALIB R/W Proximity offset calibration 0x00 0xD9 CALIBCFG R/W Proximity offset calibration control 0x50 0xDC CALIBSTAT R Proximity offset calibration status 0x00 0xDD INTENAB R/W Interrupt enables 0x00 0xE6 FAC_L R Factory data low (lot code data) 0x00 to 0xFF 0xE7 FAC_H R Factory data high (lot code data) 0x00 to 0xFF 0xF2 TEST3 R/W Test three (must be set to 0xC4) 0x44 Address Register Name R/W Register Function Reset Value
Page 18 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description Enable Register (Address 0x80) Figure 21: Enable Register Before activating AEN or PEN, preset each applicable operating mode registers and bits. Addr:0x80 Enable Bit Bit Name Default Access Bit Description 7:4 Reserved 0 RW Reserved. Must be set to default value. 3 WEN 0 RW This bit activates the wait feature. Active high. 2 PEN 0 RW This bit activates the proximity detection. Active high. 1 AEN 0 RW This bit actives the ALS function. Active high. 0P O N 0 R W This field activates the internal oscillator and ADC channels. Active high.
Page 20 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description WTIME Register (Address 0x83) Figure 24: WTIME Register The wait timer is implemented using a down counter. Wait time = Increment x 2.78ms . If WLONG is enabled then, Wait time = Increment x 2.78ms x 12. Addr:0x83 WTIME Bit Bit Name Default Access Bit Description 7:0 WTIME 0x00 RW Value that specifies the wait time between ALS and proximity cycles in 2.78ms increments Value Increments Wait Time 0x00 1 2.78ms (33.4ms) 0x01 2 5.56ms (66.7ms) 0x11 18 50.0ms (600ms) 0x23 36 100ms (1.20s) 0x3F 64 178ms (2.14s) 0xFF 256 712ms (8.54s)
Datasheet, Public Page 25 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Register Description PERS Register (Address 0x8C) Figure 33: PERS Register The frequency of consecutive proximity channel results outside of threshold limits are counted; this count value is compared against the PPERS value. If the counter is equal to the PPERS value an interrupt is asserted . Any time a pr oximity channel result is inside the threshold values the counter is cleared. Addr: 0x8C PERS Bit Bit Name Default Access Bit Description 7:4 PPERS 0 (0000) RW This register sets the proximity persistence filter. Value Interrupt 0 (0000) Every proximity cycle 1 (0001) Any value outside proximity thresholds 2 (0010) 2 consecutive proximity values out of range 3 (0011) 3 consecutive proximity values out of range …… . 15 (1111) 15 consecutive pro ximity values out of range 3:0 APERS 0 (0000) RW This register sets the ALS persistence filter. 0 (0000) Every ALS cycle 1 (0001) Any value outside ALS thresholds 2 (0010) 2 consecutive ALS values out of range 3 (0011) 3 consecutive ALS values out of range 4 (0100) 5 consecutive ALS values out of range 5 (0101) 10 consecutive ALS values out of range 6 (0110) 15 consecutive ALS values out of range 7 (0111) 20 consecutive ALS values out of range 13 (1101) 50 consecutive ALS values out of range 14 (1110) 55 consecutive ALS values out of range 15 (1111) 60 consecutive ALS values out of range
Page 26 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description The frequency of consecutive Clear (C) channel results outside of threshold limits are counted; this count value is compared against the APERS value. If the counter is equal to the APERS setting an interrupt is asserted. Any time a Clear (C) channel result is inside the threshold values the counter is cleared. CFG0 Register (Address 0x8D) Figure 34: CFG0 Register PCFG0 Register (Address 0x8E) Figure 35: PCFG0 Register Addr: 0x8D CFG0 Bit Bit Name Default Access Bit Description 7:3 Reserved 01000 RW Reserved. Must be set to default value. 2W L O N G 0 R W When WLONG (Wait Long) is asserted the wait period as set by WTIME is increased by a factor of 12. 1 Reserved 0 RW Reserved. Must be set to default value.
0 PPULSE_
LEN_16x 0R W When PPULSE_LEN_16X is asserted, the proximity pulse length is extended by a factor of 16. See the PPULSE_LEN bit description in the PCFG0 register.Addr: 0x8E PCFG0 Bit Bit Name Default Access Bit Description 7:6 PPULSE_LEN 1 (01) RW Proximity pulse length. The pulse length can be extended by a factor of 16x with the assertion of the PPULSE_LEN_16x bit in CFG0. Value Pulse Length 0 (00) 4μs / 64μs 1 (01) 8μs / 128μs 2 (10) 16μs / 256μs 3 (11) 32μs / 512μs
Datasheet, Public Page 27 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Register Description The PPULSE_LEN field sets the length (width) of all IR VCSEL pulses within the proximity cycle. Longer pulses result in increased proximity range and typically result in less electrical noise generated in the analog front end. If the PPULSE_LEN_ 16x bit in CFG0 is asserted, then the pulse length is extended by a factor of 16 times. The PPULSE field sets the maximum number of IR VCSEL pulses that may occur in a proximity cycle. The proximity engine will automatically continue to add IR VCSEL pulses, up to the value set in PPULSE or if a near-s aturation condition occurs. The dynamic range of the sensor is automatically adjusted to detect distant targets as well as prevent saturation from close targets. This operation also reduces power consumption because proximity integration period is automatically shortened when a target is either too close or far from the sensor. If Automatic Pulse Control (APC) is disabled by setting bit 6 in CFG6 to 1, then PPULSE always determines the number of proximity to be transmitted. 5:0 PPLUSE 15 (001111) RW Maximum number of pulses in a single proximity cycle. Value Maximum Number of Pulses 0 (000000) 1 1 (000001) 2 2 (000010) 3 63 (111111) 64 Addr: 0x8E PCFG0 Bit Bit Name Default Access Bit Description
Page 28 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description PCFG1 Register (Address 0x8F) Figure 36: PCFG1 Register Addr: 0x8F PCFG1 Bit Bit Name Default Access Bit Description 7:6 PGAIN 2 (10) RW This field sets the gain of the proximity IR sensor. Value Gain 0 (00) 1x 1 (01) 2x 2 (10) 4x 3 (11) 8x 5:4 Reserved 00 RW Reserved. Must be set to default value. 3:0 PLDRIVE 0 (0000) RW This field sets the drive strength of the IR VCSEL current. Values are approximate; actual current through VCSEL is factory trimmed to normalize IR intensity. Note: Bit 5 in CFG1 must be set to a 1 or the VCSEL currents will be 2x the nominal values. Value VCSEL Current 0 (0000) 2mA 1 (0001) 4mA 2 (0010) 6mA 3 (0011) 8mA 4 (0100) 10mA 5 (0101) 12mA 6 (0110) 14mA 7 (0111) 17mA 8 (1000) 19mA All other values Reserved
Page 30 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description ID Register (Address 0x92) Figure 39: ID Register Status Register (Address 0x93) Figure 40: Status Register All flags in this register can be cleared by setting the bit high. Alternatively, if the INT_READ_CLE AR in the CFG3 register bit is set, then simply reading this register automatically clears all eight flags. Addr: 0x92 ID Bit Bit Name Default Access Bit Description 7:2 ID 000100 RO Device type identification. 1:0 Reserved 00 RO Reserved Addr: 0x93 Status Register Bit Bit Name Default Access Bit Description
7 ASAT 0 R, SC Analog saturation flag signals that the ALS/Color results
may be unreliable due to saturation of the AFE.
6 PSAT 0 R, SC
Proximity saturation flag indicates that an ambient- or reflective-saturation event occurred during a previous proximity cycle. 5P I N T 0 R , S C Proximity interrupt flag indicates that proximity results have exceeded thresholds and persistence settings. 4A I N T 0 R , S C ALS interrupt flag indicates that ALS/Color results (clear channel) have exceeded thresholds and persistence settings. 3C I N T 0 R , S C Calibration interrupt flag indicates that calibration has completed. 2Z I N T 0 R , S C Zero detection interrupt flag indicates that a zero value in PDATA has caused the proximity offset to be decremented (if AUTO_OFFSET_ADJ = 1).
1 PSAT_REFLECTIVE 0 R, SC
The reflective proximity saturation interrupt flag signals that the AFE has saturated during the IR VCSEL active portion of proximity integration.
0 PSAT_AMBIENT 0 R, SC
The ambient proximity saturation interrupt flag signals that the AFE has saturated during the IR VCSEL inactive portion of proximity integration.
Datasheet, Public Page 35 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Register Description CFG3 Register (Address 0xAB) Figure 54: CFG3 Register The SAI bit sets the device operational mode following the completion of an ALS or proximity cycle. If AINT and AIEN are both set or if PINT and PIEN ar e both set, causing an interrupt on the INT pin, and the SAI bit is set, then the oscillator will deactivate. The device will appear as if PON = 0, however, PON will read as 1. The device can only be reactivated (oscillator enabled) by clearing the interrupts in the STATUS register. CFG4 Register (Address 0xAC) Figure 55: CFG4 Register Addr: 0xAB CFG3 Bit Bit Name Default Access Bit Description
7 INT_READ_CLEAR 0 RW If set, then all flag bits in the STATUS register will be
reset whenever the STATUS register is read over I²C. 6:5 Reserved 0 RW Reserved. Must be set to default value. 4S A I 0 R W The Sleep After Interrupt bit is used to place the device into a low power mode upon an interrupt pin assertion. PON SAI INT Oscillator 0X X O F F
10 X O N
3:0 Reserved 0100 RW Reserved. Mus t be set to default value. Addr: 0xAC CFG4 Bit Bit Name Default Access Bit Description 7:0 Reserved 0x3F RW Reserved. Must be set to 0x3D.
Page 36 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description CFG6 Register (Address 0xAE) Figure 56: CFG6 Register POFFSETL Register (Address 0xC0) Figure 57: POFFSETL Register POFFSETH Register (Address 0xC1) Figure 58: POFFSETH Register Typically, optical and/or electrical crosstalk negatively influence proximity operation and results. The POFFSETL/POFFSETH registers provide a mechanism to remove system crosstalk from the proximity data. POFFSETL and POFFSETH contains the magnitud e and sign of a value which adjusts PDATA is generated in the AFE. An offset value in the range of ± 255 is possible. Addr: 0xAE CFG6 Bit Bit Name Default Access Bit Description 7 Reserved 0 RW Reserved. Must be set to default value.
6 A P C D i s a b l e 0 R W
Proximity automatic pulse control (APC) disable. 0 = APC enabled 1 = APC disabled 5:0 Reserved 111111 RW Reserved. Must be set to default value.Addr: 0xC0 POFFSETL Bit Bit Name Default Access Bit Description 7:0 POFFSETL 0x00 RW This register contains the magnitude portion of proximity offset adjust value. Addr: 0xC1 POFFSETH Bit Bit Name Default Access Bit Description 7:1 Reserved 0 RW Reserved. Must be set to default value. 0P O F F S E T H 0 R W This register contains the sign portion of proximity offset adjust value.
Datasheet, Public Page 37 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Register Description CALIB Register (Address 0xD7) Figure 59: CALIB Register Proximity response in systems with electrical and optical crosstalk may be improved by using the calibration feature. Optical crosstalk is caused when the photodiode receives a portion of the VCSEL IR which wa s unintentionally reflected by a surface other than the target. Electrical offset is caused by electrical disturbance in the sensor AFE, and also influences the proximity result. The calibratio n routine adjusts the value in POFFSETL/H until the proximity resu lt is as close to the binary search target as possible. Optical and electrical calibration function identically, except that during an electrical calibration the proximity photodiode is disconnected from the AFE. An electrical calibration can be initiated anytime by setting the ELECTRICAL_CALIBRATION and START_OFFSET_CAL bits. To perform an optical (and electrical) calibration do not set the ELECTRICAL_CALIBRATION bi t when setting the START_ OFFSET_CALIB. The CINT flag will assert after calibration has finished. Upon completion proximity offset registers are automatically loaded with calibration result. Addr: 0xD7 CALIB Bit Bit Name Default Access Bit Description 7:6 Reserved 0 RW Reserved. Must be set to default value.
5 ELECTRICAL_
Selects proximity calibration type. 0 = Electrical and optical crosstalk. 1 = Electrical crosstalk only. 4:1 Reserved 0 RW Reserved. Must be set to default value.
0 START_OFFSET_
CAL 0 RW Set to 1 to start a calibration sequence.
Page 38 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Register Description CALIBCFG Register (Address 0xD9) Figure 60: CALIBCFG Register Addr: 0xD9 CALIBCFG Bit Bit Name Default Access Bit Description 7:5 BINSRCH_ TARGET (010) RW Proximity offset calibration result target. Value PDATA Target 0 (000) 3 1 (001) 7 2 (010) 15 3 (011) 31 4 (100) 63 5 (101) 127 6 (110) 255 7 (111) 511 4 Reserved 1 RW Reserved. Must be set to default value.
3 AUTO_
OFFSET_ADJ 0R W If set, this bit causes the value in POFFSETL register to be decremented if PDATA ever becomes zero. 2:0 PROX_ AVG (000) RW PROX_AVG defines the number of ADC samples collected and averaged during a cycle which become the proximity result. Value Sample Size 0 (000) Disable 1 (001) 2 2 (010) 4 3 (011) 8 4 (100) 16 5 (101) 32 6 (110) 64 7 (111) 128
Datasheet, Public Page 39 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Register Description The binary search target field is used by the calibration feature to set the baseline value for PDATA when no target is present. For example, calibration of a device in open air, with no target, and BINSEARCH_TARGET setting of 2 causes the PDATA value will be approximately 15 counts. This feature is useful because it forces PDATA result to always be above zero. The PROX_AVG field sets the number of ADC samples that are averaged to calculate the PDATA result. CALIBSTAT Register (Address 0xDC) Figure 61: CALIBSTA T Register INTENAB Register (Address 0xDD) Figure 62: INTENAB Register Addr: 0xDC CALIBSTAT Bit Bit Name Default Access Bit Description 7:3 Reserved 0 RW Reserved. Must be set to default value.
2 OFFSET_
Bit is set when the proximity offset has been automatically decremented if AUTO_OFFSET_ ADJ = 1 (see CALIBCFG register). This bit can be cleared by writing 1 to it or setting AUTO_ OFFSET_ADJ to 0. 1 Reserved 0 RW Reserved. Must be set to default value.
0 CALIB_FINISHED 0 RW
This flag indicates that calibration has finished. This bit is a copy of the CINT bit in the STATUS register. It will be cleared when the CINT bit is cleared. Addr: 0xDD INTENAB Bit Bit Name Default Access Bit Description
7 ASIEN 0 RW ALS Saturation Interrupt Enable
6 PSIEN 0 RW Proximity Saturation Interrupt Enable
5 PIEN 0 RW Proximity Interrupt Enable
4 AIEN 0 RW ALS/Color Interrupt Enable
3 CIEN 0 RW Calibration Interrupt Enable
2 ZIEN 0 RW Zero Detect Interrupt Enable
1:0 Reserved 0 RW Reserved. Must be set to default value.
Datasheet, Public Page 41 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Application Information Figure 66: Schematic Note(s): 1. The bulk capacitor (C3) can affect the stability of a regula ted supply output and should be chosen with the regulator charac teristics in mind. 2. Place the 4.7μF VDD (C1) and 10μF LEDA (C2) capacitors within 5mm of the module. 3. The value of the I²C pull up resistors RPU should be based on the 1.8V bus voltage, system bus speed and trace capacitance. 4. VSS and PGND should be connected to the same so lid ground plane as close to the device as possible. 5. To improve device ESD protection, it is recommended to connect NC to ground.
Application Information
Page 42 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Application Information Figure 67: TMD3702VC Recommended Circuit Layout Note(s): 1. The dominant factor governing device performance is the comp onent placement, not necessarily component value. The placement of the decoupling capacitor, C2, is the most critical. Place the component on the same side of PCB as device as shown in the fi gure above. Make connection as close as possible to minimize series inductance and resi stance. This is critical.
Datasheet, Public Page 43 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Package Drawings & Markings Figure 68: Package Drawing Note(s): 1. All linear dimensions are in millimeters. 2. Contact finish is Au. 3. This package contains no lead (Pb). 4. This drawing is subject to change without notice. Package Drawings & Markings GreenRoHS 3$57&/ 72$/6&/ 3$57&/ 72352;&/ 3$57&/ 729&6(/&/ $/6',2'( 352;,0,7<',2'( $/6',2'( 352;,0,7<',2'(&/ 0 & $% 0 & $% 9'' ,17 3*1' 966 6&/ /('$ 6'$
Page 44 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 69: Recommended PCB Pad Layout Note(s): 1. All dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. This drawing is subject to change without notice. PCB Pad Layout
Datasheet, Public Page 45 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Tape & Reel Information Figure 70: Tape & Reel Information Note(s): 1. All linear dimensions are in millimeters. Di mension tolerance is ±0.1 0mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001. 4. Each reel is 330mm in diameter and contains 10000 parts. 5. ams OSRAM packaging tape and reel conform to th e requirements of EIA Standard 481-B. 6. In accordance with EIA standard device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Tape & Reel Information
Page 46 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Soldering & Storage Information The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 71: Solder Reflow Profile Note(s): 1. Tolerance for peak profile temperature (T P) is defined as a supplier minimum and a user maximum. Profile Feature Preheat/ Soak Sn-Pb Eutectic Assembly Pb-Free Assembly Temperature Min ( Tsmin) 100 °C 150 °C Temperature Max ( Tsmax) 150 °C 200 °C Time (ts) from (Tsmin to Tsmax) 60-120 seconds 60-120 seconds Ramp-up rate (TL to TP) 3 °C/second max. 3 °C/second max. Liquidous temperature (TL) Time (tL) maintained above TL 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body temperature (TP) For users TP must not exceed the classification temp. of 235 °C For suppliers TP must equal or exceed the classification temp of 235 °C For users TP must not exceed the classification temp. of 260 °C For suppliers TP must equal or exceed the classification temp of 260 °C Time (tP) (1) within 5 °C of the specified classification temperature (Tc) 20 (1)seconds 30 (1)seconds Ramp-down rate (TP to TL) 6 °C/second max. 6 °C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Soldering & Storage Information
Datasheet, Public Page 47 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Soldering & Storage Information Figure 72: Solder Reflow Profile Graph Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed mois ture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with sili ca gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 24 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 24 months
- Ambient Temperature: < 40 °C
- Relative Humidity: < 90% Rebaking of the devices will be required if the devices exceed the 24 months shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Not to Scale – For Reference Only TP Temperature (°C) Time (seconds) tL TL TC - 5°C tP Tsmin Tsmax Preheat Area Max Ramp Up Rate = 3°C/s Max Ramp Down Rate = 6°C/s
Page 48 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Soldering & Storage Information Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: < 30°C
- Relative Humidity: < 60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50 °C for 12 hours.
Datasheet, Public Page 49 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Laser Eye Safety The TMD3702VC is designed to meet the Class 1 laser safety limits including single faults in compliance with IEC/EN 60825-1:2014. In an end applic ation system environment, the system may need to be tested to ensure it remains compliant. The system must not include any additional lens to concentrate the laser light or parameters set outside of the recommended operating conditions. Use ou tside of the recommended condition or any physical modification to the module during development could result in hazardous levels of radiation exposure. Laser Eye Safety
Page 50 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Ordering & Contact Information Figure 73:
Ordering Information
Buy our products or get free samples online at: www.ams.com/Products Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/Contact Headquarters ams-OSRAM AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code I²C Bus I²C Address Delivery Form Delivery Quantity TMD37024VC 1.8V 0x49 Tape & Reel (13”) 10000pcs/reel TMD37024VCM 1.8V 0x49 Tape & Reel (7”) 1000pcs/reel Ordering & Contact Information
Datasheet, Public Page 51 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
Page 52 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Copyrights & Disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provis ions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by desc ription regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications re quiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but no t limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. Copyrights & Disclaimer
Datasheet, Public Page 53 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
Page 54 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-04 (2020-Apr-07) to current revision 2-00 (2023-Mar-14) Page Updated “Shelf Life” to 24 months 47 Revision Information
Datasheet, Public Page 55 [v2-00] 2023-Mar-14 Document Feedback TMD3702VC − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignment
4A b s o l u t e M a x i m u m R a t i n g s
5 Electrical Characteristics
9 Typical Operating Characteristics
13 Detailed Description
13 Proximity
13 Color and Ambient Light Sense
13 I²C Characteristics
14 I²C Write Transaction
14 I²C Read Transaction
16 Register Description
18 Enable Register (Address 0x80)
19 ATIME Register (Address 0x81)
19 PRATE Register (Address 0x82)
20 WTIME Register (Address 0x83)
21 AILTL Register (Address 0x84)
21 AILTH Register (Address 0x85)
22 AIHTL Register (Address 0x86)
22 AIHTH Register (Address 0x87)
23 PILTL Register (Address 0x88)
23 PILTH Register (Address 0x89)
24 PIHTL Register (Address 0x8A)
24 PIHTH Register (Address 0x8B)
25 PERS Register (Address 0x8C)
26 CFG0 Register (Address 0x8D)
26 PCFG0 Register (Address 0x8E)
28 PCFG1 Register (Address 0x8F)
29 CFG1 Register (Address 0x90)
29 REVID Register (Address 0x91)
30 ID Register (Address 0x92)
30 Status Register (Address 0x93)
31 CDATAL Register (Address 0x94)
31 CDATAH Register (Address 0x95)
31 RDATAL Register (Address 0x96)
31 RDATAH Register (Address 0x97)
32 GDATAL Register (Address 0x98)
32 GDATAH Register (Address 0x99)
32 BDATAL Register (Address 0x9A)
32 BDATAH Register (Address 0x9B)
33 PDATAL Register (Address 0x9C)
33 PDATAH Register (Address 0x9D)
34 REVID2 Register (Address 0x9E)
34 CFG2 Register (Address 0x9F)
34 SOFTRST Register (Address 0xA0)
35 CFG3 Register (Address 0xAB)
35 CFG4 Register (Address 0xAC)
36 CFG6 Register (Address 0xAE)
Page 56 Datasheet, Public Document Feedback [v2-00] 2023-Mar-14 TMD3702VC − Content Guide