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[v1-03] 2020-Aug-25 Document Feedback TMD2635 Miniature Proximity Sensor Module The TMD2635 features advanced proximity measurement in a tiny (1.0mm x 2.0mm) and thin (0 .5mm) optical land grid array module that incorporates a 940nm IR VCSEL and is factory calibrated for IR proximity response. The proximity detection feature provides object detection (e.g. close proximity) by photodiode detection of reflec ted IR energy sourced by the integrated VCSEL emitter. Detect/release events can be interrupt driven, and occur when proximity result crosses upper and/or lower threshold settings. The proximity engine features a wide range offset adjustment to compensate for unwanted IR energy reflection at the sensor. Proximity results are further improved by automatic ambient light subtraction. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TMD2635 Proximity Sensor Module are listed below: Figure 1: Added Value of Using TMD2635 Benefits Features
- Optimized for small wearable devices • Tiny 1.0mm x 2.0mm x 0.5mm module
- Reduced power consumption
- 1.8V power supply with 1.8V I²C bus
- Sleep mode (0.7μA) with fast wakeup
- VCSEL IR emitter
- Enables superior proximity detection
- Integrated factory calibrated 940nm IR VCSEL
- Crosstalk and ambient light cancellation
- Wide configuration range
- Industrial design flexibility • Dual photodiode architecture
- Offset emitter/detector package design General Description
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − General Description
Applications
The TMD2635 applications for wearable products such as true-wireless stereo earbuds, glasses, and watches include:
- Power control (automatic power up/down based on user insertion/removal)
- Volume/mode control user detection (up/down/mute based on user touch/tap) Block Diagram The functional blocks of this device are shown below: Figure 2: Functional Blocks of TMD2635 SCL SDA INT VDD IR Filter Wait Control Proximity Control Prox Data Prox Thresholds Lower Upper Prox ADC I2C Interface Interrupt Open Drain Output Open Drain Current Sink GND 940nm IR VCSEL VDD3 Proximity Integration Analog Mux Near Photo- diode Far Photo- diode
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Pin Assignment Device pinout is described below. Figure 3: Pin Diagram of TMD2635 (Top View) Figure 4: Pin Description Note(s): 1. When the SDA and SCL signals are swapped, the device uses a different I²C address. See the I²C Characteristics section for more details. Pin Number Pin Name Description 1I N T Interrupt. Open drain output (active low). If INT is not used, tie to GND for enhanced ESD protection. 2V D D Supply voltage for sensor (1.8V). To enable the device to recover from a high voltage system ESD strike, it is recommended to connect VDD to a host GPIO pin for independent power control. 3 GND Ground. All voltages are referenced to GND. VDD3 Supply voltage for IR emitter (3.0/3.3V)
5 SCL (1) I²C serial clock input terminal
6 SDA (1) I²C serial data I/O terminal
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Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Note(s): 1. The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermet ic Solid State Surface Mount Devices.” Symbol Parameter Min Max Units Comments VDD Supply voltage to GND -0.3 2.0 V VDD3 IR emitter voltage to GND -0.3 3.6 V VIO Digital I/O terminal voltage -0.3 3.6 V IIO Digital output terminal voltage -1 20 mA ISCR Input current (latch up immunity) ±100 mA Class II JEDEC JESD78E ESDHBM HBM Electrostatic discharge ±20 00 V JEDEC/ ESDA JS-001-2017 ESDCDM CDM Electrostatic discharge ±500 V JEDEC JS-002-2014 TSTRG Storage temperature range -40 85 °C RHNC Relative humidity (non- condensing) 58 5 % PDISS Power dissipation 50 mW Average power dissipation over a 1 second period Absolute Maximum Ratings
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Electrical Characteristics Note(s): 1. Values are shown at the VDD pin and do not include current through the IR VCSEL . 2. Active state occurs when PON = 1 and the device is actively in tegrating. This time is determined by the number of pulses (PP ULSE) and the pulse length (PULSE_LEN) according to the formula: (7 x PULSE_LEN) + PPULSE x (2 x PULSE_LEN + 22μs) + 78.75μs. 3. Idle state occurs when PON = 1 and the device is not in the active state. 4. Sleep state occurs when PON = 0 and I²C bus is idle. If slee p state has been entered as the result of operational flow, SAI = 1, PON will remain high. 5. Digital pins: SDA, SCL, INT are tolera nt to a communication voltage up to 3.4V. Figure 8: Near Proximity Photodiode Optical Characteristics, VDD = 1.8V, VDD =3.0V, T A = 25ºC (unless otherwise noted) Note(s): 1. Representative result by characterization. 2. 3 sigma (σ) variation. 3. Response with no target varies with power supply characteristics and system noise. TWakeup Time for device to wakeup from the sleep state and enter the active state if both PON and PEN are set to one at the same time. 100 μs TActive Time from power-on to ready to receive I²C commands 1.5 ms Parameter Conditions Min Typ Max Unit Response: Absolute (1) PGAIN = 1x PLDRIVE = 7mA PPULSE = 5 pulses PPULSE_LEN = 12μs APC = disabled TEST9 = 0x07 BINSRCH_TARGET = 31 Post Calibration Target material: 18% reflective surface No glass above module Target Size: 100mm x 100mm Target Distance: 10mm 292 389 486 Counts Part to Part Variation (1)(2) Same as Response: absolute ±25 % Noise (1)(2) Same as Response: absolute ±2 % Response: No target (1)(3) Same as Response: absolute except no target above the module 19 30 41 Counts Symbol Parameter Conditions Min Typ Max Units
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Electrical Characteristics Figure 9: Far Proximity Photodiode Optical Charac teristics, VDD = 1.8V, VDD3 = 3.0V, T A = 25°C (unless otherwise noted) Note(s): 1. Representative result by characterization. 2. 3 sigma (σ) variation. 3. Response with no target varies with power supply characteristics and system noise. Parameter Conditions Min Typ Max Unit Response: Absolute (1) PGAIN = 1x PLDRIVE = 7mA PPULSE = 5 pulses PPULSE_LEN = 12μs APC = disabled TEST9 = 0x07 BINSRCH_TARGET = 31 Post Calibration Target material: 18% reflective surface No glass above module Target Size: 100mm x 100mm Target Distance: 10mm 250 333 416 Counts Part to Part variation (1)(2) Same as Response: absolute ±25 % Noise (1)(2) Same as Response: absolute ±2 % Response: No target (1)(3) Same as Response: absolute except no target above the module 19 30 41 Counts
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Timing Characteristics Figure 10: I²C Timing Diagrams For TMD2635 Timing Characteristics
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Detailed Description Proximity Operation By varying gain, VCSEL drive current, number of VCSEL pulses and VCSEL pulse duration the proximity detection range can be adjusted. Proximity Proximity results are affected by three fundamental factors: the integrated IR VCSEL emission, IR reception, and environmental factors, including target distance and surface reflectivity. The IR reception signal path begins with IR detection from a photodiode and ends with the 14 -bit proximity result in PDATA register. Signal from the photodiode is amplified, and offset adjusted to optimize performance. Offset correction or cross-talk compensation is accomplished by adjustment to the POFFSET register. The analog circuitry of the device applies the offset value as a subtraction to the signal accumulation; therefore a positive offset value has the effect of decreasing the results. I²C Characteristics The device uses I²C serial communication protocol for communication. The device support s 7-bit chip addressing and both standard and fast clock frequency modes with a chip address of 0x39. Read and write transactions comply with the standard set by Ph ilips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive read transactions, the future/repeated I²C read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address + 1. Alternate I²C Address Option If the SDA and SCL pins are swa pped as shown below, the device will switch to an alternate I²C address. This allows two devices to reside on the same bus. Afte r power is applied to the devices, a single dummy I²C access (read or write with valid I²C stop) to any address or device on the same bus is required to initialize the devices to their respective I²C addresses. The devices will generate an NOT-ACKNOWLEDGE (NACK) during this initial dummy access. Detailed Description
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Detailed Description the final byte the master places an ACK on the bus (9 th clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP . The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at: http://www.i2c-bus.org/references/ Simplified State Diagram Figure 13: Simplified State Diagram SLEEP (PON = 0) Hardware Averaging Loop 2 to 128 Times IDLE (PON = 1) ACTIVE Complete PRATE PROX_AVG (if enabled) PWTIME (if enabled) Update PDATA SAI (if enabled) Wait Time If moving average (PMAVG) is enabled, PDATA = 0 until filter fills with 2/4/8 loops PEN = 1 Y Y Idle Sleep Active IDD Supply Current
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Register Description Figure 14: Register Overview Address Register Name R/W Register Function Reset Value 0x80 ENABLE R/W Enables states and interrupts 0x00 0x82 PRATE R/W Proximity time 0x1F 0x88 PILTL R/W Proximity interrupt low threshold low byte 0x00 0x89 PILTH R/W Proximity interrupt low threshold high byte 0x00 0x8A PIHTL R/W Proximity interrupt high threshold low byte 0x00 0x8B PIHTH R/W Proximity interrupt high threshold high byte 0x00 0x8C PERS R/W Proximity interrupt persistence filters 0x00 0x8D CFG0 R/W Configuration zero 0x40 0x8E PCFG0 R/W Proximity configuration zero 0x8F 0x8F PCFG1 R/W Proximity configuration one 0x60 0x91 REVID R Revision ID 0x10 0x92 ID R Device ID 0x44 0x9B STATUS R, SC Device status 0x00 0x9C PDATAL R Proximity ADC low data 0x00 0x9D PDATAH R Proximity ADC high data 0x00 0xA6 REVID2 R Revision ID two 0x01 or 0x0E 0xA8 SOFTRST R/W Soft reset 0x00 0xA9 PWTIME R/W Proximity wait time 0x00 0xAA CFG8 R/W Configuration eight 0x02 0xAB CFG3 R/W Configuration three 0x04 0xAE CFG6 R/W Configuration six 0x3F 0xB3 PFILTER R/W Proximity filter 0x00 0xC0 POFFSETL R/W Proximity offset low data 0x00 0xC1 POFFSETH R/W Proximity offset high data 0x00 0xD7 CALIB R/W Proximity offset calibration 0x00 0xD9 CALIBCFG R/W Proximity offs et calibration control 0x50 0xDC CALIBSTAT R Proximity offset calibration status 0x00 Register Description
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Register Description PCFG0 Register (0x8E) Figure 23: PCFG0 Register The PPULSE field sets the maximum number of IR VCSEL pulses that may occur in a proximity cycle. The proximity engine will automatically continue to add IR VCSEL pulses, up to the value set in PPULSE or if a near-s aturation condition occurs if Automatic Pulse Control (APC) is enabled. The dynamic range of the sensor is automatically ad justed to detect distant targets as well as prevent saturation from close targets. This operation also reduces power consumption because proximity integration period is automatically shortened when a target is close to the sensor. If Automatic Pulse Control (APC) is disabled by setting bit 6 in CFG6 to 1, then PPULSE always determines the number of proximity pulses to be transmitted. Addr : 0x8E PCFG0 Bit Bit Name Default Access Bit Description 7:6 PGAIN 2 (10) RW This field sets the gain of the proximity IR sensor. Value Gain 0 (00) 1x 1 (01) 2x 2 (10) 4x 3 (11) 8x 5:0 PPULSE 15 (001111) RW Maximum number of pulses in a single proximity cycle. Value Maximum Number of Pulses 0 (00000) 1 1 (00001) 2 2 (00010) 3 63 (11111) 64
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Register Description PCFG1 Register (0x8F) Figure 24: PCFG1 Register The PPULSE_LEN field sets the length (width) of all IR VCSEL pulses within the proximity cycle. Longer pulses result in increased proximity range and typically result in less electrical noise generated in the analog front end. Addr : 0x8F PCFG1 Bit Bit Name Default Access Bit Description 7:5 PPULSE_ LEN (011) RW Proximity pulse length. Value Pulse Length 0 (000) 1μs 1 (001) 2μs 2 (010) 4μs 3 (011) 8μs 4 (100) 12μs 5 (101) 16μs 6 (110) 24μs 7 (111) 32μs 4 Reserved 0 RW Reserved. Must be set to default value 3:0 PLDRIVE 0 (0000) RW This field sets the drive strength of the IR VCSEL current. Values are approximate; actual current through VCSEL is factory trimmed to normalize IR intensity. For lowest part to part variation, 7mA is recommended. Value VCSEL Current 5 (0101) 7mA 6 (0110) 8mA 7 (0111) 9mA 8 (1000) 10mA All other values Reserved
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Register Description STATUS Register (0x9B) Figure 27: STATUS Register All flags in this register can be cleared by setting the bit high. Alternatively, if the INT_READ_CLE AR in the CFG3 register bit is set, then simply reading this register automatically clears all eight flags. Addr : 0x9B: STATUS Bit Bit Name Default Access Bit Description
7 PHIGH 0 R, SC Set when PINT is set and PDATA > high threshold (after
persistence). Cleared when PINT is cleared. 6P L O W 0 R , S C Set when PINT is set and PDATA < low threshold (after persistence). Cleared when PINT is cleared.
5 PSAT 0 R, SC
Proximity saturation flag indicates that an ambient or reflective-saturation event occurred during a previous proximity cycle. 4P I N T 0 R , S C Proximity interrupt flag indicates that proximity results have exceeded thresholds and persistence settings. 3C I N T 0 R , S C Calibration interrupt flag indicates that calibration has completed. 2Z I N T 0 R , S C Zero detection interrupt flag indicates that a zero value in PDATA has caused the proximity offset to be decremented (if AUTO_OFFSET_ADJ = 1).
1 PSAT_
REFLECTIVE 0R , S C The Reflective Proximity Saturation Interrupt flag signals that the AFE has saturated during the IR VCSEL active portion of proximity integration.
0 PSAT_
AMBIENT 0R , S C The Ambient Proximity Saturation Interrupt flag signals that the AFE has saturated during the IR VCSEL inactive portion of proximity integration.
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Register Description The wait timer is implemented using a down counter. Wait time = increment x 2.78ms. If PWLONG is enabled (bit 3 in CFG0), then wait time = increment x 2.78ms x 12 CFG8 Register (0xAA) Figure 33: CFG8 Register Addr : 0xAA CFG8 Bit Bit Name Default Access Bit Description 7:2 Reserved 000000 RW Reserved. Must be set to default value. 1:0 PDSELECT 10 RW Proximity photodiode selection Value Photodiode Selected
00 No photodiode
01 Far photodiode
10 Near photodiode (default)
11 Both photodiodes
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Register Description CFG3 Register (0xAB) Figure 34: CFG3 Register The SAI bit sets the device operational mode following the completion of a proximity cycle. If PINT and PIEN are both set, causing an interrupt on the INT pi n, and the SAI bit is set, then the oscillator will deactivate. The device will appear as if PON = 0, however, PON will read as 1. The device can only be reactivated (oscillator enabled) by clearing the interrupts in the STATUS register. CFG6 Register (0xAE) Figure 35: CFG6 Register Addr : 0xAB CFG3 Bit Bit Name Default Access Bit Description
7 INT_READ_
CLEAR 0R W If set, then flag bits in the STATUS register will be reset whenever the STATUS register is read over I²C. 6:5 Reserved 00 RW Reserved. Must be set to default value. 4S A I 0 R W The sleep after interrupt bit is used to place the device into a low power mode upon an interrupt pin assertion. PON SAI INT Oscillator 0X X O F F
10 X O N
111 O N
110 O F F
3:0 Reserved 0100 RW Reserved. Must be set to default value. Addr : 0xAE CFG6 Bit Bit Name Default Access Bit Description 7 Reserved 0 RW Reserved. Must be set to default value.
6 APC_DISABLE 0 RW
Proximity automatic pulse control (APC) disable. 0 = APC enable 1 = APC disable 5:0 Reserved 111111 RW Reserved. Must be set to default value.
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Register Description PFILTER Register (0xB3) Figure 36: PFIL TER Register The PMAVG bits select the moving average that is performed on the proximity data before it is loaded into PDATA and checked against the thresholds. The moving average uses data after proximity hardware averaging is performed (refer to the PROX_AVG bits in the CALIBCFG register). POFFSETL Register (0xC0) Figure 37: POFFSETL Register Addr : 0xB3 PFILTER Bit Bit Name Default Access Bit Description 7:2 Reserved 000000 RW Reserved. Must be set to default value. 1:0 PMAVG 00 RW Proximity moving average Value Proximity Moving Average
00 Disabled (default)
11 8 valuesAddr : 0xC0 POFFSETL Bit Bit Name Default Access Bit Description 7:0 POFFSETL 0x00 RW This register contains the magnitude portion of proximity offset adjust value.
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Register Description POFFSETH Register (0xC1) Figure 38: POFFSETH Register Typically, optical and/or electrical crosstalk negatively influence proximity operation and results. The POFFSETL/POFFSETH registers provide a mechanism to remove system crosstalk from the proximity data. POFFSETL and POFFSETH contains the magnitud e and sign of a value which adjusts PDATA is generated in the AFE. An offset value in the range of ± 255 is possible. CALIB Register (0xD7) Figure 39: CALIB Register Addr : 0xC1 POFFSETH Bit Bit Name Default Access Bit Description 7:1 Reserved 0000000 RW Reserved. Must be set to default value.
0 POFFSETH 0 RW This register contains the sign portion of proximity offset
adjust value. Addr : 0xD7 CALIB Bit Bit Name Default Access Bit Description 7C A L A V G 0 R W Enables proximity hardware averaging as selected with PROX_AVG during calibration. 0 = No hardware averaging 1 = Hardware averaging enabled 6 Reserved 0 RW Reserved. Must be set to default value.
5 ELECTRICAL_
Selects proximity calibration type. 0 = Electrical and optical crosstalk. 1 = Electrical crosstalk only. 4C A L P R A T E 0 R W Enables PRATE during calibration. Useful when averaging is enabled. 0 = PRATE ignored 1 = PRATE applied between averaging samples 3:1 Reserved 000 RW Reserved. Must be set to default value.
0 START_
OFFSET_CAL 0 RW Set to 1 to start a calibration sequence.
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Register Description Proximity response in systems with electrical and optical crosstalk may be improved by using the calibration feature. Optical crosstalk is caused when the photodiode receives a portion of the VCSEL IR which wa s unintentionally reflected by a surface other than the target. Electrical offset is caused by electrical disturbance in the sensor AFE, and also influences the proximity result. The calibratio n routine adjusts the value in POFFSETL/H until the proximity resu lt is as close to the binary search target as possible. Optical and electrical calibration function identically, except that during an electrical calibration the proximity photodiode is disconnected from the AFE. An electrical calibration can be initiated anytime by setting the ELECTRICAL_CALIBRATION and START_OFFSET_CAL bits. To perform an optical (and electrical) calibration do not set the ELECTRICAL_CALIBRATION bi t when setting the START_ OFFSET_CALIB. The CINT flag will assert after calibration has finished. Upon completion proximity offset registers are automatically loaded with calibration result. CALIBCFG Register (0xD9) Figure 40: CALIBCFG Register (0xD9) Addr : 0xD9 CALIBCFG Bit Bit Name Default Access Bit Description 7:5 BINSRCH_ TARGET (010) RW Proximity offset calibration result target Value PDATA Target 0 (000) 3 1(001) 7 2 (010) 15 3 (011) 31 4 (100) 63 5 (101) 127 6 (110) 255 7 (111) 511 4 Reserved 1 RW Reserved. Must be set to default value. AUTO_ OFFSET_ ADJ 0R W If set, this bit causes the value in POFFSETL register to be decremented if PDATA ever becomes zero.
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Register Description The binary search target field is used by the calibration feature to set the baseline value for PDATA when no target is present. For example, calibration of a device in open air, with no target, and BINSEARCH_TARGET setting of 2 causes the PDATA value will be approximately 15 counts. This feature is useful because it forces PDATA result to always be above zero. The PROX_AVG field sets the number of ADC samples that are averaged. Each ADC sample causes the programmed number of proximity pulses to be transmitted. Once all samples have been completed and the average is calculated, the proximity state machine will then pass this value either directly to PDATA or to the proximity moving average filter depending on the configuration of the PMAVG bits in the PFILTER register. 2:0 PROX_ AVG (000) RW PROX_AVG defines the number of ADC samples collected and hardware averaged during a proximity cycle. Value Sample Size 0 (000) Disable 1 (001) 2 2 (010) 4 3 (011) 8 4 (100) 16 5 (101) 32 6 (110) 64 7 (111) 128 Addr : 0xD9 CALIBCFG Bit Bit Name Default Access Bit Description
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Register Description CALIBSTAT Register (0xDC) Figure 41: CALIBSTA T Register INTENAB Register (0xDD) Figure 42: INTENAB Register The PIM (Proximity Interrupt Mode) bit selects the condition under which the PINT status bit and the corresponding interrupt (if enabled with PIEN) will be asserted. Addr : 0xDC CALIBSTAT Bit Bit Name Default Access Bit Description 7:3 Reserved 00000 RW Reserved. Must be set to default value.
2 OFFSET_
Bit is set when the proximity offset has been automatically decremented if AUTO_OFFSET_ADJ = 1 (see CALIBCFG register). This bit can be cleared by writing 1 to it or setting AUTO_OFFSET_ADJ to 0. 1 Reserved 0 RW Reserved. Must be set to default value.
0 CALIB_FINISHED 0 RW
This flag indicates that calibration has finished. This bit is a copy of the CINT bit in the STATUS register. It will be cleared when the CINT bit is cleared. Addr : 0xDD INTENAB Bit Bit Name Default Access Bit Description 7:6 Reserved 00 RW Reserved. Must be set to default value. 5P I M 0 R W Proximity Interrupt Mode 0 = Level based 1 = State based
4 PIEN 0 RW Proximity Interrupt Enable
3 PSIEN 0 RW Proximity Saturation Interrupt Enable
2 CIEN 0 RW Calibration Interrupt Enable
1 ZIEN 0 RW Zero Detect Interrupt Enable
0 Reserved 0 RW Reserved. Must be set to default value.
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Register Description TEST9 Register (0xF9) Figure 46: TEST9 Register Addr : 0xF9 TEST9 Bit Bit Name Default Access Bit Description 7:0 Reserved 0x00 R/W Reserved. Must be set to 0x07.
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Application Information Figure 47: Recommended Circuit Layout Note(s): 1. The dominant factor governing device performance is the comp onent placement, not necessarily component value. The placement of the decoupling capacitor, 2.2μF, is the most critical. Place th e component on the same side of PCB as device as shown in the figure above. Make connection as close as possible to minimize series inductance and resi stance. This is critical.
Application Information
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Application Information Figure 48: Schematic Note(s): 1. Place the C1 and C2 capacitors within 5mm of the module. 2. The value of the I²C pull up resistors RPU should be based on the 1.8V bus voltage, system bus speed and trace capacitance. 3. C1 and C2 are critical comp onents to protect the device during high voltage ESD strikes. 4. In systems subjected to high voltage ESD strikes, it is reco mmended to connect VDD to a host GPIO pin to allow the device to be independently power cycled. TMD2635 SCL SDA INT 2.2µF VDD VDD3 GND 22ȍ1.8V 3.0V RPU RPU 10Kȍ 2.2µF
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads Figure 49: Recommended PCB Pad Layout Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. This drawing is subject to change without notice. PCB Pad Layout
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Packaging Drawings Figure 50: Package Drawing Note(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are 0.05mm unless otherwise noted. 3. Contact finish is Au. 4. This package contains no lead (Pb). 5. This drawing is subject to change without notice. Packaging Drawings GreenRoHS 3$57&/ 72352; 9&6(/(0,77(5&/ 3$57&/ 72)$5352;&/ 3$57('*( 72352;&/ 9'' 6&/ 6'$ *1' 9'' ,17 '(9,&(3,1287 %277209,(: 0 & $% 0 & $%
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Tape & Reel Information Figure 51: Tape & Reel Information Note(s): 1. All linear dimensions are in millimeters. Di mension tolerance is ±0.1 0mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing A0, B0 and K0 are defined on ANSI EIA standard 481-B 2001. 4. ams packaging tape and reel conform to the requirements of EIA standard 481-B. 5. In accordance with EIA standard device pin 1 is located next to the sprocket holes in the tape. 6. This drawing is subject to change without notice. Tape & Reel Information
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Soldering & Storage Information The module has been tested an d has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 52: Solder Reflow Profile Note(s): 1. Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum. Profile Feature Preheat / Soak Sn-Pb Eutectic Assembly Pb- Free Assembly Temperature Min ( T smin) 100 °C 150 °C Temperature Max ( T smax) 150 °C 200 °C Time (ts) from (T smin to T smax) 60 - 120 seconds 60 - 120 seconds Ramp-up rate (TL to TP) 3 °C/second max. 3 °C/second max Liquidous temperature (TL) Time (tL) maintained above TL 183 °C 60 - 150 seconds 217 °C 60 - 150 seconds Peak package body temperature (TP) For users TP must not exceed the classification temp. of 235 °C. For suppliers T P must equal or exceed the classification temp of 235 °C. For users T P must not exceed the classification temp. of 260 °C. For suppliers T P must equal or exceed the classification temp of 260 °C. Time (t P) (1) within 5 °C of the specified classification temperature (Tc) 20 (1) 30 (1) Ramp-down rate (TP to TL) 6 °C/second max. 6 °C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Soldering & Storage Information
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Soldering & Storage Information Figure 53: Solder Reflow Profile Graph Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:
- Shelf Life: 12 months
- Ambient Temperature: <40°C
- Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region.
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Soldering & Storage Information Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
- Floor Life: 168 hours
- Ambient Temperature: <30°C
- Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Laser Eye Safety The TMD2635 is designed to meet the Class 1 laser safety limits including single faults in compliance with IEC/EN 60825-1:2014. In an end application system environment, the system may need to be tested to ensure it remains compliant. The system must not include any additional lens to concentrate the laser light or parameters set outsid e of the recommended operating conditions or any physical modification to the module during development could result in hazardous levels of radiation exposure. Laser Eye Safety
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Ordering & Contact Information Figure 54:
Ordering Information
Buy our products or get free samples online at: www.ams.com/Products Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/Contact Headquarters ams AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code I²C Bus I²C Address Delivery Form Delivery Quantity TMD26353 1.8V 0x39 Tape and Reel (13”) 10000 pcs/reel TMD26353M 1.8V 0x39 Tape and Reel (7”) 1000 pcs/reel Ordering & Contact Information
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applic ations requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-02 (2020-Jul-15) to current revision 1-03 (2020-Aug-25) Page Updated Figure 24 18 Revision Information
Document Feedback [v1-03] 2020-Aug-25 TMD2635 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignment
4A b s o l u t e M a x i m u m R a t i n g s
5 Electrical Characteristics
8 Timing Characteristics
9 Detailed Description
9P r o x i m i t y O p e r a t i o n 9P r o x i m i t y
9 I²C Characteristics
9 Alternate I²C Address Option
10 I²C Write Transaction
10 I²C Read Transaction
11 Simplified State Diagram
12 Register Description
13 ENABLE Register (0x80)
13 PRATE Register (0x82)
14 PILTL Register (0x88)
14 PILTH Register (0x89)
15 PIHTL Register (0x8A)
15 PIHTH Register (0x8B)
16 PERS Register (0x8C)
16 CFG0 Register (0x8D)
17 PCFG0 Register (0x8E)
18 PCFG1 Register (0x8F)
19 REVID Register (0x91)
19 ID Register (0x92)
20 STATUS Register (0x9B)
21 PDATAL Register (0x9C)
21 PDATAH Register (0x9D)
22 REVID2 Register (0xA6)
22 SOFTRST Register (0xA8)
22 PWTIME Register (0xA9)
23 CFG8 Register (0xAA)
24 CFG3 Register (0xAB)
24 CFG6 Register (0xAE)
25 PFILTER Register (0xB3)
25 POFFSETL Register (0xC0)
26 POFFSETH Register (0xC1)
26 CALIB Register (0xD7)
27 CALIBCFG Register (0xD9)
29 CALIBSTAT Register (0xDC)
29 INTENAB Register (0xDD)
30 FAC_L Register (0xE5)
30 FAC_H Register (0xE6)
31 TEST9 Register (0xF9)
[v1-03] 2020-Aug-25 Document Feedback TMD2635 − Content Guide