TM54S816T AVICTEK | Alldatasheet
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@ Package: 400-mil S4-pin TSOP(ID) @ Byte control(DQML and DQMU) @ JEDEC PC133/PC100 compatible ® Auto and Self Refresh @ Single 3.5V Power Supply ®@ 64ms refresh period (4K Refresh) @ LVTTL Signal Compatible @ |2-Row x 9-Column organization @ Programmable @ 4-Bank operation controlled by BAI,BAO - CAS Latency (3 or 2 clocks) @ Pin36 and 40 are “No Connected” - Burst Length (1.2.4, 8 & full page) ®@ Fully synchronous operation referenced - Burst type (Sequential & Interleave) to clock rising edge @® Burst read/write and burst read/single write operations capability Frequency ys. AC Parameter [Symbol [Parameter 6-7 8 Unit_| [tac [Max access time from CLK @CL=3 For reference only 1 TMC Rev: 1.0
[CLK [Master Clock JDQML/DQMU_[Output Disable(Write Mask) | [WE [Write Enable TVssiVssQ [Ground Ipgo-pgis fDatavo NC No Connection wot ji cs oe yo 63 [__] vats soi [_] 4 st] pata og [| 5 so,” ] cas wal] 6 45 |__| va oo [| 7 48] | patz mt [8 a7{_ | pat oes L_]io as [7] pato pos ("Jit [| car vssa [7] 12 43[7] wo sar [7] 13 az[] cas wo [_|14 TSOP( IL)-54 +1 [_] ¥ss paw [15 ao] |e Ae (_|16 Top View ss{_] now fas (__|17 33{ ] ak fos [_|18 37[__] cx fs (_|1s se[ | Bo (_]za sda sa [__|21 ui] aio L_j2 BL la wo [|e az[ la at (_]24 af as a (|p wl la as [ |26 aff” wo L la 2 | ss For reference only 2 TMC Rev: 1.0
Prin | Name Pin Function CLK System clock Active on the positive going edge to sample all inputs. cS Chip select Disables or enables device operation by masking or enabling all inputs except ICLK.CKE and DQML/DOMU. ICKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command, Disable input buffers for power down in standby AO-All Address input Row/column addresses are multiplexed on the same pins. Row address:A0~A 11, Column address: AO~A7. BAI,BAO Bank address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe —_|Latches row addresses on the positive going ledge of the CLK with /RAS low. Enables rows. laccess & pre-charge CAS (Column address strobe |Latches column addresses on the positive going ledge of the CLK with /CAS low. Enables column access. ws enable Enables write operation and row pre-charge. Latches data in starting from /CAS/WE active. IDQMU/DOML |Data 'O mask Makes data output Hi-Z, Tshz after the clock land masks the output. Blocks data input when IDQML/DQMU active. IDQo~15 Data input/output Data inputs/outputs are multiplexed on the same pins. Vdd/Vss Power supply/ground {Power and ground for the input buffers and the core logic. Vddo/VssQ Data output power Isolated power supply and ground for the ground joutput buffers to provide improved noise immunity INC/RFU No connection This pin is recommended to be left no reserved for future use [connection on the device. For reference only 3 TMC Rev: 1.0
ollage on any pin relativetoVss [VIN VouT___[0.5to 4.6 oltage supply relative to Vss Vdd.Vdda 10.50 4.6 Operating temperature [toor foto 70 Tc Power dissipation en [ Output Shorted current DC OPERATING CONDITIONS Recommended operating conditions(Referenced to Vss=0V.Ta=0C to 70C) Parameter Symbol [mo [ ye. | max | une Power Supply _ Voltage vid. Vado | 3.0 [ 33 [ 36 | v_| Input Logic High Voltage LS eT re Input Logie Low Voltage [Vw fos [ - Joos Tov | Juiput Logie High Voltage Wow J 24 fT - | - Tv | Duiput Logic Low Voltage LS A ET Input/Output Leakage Current in lan ~——s -3 ~~ 1 3 A DC Characteristics (Recommended operating condition Ta = 0C_to 70°C, unless otherwise noted.) Parameter Symbol Test Conditions Limits | 6 | 7 [3 | )perating Current lect Burst length=1, CL=3 120 | 110 | 100 | ma ‘One bank active) Htc = tee(min), tex = tex (min) Pre-charge Standby Current in liccar [Ct Vin(max), tox = 1Sns mA Power Down Mode Pre-charge Standby Current in figgN [/CS=CKE >Vi(min), 25 mA ion-Power Down Mode cx = 1Sns ccgNS_|/CS=CKE = Vantin), 15 ICLK< Vin(max) Active Standby Current in Powerliecsp [CRE ‘Vi.max), tex =15ns fo? mA Down Mode 7 loops [CREE CER Vana) Active Standby Current in iccsN[/CS=CKE>Vin(min), 35 mA Non-Power Down Mode tex =15ns iccsNS_ [/CS=CKE>Vinimin), CLK < Vin(max ) )perating Current (Burst) liccy _ [BL=4,CL=3.All Banks Active Auto Refresh Current flees _ [CBR Command, tex =tex(min)]|_ 160 [150 [140 [ ma | Self Refresh Current liccs | CKE<0.2V For reference only 4 TMC Rev: 1.0
Recommended operating conditions(Vdd=VddO=3.3V,Vss=0V,Ta= 0 to 70C) Tp om Parameter [ Min [Max | Min [Max | min [Max | [tex [olock Cycleimecis Too Tro TP so Ts | a a [af tye [lockAvcss times [sof [sa] [om |= | [a teu [ovock High Puke Wah | 35 [P23] [2s ) [= | [Sf tes otockc tow Pulse wieth | 25 |} 25] | 2s | | os _| RS [ius inp Hotd timetalt inputs) | os | [os | [os | [| LS Lf ty frransition ime ofctock [10 | [io | m]io| [ms _| [of fac [Row to Column delay] 8 |} is | [20 | [= | UP tye fRowcyceume |» | pa] [7] |» | [2] teas [Rowaetvenime J 2 |} 2 | [as |] | [15] gy [Row Pressharge time J 1s | Js | | 20 | [an [Rowacive wacveday [2 ff {Pst [= _] ET For reference only 5 TMC Rev: 1.0
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| Le 3 Sikes our eer iresar PE 9] srw wewem amon ® 1 iain tail ital ana aa la bi dl See! "= ES] i \\ - y mo es f | Pi AORAARA Te | antl lig a. = ser = oer For reference only 6 TMC Rev: 1.0