TLE94110ES

TLE94110ES INFINEON | Alldatasheet

Document overview

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• PDF pages: 80

Technical content

Features

• T e n h a l f b r i d g e p o w e r o u t p u t s
• Very low power consumption in sleep mode
• 3.3V / 5V compatible inputs with hysteresis
• All outputs with overload and short circuit protection
• Independently diagnosable outp uts (overcurrent, open load)
• Open load diagnostics in ON-state for all high-side and low-side
• Outputs with selectable open load thresholds (HS1, HS2)
• 16-bit Standard SPI interface with daisy chain and in-frame response capability for control and diagnosis
• Fast diagnosis with the global error flag
• PWM capable outputs for fre quencies 80Hz, 100Hz and 200Hz with 8-bit duty cycle resolution
• Overtemperature pre-warning and protection
• Over- and Undervoltage lockout
• Cross-current protection

Applications

• H V A C F l a p D C m o t o r s
• Monostable and bistable Relays
• Side mirror x-y adjustment and mirror fold
• L E D s

Description

The TLE94110ES is a protected ten-fold half-bridge driver designed especially for automotive motion control applications such as Heating, Ventilat ion and Air Conditioning (HVAC) flap DC motor control. It is part of a larger family offering half-bridge dr ivers from three outputs to twelve ou tputs with direct interface or SPI interface. The half bridge drivers are designed to drive DC motor loads in sequ ential or parallel operation. Operation modes forward (cw), reverse (ccw), br ake and high impedance are controll ed from a 16-bit SPI interface. It offers diagnosis features such as short circuit, open load, power supply fa ilure and overtemperature detection. In combination with its low quiescent current, this device is attractive among others for automotive applications. The small fine pitch exposed pad package, PG-TSDSO-24, provides good thermal performance and reduces PCB-board space and costs.

Data Sheet 2 1.0 2020-09-29 TLE94110ES Type Package Marking TLE94110ES PG-TSDSO-24 TLE94110ES Table 1 Product Summary Normal Operating Voltage VS 5.5 ... 18 V Extended Operating Voltage VS 18 ... 20 V Maximum Supply Voltage for Load Dump Protection VS(LD) 40 V Minimum Overcurrent Threshold ISD 0.9 A Maximum On-State Path Resistance at Tj = 150°C R DSON(total)_HSx+LSy 1.8 + 1.8 Ω Typical Quiescent Current at Tj = 85°C I SQ 0.1 µA Maximum SPI Access Frequency f SCLK 5M H z

Data Sheet 3 1.0 2020-09-29 TLE94110ES Table of Contents

Data Sheet 4 1.0 2020-09-29 TLE94110ES

Data Sheet 5 1.0 2020-09-29 TLE94110ES Pin Configuration

1 Pin Configuration

1.1 Pin Assignment

Figure 1 Pin Configuration TLE94110ES

1.2 Pin Definitions and Functions

1 GND Ground. All ground pins should be externally connected together. 2O U T 1 P o w e r h a l f - b r i d g e 1 3O U T 5 P o w e r h a l f - b r i d g e 5 4O U T 7 P o w e r h a l f - b r i d g e 7

5 SDI Serial data input with internal pull down

6 VDD Logic supply voltage

7 SDO Serial data output

8 EN Enable with internal pull-down; Places de vice in standby mode by pulling the EN

9O U T 9 P o w e r h a l f - b r i d g e 9

10 OUT 6 Power half-bridge 6

11 OUT 4 Power half-bridge 4

12 GND Ground. All ground pins should be externally connected together. GND OUT 2 OUT 8 VS2 SCLK CSN N.U.SDO EN OUT 9 OUT 6 OUT 4 GND GND OUT 1 OUT 5 OUT 7 SDI VDD N.U. VS1 OUT 10 OUT 3 GND

Data Sheet 6 1.0 2020-09-29 TLE94110ES Pin Configuration Note: Not used (N.U.) pins and unused outputs are recommended to be left unconnected (open) on the application board. If N.U. pins or unused output pins are routed to an external connector which leaves the PCB, then these outputs should have provision for a zero ohm jumper (depopulated if unused) or ESD protection. In other words, they should be treated like used pins. 13 GND Ground. All ground pins should be externally connected together.

14 OUT 3 Power half-bridge 3

15 OUT 10 Power half-bridge 10

16 VS1 Main supply voltage for power half bridge s. VS1 should be externally connected to VS2. 17 N.U. Not used. This pin should be left open. 18 N.U. Not used. This pin should be left open.

19 CSN Chip select Not input with internal pull up

20 SCLK Serial clock input with internal pull down

21 VS2 Main supply voltage for power half bridge s. VS1 should be externally connected to VS2.

22 OUT 8 Power half-bridge 8

23 OUT 2 Power half-bridge 2

24 GND Ground. All ground pins should be externally connected together. EDP - Exposed Die Pad; For cooling and EMC pu rposes only - not usable as electrical ground. Electrical ground must be provided by pins 1,12,13,24. 1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The exposed pad (EP) must be either left open or connected to GND. It is recommended to connect EP to GND for best EMC and thermal performance. Pin Symbol Function

Data Sheet 7 1.0 2020-09-29 TLE94110ES Block Diagram

2 Block Diagram

Figure 2 Block Diagram TL E94110ES (SPI Interface) SCLK EN CSN SDI SDO BIAS MONITOR UNDERVOLTAGE OVERVOLTAGE MONITOR VDD ERROR DETECTION CHARGE PUMP open load detection current control high-side driver low-side driver short to battery detection temp sensor current control short to battery detection high-side driver low-side driver short to battery detection temp sensor open load detection current control short to battery detection high-side driver low-side driver short to battery detection temp sensor open load detection current control short to battery detection high-side driver low-side driver short to battery detection temp sensor current control short to battery detection OUT 7 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1 open load detection current control short to battery detection low-side driver short to battery detection temp sensor open load detection current control short to battery detection high-side driver low-side driver short to battery detection temp sensor current control short to battery detection high-side driver low-side driver short to battery detection temp sensor current control short to battery detection high-side driver low-side driver short to battery detection temp sensor current control short to battery detection temp sensor high-side driver low-side driver Power driver temp sensor Po wer stag e OUT 10 OUT 9 OUT 8 OUT 6 LOGIC CONTROL & LATCH SPI INTERFACE 10-Fold Half Bridge Driver SPI Interface open load detection short to ground detection overtemperature detection open load detection short to battery detection overtemperature detection GNDGND GND GND VS1 VS2 PWM GENERATOR

Data Sheet 8 1.0 2020-09-29 TLE94110ES Block Diagram

2.1 Voltage and current definition

Figure 3 shows terms used in this datasheet, with associated convention for positive values. Figure 3 Voltage and Current Definition SPI INTERFACE DRIVER VDD VSD O VS IS1 VDD SDO SDI CSN VS1 VSD I VCS N VSC LK SCLK GND IGND VEN EN OUT x IOUTx VDS LS x VDSHS xICS N ISD I ISC LK ISD O IEN IDD IS2 VS2 GNDGNDGND IGNDIGNDIGND

Data Sheet 9 1.0 2020-09-29 TLE94110ES General Product Characteristics

3 General Product Characteristics

3.1 Absolute Maximum Ratings

Table 2 Absolute Maximum Ratings 1)Tj = -40°C to +150°C 1) Not subject to production test, specified by design Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Supply voltage V S -0.3 – 40 V VS = VS1 = VS2 P_4.1.1 Supply Voltage Slew Rate | dVS/dt | –– 1 0 V / µ s VS increasing and decreasing 1) P_4.2.2 Power half-bridge output voltage VOUT -0.3 – 40 V 0 V < VOUT < VS 2) 2) Also applicable to not used (N.U.) pins P_4.1.2 Logic supply voltage VDD -0.3 – 5.5 V 0 V < VS < 40 V P_4.1.3 Logic input voltages (SDI, SCLK, CSN, EN) VSDI, VSCLK, VCSN, VEN -0.3 – VDD V 0 V < VS < 40 V 0 V < VDD < 5.5V P_4.1.4 Logic output voltage (SDO) VSDO -0.3 – VDD V 0 V < VS < 40 V 0 V < VDD < 5.5V P_4.1.5 Currents Continuous Supply Current for VS1 IS1 0– 2 . 5 A – P_4.1.6 Continuous Supply Current for VS2 IS2 0– 2 . 5 A – P_4.1.7 Current per GND pin IGND 0– 2 . 0 A – P_4.1.14 Output Currents IOUT -2.0 – 2.0 A – P_4.1.15 Temperatures Junction temperature Tj -40 – 150 °C – P_4.1.8 Storage temperature Tstg -50 – 150 °C – P_4.1.9 ESD Susceptibility ESD susceptibility OUTn and VSx pins versus GND. All other pins grounded. VESD -8 – 8 kV JEDEC HBM 1)3) 3) ESD susceptibility, “JEDEC HBM” according to ANSI/ ESDA/ JEDEC JS001 (1.5 k Ω, 100pF) P_4.1.10 ESD susceptibility all pins VESD -2 – 2 kV JEDEC HBM 1)3) P_4.1.11 ESD susceptibility all pins VESD -500 – 500 V CDM 1)4) 4) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 P_4.1.12 ESD susceptibility corner pins VESD -750 – 750 V CDM 1)4) P_4.1.13

Data Sheet 10 1.0 2020-09-29 TLE94110ES General Product Characteristics Notes 1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

Data Sheet 11 1.0 2020-09-29 TLE94110ES General Product Characteristics

3.2 Functional Range

Note: Within the normal functional range the IC oper ates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Table 3 Functional Range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply voltage range for normal operation VS(nor) 5.5 – 18 V – P_4.2.1 Extended supply voltage range VS(ext) 18 – 20 V 1)2) 1) Not subject to production test, specified by design. 2) In the extended supply range, the device is still func tional. However, deviations of the specified electrical characteristics are possible. P_4.2.7 Logic supply voltage range for normal operation Logic input voltages (SDI, SCLK, CSN, EN) VSDI, VSCLK, VCSN, VEN Junction temperature Tj -40 – 150 °C P_4.2.5

Data Sheet 12 1.0 2020-09-29 TLE94110ES General Product Characteristics

3.3 Thermal Resistance

Table 4 Thermal Resistance Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to Case, TA = 85°C RthjC_hot – 2.1 –K / W 1) Junction to ambient, TA = 85°C (1s0p, minimal footprint) RthjA_hot_m in – 78.9 – K/W 1) 2) Junction to ambient, TA = 85°C (1s0p, 300mm2 Cu) RthjA_hot_30 – 45.9 – K/W 1) 3) Junction to ambient, TA = 85°C (1s0p, 600mm2 Cu) RthjA_hot_60 – 39 –K / W 1) 1) 1) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 600mm2 copper area and 35µm thickness. Ta = 85°C, each channel dissipates 0.135W. Junction to ambient, TA = 85°C (2s2p) RthjA_hot_2s – 27.4 – K/W 1) 5)

Data Sheet 13 1.0 2020-09-29 TLE94110ES General Product Characteristics

3.4 Electrical Characteristics

Table 5 Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise specified; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current Consumption, EN = GND Supply Quiescent current I Logic supply quiescent current IDD_Q – 0.1 1 µA -40°C ≤ Tj ≤ 85°C P_4.4.2 Total quiescent current ISQ + IDD_Q – 0.6 3 µA -40°C ≤ Tj ≤ 85°C P_4.4.3 Current Consumption, EN=HIGH Supply current IS – 0.5 1 mA Power drivers and power stages are off P_4.4.4 Supply current IS_HSON – 4.5 9 mA All high-sides ON 1) P_4.4.101 Logic supply current IDD –1 . 5 3m A S P I n o t a c t i v e P_4.4.5 Logic supply current IDD_RUN –5 –m A S P I 5 M H z 3) P_4.4.6 Total supply current IS + IDD_RUN –5 . 5 –m A S P I 5 M H z 3) P_4.4.7 Over- and Undervoltage Lockout Undervoltage Switch ON voltage threshold VUV ON 4.25 – 5.25 V VS increasing P_4.4.8 Undervoltage Switch OFF voltage threshold VUV OFF 4– 5 . 0 V VS decreasing P_4.4.9 Undervoltage Switch ON/OFF hysteresis VUV HY –0 . 2 5 –V VUV ON - VUV OFF 3) P_4.4.10 Overvoltage Switch OFF voltage threshold VOV OFF 21 – 25 V VS increasing P_4.4.11 Overvoltage Switch ON voltage threshold VOV ON 20 – 24 V VS decreasing P_4.4.12 Overvoltage Switch ON/OFF hysteresis VOV HY –1 –V VOV OFF - VOV ON 3) P_4.4.13 VDD Power ON/OFF hysteresis VDD POR HY –0 . 0 5 –V VDD POR - VDD POffR 3) P_4.4.98 Static Drain-source ON-Resistance (High-Side or Low-Side) High-Side or Low-Side RDSON (all outputs) RDSON_HB_25C – 850 1200 m Ω IOUT = ±0.5 A; Tj = 25 °C P_4.4.16 High-Side or Low-Side RDSON (all outputs) RDSON_HB_150 C – 1400 1800 m Ω IOUT = ±0.5 A; Tj = 150 °C P_4.4.17

Data Sheet 14 1.0 2020-09-29 TLE94110ES General Product Characteristics High-Side RDSON (HS1 and HS2 in LED mode) RDSON_HI_HB_ 25C – 950 1300 m Ω 2) IOUT = -0.1 A; Tj = 25 °C P_4.4.18 High-Side RDSON (HS1 and HS2 in LED mode) RDSON_HI_HB_ 150C – 1500 2000 m Ω 2) IOUT = -0.1 A; Tj = 150 °C P_4.4.19 Output Protection and Diagnosis of high-side (HS) channels of half-bridge output HS Overcurrent Shutdown Threshold Difference between shutdown and limit current ILIM_HS - ISD_HS -1.2 -0.6 0 A 3) |ILIM_HS| ≥ |ISD_HS| See Figure 7 P_4.4.21 Overcurrent Shutdown filter time tdSD_HS 15 19 23 µs 3) P_4.4.22 Open Load Detection Current IOLD1_HS -15 -8 -3 mA - P_4.4.23 Open Load Detection filter time tOLD1_HS 2000 3000 4000 µs 3) P_4.4.24 Open Load Detection Current for LED mode (HS1 & HS2) IOLD2_HS1,2 -3.2 -2 -0.5 mA Bit OL_SEL_HS1 = 1, OL_SEL_HS2 = 1 P_4.4.25 Open Load Detection filter time for LED mode (HS1 & HS2) tOLD2_HS1,2 100 200 300 µs Bit OL_SEL_HS1 = 1, OL_SEL_HS2 = 1; P_4.4.26 Output Protection and Diagnosis of low-side (LS) channels of half-bridge output LS Overcurrent Shutdown Threshold Difference between shutdown and limit current ILIM_LS - ISD_LS 00 . 6 1 . 2 A 3) ILIM_LS ≥ ISD_LS Figure 8 P_4.4.28 Overcurrent Shutdown filter time tdSD_LS 15 19 23 µs 3) P_4.4.29 Open Load Detection Current IOLD_LS 38 1 5 m A - P_4.4.30 Open Load Detection filter time tOLD_LS 2000 3000 4000 µs 3) P_4.4.31 Outputs OUT(1...n) leakage current HS leakage current in off state I QLHn_NOR -2 -0.5 – µA VOUTn = 0V ; EN=High P_4.4.32 HS leakage current in off state IQLHn_SLE -2 -0.5 – µA VOUTn = 0V; EN=GND P_4.4.33 LS Leakage current in off state IQLLn_NOR –0 . 5 2µ A VOUTn = VS ; EN=High P_4.4.34 LS Leakage current in off state IQLLn_SLE –0 . 5 2µ A VOUTn = VS ; EN=GND P_4.4.35 Output Switching Times. See Figure 9 and Figure 10. Slew rate of high-side and low- side outputs dVOUT/ dt 0.1 0.45 0.75 V/µs Resistive load = 100Ω; VS=13.5V 4) P_4.4.36 Table 5 Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise specified; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) (cont’d) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 15 1.0 2020-09-29 TLE94110ES General Product Characteristics Output delay time high side driver on tdONH 52 0 3 5 µ s R e s i s t i v e l o a d = 100Ω to GND P_4.4.37 Output delay time high side driver off tdOFFH 15 45 75 µs Resistive load = 100Ω to GND P_4.4.38 Output delay time low side driver on tdONL 52 0 3 5 µ s R e s i s t i v e l o a d = 100Ω to VS P_4.4.39 Output delay time low side driver off tdOFFL 15 45 75 µs Resistive load = 100Ω to VS P_4.4.40 Cross current protection time, high to low tDHL 100 130 160 µs Resistive load = 100Ω3) P_4.4.41 Cross current protection time, low to high tDLH 100 130 160 µs Resistive load = 100Ω3) P_4.4.42 Input Interface: Logic Input EN High-input voltage VENH 0.7 * VDD –– V – P_4.4.43 Low-input voltage VENL – – 0.3 * VDD V– P_4.4.44 Hysteresis of input voltage VENHY – 500 – mV 3) P_4.4.45 Pull down resistor RPD_EN 20 40 70 k Ω VEN = 0.2 x VDD P_4.4.46 SPI frequency Maximum SPI frequency f SPI,max –– 5 . 0 M H z 3) 5) P_4.4.47 SPI INTERFACE: Delay Time from EN rising edge to first Data in Setup time tset – – 150 µs 3) See Figure 14 P_4.4.48 SPI INTERFACE: Input Interface, Logic Inputs SDI, SCLK, CSN H-input voltage threshold VIH 0.7 * VDD –– V – P_4.4.50 L-input voltage threshold VIL – – 0.3 * VDD V– P_4.4.51 Hysteresis of input voltage VIHY – 500 – mV 3) P_4.4.52 Pull up resistor at pin CSN RPU_CSN 30 50 80 k Ω VCSN = 0.7 x VDD P_4.4.53 Pull down resistor at pin SDI, SCLK RPD_SDI, RPD_SCLK 20 40 70 k Ω VSDI, VSCLK = 0.2 x VDD P_4.4.54 Input capacitance at pin CSN, SDI or SCLK CI –1 0 1 5 p F 0 V < VDD < 5.25V 3) P_4.4.55 Input Interface, Logic Output SDO H-output voltage level VSDOH VDD - 0.4 VDD - 0.2 –V ISDOH = -1.6 mA P_4.4.56 Table 5 Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise specified; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) (cont’d) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 16 1.0 2020-09-29 TLE94110ES General Product Characteristics Tri-state Leakage Current ISDOLK -1 – 1 µA VCSN = VDD; 0V < VSDO < VDD P_4.4.58 Tri-state input capacitance CSDO –1 0 1 5 p F 3) P_4.4.59 Data Input Timing. See Figure 15 and Figure 17. SCLK Period tpCLK 200 – – ns 3) P_4.4.60 SCLK High Time tSCLKH 0.45 * tpCLK – 0.55 * tpCLK ns 3) P_4.4.61 SCLK Low Time tSCLKL 0.45 * tpCLK – 0.55 * tpCLK ns 3) P_4.4.62 SCLK Low before CSN Low tBEF 125 – – ns 3) P_4.4.63 CSN Setup Time tlead 250 – – ns 3) P_4.4.64 SCLK Setup Time tlag 250 – – ns 3) P_4.4.65 SCLK Low after CSN High tBEH 125 – – ns 3) P_4.4.66 SDI Setup Time tSDI_setup 30 – – ns 3) P_4.4.67 SDI Hold Time tSDI_hold 30 – – ns 3) P_4.4.68 Input Signal Rise Time at pin SDI, SCLK, CSN trIN –– 5 0 n s 3) P_4.4.69 Input Signal Fall Time at pin SDI, SCLK, CSN tfIN –– 5 0 n s 3) P_4.4.70 Delay time from EN falling edge to standby mode tDMODE –– 8µ s 3) P_4.4.71 Minimum CSN High Time tCSNH 5– –µ s 3) P_4.4.72 Data Output Timing. See Figure 15. SDO Rise Time trSDO –3 0 8 0 n s C load = 40pF 3) P_4.4.73 SDO Fall Time tfSDO –3 0 8 0 n s C load = 40pF 3) P_4.4.74 SDO Enable Time after CSN falling edge tENSDO – – 75 ns Low Impedance 3) P_4.4.75 SDO Disable Time after CSN rising edge tDISSDO –– 7 5 n s H i g h I m p e d a n c e 3) P_4.4.76 Duty cycle of incoming clock at SCLK dutySCLK 45 – 55 % 3) P_4.4.77 SDO Valid Time for VDD = 3.3V tVASDO3 –7 0 9 5 n s VSDO < 0.2 x VDD VSDO > 0.8 x VDD Cload = 40pF 3) P_4.4.78 Table 5 Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise specified; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) (cont’d) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 17 1.0 2020-09-29 TLE94110ES General Product Characteristics SDO Valid Time for VDD = 5V tVASDO5 –5 0 6 5 n s VSDO < 0.2 x VDD VSDO > 0.8 VDD Cload = 40pF 3) P_4.4.79 Thermal warning & Shutdown Thermal warning junction temperature TjW 120 140 170 °C See Figure 113) P_4.4.80 Thermal shutdown junction temperature TjSD 150 175 200 °C See Figure 113) P_4.4.81 Thermal comparator hysteresis TjHYS –5 –° C 3) P_4.4.82 Ratio of SD to W temperature TjSD / TjW 1.05 1.20 – – 3) P_4.4.83 1) IS_HSON does not include the load current 2) HS1, respectively HS2, is set to LED mode by setting OL_SEL_HS1 bit to 1, respectively OL_SEL_HS2 bit to 1 3) Not subject to production test, specified by design 4) Measured for 20% - 80% of V 5) Not applicable in daisy chain configuration Table 5 Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise specified; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) (cont’d) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 18 1.0 2020-09-29 TLE94110ES Characterization results

4 Characterization results

Performed on 7 devices from 2 lots, over operating temperature and nominal/extended supply range. Typical performance characteristics Supply quiescent current Supply current Logic supply quiescent current Logic supply current -0.1 0.9 1.9 2.9 3.9 4.9 5.9 -50 -30 -10 10 30 50 70 90 110 130 150 ISQ [uA] Junction Temperature [°C] P_4.4.1 VS=5.5V VS=13.5V VS=18V VS=19V VS=21 100 150 200 250 300 -50 -30 -10 10 30 50 70 90 110 130 150 IS[uA] Junction Temperature [°C] P_4.4.4 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 - 5 0 - 3 0 - 1 0 1 03 05 07 09 0 1 1 0 1 3 0 1 5 0 IDD_Q[uA] Junction Temperature [°C] P_4.4.2 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 0.84 0.85 0.86 0.87 0.88 0.89 -50 -30 -10 10 30 50 70 90 110 130 150 IDD[mA] Junction Temperature [°C] P_4.4.5 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V

Data Sheet 19 1.0 2020-09-29 TLE94110ES Characterization results HS static Drain-source ON-resistance L S static Drain-source ON-resistance HS static drain-source ON-resistance VS = 13.5V and VDD = 5V LS static drain-source ON-resistance VS = 13.5V and VDD = 5V 600 700 800 900 1000 1100 1200 1300 1400 1500 - 5 0 - 3 0 - 1 0 1 03 05 07 09 0 1 1 0 1 3 0 1 5 0 RDSON_HS [mΩ] Junction Temperature [°C] VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 -50 -30 -10 10 30 50 70 90 110 130 150 RDSON_LS [mΩ] Junction Temperature [°C] VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 -50 -30 -10 10 30 50 70 90 110 130 150 RDSON_HS [mΩ] Junction Temperature [°C] OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 -50 -30 -10 10 30 50 70 90 110 130 150 RDSON_LS [mΩ] Junction Temperature [°C] OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10

Data Sheet 20 1.0 2020-09-29 TLE94110ES Characterization results Slew rate ON of high-side outputs Slew rate ON of low-side outputs Slew rate OFF of high-side outputs S lew rate OFF of low-side outputs 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50 -30 -10 10 30 50 70 90 110 130 150 dVOUT/ dt [V/us] Junction Temperature [°C] P_4.4.36 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 -50 -30 -10 10 30 50 70 90 110 130 150 dVOUT/ dt [V/us] Junction Temperature [°C] P_4.4.36 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 -50 -30 -10 10 30 50 70 90 110 130 150 dVOUT/ dt [V/us] Junction Temperature [°C] P_4.4.36 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 -50 -30 -10 10 30 50 70 90 110 130 150 dVOUT/ dt [V/us] Junction Temperature [°C] P_4.4.36 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V

Data Sheet 21 1.0 2020-09-29 TLE94110ES Characterization results HS overcurrent shutdown threshold L S overcurrent shutdown threshold Undervoltage switch ON voltage threshold U ndervoltage switch OFF voltage threshold -1200 -1180 -1160 -1140 -1120 -1100 -1080 -1060 -1040 -1020 -1000 -50 -30 -10 10 30 50 70 90 110 130 150 ISD_HS [mA] Junction Temperature [°C] P_4.4.89 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 1000 1020 1040 1060 1080 1100 1120 1140 1160 -50 -30 -10 10 30 50 70 90 110 130 150 ISD_LS [mA] Junction Temperature [°C] P_4.4.104 VS=5.5V VS=13.5V VS=18V VS=19V VS=21V 4.65 4.7 4.75 4.8 4.85 4.9 4.95 -50 -30 -10 10 30 50 70 90 110 130 150 VUV_ON [V] Junction Temperature [°C] P_4.4.8 VDD=3V VDD=5V VDD=5.5V 4.54 4.59 4.64 4.69 4.74 4.79 -50 -30 -10 10 30 50 70 90 110 130 150 VUV_OFF [V] Junction Temperature [°C] P_4.4.9 VDD=3V VDD=5V VDD=5.5V

Data Sheet 22 1.0 2020-09-29 TLE94110ES Characterization results Overvoltage switch ON voltage threshold O vervoltage switch OFF voltage threshold VDD Power-on-reset and VDD Power-off-reset 21.9 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 - 5 0 - 3 0 - 1 0 1 03 05 07 09 0 1 1 0 1 3 0 1 5 0 VOV_ON [V] Junction Temperature [°C] P_4.4.12 VDD=3V VDD=5V VDD=5.5V 22.8 22.9 23.1 23.2 23.3 23.4 23.5 23.6 -50 -30 -10 10 30 50 70 90 110 130 150 VOV_OFF [V] Junction Temperature [°C] P_4.4.11 VDD=3V VDD=5V VDD=5.5V 2.56 2.58 2.60 2.62 2.64 2.66 2.68 -50 -30 -10 10 30 50 70 90 110 130 150 VDD threshold [V] Junction Temperature [°C] VDD POR VDD POffR

Data Sheet 23 1.0 2020-09-29 TLE94110ES General Description

5 General Description

5.1 Power Supply

The TLE94110ES has two power supply inputs, VS and VDD. The half bridge outputs are supplied by VS, which is connected to the 12V au tomotive supply rail. VDD is used to supply the I/O buffers and internal voltage regulator of the device. VS and VDD supplies are separated so that in formation stored in the logic bloc k remains intact in the event of voltage drop outs or disturbances on VS. The system can therefore continue to operate once VS has recovered, without having to resend commands to the device. A rising edge on VDD crossing VDD POR triggers an internal Power-On Reset (POR) to initialize the IC at power-on. All data stored internally is deleted, and the outputs are switched off (high impedance). An electrolytic and 100nF ce ramic capacitors are recommended to be placed as close as possible to the VS supply pin of the device for improved EMC performanc e in the high and low frequency band. The electrolytic capacitor must be dimensioned to prevent the VS vo ltage from exceeding the ab solute maximum rating. In addition, decoupling capacitors are recommended on the VDD supply pin.

5.2 Operation modes

5.2.1 Normal mode

The TLE94110ES enters normal mode by setting the EN input High. In normal mode, the charge pump is active and all output transistors can be configured via SPI.

5.2.2 Sleep mode

The TLE94110ES enters sleep mode by setting the EN input Low. The EN input has an internal pull-down resistor. In sleep mode, all output transistors are turned of f and the SPI register banks are reset. The current consumption is reduced to ISQ + IDD_Q.

5.3 Reset Behaviour

The following reset triggers have been implemented in the TLE94110ES: VDD Undervoltage Reset: The SPI Interface shall not function if VDD is below the underv oltage threshold, VDD POffR. The digital block will be deactivated, the logic contents cleared and the output stages are switched off . The digital block is initialized once VDD voltage levels is above the undervoltage threshold, VDD POR . Then the NPOR bit is reset (NPOR = 0 in SYS_DIAG1 and Global Status Register). Reset on EN pin: If the EN pin is pulled Low, the logic content is reset and the device enters sleep mode. The reset event is reported by the NPOR bit (NPOR = 0) once the TLE94110ES is in normal mode (EN = High; VDD > V DD POR).

Data Sheet 24 1.0 2020-09-29 TLE94110ES General Description

5.4 Reverse Polarity Protection

The TLE94110ES requires an external re verse polarity protection. During reverse polarity, the free-wheeling diodes across the half bridge output will begin to conduct, causing an undesired current flow (IRB) from ground potential to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection diode is recommended (see Figure 4). Figure 4 Reverse Polarity Protection VBAT OUTx GND HSx LSx IRB VBAT OUTx GND HSx LSx a) b) CS DRP CS2

Data Sheet 25 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6 Half-Bridge Outputs

6.1 Functional Description

The half-bridge outputs of the TLE 94110ES are intended to drive motor lo ads. These outputs can either be driven continuously or PWM enabled via SPI. If the outputs are driven continuously via SPI, for example HS1 and LS2 used to drive a motor, then the following suggested SPI commands shall be sent:

• Activate HS1: Bit HB1_HS_EN in HB_ACT_1_CTRL register
• Activate LS2: Bit HB2_LS_EN in HB_ACT_1_CTRL register

6.1.1 Half-bridge operation with PWM enabled

All half-bridge outputs of the TLE94110ES are capable of PWM operation. They can either be used to drive an allocated a maximum of three PWM channels with indi vidual duty cycle settings with 8-bit resolution. Each channel is further mapped to a maximum of three PWM frequency options, i. e. 80Hz,100Hz and 200Hz. This feature enables a highly flexible PWM operation while driving loads with varying control profiles. PWM frequency and duty cycle can be changed on demand during PWM operation of the desired half-bridge output. Glitches on the PWM output waveform, which may arise as a result of on-demand changes in PWM operation, will be prevented by the internal logic circuitry. When operating with motor loads, active or passive fr ee-wheeling configuration is available via SPI to select the speed at which the inductive curr ent can decay over the full-bridge ci rcuit. The default setting is passive free-wheeling. Note: Active free-wheeling is effectivel y applied if the selected duty cycle corresponds to turn-on times of the HS and the LS, which are longer than the sum of the cross conduction times tDHL + tDLH. Table 6 PWM capability and freque ncy selection per half-bridge output Control Register: HBx_MODEn (n=0,1) PWM Frequency 80Hz (Control Register: PWM_CH_FREQ_CTRL) PWM Frequency 100Hz (Control Register: PWM_CH_FREQ_CTRL) PWM Frequency 200Hz (Control Register: PWM_CH_FREQ_CTRL) PWM Channel 1 PWM_CH1_FREQ_n (n=0,1) Bit ‘01B’ PWM_CH1_FREQ_n (n=0,1) Bit ‘10B’ PWM_CH1_FREQ_n (n=0,1) Bit ‘11B’ PWM Channel 2 PWM_CH2_FREQ_n (n=0,1) Bit ‘01B’ PWM_CH2_FREQ_n (n=0,1) Bit ‘10B’ PWM_CH2_FREQ_n (n=0,1) Bit ‘11B’ PWM Channel 3 PWM_CH3_FREQ_n (n=0,1) Bit ‘01B’ PWM_CH3_FREQ_n (n=0,1) Bit ‘10B’ PWM_CH3_FREQ_n (n=0,1) Bit ‘11B’

Data Sheet 26 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.1.1.1 Inductive Load

An illustration is shown in Figure 5 with OUT1 and OUT2 driving a DC br ush motor. With this configuration, HS1 is permanently driven while LS2 is driven in PWM operation. HS2 serves to actively free-wheel (FW) the motor current load, reducing the power dissipation of the device. Figure 5 PWM operation on OUT 2 Assuming HBx Mode = 00 and both HSx and LSx are cons idered off (tri-state). The suggested SPI control commands for proper PWM operation are: Option 1: The considered output is not put in parallel with another one

• Configure the frequency to 00 (PWM is st opped and off) for selected PWM channel
• Configure active or passive free-wheeling of the inductive decay current in FW_CTRL register
• Assign an appropriate PWM channel for selected half-bridge output in HB_MODE_CTRL register
• Configure the duty cycle of the selected half-bridge output in PWM_DC_CTRL register
• Select the PWM frequency in PWM_CH_FREQ_ CTRL register to begin the PWM period
• Activate the channel to be driven in PWM oper ation: HSn or LSn in the HB_ACT_CTRL register Option 2: Outputs controlled by di fferent control registers are put pa ralleled. This sequence ensures that corresponding HS or LS are activated simultaneously
• Configure the frequency 00 (PWM is stopped and off) for selected PWM channel
• Configure active or passive free-wheeling of the inductive decay current in FW_CTRL register
• Assign an appropriate PWM channel for selected half-bridge output in HB_MODE_CTRL register
• Configure the duty cycle of the selected half-bridge output in PWM_DC_CTRL register
• Activate the channel to be driven in PWM oper ation: HSn or LSn in the HB_ACT_CTRL register
• Select the PWM frequency in PWM_CH_FREQ_ CTRL register to begin the PWM period Careful attention should be paid to the free-wheeling configuration of the half-bridge required to be driven in PWM operation. For example, in the event a high-side channel is activated and assigned a PWM channel, and active free-wheeling is selected, but a frequency mode of ‘00’ (PWM is stopped and off) is configured in the OUT 2OUT 1 VS HS1 ON LS1 HS2 active FW LS2 PWM OUT 1 OUT 2 t HBn t CW FW CW FW CW CW FW FW CW = motor clockwise FW = Free-wheeling

Data Sheet 27 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs PWM_CH_FREQ_CTRL register, then the respective high-side channel will be configured low and the adjacent low-side channel within the half-bridge will be enabled. This is a result of enabling active free-wheeling.

Data Sheet 28 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.1.1.2 LED mode (optional)

Outputs, OUT1 and OUT2, are designed to optionally drive low current loads such as LEDs. The high-side channels, HS1 and HS2 are equipped with a lower open load threshold detection current and shorter filter time, specifically for low current loads such as LEDs. See OL_SEL_HS1 and OL_SEL_HS2 bits in FW_OL_CTRL register. Setting HS1 or HS2 in LED mode increases the RDSON and decreases the open load detection threshold. An illustration is shown in Figure 6 with OUT1 driving an LED. With this configuration, HS1 is driven in PWM operation while LS1 is deactivated. Figure 6 PWM operation on OUT 1 Assuming HBx Mode = 00 and both HSx and LSx are cons idered off (tri-state). The suggested SPI control commands are:

• Configure frequency 00 (PWM is stopped and off) for selected channel to ensure PWM is off.
• Assign an appropriate PWM channel for selected HS1 or HS2 output in HB_MODE_CTRL register
• Configure duty cycle of selected HS1 or HS2 output in PWM_DC_CTRL register
• Activate channel to be driven in PWM operat ion: HS1 or HS2 in the HB_ACT_CTRL register
• Select low current open load detection threshold for HS1 or HS2 in FW_OL_CTRL register
• Select PWM frequency in PW M_CH_FREQ_CTRL register to begin the PWM period. OUT 1 HS1 PWM VS

Data Sheet 29 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.2 Protection & Diagnosis

The TLE94110ES is equipped with an SPI interface to control and diagnose the state of the half-bridge drivers. This device has embedded protective functions which are designed to prevent IC destruction under fault conditions described in the followin g sections. Fault conditions are treated as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. The following table provides a summary of fault conditions, protec tion mechanisms and recovery states embedded in the TLE94110ES device. Table 7 Summary of diagnosi s and monitoring of outputs Fault condition Error Flag (EF) behaviour Error bit: Status Register Output Protection mechanism Output error state Output and error flag (EF) recovery Overcurrent Latch 1. Load Er ror bit, LE (bit 6) in SYS_DIAG 1: Global Status 1 Register 2. Localized error for each HS and LS channel of half-bridge, HBn_HS_OC and HBn_LS_OC bits in SYS_DIAG_2, SYS_DIAG_3, SYS_DIAG_4 status registers. Error output shutdown and latched High-Z Half-bridge control bits remain set despite error, however the output stage is shutdown. Clear EF to reactivate output stage. Open load Latch 1. Load Error bit, LE (bit 6) in SYS_DIAG 1: Global Status 1 Register 2. Localized error for each HS and LS channel of half-bridge, HBn_HS_OL and HBn_LS_OL bits in SYS_DIAG_5, SYS_DIAG_6, SYS_DIAG_7 status registers. None No state change An open load detection does not change the state of the output. EF to be cleared. Temperature pre-warning Latch Global error bit 1, TPW in SYS_DIAG_1: Global Status 1 register None No state change Not applicable Temperature shutdown Latch Global error bit 2, TSD in SYS_DIAG_1: Global Status 1 register All outputs shutdown and latched. High-Z Half-bridge control bits remain set despite error, however the output stage is shutdown. Clear EF to reactivate output stage.

Data Sheet 30 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs Power supply failure due to undervoltage Latch Global error bit 5, VS_UV in SYS_DIAG_1: Global Status 1 register All outputs shutdown and automatically recovers. High-Z Half-bridge control bits remain set despite error, however the output stage is shutdown. They will automatically be reactivated once the power supply recovers. EF to be cleared. Power supply failure due to overvoltage Latch Global error bit 4, VS_OV in SYS_DIAG_1: Global Status 1 register All outputs shutdown and automatically recover. High-Z Half-bridge control bits remain set despite error, however the output stage is shutdown. They will automatically be reactivated once the power supply recovers. EF to be cleared. Table 7 Summary of diagnosi s and monitoring of outputs (cont’d) Fault condition Error Flag (EF) behaviour Error bit: Status Register Output Protection mechanism Output error state Output and error flag (EF) recovery

Data Sheet 31 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.2.1 Short Circuit of Output to Supply or Ground

The high-side switches are protected against short to ground whereas the low-side switches are protected against short to supply. The high-side and low-side power switches will enter into an over-current condition if the current within the switch exceeds the overcurrent shutdown detection threshold, ISD. Upon detection of the ISD threshold, an overcurrent shutdown filter, tdSD is begun. As the current rises beyond the threshold ISD, it will be limited by the current limit threshold, ILIM. Upon expiry of the overcurrent shutdown filter time, the affected power switch is latched off and the corresponding error bit, HB n_HS_OC or HBn_LS_OC is set and latched. See Figure 7 and Figure 8 for more detail. A global load error bit, LE, contained in the global status register, SYS_DIAG_1, is also set for ease of error scanning by the application soft ware. The power switch remains deactivated as long as the error bit is set. To resume normal functionality of the power switch (i n the event the overcurrent condition disappears or to verify if the failure still ex ists) the microcontroller shall clear the erro r bit in the respective status register to reactivate the desired power switch. Figure 7 High-Side Switch - Short Circuit and Overcurrent Protection Figure 8 Low-Side Switch - Shor t Circuit and Overcurrent Protection tdSD_ HS t OUTn Short to GND Short condition on High -Side Switch | IHS | I ISD_HS I I ILIM_HS -I SD_HS I I ILIM _HS I ON VS tdSD_LS t OUTn Short condition on Low-Side Switch ILS Short to Supply VS ISD_LS ILIM _LS ILIM _LS -I SD_LS ON VS

Data Sheet 32 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs Table 8 Control and Status register bit state in the event of an overcurrent condition for an activated power switch REGISTER TYPE REGISTER NAME Bit BEFORE OVERCURRENT DURING OVERCURRENT AFTER OVERCURRENT Bit State Bit State Bit State Control HB_ACT_CTRL_n HBn_HS_EN HBn_LS_EN 1 1 1 (corresponding half-bridge deactivated) Status SYS_DIAG_1: Global Status 1 L E 001 Status SYS_DIAG_x where x=2,3,4 HBn_HS_OC HBn_LS_OC 001

Data Sheet 33 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.2.2 Cross-Current

In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously “ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to create a dead-time between switching off of one power transistor and switching on of the adjacent power transistor within the half-bridge. The dead times, tDHL and tDLH, as shown in Figure 9 case 3 and Figure 10 case 3, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross conduction event. Figure 9 Half bridge outputs switching times - high-side to low-side transition CSN 80% 20% 80% 20% VS VOUT_HSx [V] Low-Side ON delay time tdOFFH tdONL +tDHL t GND t t VS GND VOUT_LSx [ V] 80% 20% VS VOUT_LSx [ V] tdONL GND t 2) Delay time LS ON without dead time ; HS previously OFF 3) Delay time LS ON with dead time ; HS previously ON HS ON à HS OFF Previous State àNew State LS OFF à LS OFF Case 1: Delay Time High Side Driver OFF 1) Delay time HS OFF HS OFF à HS OFF Previous State àNew State LS OFF à LS ON Case 2: Delay Time Low Side Driver ON HS ON à HS OFF Previous State àNew State LS OFF à LS ON Case 3: Delay Time Low Side Driver ON with tDHL dead time

Data Sheet 34 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs Figure 10 Half bridge outputs switchin g times- low-side to high-side transition CSN 80% 20% 20% 80% High-Side ON delay time t tdONH +tDLH tdOFFL t t VOUT _HSx [ V] VS GND VS GND VOUT_LSx [V] 20% 80% t tdONH VS GND VOUT_HSx [V] 2) Delay time HS ON without dead time ; LS previously OFF HS ON delay time with dead time ; LS previously ON HS OFF à HS OFF Previous State àNew State LS ON à LS OFF Case 1: Delay Time High Side Driver OFF 1) Delay time LS OFF HS OFF à HS ON Previous State àNew State LS OFF à LS OFF Case 2: Delay Time High Side Driver ON HS OFF à HS ON Previous State àNew State LS ON à LS OFF Case 3: Delay Time High Side Driver ON with tDLH dead time

Data Sheet 35 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.2.3 Temperature Monitoring

Temperature sensors are integrated in the power stag es. The temperature monitori ng circuit compares the measured temperature to the warning and shutdown th resholds. If one or more temperature sensors reach the warning temperature, the temperat ure pre-warning bit, TPW is set. Th is bit is latched and can only be cleared via SPI. The outputs stages however remain activated. If one or more temperature sensors reach the shut-down temperature threshold, all outputs are latched off. The TSD bit in SYS_DIAG_1: Global Status 1 is set. All outputs remain deactivated until the TSD bit is cleared. See Figure 11. To resume normal functionality of the power switch (in the event the overtemperature condition disappears, or to verify if the failure still exis ts) the microcontroller sha ll clear the TSD error bit in the status register to reactivate the respective power switch. Figure 11 Overtemperature Behavior VOUTx t t ON High Z Tj no error TjSD TjW TPW error bit t High Low no error TPW is latched, can be cleared via SPI Output is switched off if TjSD is reached, can be reactivated if TSD bit is cleared TSD error bit t High Low no error TSD is latched, can be cleared via SPI

Data Sheet 36 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs

6.2.4 Overvoltage and undervoltage shutdown

The power supply rails VS and VDD are monitored for supply fluctuations. The VS supply is monitored for under- and over-voltage conditions where as the VDD supply is monitored for under-voltage conditions.

6.2.4.1 VS Undervoltage

In the event the supply voltage VS drops below the switch off voltage VUV OFF, all output stages are switched off, however, the logic information rema ins intact and uncorrupted. The VS under-voltage error bit, VS_UV, located in SYS_DIAG_1: Global Status 1 status register, will be set and latched. If VS rises again and reaches the switch on voltage VUV ON threshold, the power stages will automa tically be activated. The VS_UV error bit should be cleared to verify if the supply disruption is still present. See Figure 12.

6.2.4.2 VS Overvoltage

In the event the supply voltage VS rises above the switch off voltage VOV OFF, all output stages are switched off. The VS over-voltage error bit, VS_OV, located in SYS_DIAG _1: Global Status 1 status register, will be set and latched. If VS falls again and reaches the switch on voltage VOV ON threshold, the power stages will automatically be activated. The VS_OV error bit should be cleared to verify if the overvo ltage condition is still present. See Figure 12.

6.2.4.3 VDD Undervoltage

In the event the VDD logic supply decreases below the undervoltage threshold, VDD POffR, the SPI interface shall no longer be functional and the TLE94110ES will enter reset. The digital block will be initialized and the output stages are switched off to High impedance. The undervoltage reset is released once VDD voltage levels are above the undervoltage threshold, VDD POR. The reset event is reported in SYS_DIAG1 by the NPOR bit (NPOR = 0) once the TLE94110ES is in normal mode (EN = High ; VDD > VDD POR). Table 9 Control and Status register bit state in the event of an overtemperature condition for an activated power switch REGISTER TYPE REGISTER NAME Bit Tj < TjW Tj > TjW Tj > TjSD Tj < TjSD - TjHYS Bit State Bit State Bit State Bit State Control HB_ACT_CTRL_n HBn_HS_EN HBn_LS_EN 111 (all outputs are latched off) ‘1’ (outputs are latched off unless error is cleared) Status SYS_DIAG_1: Global status 1 TPW 0 1 (latched) (latched) ‘0’ if error is cleared and T j < TjW , else ‘1’ Status SYS_DIAG_1: Global status 1 TSD 0 0 1 (latched) ‘0’ if error is cleared, else ‘1’

Data Sheet 37 1.0 2020-09-29 TLE94110ES Half-Bridge Outputs Figure 12 Output behavior during under- and overvoltage V S condition

6.2.5 Open Load

Both high-side and low-side switches of the half-bridge power outputs are capable of detecting an open load in their activated state. If a load current lower than the open load detection threshold, IOLD for at least tdOLD is detected at the activated switch, the corresponding error bit, HBn_HS_OL or HBn_LS_OL is set and latched. A global load error bit, LE, in the global status register, SYS_DIAG_1: Global Status 1, is also set for ease of error scanning by the application software. The half-bridge output however, remains activated. The microcontroller must clear the error bit in the respec tive status register to determine if the open load is still present or disappeared. High-side outputs, HS1 and HS2, are specifically designed to detect open load thresholds for LED loads. Both HS1 and HS2 have a unique and lower open load current threshold and filter time which are configurable via SPI in control register, FW_OL_CTRL. During PWM operation, the open load detection is blanked and will not be visible in the status register for power stages used in active free-wheeling Output reactivated VUV OFF VUV ON VUV HY t VS VOV HY VOV ON VOV OFF VOUTx t ON High Z VS _UV error bit t High Low VOUTx t ON High Z VS _OV error bit t High Low Output reactivated SPI command : Clear SYS _DIAG 1 SPI command Clear SYS _DIAG 1

Data Sheet 38 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7 Serial Peripheral Interface (SPI)

The TLE94110ES has a 16-bit SPI interface for output cont rol and diagnostics. This section describes the SPI protocol, the control and status registers.

7.1 SPI Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input SCLK provided by the microcontroller. SCLK must be Low during CSN falling edge (Clock Polarity = 0). The SPI incorporates an in-frame response: the content of the addressed register is shifted out at SDO within the same SPI frame (see Figure 19 and Figure 21).The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), Low active. After the CSN input returns from Low to High, the word that has been read is interpreted according to the conten t. The SDO output switches to tri-st ate status (High impedance) at this point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input register with every falling edge on SCLK. The state of SDO is shifted out of the output register at every rising edge on SCLK (Clock Phase = 1). The SPI protocol of the TLE94110ES is comp atible with independent slave configuration and with daisy chain. Daisy chaining is applicable to SPI devices with the same protocol. Writing, clearing and reading is done byte wise. Th e SPI configuration and status bits are not cleared automatically by the device and theref ore must be cleared by the microcontr oller, e.g. if the TSD bit was set due to over temperature (refer to the respective register description for detailed information). Figure 13 SPI Data Transfer Timing (note the revers ed order of LSB and MSB as shown in this figure compared to the register description) SPI messages are only recognized if a minimum set time, tSET, is observed upon rising edge of the EN pin (Figure 14). 0 0 +1 2 3 4 5 6 7 8 9 10 15 1 0 1 2 3 4 5 6 11 12 13 147 8 9 10 15 CSN high to low: SDO is enabled. Status information transferred to output shift register CSN low to high: data from shift register is transferred to output functions SDI: will accept data on the falling edge of SCLK signal SDO will change state on the rising edge of SCLK signal Actual status 11 12 13 14 Actual data New data New status SDO SDI CSN SCLK time time time time GEF +GEF 0 LSB MSB

Data Sheet 39 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 14 Setup time from EN risi ng edge to first SPI communication Figure 15 SPI Data Timing

7.1.1 Global Error Flag

A logic OR combination between Global Error Flag (GEF ) and the signal present on SDI is reported on SDO between a CSN falling edge and the first SCLK rising edge (Figure 13). GEF is set if a fault condition is detected or if the device comes from a Power On Reset (POR). Note: The SDI pin of all devices in daisy chain or non daisy chain mode must be Low at the beginning of the SPI frame (between the CSN falling edge and the first SCLK rising edge). It is possible to check if the TL E94110ES has detected a fault by read ing the GEF without SPI clock pulse (Figure 16). EN SPI A) SPI message ignored EN SPI B) SPI message accepted tSET CSN SCLK SDI tlead tCS NHtlag tSC LKH tSC LKL tpCLK tS DI_hold SDO tVASD OtEN SD O tD ISSD O 0.8VDD 0.2VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD tSDI_ se tu p

Data Sheet 40 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 16 SDO behaviour with 0-clock cycle

7.1.2 Global Status Register

The SDO shifts out during the first ei ght SCLK cycles the Global Status Register. This register provides an overview of the device status. All failures conditions are reported in this byte:

• SPI protocol error (SPI_ERR)
• Load Error (LE bit): logical OR between Open Load (OL) and Overcurrent (OC) failures
• VS Undervoltage (VS_UV bit)
• VS Overvoltage (VS_OV bit)
• Negated Power ON Reset (NPOR bit)
• Temperature Shutdown (TSD bit)
• Temperature Pre-Warning (TPW bit) See Chapter 7.7.1 for details. Note: The Global Error Flag is a logic OR combination of every bit of the Global Status Register with the exception of NPOR: GEF = (SPI_ERR) OR (LE) OR (VS_UV) OR (VS_OV) OR (NOT(NPOR)) OR (TSD) OR (TPW). The following table shows how failures are reported in the Global Status Register and by the Global Error Flag. Table 10 Failure reported in the Global Status Register and Global Error Flag Type of Error Failure reported in the Global Status Register Global Error Flag SPI protocol error SPI_ERR = 1 1 Open load or Overcurrent LE = 1 1 VS Undervoltage VS_UV = 1 1 VS Overvoltage VS_OV = 1 1 Power ON Reset NPOR = 0 1 Thermal Shutdown TSD = 1 1 CSN time SCLK time Global Error FlagSDO time SDI time High ImpedanceHigh Impedance

Data Sheet 41 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: The default value (after Power ON Reset) of NP OR is 0, therefore the default value of GEF is 1.

7.1.3 SPI protocol error detection

The SPI incorporates an error flag in the Global Status Register (SPI_ERR, Bit7) to supervise and preserve the data integrity. If an SPI protocol er ror is detected during a given frame, th e SPI_ERR bit is set in the next SPI communication. The SPI_ERR bit is set in the following error conditions:

• the number of SCLK clock pulses received when CSN is Low is not 0, or is not a multiple of 8 and at least 16
• the microcontroller sends an SPI command to an unus ed address. In particular, SDI stuck to High is reported in the SPI_ERR bit
• the LSB of an address byte is not set to 1. In particular, SDI stuck to Low is reported in the SPI_ERR bit
• the Last Address Bit Token (LABT, bit 1 of the address byte, see Chapter 7.2) in independent slave configuration is not set to 1
• the LABT bit of the last address byte in daisy chain configuration is not set to 1 (see Chapter 7.3)
• a clock polarity error is detected (see Figure 17 Case 2 and Case 3): the incoming clock signal was High during CSN rising or falling edges. For a correct SPI communication:
• SCLK must be Low for a minimum t BEF before CSN falling edge and tlead after CSN falling edge
• SCLK must be Low for a minimum t lag before CSN rising edge and tBEH after CSN rising edge Thermal Warning TPW = 1 1 No Error and no Power ON Reset SPI_ERR = 0 LE = 0 VS_UV = 0 VS_OV = 0 NPOR = 1 TSD = 0 TPW = 0 Table 10 Failure reported in the Global Status Register and Global Error Flag Type of Error Failure reported in the Global Status Register Global Error Flag

Data Sheet 42 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 17 Clock Polarity Error CSN SCLK time tBEF tBEH Correct incoming clock signal CSN SCLK time SCLK is High with CSN falling edge SCLK Clock is High with CSN rising edge time time time tlead tlag Correct clock during CSN rising edge Case 2: Erroneous incoming clock signal CSN time Case 3: Erroneous clock signal during CSN rising edge Case 1: Correct SCLK signal

Data Sheet 43 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.2 SPI with independent slave configuration

In an independent slave configuration, the microcon troller controls the CSN of each slave individually (Figure 18). Figure 18 SPI with indepe ndent slave configuration Each SPI communication starts with one ad dress byte followed by one data byte ( Figure 19).The LSB of the data byte must be set to ‘1’.The address bytes specifies:

• the type of operation: READ ONLY (OP bit =0) or READ/ WRITE (OP bit = 1) of the configuration bits, and READ ONLY (OP bit =0)or READ & CLEAR (OP bit = 1) of the status bits.
• The target register address (A[6:2]) The Last Address Byte Token bit (LABT, Bit1 of the address byte) must be set to 1, as no daisy chain configuration is used. While the microcontroller sends the address byte on SDI, SDO shifts out GEF and the Global Status Register. A further data byte (Bit15...8) is allocated to either configure the half-bridges or retrieve status information of the TLE94110ES. Microcontroller SDI1 TLE941xy_1 SPI SCLK SDO1 CSN SDI2 TLE941xy_2 SPI SCLK SDO2 CSN SDI3 TLE941xy_3 SPI SCLK SDO3 CSN MO MI MCLK MCSN1 MCSN2 MCSN3

Data Sheet 44 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 19 SPI Operation Mode with independent slave configuration The in-frame response char acteristic enables the microcontroller to read the contents of the addressed register within the SPI command. See Figure 19. Data ByteAddress Byte

1 LABT

= 1 A2 A3 A4 A5 A6 OP 0 1 2 3 4 5 6 7 SDI LSB D0 D1 D2 D3 D4 D5 D6 D7 8 9 10 11 12 13 14 15 MSB Data Byte (Response )Global Status Register

0 TPW TSD NPOR VS_OV VS_UV LE SPI_

Register content of the selected address Time LSB is sent first in SPI message

Data Sheet 45 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.3 Daisy chain operation

The TLE94110ES supports daisy chain operation with de vices with the same SPI protocol.This section describes the daisy chain hardware configuration with three device s from the TLE941xy family (See Figure 20). The master output (noted MO) is connected to a slave SDI and the first slave SDO is connected to the next slave SDI to form a chain. The SDO of the final slave in the chain will be connected to the master input (MI) to close the loop of the SPI communication frame. In daisy chai n configuration, a single chip select, CSN, and clock signal, SCLK, connected in parallel to each slave device , are used by the microcontr oller to control or access the SPI devices. In this configuration, the Master Output must send the address bytes and data bytes in the following order:

• All address bytes must be sent first: – Address Byte 1 (for TLE941xy_1) is sent first, followed by Address Byte 2 (for TLE941xy_2) etc,... – The LABT bit of the last address byte must be 1, while the LABT bit of all the other address bytes must be 0
• The data bytes are sent all together once all addr ess bytes have been transmitted: Data Byte 1 (for TLE941xy_1) is sent first, followed by Data Byte 2 (for TLE941xy_2) etc,... Note: The signal on the SDI pin of the first IC in dais y chain (and in non-daisy chain mode), must be Low at the beginning of the SPI frame (between CSN falling edge and the first SCLK rising edge). This is because each Global Error Flag in daisy chain operation is implemented in OR logic. The Master Input (MI), which is connected to the SDO of the last device in the daisy chain receives:
• A logic OR combination of all Global Error Flags (G EF), at the beginning of the SPI frame, between CSN falling edge and the first SCLK rising edge
• The logic OR combination of the GEFs is followed by the Global Status Registers in reverse order. In other words MI receives first the Global Status Register of the last device of the daisy chain
• Once all Global Status Registers are received, MI receives the response bytes corresponding to the respective address and data bytes in reverse order. For example, if the daisy chain consists of three devices with SDO or TLE941xy_3 connected to MI, the master receives first the Response Byte 3 of TLE941xy_3 (corresponding to Address Byte 3 and Data Byte 3) followed by the Response Byte 2 of TLE941xy_2 and finally the Response Byte 1 of TLE941xy_1. An example of an SPI frame with three devices from the TLE941xy family is shown in Figure 21.

Data Sheet 46 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 20 Example of dais y chain hardware configuration with devices from the TLE941xy family Figure 21 SPI frame with three devices of the TLE941xy family Like in the individual slave configuration, it is possible to check if one or several TLE941xy have detected a fault condition by reading the logic OR combination of all the Global Error Flags when CSN goes Low without any clock cycle (Figure 22). SDI1 TLE941xy_1 SPI SCLK SDO1 CSN SDI2 TLE941xy_2 SPI SCLK SDO2 CSN SDI3 TLE941xy_3 SPI SCLK SDO3 CSN Microcontroller MO MI MCSN MCLK MO = SDI1 0 CSN Time SDI2 = SDO1 GLOBAL STATUS 1 ADDRESS BYTE 2 ADDRESS BYTE 3 RESPONSE 1 DATA BYTE 2 DATA BYTE 3GEF1 SDI3 = SDO2 GLOBAL STATUS 2OR GEF1/2 ADDRESS BYTE 3 RESPONSE 2 RESPONSE 1 DATA BYTE 3 MI =SDO3 OR GEF1/2/3 GLOBAL STATUS 3 GLOBAL STATUS 1 GLOBAL STATUS 2 GLOBAL STATUS 1 RESPONSE 3 RESPONSE 2 RESPONSE 1 SCLK 0 8 CLOCK CYCLES 8 CLOCK CYLES ADDRESS BYTE 1 ADDRESS BYTE 2 ADDRESS BYTE 3 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 LABT=0 LABT=1LABT=0

8 CLOCK CYCLES 8 CLOCK CYLES 8 CLOCK CYCLES 8 CLOCK CYLES

Data Sheet 47 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 22 Global Error Flag with zero SCLK clock cycle in daisy chain consisting only of TLE941xy devices Note: Some SPI protocol errors such as the LSB of an address byte is wrongly equal to 0, may be reported in the SPI_ERR bit of another device in the daisy chain (refer to Chapter 7.1.3 and Chapter 7.7 for more details on SPI_ERR). In this case some devices might accept wrong data during the corrupted SPI frame. Therefore if one of the devices in the daisy chain reports an SPI error, it is recommended to verify the content of the registers of all devices.

7.4 Status register change during SPI communication

If a new failure occurs after the transf er of the data byte(s), i.e. between the end of the last address byte and the CSN rising edge, this failure will be reported in the next SPI frame (see example in Figure 23). Figure 23 Status register change during transfer of data byte - Example in independent slave configuration CSN Time SCLK 0 SDI2 = SDO1 GEF1 GEF1HiZ HiZ SDI3 = SDO2 OR GEF1/2 OR GEF1/2 HiZ HiZ MI = SDO3 OR GEF1/2/3 HiZ OR GEF1/2/3 HiZ MO = SDI1 0 SDI 0 CSN Time SDO GLOBAL STATUS DATA BYTEGEF SCLK 0 8 CLOCK CYCLES 8 CLOCK CYLES ADDRESS BYTE DATA BYTE GLOBAL STATUS DATA BYTEGEF ADDRESS BYTE DATA BYTE

8 CLOCK CYCLES 8 CLOCK CYLES

Failure notified in the new SPI frame Read status byte corresponding to the failure Failure is NOT notified in this SPI frame

Data Sheet 48 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) No information is lost, even if a status register is changed during a SP I frame, in particular during a Read and Clear command. For example:

• the microcontroller sends a Read and Clear command to a status register
• the TLE94110ES detects during the tran sfer the data byte(s) a new fault condition, which is normally reported in the target status register The incoming Clear command will be ignored, so that the microcontroller can read the new failure in the subsequent SPI frames. Data inconsistency between the Global Status Register (see Chapter 7.7) and the data byte (status register) within the same SPI frame is possible if:
• an open load or overcurrent error is dete cted during the transfer of the data byte
• the target status register corres ponds to the new detected failure In this case the new failure:
• is not reported in the Global Status Register of the current SPI frame but in the next one
• is reported in the data by te of the current SPI frame Refer to Figure 23.

Data Sheet 49 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 24 Example of inconsistency be tween Global Error Flag and Status Register when a status bit is changed during the transfer of an address byte Data ByteAddress Byte Response Data Byte : SYS_DIAG2Global Status Register

0 TPW TSD NPOR VS_OV VS_UV LE

SPI_ ERR 0 1 2 3 4 5 6 7 SDO LSB 8 9 10 11 12 13 14 15 MSB Time Overcurrent failure detected on HS of HB 1 during the transfer of the address byte Overcurrent failure detected on HS of HB 1 SPI frame: Read SYS _DIAG2 (OC error of HB 1-4) Load Error bit (Overcurrent or Open Load ) does not report the new Overcurrent failure HB1_HS_OC reports the new Overcurrent failure on the HS of HB 1 Target status register : OC error of HB 1-4 Inconsistency between Global Status Register and target Status Register Data ByteAddress Byte Response Data Byte : SYS_DIAG2Global Status Register SPI_ ERR 0 1 2 3 4 5 6 7 LSB 8 9 10 11 12 13 14 15 MSB Target status register : OC error of HB 1-4 New SPI frame : e.g. Read SYS _DIAG2 (OC error of HB 1-4) Consistent information : Both Load Error bit and HB 1_HS_OC report the Overcurrent failure detected during the previous SPI frame SPI Frame 1 SPI frame 2 (new)

Data Sheet 50 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.5 SPI Bit Mapping

The SPI Registers have been mapped as shown in Figure 25 and Figure 26 respectively. The control registers are READ/ WRITE re gisters. To set the control register to READ, bit 7 of the address byte (OP bit) must be programmed to ‘0’, otherwise ‘1’ for WRITE. The status registers are READ/CLEAR registers. To CLEAR any Status Register, bit 7 of the address byte must be set to ‘1’, otherwise ‘0’ for READ. Figure 25 TLE94110ES SPI Register mapping Note: LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 65432 1 0 Access type read/write 00000 LABT 1 read/write 10000 LABT 1 read/write 01000 LABT 1 read/write 11000 LABT 1 read/write 00100 LABT 1 read/write 10100 LABT 1 read/write 01100 LABT 1 read/write 11100 LABT 1 read/write 00010 LABT 1 read/write 10010 LABT 1 read/write 01010 LABT 1 read/write 11010 LABT 1 read 11001 LABT 1 read/clear 00110 LABT 1 read/clear 10110 LABT 1 read/clear 01110 LABT 1 read/clear 11110 LABT 1 read/clear 00001 LABT 1 read/clear 10001 LABT 1 read/clear 01001 LABT 1 S T A T U S R E G I S T E R S SYS_DIAG_1 : Global status 1 SYS_DIAG_2 : OP ERROR_1_STAT SYS_DIAG_3 : OP ERROR_2_STAT SYS_DIAG_4 : OP ERROR_3_STAT SYS_DIAG_5 : OP ERROR_4_STAT SYS_DIAG_6 : OP ERROR_5_STAT SYS_DIAG_7 : OP ERROR_6_STAT PWM1_DC_CTRL PWM2_DC_CTRL PWM3_DC_CTRL FW_OL_CTRL FW_CTRL CONFIG_CTRL

8 Data Bits [D7…D0]

for Configuration & Status Information

8 Address Bits [A7…A0]

HB_ACT_1_CTRL HB_ACT_2_CTRL HB_ACT_3_CTRL HB_MODE_1_CTRL HB_MODE_2_CTRL HB_MODE_3_CTRL PWM_CH_FREQ_CTRL

Data Sheet 51 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Figure 26 TLE94110ES Bit Mapping Note: LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 65432 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Access type HB_ACT_1_CTRL HB4_HS_EN HB4_LS_EN HB3_HS_EN HB3_LS_EN HB2_HS_EN HB2_LS_EN HB1_HS_EN HB1_LS_EN read/write 00000 LABT 1 HB_ACT_2_CTRL HB8_HS_EN HB8_LS_EN HB7_HS_EN HB7_LS_EN HB6_HS_EN HB6_LS_EN HB5_HS_EN HB5_LS_EN read/write 10000 LABT 1 HB_ACT_3_CTRL reserved reserved reserved reserved HB10_HS_EN HB10_LS_EN HB9_HS_EN HB9_LS_EN read/write 01000 LABT 1 HB_MODE_1_CTRL HB4_MODE1 HB4_MODE0 HB3_MODE1 HB3_MODE0 HB2_MODE1 HB2_MODE0 HB1_MODE1 HB1_MODE0 read/write 11000 LABT 1 HB_MODE_2_CTRL HB8_MODE1 HB8_MODE0 HB7_MODE1 HB7_MODE0 HB6_MODE1 HB6_MODE0 HB5_MODE1 HB5_MODE0 read/write 00100 LABT 1 HB_MODE_3_CTRL reserved reserved reserved reserved HB10_MODE1 HB10_MODE0 HB9_MODE1 HB9_MODE0 read/write 10100 LABT 1 PWM_CH_FREQ_CTRL FM_CLK_MOD1 FM_CLK_MOD0 PWM_CH3_FREQ_1 PWM_CH3_FREQ_0 PWM_CH2_FREQ_1 PWM_CH2_FREQ_0 PWM_CH1_FREQ_1 PWM_CH1_FREQ_0 read/write 01100 LABT 1 PWM1_DC_CTRL PWM1_DC_CTRL_7 PWM1_DC_CTRL_6 PWM1_DC_CTRL_5 PWM1_DC_CTRL_4 PWM1_DC_CTRL_3 PWM1_DC_CTRL_2 PWM1_DC_CTRL_1 PWM1_DC_CTRL_0 read/write 11100 LABT 1 PWM2_DC_CTRL PWM2_DC_CTRL_7 PWM2_DC_CTRL_6 PWM2_DC_CTRL_5 PWM2_DC_CTRL_4 PWM2_DC_CTRL_3 PWM2_DC_CTRL_2 PWM2_DC_CTRL_1 PWM2_DC_CTRL_0 read/write 00010 LABT 1 PWM3_DC_CTRL PWM3_DC_CTRL_7 PWM3_DC_CTRL_6 PWM3_DC_CTRL_5 PWM3_DC_CTRL_4 PWM3_DC_CTRL_3 PWM3_DC_CTRL_2 PWM3_DC_CTRL_1 PWM3_DC_CTRL_0 read/write 10010 LABT 1 FW_OL_CTRL reserved FW_HB5 FW_HB4 FW_HB3 FW_HB2 FW_HB1 OL_SEL_HS2 OL_SEL_HS1 read/write 01010 LABT 1 FW_CTRL reserved reserved reserved reserved FW_HB10 FW_HB9 FW_HB8 FW_HB7 read/write 11010 LABT 1 CONFIG_CTRL reserved reserved reserved reserved reserved DEV_ID2 DEV_ID1 DEV_ID0 read 11001 LABT 1 SYS_DIAG_1 : Global status 1 SPI_ERR LE VS_UV VS_OV NPOR TSD TPW 0 read/clear 00110 LABT 1 SYS_DIAG_2 : OP ERROR_1_STAT HB4_HS_OC HB4_LS_OC HB3_HS_OC HB3_LS_OC HB2_HS_OC HB2_LS_OC HB1_HS_OC HB1_LS_OC read/clear 10110 LABT 1 SYS_DIAG_3 : OP ERROR_2_STAT HB8_HS_OC HB8_LS_OC HB7_HS_OC HB7_LS_OC HB6_HS_OC HB6_LS_OC HB5_HS_OC HB5_LS_OC read/clear 01110 LABT 1 SYS_DIAG_4 : OP ERROR_3_STAT reserved reserved reserved reserved HB10_HS_OC HB10_LS_OC HB9_HS_OC HB9_LS_OC read/clear 11110 LABT 1 SYS_DIAG_5 : OP ERROR_4_STAT HB4_HS_OL HB4_LS_OL HB3_HS_OL HB3_LS_OL HB2_HS_OL HB2_LS_OL HB1_HS_OL HB1_LS_OL read/clear 00001 LABT 1 SYS_DIAG_6 : OP ERROR_5_STAT HB8_HS_OL HB8_LS_OL HB7_HS_OL HB7_LS_OL HB6_HS_OL HB6_LS_OL HB5_HS_OL HB5_LS_OL read/clear 10001 LABT 1 SYS_DIAG_7 : OP ERROR_6_STAT reserved reserved reserved reserved HB10_HS_OL HB10_LS_OL HB9_HS_OL HB9_LS_OL read/clear 01001 LABT 1 S T A T U S R E G I S T E R S S T A T U S R E G I S T E R S Register Name C O N T R O L R E G I S T E R S C O N T R O L R E G I S T E R S Data Bits D7…D0 Address Bits A7…A0

Data Sheet 52 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.6 SPI Control Registers

The Control Registers have a READ/WRITE access (see Chapter 7.5):

• The ‘POR’ value is defined by the regist er content after a POR or device Reset – The default value of all control registers is 0000 0000B with the exception of CONFIG_CTRL – The default value of the CO NFIG_CTRL register is 0000 0001B
• One 16-bit SPI command consists of two bytes (see Figure 25 and Figure 26), i.e. – an address byte – followed by a data byte
• The control bits are not cleared or changed automa tically by the device. This must be done by the microcontroller via SPI programming.
• Reading a register is done byte wise by setting the SPI bit 7 to “0” (= READ ONLY).
• Writing to a register is done byte wise by setting the SPI bit 7 to “1”.

Data Sheet 53 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.6.1 Control register definition

Note: The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the logic turns off this half-bridge. HB_ACT_1_CTRL Half-bridge output control 1 (Address Byte [OP] 000 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 r rw rw rw rw rw rw rw rw Field Bits Type Description HB4_HS_EN D7 rw Half-bridge output 4 high side switch enable 0B HS4 OFF/ High-Z (default value) 1B HS4 ON HB4_LS_EN D6 rw Half-bridge output 4 low side switch enable 0B LS4 OFF/ High-Z (default value) 1B LS4 ON HB3_HS_EN D5 rw Half-bridge output 3 high side switch enable 0B HS3 OFF/ High-Z (default value) 1B HS3 ON HB3_LS_EN D4 rw Half-bridge output 3 low side switch enable 0B LS3 OFF/ High-Z (default value) 1B LS3 ON HB2_HS_EN D3 rw Half-bridge output 2 high side switch enable 0B HS2 OFF/ High-Z (default value) 1B HS2 ON HB2_LS_EN D2 rw Half-bridge output 2 low side switch enable 0B LS2 OFF/ High-Z (default value) 1B LS2 ON HB1_HS_EN D1 rw Half-bridge output 1 high side switch enable 0B HS1 OFF/ High-Z (default value) 1B HS1 ON HB1_LS_EN D0 rw Half-bridge output 1 low side switch enable 0B LS1 OFF/ High-Z (default value) 1B LS1 ON

Data Sheet 54 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the logic turns off this half-bridge. HB_ACT_2_CTRL Half-bridge output control 2 (Address Byte [OP]100 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 r rw rw rw rw rw rw rw rw Field Bits Type Description HB8_HS_EN D7 rw Half-bridge output 8 high side switch enable 0B HS8 OFF/ High-Z (default value) 1B HS8 ON HB8_LS_EN D6 rw Half-bridge output 8 low side switch enable 0B LS8 OFF/ High-Z (default value) 1B LS8 ON HB7_HS_EN D5 rw Half-bridge output 7 high side switch enable 0B HS7 OFF/ High-Z (default value) 1B HS7 ON HB7_LS_EN D4 rw Half-bridge output 7 low side switch enable 0B LS7 OFF/ High-Z (default value) 1B LS7 ON HB6_HS_EN D3 rw Half-bridge output 6 high side switch enable 0B HS6 OFF/ High-Z (default value) 1B HS6 ON HB6_LS_EN D2 rw Half-bridge output 6 low side switch enable 0B LS6 OFF/ High-Z (default value) 1B LS6 ON HB5_HS_EN D1 rw Half-bridge output 5 high side switch enable 0B HS5 OFF/ High-Z (default value) 1B HS5 ON HB5_LS_EN D0 rw Half-bridge output 5 low side switch enable 0B LS5 OFF/ High-Z (default value) 1B LS5 ON

Data Sheet 55 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the logic turns off this half-bridge. HB_ACT_3_CTRL Half-bridge output control 3 (Address Byte [OP]010 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved HB10_HS_EN HB10_LS_EN HB9_HS_EN HB9_LS_EN r rw rw rw rw rw rw rw rw Field Bits Type Description reserved D7 rw Reserved. Always reads as ‘0’. reserved D6 rw Reserved. Always reads as ‘0’. reserved D5 rw Reserved. Always reads as ‘0’. reserved D4 rw Reserved. Always reads as ‘0’. HB10_HS_EN D3 rw Half-bridge output 10 high side switch enable 0B HS10 OFF/ High-Z (default value) 1B HS10 ON HB10_LS_EN D2 rw Half-bridge output 10 low side switch enable 0B LS10 OFF/ High-Z (default value) 1B LS10 ON HB9_HS_EN D1 rw Half-bridge output 9 high side switch enable 0B HS9 OFF/ High-Z (default value) 1B HS9 ON HB9_LS_EN D0 rw Half-bridge output 9 low side switch enable 0B LS9 OFF/ High-Z (default value) 1B LS9 ON

Data Sheet 56 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation HB_MODE_1_CTRL Half-bridge output mode control 1 (Address Byte [OP]110 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 HB4_MODE1 HB4_MODE0 HB3_MODE1 HB3_MODE0 HB2_MODE1 HB2_MODE0 HB1_MODE1 HB1_MODE0 r rw rw rw rw rw rw rw rw Field Bits Type Description HB4_MODEn (n = 0,1) D7:D6 rw Half-bridge output 4 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB3_MODEn (n = 0,1) D5:D4 rw Half-bridge output 3 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB2_MODEn (n = 0,1) D3:D2 rw Half-bridge output 2 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB1_MODEn (n = 0,1) D1:D0 rw Half-bridge output 1 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3

Data Sheet 57 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation HB_MODE_2_CTRL Half-bridge output mode control 2 (Address Byte [OP]001 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 HB8_MODE1 HB8_MODE0 HB7_MODE1 HB7_MODE0 HB6_MODE1 HB6_MODE0 HB5_MODE1 HB5_MODE0 r rw rw rw rw rw rw rw rw Field Bits Type Description HB8_MODEn (n = 0,1) D7:D6 rw Half-bridge output 8 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB7_MODEn (n = 0,1) D5:D4 rw Half-bridge output 7 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB6_MODEn (n = 0,1) D3:D2 rw Half-bridge output 6 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB5_MODEn (n = 0,1) D1:D0 rw Half-bridge output 5 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3

Data Sheet 58 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation HB_MODE_3_CTRL Half-bridge output mode control 3 (Address Byte [OP]101 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved HB10_MODE1 HB10_MODE0 HB9_MODE1 HB9_MODE0 r rw rw rw rw rw rw rw rw Field Bits Type Description reserved D7:D4 rw Reserved. Always reads as ‘0’. HB10_MODEn (n = 0,1) D3:D2 rw Half-bridge output 10 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3 HB9_MODEn (n = 0,1) D1:D0 rw Half-bridge output 9 mode select 00B No PWM (default value) 01B PWM control with PWM Channel 1 10B PWM control with PWM Channel 2 11B PWM control with PWM Channel 3

Data Sheet 59 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation PWM_CH_FREQ_CTRL PWM channel frequency select (Address Byte [OP]011 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 FM_CLK_ MOD1 FM_CLK_ MOD0 PWM_CH3_F REQ_1 PWM_CH3_F REQ_0 PWM_CH2_F REQ_1 PWM_CH2_F REQ_0 PWM_CH1_F REQ_1 PWM_CH1_F REQ_0 r rw rw rw rw rw rw rw rw Field Bits Type Description FM_MOD_EN D7:D6 rw FM Modulation Enable1) 00B No modulation (default) 01B Modulation frequency 15.625kHz 10B Modulation frequency 31.25kHz 11B Modulation frequency 62.5kHz 1) Not subject to production test, guaranteed by design. Frequency may deviate by ±10% PWM_CH3_FREQ_ n (n=0,1) D5:D4 rw PWM Channel 3 frequency select 00B PWM is stopped and off (default value) 01B PWM frequency 1 : 80Hz 10B PWM frequency 2 : 100Hz 11B PWM frequency 3 : 200Hz PWM_CH2_FREQ_ n (n=0,1) D3:D2 rw PWM Channel 2 frequency select 00B PWM is stopped and off (default value) 01B PWM frequency 1 : 80Hz 10B PWM frequency 2 : 100Hz 11B PWM frequency 3 : 200Hz PWM_CH1_FREQ_ n (n=0,1) D1:D0 rw PWM Channel 1 frequency select 00B PWM is stopped and off (default value) 01B PWM frequency 1 : 80Hz 10B PWM frequency 2 : 100Hz 11B PWM frequency 3 : 200Hz

Data Sheet 60 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation Note: Refer to Chapter 6.1.1 for more information on PWM operation PWM1_DC_CTRL PWM channel 1 duty cycle configuration (Address Byte [OP]111 00[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 PWM1_DC_ CTRL_7 PWM1_DC_ CTRL_6 PWM1_DC_ CTRL_5 PWM1_DC_ CTRL_4 PWM1_DC_ CTRL_3 PWM1_DC_ CTRL_2 PWM1_DC_ CTRL_1 PWM1_DC_ CTRL_0 r rw rw rw rw rw rw rw rw Field Bits Type Description PWM1_DC_CTRLn D7:D0 rw PWM Channel 1 Duty Cycle configuration (bit7=MSB; bit0) 0000 0000B 100% OFF (default value) xxxx xxxx B parts of 255 ON 1111 1111B 100% ON PWM2_DC_CTRL PWM channel 2 duty cycle configuration (Address [OP]000 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 PWM2_DC_ CTRL_7 PWM2_DC_ CTRL_6 PWM2_DC_ CTRL_5 PWM2_DC_ CTRL_4 PWM2_DC_ CTRL_3 PWM2_DC_ CTRL_2 PWM2_DC_ CTRL_1 PWM2_DC_ CTRL_0 r rw rw rw rw rw rw rw rw Field Bits Type Description PWM2_DC_CTRLn D7:D0 rw PWM Channel 2 Duty Cycle configuration (bit7=MSB; bit0) 0000 0000B 100% OFF (default value) xxxx xxxx B parts of 255 ON 1111 1111B 100% ON

Data Sheet 61 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation PWM3_DC_CTRL PWM channel 3 duty cycle configuration (Address Byte [OP]100 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 PWM3_DC_ CTRL_7 PWM3_DC_ CTRL_6 PWM3_DC_ CTRL_5 PWM3_DC_ CTRL_4 PWM3_DC_ CTRL_3 PWM3_DC_ CTRL_2 PWM3_DC_ CTRL_1 PWM3_DC_ CTRL_0 r rw rw rw rw rw rw rw rw Field Bits Type Description PWM3_DC_CTRLn D7:D0 rw PWM Channel 3 Duty Cycle configuration (bit7=MSB; bit0) 0000 0000B 100% OFF (default value) xxxx xxxx B parts of 255 ON 1111 1111B 100% ON

Data Sheet 62 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation FW_OL_CTRL Free-wheeling configuration and Open load detection setting of HS1 and HS2 (Address Byte [OP]010 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 FW_HB6 FW_HB5 FW_HB4 FW_HB3 FW_HB2 FW_HB1 OL_SEL_HS2 OL_SEL_HS1 r rw rw rw rw rw rw rw rw Field Bits Type Description FW_HB6 D7 rw HB6 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB5 D6 rw HB5 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB4 D5 rw HB4 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB3 D4 rw HB3 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB2 D3 rw HB2 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB1 D2 rw HB1 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling OL_SEL_HS2 D1 rw HS2 open load detection current and filter time select 0B High-current mode (default value) 1B LED Mode (Low current mode) OL_SEL_HS1 D0 rw HS1 open load detection current and filter time select 0B High current mode (default value) 1B LED Mode (Low current mode)

Data Sheet 63 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Refer to Chapter 6.1.1 for more information on PWM operation FW_CTRL Free-wheeling configuration (Address Byte [OP]110 10[LABT]1)B D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved FW_HB10 FW_HB9 FW_HB8 FW_HB7 r rw rw rw rw rw rw rw rw Field Bits Type Description reserved D7:D6 rw To be programmed as ‘0’. reserved D5 rw Reserved. Always reads as ‘0’. reserved D4 rw Reserved. Always reads as ‘0’. FW_HB10 D3 rw HB10 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB9 D2 rw HB9 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB8 D1 rw HB8 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling FW_HB7 D0 rw HB7 free-wheeling configuration 0B Passive free-wheeling (default value) 1B Active free-wheeling

Data Sheet 64 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) CONFIG_CTRL Device Configuration control (Address Byte [OP]110 01[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved reserved DEV_ID2 DEV_ID1 DEV_ID0 r rrrrrrrr Field Bits Type Description reserved D7:D3 r Always reads as ‘0’ DEV_IDn D2:D0 r Device/ derivative identifier Note: These bits can be used to verify the silicon content of the device 000B TLE94112EL/ES chip 001B TLE94110EL/ES chip 010B TLE94108EL/ES chip 011B TLE94106EL/ES chip 100B TLE94104EP chip 101B TLE94103EP chip 110B reserved 111B reserved

Data Sheet 65 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.7 SPI Status Registers

The Control Registers have a READ/CLEAR access (see also Chapter 7.5):

• The ‘POR Value’ of the Status registers (content after a POR or device Reset) and is 0000 0000B.
• One 16-bit SPI command consists of two bytes (see Figure 25 and Figure 26), i.e. – an address byte – followed by a data byte
• Reading a register is done byte wise by setting th e SPI bit 7 of the address byte to “0” (= Read Only).
• Clearing a register is done byte wise by se tting the SPI bit 7 of the address byte to “1”.
• SPI status registers are not cleared automatically by the device. This must be done by the microcontroller via SPI command.

Data Sheet 66 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI)

7.7.1 Status register definition

Note: The LE bit in the Global Status register is read only. It reflects an OR combination of the respective open load and overcurrent errors of the half-bridge channels. If all OC/ OL bits of the respective high- side and low-side channels are cleared to ‘0’, the LE bit will be automatically updated to ‘0’. SYS_DIAG1 Global status 1 (Address Byte [OP]001 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 SPI_ERR LE VS_UV VS_OV NPOR TSD TPW reserved r r c r r cr cr cr cr c r Field Bits Type Description SPI_ERR D7 rc SPI error detection 0B No SPI protocol error is detected (default value). 1B An SPI protocol error is detected. LE D6 r Load error detection (logic OR combination of Open Load and Overcurrent) 0B No Open Load and no Overcurrent detected (default value) 1B Open Load or Overcurrent detected in at least one of the power outputs. Error latched. Faulty output is latched off in case of Overcurrent VS_UV D5 rc VS Undervoltage error detection 0B No undervoltage on VS detected (default value) 1B Undervoltage on VS detected. Error latched and all outputs disabled. VS_OV D4 rc VS Overvoltage error detection 0B No overvoltage on VS detected (default value) 1B Overvoltage on VS detected. Error latched and all outputs disabled. NPOR D3 rc Not Power On Reset (NPOR) detection 0B POR on EN or VDD supply rail (default value) 1B No POR TSD D2 rc Temperature shutdown error detection 0B Junction temperature below temperature shutdown threshold (default value) B Junction temperature has reached temperature shutdown threshold. Error latched and all outputs disabled. TPW D1 rc Temperature pre-warning error detection 0B Junction temperature below temperature pre-warning threshold (default value) B Junction temperature has reached temperature pre-warning threshold. reserved D0 r Bit reserved. Always reads ‘0’.

Data Sheet 67 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) SYS_DIAG_2 : OP_ERROR_1_STAT Overcurrent error status of half-bridge outputs 1 - 4 (Address Byte [OP]101 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 r rc rc rc rc rc rc rc rc Field Bits Type Description HB4_HS_OC D7 rc High-side (HS) switch of half-bridge 4 overcurrent detection 0B No error on HS4 switch (default value) 1B Overcurrent detected on HS4 switch. Error latched and HS4 disabled. HB4_LS_OC D6 rc Low-side (LS) switch of half-bridge 4 overcurrent detection 0B No error on LS4 switch (default value) 1B Overcurrent detected on LS4 switch. Error latched and LS4 disabled. HB3_HS_OC D5 rc High-side (HS) switch of half-bridge 3 overcurrent detection 0B No error on HS3 switch (default value) 1B Overcurrent detected on HS3 switch. Error latched and HS3 disabled. HB3_LS_OC D4 rc Low-side (LS) switch of half-bridge 3 overcurrent detection 0B No error on LS3 switch (default value) 1B Overcurrent detected on LS3 switch. Error latched and LS3 disabled. HB2_HS_OC D3 rc High-side (HS) switch of half-bridge 2 overcurrent detection 0B No error on HS2 switch (default value) 1B Overcurrent detected on HS2 switch. Error latched and HS2 disabled. HB2_LS_OC D2 rc Low-side (LS) switch of half-bridge 2 overcurrent detection 0B No error on LS2 switch (default value) 1B Overcurrent detected on LS2 switch. Error latched and LS2 disabled. HB1_HS_OC D1 rc High-side (HS) switch of half-bridge 1 overcurrent detection 0B No error on HS1 switch (default value) 1B Overcurrent detected on HS1 switch. Error latched and HS1 disabled. HB1_LS_OC D0 rc Low-side (LS) switch of half-bridge 1 overcurrent detection 0B No error on LS1 switch (default value) 1B Overcurrent detected on LS1 switch. Error latched and LS1 disabled.

Data Sheet 68 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) SYS_DIAG_3 : OP_ERROR_2_STAT Overcurrent error status of half-bridge outputs 5 - 8 (Address Byte [OP]011 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 r rc rc rc rc rc rc rc rc Field Bits Type Description HB8_HS_OC D7 rc High-side (HS) switch of half-bridge 8 overcurrent detection 0B No error on HS8 switch (default value) 1B Overcurrent detected on HS8 switch. Error latched and HS8 disabled. HB8_LS_OC D6 rc Low-side (LS) switch of half-bridge 8 overcurrent detection 0B No error on LS8 switch (default value) 1B Overcurrent detected on LS8 switch. Error latched and LS8 disabled. HB7_HS_OC D5 rc High-side (HS) switch of half-bridge 7 overcurrent detection 0B No error on HS7 switch (default value) 1B Overcurrent detected on HS7 switch. Error latched and HS7 disabled. HB7_LS_OC D4 rc Low-side (LS) switch of half-bridge 7 overcurrent detection 0B No error on LS7 switch (default value) 1B Overcurrent detected on LS7 switch. Error latched and LS7 disabled. HB6_HS_OC D3 rc High-side (HS) switch of half-bridge 6 overcurrent detection 0B No error on HS6 switch (default value) 1B Overcurrent detected on HS6 switch. Error latched and HS6 disabled. HB6_LS_OC D2 rc Low-side (LS) switch of half-bridge 6 overcurrent detection 0B No error on LS6 switch (default value) 1B Overcurrent detected on LS6 switch. Error latched and LS6 disabled. HB5_HS_OC D1 rc High-side (HS) switch of half-bridge 5 overcurrent detection 0B No error on HS5 switch (default value) 1B Overcurrent detected on HS5 switch. Error latched and HS5 disabled. HB5_LS_OC D0 rc Low-side (LS) switch of half-bridge 5 overcurrent detection 0B No error on LS5 switch (default value) 1B Overcurrent detected on LS5 switch. Error latched and LS5 disabled.

Data Sheet 69 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) Note: Unused or not connected outputs for lower derivatives, i.e. TLE94110ES, TLE94108ES and TLE94106ES will be defined as ‘reserved’, always reads as ‘0’ SYS_DIAG_4 : OP_ERROR_3_STAT Overcurrent error status of half-bridge outputs 9 - 12(Address Byte [OP]111 10[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved HB10_ HS_OC HB10_LS_OC HB9_HS_OC HB9_LS_OC r rc rc rc rc rc rc rc rc Field Bits Type Description reserved D7 rc Reserved. Always reads as ‘0’. reserved D6 rc Reserved. Always reads as ‘0’. reserved D5 rc Reserved. Always reads as ‘0’. reserved D4 rc Reserved. Always reads as ‘0’. HB10_HS_OC D3 rc High-side (HS) switch of half-bridge 10 overcurrent detection 0B No error on HS10 switch (default value) 1B Overcurrent detected on HS10 switch. Error latched and HS10 disabled. HB10_LS_OC D2 rc Low-side (LS) switch of half-bridge 10 overcurrent detection 0B No error on LS10 switch (default value) 1B Overcurrent detected on LS10 switch. Error latched and LS10 disabled. HB9_HS_OC D1 rc High-side (HS) switch of half-bridge 9 overcurrent detection 0B No error on HS9 switch (default value) 1B Overcurrent detected on HS9 switch. Error latched and HS9 disabled. HB9_LS_OC D0 rc Low-side (LS) switch of half-bridge 9 overcurrent detection 0B No error on LS9 switch (default value) 1B Overcurrent detected on LS9 switch. Error latched and LS9 disabled.

Data Sheet 70 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) SYS_DIAG_5 : OP_ERROR_4_STAT Open load error status of half-bridge outputs 1 - 4 (Address Byte [OP]000 01[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 r rc rc rc rc rc rc rc rc Field Bits Type Description HB4_HS_OL D7 rc High-side (HS) switch of half-bridge 4 open load detection 0B No error on HS4 switch (default value) 1B Open load detected on HS4 switch. Error latched. HB4_LS_OL D6 rc Low-side (LS) switch of half-bridge 4 open load detection 0B No error on LS4 switch (default value) 1B Open load detected on LS4 switch. Error latched. HB3_HS_OL D5 rc High-side (HS) switch of half-bridge 3 open load detection 0B No error on HS3 switch (default value) 1B Open load detected on HS3 switch. Error latched. HB3_LS_OL D4 rc Low-side (LS) switch of half-bridge 3 open load detection 0B No error on LS3 switch (default value) 1B Open load detected on LS3 switch. Error latched. HB2_HS_OL D3 rc High-side (HS) switch of half-bridge 2 open load detection 0B No error on HS2 switch (default value) 1B Open load detected on HS2 switch. Error latched. HB2_LS_OL D2 rc Low-side (LS) switch of half-bridge 2 open load detection 0B No error on LS2 switch (default value) 1B Open load detected on LS2 switch. Error latched. HB1_HS_OL D1 rc High-side (HS) switch of half-bridge 1 open load detection 0B No error on HS1 switch (default value) 1B Open load detected on HS1 switch. Error latched. HB1_LS_OL D0 rc Low-side (LS) switch of half-bridge 1 open load detection 0B No error on LS1 switch (default value) 1B Open load detected on LS1 switch. Error latched.

Data Sheet 71 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) SYS_DIAG_6 : OP_ERROR_5_STAT Open load error status of half-bridge outputs 5 - 8 (Address Byte [OP]100 01[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 r rc rc rc rc rc rc rc rc Field Bits Type Description HB8_HS_OL D7 rc High-side (HS) switch of half-bridge 8 open load detection 0B No error on HS8 switch (default value) 1B Open load detected on HS8 switch. Error latched. HB8_LS_OL D6 rc Low-side (LS) switch of half-bridge 8 open load detection 0B No error on LS8 switch (default value) 1B Open load detected on LS8 switch. Error latched. HB7_HS_OL D5 rc High-side (HS) switch of half-bridge 7 open load detection 0B No error on HS7 switch (default value) 1B Open load detected on HS7 switch. Error latched. HB7_LS_OL D4 rc Low-side (LS) switch of half-bridge 7 open load detection 0B No error on LS7 switch (default value) 1B Open load detected on LS7 switch. Error latched. HB6_HS_OL D3 rc High-side (HS) switch of half-bridge 6 open load detection 0B No error on HS6 switch (default value) 1B Open load detected on HS6 switch. Error latched. HB6_LS_OL D2 rc Low-side (LS) switch of half-bridge 6 open load detection 0B No error on LS6 switch (default value) 1B Open load detected on LS6 switch. Error latched. HB5_HS_OL D1 rc High-side (HS) switch of half-bridge 5 open load detection 0B No error on HS5 switch (default value) 1B Open load detected on HS5 switch. Error latched. HB5_LS_OL D0 rc Low-side (LS) switch of half-bridge 5 open load detection 0B No error on LS5 switch (default value) 1B Open load detected on LS5 switch. Error latched.

Data Sheet 72 1.0 2020-09-29 TLE94110ES Serial Peripheral Interface (SPI) SYS_DIAG_7 : OP_ERROR_6_STAT Open load error status of half-bridge outputs 9 - 12 (Address Byte [OP]010 01[LABT]1B) D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved HB10_HS_OL HB10_LS_OL HB9_HS_OL HB9_LS_OL r rc rc rc rc rc rc rc rc Field Bits Type Description reserved D7:D4 rc Reserved. Always reads as ‘0. HB10_HS_OL D3 rc High-side (HS) switch of half-bridge 10 open load detection 0B No error on HS10 switch (default value) 1B Open load detected on HS10 switch. Error latched. HB10_LS_OL D2 rc Low-side (LS) switch of half-bridge 10 open load detection 0B No error on LS10 switch (default value) 1B Open load detected on LS10 switch. Error latched. HB9_HS_OL D1 rc High-side (HS) switch of half-bridge 9 open load detection 0B No error on HS9 switch (default value) 1B Open load detected on HS9 switch. Error latched. HB9_LS_OL D0 rc Low-side (LS) switch of half-bridge 9 open load detection 0B No error on LS9 switch (default value) 1B Open load detected on LS9 switch. Error latched.

Data Sheet 73 1.0 2020-09-29 TLE94110ES

Application Information

8 Application Information

Note: The following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. The function of the described circuits must be verified in the real application.

8.1 Application Diagram

Figure 27 Application example for DC-motor loads VS2 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 VDD EN SDO SDI CSN SCLK 60Ω CANH 47nF 60Ω CANL CAN-H CAN-L SP LIT VBAT 1kΩ WK 22nF, 50V 10kΩ WK µC SDO SDI /CS SCLK VCC2 VCCHSCAN 10µF INT RO VS VBAT VBAT VS VCC1 VDD TLE94110ESTLE9263 10 0nF GND GND 10kΩ VDD OUT 7 OUT 8 OUT 9 OUT 10 100nF10µF 6 motors in non-cascaded configuration + 4 motors in cascaded configuration100nF Landing pads for ceramic capacitors at OUTx Series resistors are recommended if VS1/2 of the TLE94110ES are protected by an active reverse polarity protection VS1 GND GND GND GND

Data Sheet 74 1.0 2020-09-29 TLE94110ES Figure 28 Application example for side-mirror control Notes on the application example 1. Series resistors between the microc ontroller and the signal pins of the TLE94110ES are recommended if an active reverse polarity protection (MOSFET) is used to protect VS1 and VS2 pins. These resistors limit the current between the microcontroller and the device during negative transients on VBAT (e.g. ISO/TR 7637 pulse 1) 2. Landing pads for ceramic capacitors at the outputs of the TLE94110ES as close as possible to the connectors are recommended (the ceramic capacitors are not populated if unused). These ceramic capacitors can be mounted if a higher performance in term of ESD capability is required. 3. The electrolytic capa citor at the VSx pins should be dimensioned in order to prevent the VS voltage from exceeding the absolute maximum rating. PWM operation with a too low capacitance can lead to a VS voltage overshoot, which results in a VS overvoltage detection. VS2 OUT 9 OUT 10 M OUT 1 OUT 2 VDD EN SDO SDI CSN SCLK Embedded Power IC VS VBAT VBAT VS VDDP TLE94110ES GND OUT 3 OUT 4 100nF 100nF Landing pads for ceramic capacitors at OUTx Series resistors are recommended if the VS1/2 of the TLE94110ES are protected by an active reverse polarity protection VS1 GND GND GND GND TLE984xLIN M OUT 5 OUT 6 OUT 7 OUT 8 M Reverse battery protection PROFETTM VBAT VBAT M x-adjustment y-adjustment Mirror fold Current < 3.6A

Data Sheet 75 1.0 2020-09-29 TLE94110ES

1. Not used (NU) pins and unused outputs are recommended to be left unconnected (open) in the application. If NU pins or unused output pins are routed to an external connector which leaves the PCB, then these outputs should have provision for a zero ohm jumper (depopulated if unused) or ESD protection. In other words, NU and unused pins should be treated like used pins. 5. Place bypass ceramic capacitors as close as possible to the VSx pins, with shortest connections the GND pins and GND layer, for best EMC performance

Data Sheet 76 1.0 2020-09-29 TLE94110ES

8.2 Thermal applic ation information

Ta = 85°C, Ch1 to Ch10 are dissipating a total of 1.35W (0.135W each). Figure 29 ZthJA Curve for different PCB setups Figure 30 ZthJC Curve Zth-ja [K/W] time [sec] Zth-ja for TLE94110ES 1s0p / 600 mm² / +85 °C 1s0p / 300 mm² / +85 °C 1s0p / footprint/ +85 °C 2s2p / +85 °C 0.5 1.5 2.5 Zth-jc [K/W] time [sec] Zth-jc for TLE94110ES Tamb = +85 °C

Data Sheet 77 1.0 2020-09-29 TLE94110ES

8.3 EMC Enhancement

In the event the emissions of the device exceed the allowable limits, a modulation of the oscillator frequency is incorporated to reduce eventual harmonics of the 8MHz base clock. The frequencies can be selected based on the resolution bandwidth of the peak detector during EMC testing. The selection is achieved by setting the FM_CLK_MODn bits in the PWM_CH_FREQ_CTRL register as follows: 00B: OFF 01B: FM CLK=15.625 kHZ 10B: FM CLK=31.25 kHz 11B: FM CLK=62.5 kHz

Data Sheet 78 1.0 2020-09-29 TLE94110ES Package Outlines

9 Package Outlines

Figure 31 PG-TSDSO-24 (Plastic/Plastic Green - Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e lead-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Data Sheet 79 1.0 2020-09-29 TLE94110ES

Revision History

1.0 2020-09-29 Initial release

Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™ , C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP ™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, Ec onoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, Ga NpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LI TIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, O PTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PR OFET™, PRO-SIL™, RASIC™, REAL 3™, SmartLEWIS™, SOLID FLAS H™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™. Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2020-09-29 Published by Infineon Technologies AG

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