TLE8888-1QK

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Rev. 1.1, 2014-08-20 TLE8888-1QK Engine Management System IC for 4 Cylinder Cars Engine Management System IC TLE8888-1QK TLE8888QK TLE8888-2QK

Data Sheet 2 Rev. 1.1, 2014-08-20 TLE8888-1QK Table of Contents Table of Contents

Data Sheet 3 Rev. 1.1, 2014-08-20

Data Sheet 4 Rev. 1.1, 2014-08-20 TLE8888-1QK Table of Contents

TLE8888-1QK LQFP-100 TLE8888-1QK TLE8888QK LQFP-100 TLE8888QK TLE8888-2QK LQFP-100 TLE8888-2QK Data Sheet 5 Rev. 1.1, 2014-08-20 Engine Management System IC TLE8888-1QK 1O v e r v i e w

Features

• Voltage pre-regulator
• Integrated 5V regulator
• 2 integrated 5V trackers
• Standby regulator
• Separate internal supply
• Voltage monitoring
• High speed CAN interface with wake up by bus
• LIN interface with high speed mode for K-Line operation
• Variable reluctance sensor interface
• Micro Second Channel interface (MSC) with low voltage differential signal (LVDS) inputs pads for low EME
• SPI and direct control inputs for high flexibility
• Main relay driver
• Ignition Key detection with key off delay output
• Wake up input
• Engine off timer
• 4 low side power stages especi ally to drive injectors ( Ron=550mΩ) with enable input
• 3 low side power stages ( Ron=350mΩ)
• 6 push pull stages for driving on-board MOSFET with drain feedback
• 7 low side power stages especially to drive relays ( Ron=1.5Ω), one with delayed switch off functionality
• 4 half bridge stages for hi gh flexibility, one with delayed switch off functionality
• 4 push pull stages for driving on- and off- board IGBT with back supply suppression and high voltage capability
• Open-load, short-to-GND and short-to-BAT diagnostic
• Over temperature and short-to-BAT protection
• Monitoring watchdog module
• Green Product (RoHS compliant)
• AEC Qualified

Description

The device is a U-Chip suitable for automotive engine management systems. It contains the basic functionality to supply the micro controller and the E CU, establish the communication on- and off- board and drive EMS typical actuators. Furthermore it controls the main relay driver.

Data Sheet 6 Rev. 1.1, 2014-08-20 TLE8888-1QK Overview Device Variants TLE8888QK and TLE8888-2QK The device variants TLE8888QK and TLE8888-2QK differ from the main version TLE8888-1QK in the watchdog functionality. The TLE8888QK has a fixed set of parameter for th e watchdog (see datasheet addendum “TLE8888QK - Addendum”). For the TLE8888-2QK the watchdog function is disabled (see datasheet addendum “TLE8888-2QK - Addendum”). Only the main version TLE8888-1QK is described in this datasheet. For order conditions please contact the nearest Infineon Technologies office.

Data Sheet 7 Rev. 1.1, 2014-08-20

1.1 Abbreviations

SPI Serial peripheral interface LVDS Low voltage differential signal EME Electromagnetic emission EMI Electromagnetic interference LIN Local interconnect network HS CAN High speed controller area network

Data Sheet 8 Rev. 1.1, 2014-08-20 TLE8888-1QK Block Diagram

2 Block Diagram

Power Stage 0.6A Half Bridge Power Stage 4.5A Power Stage 2.2A Linear Regulator (Tracker) V5V T5V1 BAT VG V6V T5V2 Linear Pre-regulator Linear Regulator Linear Regulator (Tracker) Vref V5V Vref Key Off Delay KOFFDO to internal supply Main Relay Driver Key and WK Detection KEY WK MR Voltage Monitoring Chargepump CP BATPA BATPB OUT21 OUT24 OUT22 OUT23 Power Stage 2.2A OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B OUT5A OUT5B Power Stage 4.5A OUT5C OUT6A OUT6B OUT6C OUT7A OUT7B OUT7C Half Bridge OUT14 OUT15 OUT17 OUT18 Power Stage 0.6A OUT16 OUT19 OUT20 VR Sensor Interface VRIN1 VRIN2 VROUT LIN Interface LINIO LINTX LINRX DFB8 OUT8 DFB9 OUT9 DFB10 OUT10 DFB11 OUT11 DFB12 OUT12 DFB13 OUT13 Push Pull Driver 20mA DFBx Diagnosis CAN Interface Wake Receiver CANH CANTX CANRX CANL Monitoring Watchdog VDDIO MON RST IN12 IN1 SIP SIN FCLP FCLN CSN SDO MSC/SPI InterfaceDirect Drive Inputs AGND PGND Exposed Pad Control Logic Standby Supply BATSTBY V5VSTBY Ignition Driver Ignition Driver 20mA IGN1 IGN3 IGN4 IGN2 Engine Off Timer EOTEN CANWKEN INJEN IGNEN PGND Exposed pad internally connected to PGND pins V5VCAN

Data Sheet 9 Rev. 1.1, 2014-08-20

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration

3.2 Pin Definitions and Functions

Pin Symbol Function Function

1 RST IN/OUT Reset; Bidirectional pin for reset functions

2 MON IN/OUT Monitor; Bidirectional pin for monitoring functions

3 CSN IN MSC/SPI slave chip select; Single ended chip select for MSC and SPI

4 SDO OUT MSC/SPI serial data output; Output for MSC and SPI

5 SIP IN MSC/SPI Data input; positive data input of LVDS in MSC mode or single ended

n.c. INJEN KOFFDO IGNEN EOTEN CANWKEN V5VCAN CANH

Data Sheet 10 Rev. 1.1, 2014-08-20 TLE8888-1QK Pin Configuration

6 SIN IN MSC data input or select input; negative data input of LVDS in MSC mode or

7 FCLP IN MSC/SPI Clock input; positive clock input of LVDS in MSC mode or single

ended clock input in SPI mode

8 FCLN IN Select input or MSC clock input; negative clock input of LVDS in MSC mode

or select input for single ended mode (SPI or MSC)

9 T5V1 OUT 5V tracker; Supply voltage for off- board sensors

10 T5V2 OUT 5V tracker; Supply voltage for off- board sensors

11 V5V OUT 5V supply; Supply voltage for main functions of the ECU

12 V6V IN Source of external pre-regulator

13 VG OUT Gate of external pre-regulator

14 OUT7A OUT Low side power stage; Must be connected to OUT7B and OUT7C without

15 OUT7B OUT Low side power stage; Must be connected to OUT7A and OUT7C without

16 OUT7C OUT Low side power stage; Must be connected to OUT7A and OUT7B without

17 OUT20 OUT Low side small signal stage;

18 OUT19 OUT Low side small signal stage;

19 n.c. leave open or connect to GND

20 VDDIO Supply Supply input for logic level inputs and outputs

21 VROUT OUT Output of variable reluctance sensor interface; Digital output to micro

22 LINTX IN Transmit digital input for LIN interface;

23 LINRX OUT Receive digital output for LIN interface;

24 INJEN IN Injector enable input;

25 PGND GND Power ground; internally connected to cooling tab

26 KOFFDO OUT Key off delay output;

27 IGNEN IN Ignition enable input;

28 IN1 IN Parallel input; Input pin for direct control of power stage OUT1,

29 IN2 IN Parallel input; Input pin for direct control of power stage OUT2

30 IN3 IN Parallel input; Input pin for direct control of power stage OUT3

31 IN4 IN Parallel input; Input pin for direct control of power stage OUT4

32 IN5 IN Parallel input; Input pin for direct control of push pull state IGN1

33 IN6 IN Parallel input; Input pin for direct control of push pull state IGN2

34 IN7 IN Parallel input; Input pin for direct control of push pull state IGN3

35 IN8 IN Parallel input; Input pin for direct control of push pull state IGN4

36 IN9 IN Parallel input; Input pin for direct control of power stages, could be multiplexed

37 IN10 IN Parallel input; Input pin for direct control of power stages, could be multiplexed

38 IN11 IN Parallel input; Input pin for direct control of power stages, could be multiplexed

Pin Symbol Function Function

Data Sheet 11 Rev. 1.1, 2014-08-20

39 IN12 IN Parallel input; Input pin for direct control of power stages, could be multiplexed

40 EOTEN IN Engine off timer enable input;

41 V5VSTBY OUT 5V standby supply; Supply voltage in sleep mode

42 CANWKE

N IN Enable input for remote CAN wake up;

43 CANRX OUT Receive digital output for CAN;

44 CANTX IN Transmit digital input for CAN;

45 V5VCAN Supply 5V supply input for CAN;

46 CANH IN/OUT CAN bus high;

47 CANL IN/OUT CAN bus low;

48 WK IN Wake up input; Input signal and supply for MR

49 KEY IN Key input; Input signal and supply for MR

50 PGND GND Power ground; internally connected to cooling tab

51 VRIN2 IN Differential input of variable reluctance sensor; Analog input from sensor

52 VRIN1 IN Differential input of variable reluctance sensor; Analog input from sensor

53 BATSTBY Supply Battery input for standby supply; Battery supply voltage standby supply

54 BAT Supply Battery; Supply voltage for main functions of the device.

55 MR OUT Low side power stage for main relay;

56 OUT18 OUT Low side power stage;

57 OUT17 OUT Low side power stage;

58 OUT16 OUT Low side power stage;

59 OUT1A OUT Low side power stage; Must be connected to OUT1B without any parasitic

60 OUT1B OUT Low side power stage; Must be connected to OUT1A without any parasitic

61 OUT2A OUT Low side power stage; Must be connected to OUT2B without any parasitic

62 OUT2B OUT Low side power stage; Must be connected to OUT2A without any parasitic

63 OUT3A OUT Low side power stage; Must be connected to OUT3B without any parasitic

64 OUT3B OUT Low side power stage; Must be connected to OUT3A without any parasitic

65 OUT4A OUT Low side power stage; Must be connected to OUT4B without any parasitic

66 OUT4B OUT Low side power stage; Must be connected to OUT4A without any parasitic

67 OUT15 OUT Low side power stage;

68 OUT14 OUT Low side power stage;

69 DFB8 IN Drain Feedback; Related to OUT8

70 OUT8 OUT Push pull stage; To control on- board MOSFET

71 DFB9 IN Drain Feedback; Related to OUT9

72 OUT9 OUT Push pull stage; To control on- board MOSFET

73 DFB10 IN Drain Feedback; Related to OUT10

74 OUT10 OUT Push pull stage; To control on- board MOSFET

75 PGND GND Power ground; internally connected to cooling tab

76 DFB11 IN Drain Feedback; Related to OUT11

77 OUT11 OUT Push pull stage; To control on- board MOSFET

Pin Symbol Function Function

Data Sheet 12 Rev. 1.1, 2014-08-20 TLE8888-1QK Pin Configuration

78 DFB12 IN Drain Feedback; Related to OUT12

79 OUT12 OUT Push pull stage; To control on- board MOSFET

80 DFB13 IN Drain Feedback; Related to OUT13

81 OUT13 OUT Push pull stage; To control on- board MOSFET

82 LINIO IN/OUT BUS for LIN interface;

83 OUT5A OUT Low side power stage; Must be connected to OUT5B and OUT5C without

84 OUT5B OUT Low side power stage; Must be connected to OUT5A and OUT5C without

85 OUT5C OUT Low side power stage; Must be connected to OUT5A and OUT5B without

86 OUT24 OUT Half bridge stage;

87 BATPA Supply Battery; Supply voltage for half bridges and the charge pump; must be

connected to BATPB without any parasitic

88 OUT23 OUT Half bridge stage;

89 OUT22 OUT Half bridge stage;

90 BATPB Supply Battery; Supply voltage for half bridges and the charge pump; must be

connected to BATPA without any parasitic

91 OUT21 OUT Half bridge stage;

92 OUT6A OUT Low side power stage; Must be connected to OUT6B and OUT6C without

93 OUT6B OUT Low side power stage; Must be connected to OUT6A and OUT6C without

94 OUT6C OUT Low side power stage; Must be connected to OUT6A and OUT6B without

95 CP OUT Charge pump; add external capacitance to stabilise charge pump voltage

96 IGN1 OUT Push pull stage; To control on- or off- board IGBT

97 IGN2 OUT Push pull stage; To control on- or off- board IGBT

98 IGN3 OUT Push pull stage; To control on- or off- board IGBT

99 IGN4 OUT Push pull stage; To control on- or off- board IGBT

100 AGND GND Signal ground; internally connected to PGND and cooling tab

g tab1) PGND GND Power ground; internally connected PGND pins 1) Cooling tab is also called exposed pad Pin Symbol Function Function

General Product Characteristics Data Sheet 13 Rev. 1.1, 2014-08-20

4 General Product Characteristics

General definition: VS is the short cut for all battery supplies of the TLE8888-1QK ( BAT, BATPA, BATPB, BATSTBY) unless otherwise specified GND is the short cut for all grounds of the TLE8888-1QK (AGND, PGND) unless otherwise specified. Table 2 Absolute Maximum Ratings 1) Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Voltages BATPA, BATPB, OUT8...13, DFB8...13 VBATPA,MR, VBATPB,MR, VOUT8...13,MR, VDFB8...13,MR, CP VCP,MR -0.3 – 45 V -0.3V< VCP-VBATPA<5V P_4.2 VOUT14..20,MR -0.3 – 50 V OUTn is switched off, clamping is allowed according Chapter 9.6 P_4.3 V6V VV6V,MR -0.3 – 10 V – P_4.4 VG VVG,MR -0.3 – 12 V VVG-VV6V<5V P_4.5 V5V, V5VSTBY, VDDIO, V5VCAN VV5V,MR, VV5VSTBY,MR VVDIO,MR, VV5VCAN,MR T5V1, T5V2, IGN1...4 VT5V1,MR, VT5V2,MR, VIGN1...4,MR -1 – 40 V – P_4.7 BAT, BATSTBY, KEY, WK, MR VBAT,MR, VKEY,MR, VWK,MR, VBATSTBY,MR, VMR,MR -16 – 40 V – P_4.8 IN1...12, SIP, SIN, FCLP, FCLN, CSN, LINTX, CANTX, IGNEN, INJEN, CANWKEN, EOTEN VIN1...12,MR, VFCLP,MR, VFCLN,MR, VSIP,MR, VSIN,MR, VCSN,MR, VLINTX,MR, VCANTX,MR, VIGNEN,MR, VINJEN,MR, VEOTEN,MR, VCANWKEN,MR

General Product Characteristics Data Sheet 14 Rev. 1.1, 2014-08-20 SDO, RST,VROUT, LINRX, CANRX VSDO,MR, VRST,MR, VVROUT,MR, VLINRX,MR, VCANRX,MR -0.3 – VDDIO +0.3 V both conditions must be observed P_4.31 -0.3 – 5.5 V MON, KOFFDO VMON,MR, VKOFFDO,MR -0.3 – V5V+0. V both conditions must be observed P_4.10 -0.3 – 5.5 V VRIN1 VVRIN1,MR -0.3 – 40 V VRIN2 open P_4.11 VRIN2 VVRIN2_MR -0.3 – 40 V VRIN1 open P_4.12 LINIO, CANH, CANL V LINIO,MR, VCANH,MR, VCANL,MR 0.3 V– P_4.14 Currents Common Mode Input Current of VRIN1 and VRIN2 I VRIN,CM,MR -5 – 5 mA I VRIN,CM,MR=I VRIN1+I VRIN2 P_4.16 Common Mode Input Current of VRIN1 and VRIN2, non permanent I VRIN,CM,MR -15 – 15 mA I VRIN,CM,MR=I VRIN1+I VRIN2 2), maximum duty cycle 60% and maximum on time of 1ms, 100h P_4.34 Differential Current of VRIN1 and VRIN2 ΔI VRIN,MR -50 – 50 mA ΔI VRIN,MR=(I VRIN1-I VRIN2)/2 P_4.17 PGND IPGND,MR -25 – 25 A – P_4.18 Temperatures Junction Temperature Tj -40 – 150 °C 3) P_4.20 Storage Temperature Tstg -55 – 150 °C– P_4.21 ESD Susceptibility ESD Susceptibility VESDHBM -2 – 2 kV HBM 4) P_4.22 ESD Susceptibility BAT, BATPA, BATPB, T5V1, T5V2, BATSTBY, KEY, WK, MR, CANL, LINIO, VRIN1, VRIN2 to PGND VESD,HBM -4 – 4 kV HBM 4) P_4.23 Table 2 Absolute Maximum Ratings 1) (cont’d) Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

General Product Characteristics Data Sheet 15 Rev. 1.1, 2014-08-20 Notes 1. Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. ESD Susceptibility VESDCDM -500 – 500 V CDM 5) P_4.24 ESD Susceptibility Pin 1, 25, 26, 50, 51, 75, 76, and 100 (corner pins) VESD1, 25, 26, 50, 51, 75, 76, 100 -750 – 750 V CDM 5) P_4.25 1) not subject to production test 2) Current has to be limited when maximum voltages are exceeded 3) according to qualification 4) ESD susceptibility, HBM accord ing to EIA/JESD 22-A114F (1.5kΩ, 100pF) 5) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 Table 3 Functional Range Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Supply Voltage - Reduced Operation VBAT,ro 4.5 – 6 V reduced operation range, main relay and delayed off power stages are on if enabled, remaining functions not working P_4.26 Supply Voltage - Low Drop Range VBAT,ld 6 – 9 V low drop operation range, supply regulators working with supply out of the charge pump, standby supply regulator out of operation range P_4.27 Supply Voltage - Normal Operation range VBAT,nop 9 – 28 V normal operation range1) P_4.28 Table 2 Absolute Maximum Ratings 1) (cont’d) Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

General Product Characteristics Data Sheet 16 Rev. 1.1, 2014-08-20 Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Supply Voltage - Over Voltage Range VBAT,ov 28 – 40 V over voltage, power stages are switched off P_4.29 Supply Voltage transients2) dVBAT/dt -1 – 1 V/µs – P_4.30 1) over temperature due to bad RthJA of the ECU or overload can happen 2) not subject to production test, specified by design Table 4 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Junction to Case1) 1) Not subject to production test, specified by design. RthJC –2 . 4 –K / W – P_4.32 Junction to Ambient RthJA –––K / W 2) 2) EIA/JESD 52_2, FR4, 80 × 80 × 1.5 mm; 35 × Cu, 5 × Sn; 300 mm 2 P_4.33 Table 3 Functional Range (cont’d) Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 17 Rev. 1.1, 2014-08-20

5 Operation Behavior

The TLE8888-1QK has implemented the whole supply of an ECU. Therefore a complex control logic is implemented to provide several operation states. In this chapter

• the ramp up and down behavior and
• the status of the TLE8888-1QK during special conditions like 5V undervoltage is described. For the description of the monitoring watchdog module see Chapter 6. In Figure 3 the block diagram with all blocks affecting the status of the device and the ECU are shown. Following blocks are influenced during the different operation states and reset functions:
• Serial Interface MSC/SPI: with the serial interface the setup of the device is done
• Key input detection: start signal from key switch (KL15)
• Wake up input detection: additional start signal e.g. from external CAN with wake up by bus function
• Engine off timer: wake up signal in comparator mode
• Power supply: ECU 5V supply and 5V sensor supplies, 5V standby supply
• Voltage monitoring: supervision of all supplies (BAT, V5V, T5V1, T5V2)
• Main relay driver: controls external main relay to switch battery voltage to an ECU supply pin (see also application setups in Chapter 17)
• Power stages and half-bridges control block
• LIN/K-Line: transmission mode depends on operation state of the ECU
• CAN: transmission mode depends on operation state of the ECU, remote wake up function
• Reset outputs MON and RST
• Monitoring watchdog module: signature watchdog for safety applications
• Operation Mode Control The operation mode control block consists of:
• ramp up and down sequence control logic
• the reset control logic and
• status output logic.

Data Sheet 18 Rev. 1.1, 2014-08-20 TLE8888-1QK Operation Behavior Figure 3 Block diagram operation mode control

5.1 Operation States

In Figure 4 the state diagram of the whole ramp up and do wn sequence is shown. There are seven operation states:

• ECU sleep state: KEY and WK input are “low”, no wake up signals from engine off timer or CAN are active, main relay is off, the whole ECU inclusive TLE8888-1QK is not supplied, 5V standby supply is working if pin BATSTBY is supplied, engine off timer and CAN wake up circuits are active if enabled and supplied. Power Supply Main Relay Driver Power Stages Half Bridges LIN/K-Line Key Input Detection Monitoring Watchdog MSC/SPI Input RegisterOutput Register Operation Mode Control KEY CSN FCLP FCLN SIP SIN SDO MR LINIO MON RST BATPA V5V T5V1 T5V2 Voltage Monitoring BATSTBY V5VSTBY Wake Up Input DetectionWK BAT BATPB Engine Off Timer Battery Detection CAN & remote wake up CANWKEN CANL CANH EOTEN OUTx IGNx CANWKEN

Data Sheet 19 Rev. 1.1, 2014-08-20

• Supply ramp up state: KEY input or wake1) are “high” and the supply of the TLE8888-1QK starts working, the voltage of V6V, V5V, T5V1 and T5V2 are ramping up but the voltage levels are below the under voltage threshold. For wake up by wake1) the ramp up of the main supply has to be finished before the ramp up timer overflow. The main relay is switched on depending on the voltage level at the pin BAT (see Chapter 7.2)
• Normal operation state: KEY input or wake are “high” and main relay is switched on depending on the voltage level at the pin BAT or the status of bit MR in the status register OpStat0 (see Chapter 7.2), the whole ECU is supplied and the status of the different functions and registers is according Table 6 and Table 7.
• Afterrun state: KEY is “low” but afterrun enable bit is set and therefore the whole ECU is supplied, the status of the different functions and registers is according Table 6 and Table 7 and the micro controller can execute afterrun routines
• Afterrun reset state: the reset procedure before direct reentry in normal operation is executed if bit AR =1 in the configuration register OpConfig0
• General power down state: the supplies of the ECU (V5V, T5V1, T5V2) are disabled and the power down timer is counting, main relay remains in the switching status and the TLE8888-1QK is supplied to ensure the power down (V5V drops down to 0V) of the ECU, V5VSTBY is working if BATSTBY is supplied, all functions to external are disabled.
• Wake clear state: this state avoids permanent wake up in failure cases. The wake clear command is executed (function according setting bit WKCLR in the command register Cmd0). All wake signals which are active after the supply ramp up and the general power down state are reset. 1) description see Figure 4, Chapter 7.2, Chapter 7.4 and Chapter 12.2.4

Data Sheet 20 Rev. 1.1, 2014-08-20 TLE8888-1QK Operation Behavior Figure 4 Operation state diagram ECU Sleep Supply Ramp Up Normal Operation*Afterrun* KEY=1 or wake=1 KEY=0& wake=0 & AE=0 KEY filtered KEY si gnal RT_OF ramp up timer overflow AE afterrun enable bit AR afterrun reset configuration bit PDT_OF power down timer overflow PD_OF overflow of minimum one of the three PD counter POR internal power on reset SSOT_OF secure shut off timer overflow V5VUV under voltage of V5V active 0 … function inactive 1 … function active (e.g. V5VUV=1 Æ 5V supply is below undervoltage threshold V5VUV=0 Æ 5V supply is above undervoltage threshold) Afterrun Reset* AR=0 & KEY=1 AR=1 & KEY=1 wake=0 & KEY=0 & AE=0 * POR=1: active internal power on reset forces transition to ECU sleep (wake=0 & KEY=0) or supply ramp up mode (wake=1 or KEY=1) from all states PD_OF=1 or SSOT_OF=1 KEY=0 & wake=0 KEY=0 & wake=1 & RT_OF=1 Gerneral Power Down* KEY=0 & AE=1 (PD_ OF=1 or SSOT _OF =1) &KE Y=0 wake clear* PDT _OF=1 KEY=1 KEY=0 (KEY=1 or wake=1) & V5VUV=0 wake = WKINT or CANWK or EOTWK wake = 1: one of the signals WKINT, CANWK, EOTWK is „1" wake = 0: all signals are „0"

Data Sheet 21 Rev. 1.1, 2014-08-20 Description of the transitions: Table 5 Operation State Transitions Transition Condition Description from all states to ECU sleep state internal supply voltage < internal por threshold and KEY=0 and wake1)=02) internal power on reset is active and reset the whole digital logic, ECU sleep state is entered due to no wake up signal at KEY or wake from all states to supply ramp up state internal supply voltage < internal por threshold and KEY=1 or wake=12) internal power on reset is active and reset the whole digital logic, supply ramp up state is entered due to a wake up signal at KEY or wake ECU sleep state to supply ramp up state KEY>VKEY,th or wake=1 With a “high” voltage at KEY or wake the wake up of the TLE8888-1QK starts Supply ramp up state to ECU sleep state KEY<VKEY,th and wake=02) The external supply ramp up is not finished but the wake up signals are low Supply ramp up state to wake clear state KEY<VKEY,th and wake=12) and RT_OF=1 The KEY signal is low and the wake up signals are active. The ramp up timer has an overflow which indicates a ramp up problem of the external supply (e.g. short to GND). To avoid permanent high current consumption the internal wake signals must be reset to enter the ECU sleep state. Supply ramp up state to normal operation state KEY>VKEY,th or wake=1) and V5V>Vuv,V5V normal operation state is entered if the main supply voltage V5V is above the under voltage threshold, KEY is high or one of the wake up conditions are active Normal operation state to afterrun state KEY<VKEY,th and AE=12) KEY is “low” and afterrun function is enabled: no changes in the setup of the TLE8888-1QK Normal operation state to ECU sleep state AE=0 and KEY<VKEY,th and wake=02) normal shut off Normal operation state to general power down state (PD_OF=1 or SSOT_OF=1) and KEY<VKEY,th 2) KEY is low and watchdog error shut off with overflow of the power down counter or secure shut off due to expired secure shut off timer Afterrun state to ECU sleep state AE=0 and KEY< VKEY,th and wake=0 2) normal shut off in afterrun mode with the reset of the afterrun enable bit AE by the micro controller Afterrun state to general power down state PD_OF=1 or SSOT_OF=1 watchdog error shut off with overflow of the power down counter or secure shut off due to expired secure shut off timer Afterrun state to normal operation state KEY>VKEY,th and AR=02) reentry of normal operation with KEY on during afterrun operation, no reset is performed (AR=0) Afterrun state to afterrun reset state KEY>VKEY,th and AR=12) reentry of normal operation with KEY on during afterrun operation with reset (AR=1) Afterrun reset state to normal operation state transition to normal operation with the next active internal clock edge after entry to the afterrun reset state General power down state to wake clear state PDT_OF=1 with the power down timer overflow the reset of the internal wake signals must be performed

Data Sheet 22 Rev. 1.1, 2014-08-20 TLE8888-1QK Operation Behavior The two states:

• normal operation
• afterrun are reflected in the bit OM of the status register OpStat0. The power down time is defined with the bits PDT of the configuration register OpConfig0. In Figure 5 a sequence with wake up by KEY and go to sleep with afterrun mode is shown. Figure 5 Ramp up and down sequence diagram with wake up by KEY and afterrun mode

5.2 Reset and Operation Modes

The TLE8888-1QK provides several supervision functions which lead to some dedicated reset states and special operation modes of the device and the ECU. There are two bidirectional reset pins MON and RST implemented. For the behavior during reset of the reset pins MON and RST and the other status of the TLE8888-1QK see Table 6 and Table 7. Following reset functions and special states are implemented: Wake clear state to ECU sleep state KEY<VKEY,th after reset of the internal wake signals and KEY is low the ECU sleep state is entered, no unwanted wake up due to a failure condition will occur Wake clear state to supply ramp up state KEY>VKEY,th after reset of the internal wake signals and KEY is high the supply ramp up state is entered, no unwanted wake up due to a failure condition at the CAN bus and pin WK will occur 1) wake = WKINT or CANWK or EOTWK (see Chapter 7.2, Chapter 7.4 and Chapter 12.2.4) 2) including defined filter times Table 5 Operation State Transitions (cont’d) Transition Condition Description wake RST t t t ECU Sleep Supply Ramp Up Normal operationRamp UP/Down Statemachine Afterrun ECU Sleep WK KEY V5V VUVV5V AE t tpu,r

Data Sheet 23 Rev. 1.1, 2014-08-20

• Internal power on reset: the internal power on reset detection circuit monitors the voltage level of the internal supply. For an internal supply voltage below the internal power on reset threshold the whole digital logic of the TLE8888-1QK is reset which results in the ECU sleep state or supply ramp up state depending on the state of KEY and wake. If the voltage level for operation is high enough the 6V pre regulator is working. The 5V supplies are disabled till the internal supply level is over the power on threshold level.
• ECU power on reset: this is the reset at ramp up of the power supplies and the beginning of the operation. The pins RST and MON are pulled to GND to reset the micro controller and all devices connected to the pin MON. The device is reset to the initial reset status. The reset is released with a voltage at pin V5V higher than the V5V Under Voltage Detection Hysteresis after tpu,r.
• Reset during under voltage of the 5V supply V5V: this reset occurs during under voltage of the 5V ECU supply. The pins RST and MON are pulled to GND to reset the micro controller and all devices connected to the pin MON. The delayed switch off function is active regarding the configuration setup. The status of the main relay is according to the status of the wake up pins KEY and WK and the voltage level of the supply pin BAT.
• State during under voltage of the 5V supplies T5V1 and T5V2: with the under voltage detection of the tracker supplies diagnosis bits are set but there is no effect to the behavior of the device.
• Reset during over voltage of the 5V supply V5V: with the over voltage detection of the 5V ECU supply all functions of the device which have an effect externally or can lead to over current or over temperature are disabled (e.g. power stages, LIN/CAN/MSC/SPI communication). The pins RST and MON are low.
• State during over voltage of the 5V supplies T5V1 and T5V2: with the detection of over voltage of the tracker supplies diagnosis bits are set but there is no effect to the behavior of the device.
• Power stages switch off during over voltage of the battery supply BAT: For voltages at the supply pin BAT higher than the over voltage threshold the power stages are disabled to avoid too high clamping energy during switch off. Damage of the switches is prevented.
• Watchdog reset: If the reset counter is incremented and the reset is enabled (bit WDREN = 1) the micro controller is reset with a “low” at the pin RST. The power stages are disabled and the LIN/CAN communication is set to receive only mode.
• Software reset from micro controller: with the software reset command (command register CmdSR) the software reset is activated. The device is reset to the reset status defined in Table 6 and Table 7. The activation of the software reset triggers an increase of the power down counter by 1.
• Reset with an external forced “low” at RST: With a detected “low” at the RST pin the TLE8888-1QK is reset to the reset status defined in Table 6 and Table 7.
• Power stages switch off with an external forced “low” at MON: With a detected “low” at the MON pin the power stages are disabled (O1E to O24E, IGN1E to IGN4E are set to “0”). After MON=0 event the power stages must be enabled again.
• State with time out of the MSC communication: With the time out of the MSC communication the power stages are disabled (O1E to O24E, IGN1E to IGN4E are set to “0”). After the next valid received data frame the power stages must be enabled again.
• Afterrun reset: This reset is executed if the bit AR of register OpConfig0 is 1 and the transition from afterrun state to normal operation is triggered (definition see Table 7).

Data Sheet 24 Rev. 1.1, 2014-08-20Table 6 Overview Behavior at Reset and Operation Conditions (part 1) Effect to functions: Conditions Internal power on reset ECU power on reset Under voltage V5V Under voltage T5V1, T5V2 Over voltage V5V1) Over voltage T5V1, T5V2 Over voltage BAT notes forces state change only after transition from Supply Ramp Up to Normal Operation state for t pu,r timing see Chapter 8.7 and Table 8 timing see Chapter 8.7 timing see Chapter 8.7 and Table 8 timing see Chapter 8.7 timing see Chapter 8.7 Main relay en. Low Side switches / Half bridges / Push Pull Driver OUT17 and OUT21 with delayed switch off function dis. dis. delayed switch off activated en. delayed switch off activated en. dis. LIN/CAN communication dis. rec. only, after release setup acc. bits CAN, LIN, CANWE, LINWE3) rec. only, after release setup acc. bits CAN, LIN, CANWE, LINWE3) acc. bits CAN, LIN, CANWE, LINWE dis., after release setup acc. bits CAN, LIN, CANWE, LINWE acc. bits CAN, LIN, CANWE, LINWE acc. bits CAN, LIN, CANWE, LINWE MON (output function) “low” 4) “low” “low” no effect 5) “low” no effect 5) no effect5) RST (output function) “low” 4) “low” “low” no effect 5) “low” no effect 5) no effect5) Watchdog Sequence, Heartbeat Timer6) reset reset reset no effect reset no effect no effect WWD Error Counter, FWD pass counter, Total error counter reset reset reset no effect reset no effect no effect PD Counter reset reset reset no effect reset no effect no effect Reset Counter; SSOT reset reset reset no effect reset no effect no effect AR; CANWE; LINWE; FWDQUEST reset reset reset no effect reset no effect no effect AE; WWDConfig0; WDConfig0; watchdog diagnosis bits reset reset reset no effect reset no effect no effect

Data Sheet 25 Rev. 1.1, 2014-08-20 Logic and MSC/SPI register bits7)8) reset reset reset, diagnosis bit is set diagnosis bits are set no effect diagnosis bits are set diagnosis bit is set EOTWK, CANWK, WKINT no effect no effect reset no effe ct no effect no effect no effect 1) for voltages greater than the maximum ratings of pin V5V behavior is not guaranteed 2) according the definition in Chapter 7 3) after release of RST (transition from low to high) there is a time delay of tdel,r before configuration is enabled 4) active pull down if supply voltage is high enough 5) pull up of open drain output is active 6) start of watchdog sequence after release of reset 7) valid for all register bits which are not described in Table 6 or Table 7 8) During active delayed switch off mode some register bits related to the power stages are not reset, see Chapter 9.4 Table 6 Overview Behavior at Reset and Operation Conditions (part 1) (cont’d) Effect to functions: Conditions Internal power on reset ECU power on reset Under voltage V5V Under voltage T5V1, T5V2 Over voltage V5V1) Over voltage T5V1, T5V2 Over voltage BAT

Data Sheet 26 Rev. 1.1, 2014-08-20 Table 7 Overview Behavior at Reset and Operation Conditions (part 2) Effect to functions: Conditions Watchdog reset Safe State SW reset from micro controller MON switch off (input function) RST reset (input function) MSC time out afterrun reset no reset AR=0 reset AR=1 note status during reset pulse top,r status during reset pulse tint,r masked by MON output function masked by RST output function status till next valid MSC communication MSC/SPI communication Low Side switches / Half bridges / Push Pull Driver OUT17 and OUT21 with delayed switch off function no trigger if termination of delayed switch off function no trigger if terminatio n of delayed switch off function dis. 3) delayed switch off activated delayed switch off activated delayed switch off activated en. dis. LIN/CAN communication acc. bits CAN, LIN, CANWE, LINWE acc. bits CAN, LIN, CANWE, LINWE acc. bits CAN, LIN, CANWE, LINWE acc. bits CAN, LIN, CANWE, LINWE rec. only, after release setup acc. bits CAN, LIN, CANWE, LINWE2) acc. bits CAN, LIN, CANWE, LINWE acc. bits CAN, LIN, CANWE, LINWE rec. only, after release setup acc. bits CAN, LIN, CANWE, LINWE MON “low” “low” “low” 3) forced from outside “low” no effect 4) no effect4) “low” RST “low” no effect 4) no effect4) no effect4) forced from outside no effect4) no effect4) “low”

Data Sheet 27 Rev. 1.1, 2014-08-20 Watchdog Sequence, Heartbeat Timer5) reset no effect reset n o effect reset no effect no effect reset WWD Error Counter, FWD pass counter, Total error counter reset no effect reset n o effect reset no effect no effect reset PD Counter no effect no effect increment +1 no effect no effect no effect no effect no effect Reset Counter; SSOT no effect no effect no effect no effect no effect no effect no effect 6) no effect6) AR; CANWE; LINWE; FWDQUEST no effect no effect no effect no effect no effect no effect no effect no effect AE; WWDConfig0; WDConfig0; watchdog diagnosis bit reset no effect reset n o effect reset no effect no effect reset Logic and MSC/SPI register bits7)8) no effect no effect reset n o effect reset diagnosis bit is set no effect reset EOTWK, CANWK, WKINT no effect no effect no effect no effect no effect no effect no effect no effect 1) according the definition in Chapter 7 2) after release of RST (transition from low to high) there is a time delay of tdel,r before configuration is enabled 3) status for time top,r 4) pull up of open drain output is active 5) start of watchdog sequence after release of reset 6) SSOT reset due to KEY=1 7) valid for all register bits which are not described in Table 6 or Table 7 8) During active delayed switch off mode some register bits related to the power stages are not reset, see Chapter 9.4 Table 7 Overview Behavior at Reset and Operation Conditions (part 2) (cont’d) Effect to functions: Conditions Watchdog reset Safe State SW reset from micro controller MON switch off (input function) RST reset (input function) MSC time out afterrun reset no reset AR=0 reset AR=1

Data Sheet 28 Rev. 1.1, 2014-08-20 TLE8888-1QK Operation Behavior After a reset with pin RST the configuration of the CAN and LIN bus is delayed by the time tdel,r to avoid that undefined micro controller pins are affecting the buses. During this delay time the configuration bits can be changed by a write access to the register. Table 8 Reset Time Definition Reset Function Reset Time at RST Output Related Status Bits in Register OpStat1 internal power on reset all registers are reset ECU power on reset tpu,r Under voltage V5V tpu,r V5VUVR Over voltage V5V tpu,r V5VOVR Watchdog reset top,r WDRES RST reset forced from outside forced from outside RSTR Software reset from micro controller no effect all registers are reset 1) 1) internal reset with tint,r active Afterrun reset AR=”0” no effect AR=”1” top,r ARES

Data Sheet 29 Rev. 1.1, 2014-08-20

5.3 Electrical Characteris tics Operation Behavior

Table 9 Electrical Characteristics: Operation Behavior VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Internal power on reset threshold Vpor,int,th – – 2.8 V of internal supply voltage P_5.3.1 Supply voltage range for internal supply VBATP,int 4.5 – – V only valid if the charge pump has ramped up before voltage drop, both condition must be fulfilled to ensure no internal power on reset P_5.3.2 VV6V,int 3.5 – – V Power Down Timer Power down time 1 tpd,1 – 100 – ms – P_5.3.3 Power down time 2 tpd,2 – 200 – ms – P_5.3.4 Power down time 3 tpd,3 – 300 – ms – P_5.3.5 Power down time 4 tpd,4 – 400 – ms – P_5.3.6 Power down time accuracy tpd,a -10 – +10 % – P_5.3.7 Ramp Up timer Ramp up time tru 1 8 5– 6 5 0m s – P_5.3.8 MON In- Output Input low level Vil – – 0.29* V V– P_5.3.10 Input high level Vih 0.7*V5 V ––V – P_5.3.11 Input hysteresis Vihys 0.1 – 1 V – P_5.3.12 Pull up current Iimax -100 – – µA Vin=0V, pull up to V5V P_5.3.13 Input de-glitch time for low and high level detection Output low level operation Vol ––0 . 7 V Iout=2mA; VV5V=2.5V P_5.3.15 Output current capability Iomax 151) ––m A VMON=5V P_5.3.16 RST In- Output Input low level Vil – – 0.29* V DDIO V– P_5.3.17 Input high level Vih 0.7*V DDIO ––V – P_5.3.18 Input hysteresis Vihys 0.1 – 1 V – P_5.3.19

Data Sheet 30 Rev. 1.1, 2014-08-20 TLE8888-1QK Operation Behavior Pull up current Iimax -100 – – µA Vin=0V, pull up to VDDIO P_5.3.20 Input de-glitch time for low and high level detection Output low level operation Vol ––0 . 7 V Iout=2mA; VV5V=2.5V P_5.3.22 Output current capability Iomax 151) ––m A VRST=5V P_5.3.23 Reset Times Power up reset time tpu,r 12 16 20 ms – P_5.3.24 Operation reset time top,r 124m s – P_5.3.25 Internal reset time tint,r ––1µ s – P_5.3.26 Delay time after reset tdel,r 61 0 1 4 µ s – P_5.3.27 1) Application must ensure t hat current into this pin does not exceed this value. Table 9 Electrical Characteristics: Operation Behavior (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 31 Rev. 1.1, 2014-08-20

6 Monitoring Watchdog Modu le (Signature Watchdog)

The watchdog function is intended for a temporal and logical monitoring of the micro controller’s program sequence. In Figure 6 the block diagram of the monitoring module is drawn. The module has an interface to the MSC/SPI block. The monitoring of the micro controller is done by the separate check of the timing with the window watchdog and the logical operation check by the functional watchdog. Therefore the micro controller must send a window watchdog service command for the window watchdog and four response bytes for the functional check. The results of the checks affect the corresponding counter (window watchdog error counter or functional watchdog pass counter). Additionally a total error counter module is implemented which detects the occurrence of watchdog errors (the timing check or the functional is not pa ssed) and changes the status of the total error counter regardingly. For the independent functional watchdog and the total erro r counter a heartbeat is implemented to define the increment timing of both functions. Figure 6 Block diagram of the Monitoring Watchdog Function Micro Controller Interface Window Watchdog Statemachine Window Watchdog Error Counter Watchdog Heartbeat Increment Decrement Functional Watchdog Statemachine Functional Watchdog Pass Counter Decrement RST MON Response QuestionWindow Watchdog Service Command Pass WWD Pass FWD Error Check Statemachine fail Total Error Power Down Counter (Overflow ) OF OF Power down Restart Reset Counter (Overflow) Reset/Disable Signal Generation Fail WWD Total Error Counter OF fail Increment Decrement Increment Window Watchdog Power Down Counter (Overflow ) Functional Watchdog Power Down Counter (Overflow)

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 32 Rev. 1.1, 2014-08-20 The status of the counters (window watchdog error counte r, functional watchdog pass counter and total error counter) and the corresponding overfl ow signals are inputs to the watchdog reset, power down counter and the secure shut off timer. This information is used to affe ct the operation status of the TLE8888-1QK and the status of the pins MON and RST. The software of the micro controller has to make sure th at the program sequence and any safety critical parts of the micro controller are self tested by performing related routines according to the received questions. Table 10 Bit Name Register Type Description General WDRES OpStat1 status reset caused by wa tchdog (general status bit) RESC WdStat0 status reset counter value SSOTS WdStat0 status Secure shut off timer start status WDHBTPRE WDHBT0 status heartbeat timer pre divider value WDHBT WDHBT1 status heartbeat timer value WDHBTP WDConfig0 configuration definition of heartbeat peri od for functional watchdog and total error counter CANWE WDConfig1 configuration CAN operation mode during safe state LINWE WDConfig1 configuration LIN operation mode during safe state WDREN WDConfig1 configuration watchdog reset enable FWDQG WDConfig1 configuration Functional watchdog q uestion generation pattern setup MSCReadWd0 command Multi read command for WdStat0, TECStat, FWDStat0, FWDStat1, WdDiag, WWDStat, WDConfig0 and WWDConfig0 MSCReadWd1 command Multi read command for WDHBT0, WDHBT1, WdStat0 and WdStat1 WDHBTPSync Cmd command heartbeat period synchronization command WDHBTS Cmd0 command watchdog heartbeat timer sample command Window Watchdog WWDEC WWDStat status value of error counter for window watchdog WWDSCR WdStat0 status Window watchdog service command received status WWDPDC WdStat0 status power down counter value of window watchdog WWDECI WWDConfig1 configuration definition of the increment value of error counter for window watchdog WWDECD WWDConfig1 configuration definition of the decrement value of error counter for window watchdog WWDCWT WWDConfig0 configuration closed window time WWDOWT WWDConfig0 configuration open window time WWDServiceC md command window watchdog service command WWDSCE WdDiag diagnosis window watchdog service command too early WWDTO WdDiag diagnosis window watchdog time out WWDRES WdDiag diagnosis reset caused by window watchdog

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 33 Rev. 1.1, 2014-08-20

6.1 Window Watchdog

For the timing check the micro controller has to s end periodically the window watchdog service command WWDServiceCmd. The window watchdog is triggered correctly if the command is received inside the open window of the window watchdog sequence. The check result is used to change the value of the window watchdog error counter. If the check is pass ed the counter will be decremented an d for errors it will be incremented. Additionally a write access to configuration register WWDConfig0 causes also an incrementation of the window watchdog error counter. The incrementation of the window watchdog error coun ter (error is occurred) is an input for the total error counter (Chapter 6.3). In Figure 7 the state machine of the window watchdog is shown. The values for incrementation or decrementat ion can be set in the configuration register WWDConfig1. The window watchdog error counter is a 6 bit counter. The influence of the counter values to the operation behavior is shown in Table 12 and Table 13. The window watchdog sequence for the timing check cons ists of a closed window followed by an open window (see Figure 8). A watchdog sequence starts with:

• the release of a reset of the monitoring module (see Table 6 and Table 7 in Chapter 5.2)
• a window watchdog service command
• a write to the window time configuration register WWDConfig0
• a timer overflow of the watchdog timer In Figure 8 the two parts of one watchdog sequence are shown. After the power on reset it is running in an endless loop with the defined time for the open and closed window . It is only stopped at active reset signals or outside Functional Watchdog FWDQUEST FWDStat1 status question definition FWDRESPC FWDStat1 status response counter FWDPC FWDStat0 status pass counter value of functional watchdog FWDPDC WdStat1 status power down counter value of functional watchdog FWDPCI FWDConfig configuration definitio n of the increment value of pass counter for functional watchdog FWDPCD FWDConfig configuration definition of the decrement value of pass counter for functional watchdog FWDKQ WDConfig1 configuration Keep question function set up FWDRespCmd command response write command FWDRespSync Cmd command response write command wit h heartbeat synchronization at received response byte 0 FWDREA WdDiag diagnosis response erro r of actual question FWDREL WdDiag diagnosis response error of last answer FWDRES WdDiag diagnosis reset caused by functional watchdog Total Error Counter TEC TECStat status total error counter value TECPDC WdStat1 status power down counter value of total error counter part TECI TECConfig configuration definition of the increment value of total error counter TECD TECConfig configuration definition of the decrement value of total error counter TECRES WdDiag diagnosis reset caused by total error counter Table 10 (cont’d) Bit Name Register Type Description

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 34 Rev. 1.1, 2014-08-20 normal operating conditions Table 6 and Table 7 in Chapter 5.2. The timing of the window watchdog sequence can be set with a write command to the configuration register WWDConfig0 or directly with the data bits of the WWDServiceCmd. With a write access to the configuration register WWDConfig0 the watchdog window sequence is started and the window watchdog error counter is incremented. The check is passed if the command is received inside the open window. A command send too early or a missing command leads to an error. In the diagnosis register WdDiag the bit WWDSCE signalizes a window watchdog service command received too early and the bit WWDTO signalizes a time out (no window watchdog service command received before end of open window) of the last sequence. The diagnosis information is not cleared with the read out. The bit WWDSCR in the status register WdStat0 signalizes a received window watchdog service command at the last watchdog sequence. The reset of this bit is done with a readout of the bit or with the window watchdog time- out. Figure 7 State Diagram of the Window Watchdog Module Waiting for WWD service command Timing check Decrement WWD error counter Reset WWD error: Timer expired OR Write access to WWDConfig0 Inside open window WWD error: Outside open window Increment WWD error counter Start watchdog sequence WWD service command

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 35 Rev. 1.1, 2014-08-20 Figure 8 Watchdog Sequence Timing

6.2 Functional Watchdog

For the functional check the micro controller has to send with the commands FWDRespCmd (functional watchdog response command) or FWDRespSyncCmd (functional watchdog response and synchronisation command) the right four response bytes to the act ual question defined by the TLE8888-1QK. The response bytes are checked for correctness. A pass of the check triggers a decrement of the functional watchdog pass counter. A functional watchdog error (FWD error) is not affecting the functional watchdog pass counter but it is used for the total error counter as an input signal (see Chapter 6.3). A FWD error is defined as:

• received response byte 0 with FWDRespCmd and minimum one of the response bytes are wrong
• received response byte 0 with FWDRespSyncCmd and minimum one of the response bytes are wrong
• the watchdog heartbeat timer period synchronisation command WDHBTPSyncCmd is received In the diagnosis register WdDiag the bit FWDREA signalizes an error of the received response bytes to the actual question and the bit FWDREL signalizes an error of the response bytes of the last answer. With a read out the diagnosis bits are not cleared. To detect that the functional check is missing a heartbeat is implemented. With an heartbeat event the functional watchdog pass counter is incremented. An heartbeat event occurs:
• with expiring of the heartbeat period timer or
• with receiving the watchdog heartbeat period synchronisation command WDHBTPSyncCmd (response counter is also reset) or
• with receiving the functional watchdog response and synchronisation command FWDRespSyncCmd if response byte 0 is received The heartbeat period can be set by a writ e access to the configuration register WDConfig0 or by the watchdog heartbeat period synchronisation command WDHBTPSyncCmd. If the data is 000 0000 B the value of the heartbeat period is not changed. Behavior of the heartbeat period in case of changing the period time: WWD Service Command WWD Service Command WWD Service Command tC2 tO2 CSN tC1 tO1 tC3 WWD Service Command tC1 tO1 CSN tC1 tO1 tC2 WWD Service Command Time out Too early tO2 Correct Timing of WWDService Command Wrong Timing of WWDService Command

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 36 Rev. 1.1, 2014-08-20

• WDHBTPSyncCmd: the response counter and the heartbeat timer are reset and a heartbeat event is triggered, the new value of the period is executed with next period.
• write access to the configuration register WDConfig0: the new value of the period is effective after the write command. If the new value is lower than the actual heartbeat timer value then the heartbeat event is immediately triggered otherwise the actual period length is immediately changed to the new value. The functional watchdog pass counter is a six bit counter (see status register FWDStat0). The values for incrementation or decrementation can be set in the configuration register FWDConfig. The influence of the counter values to the operation behavior is shown in Table 12 and Table 13. In Figure 9 the state machine of the functional watchdog is shown. There are two possible principles available to serve the function watchdog:
• unsynchronized heartbeat and use of functional watchdog response command FWDRespCmd and write access to the configuration register WDConfig0 to change the heartbeat period time or
• heartbeat is started with receiving the function al watchdog response and synchronisation command FWDRespSyncCmd and use of the watchdog heartbeat period synchronisation command WDHBTPSyncCmd for changing the heartbeat period The commands can be used in all possible combinations without restrictions. Using FWDRespCmd has the advantage that with fast correct responses the decrement of the functional watchdog pass counter can be speed up. The bit FWDKQ in the configuration register WDConfig1 is used to enable the keep question function for the functional watchdog. If the bit is set in case of a passed functional check the next functional check procedure is done with the same question if minimum one of the bits WWDSCE or WWDTO is set (window watchdog error).

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 37 Rev. 1.1, 2014-08-20 Figure 9 Functional Watchdog State diagram

6.2.1 Question and Response Definition

The bits FWDQUEST in the watchdog status register FWDStat1 represent the actual valid question. The reset value is 0000 B and it will be changed regarding the definition of the state machine for the monitoring module (see Figure 7). The expected response is shown in Table 11. The answer of the micro controller is done by a write access to the command registers FWDRespCmd or FWDRespSyncCmd. The actual value of the bits FWDRESPC in the watchdog status register FWDStat1 defines the interpretation of the 8 bit content of these commands as RESP3 to RESP0 (definition see FWDRESPC). Waiting for response 3 Response check FWD pass counter change1.) AND Restart Heartbeat Timer Define next question Reset FWDRespCmd OR FW DRespSynchCmd rec eived Correct response Define start question Increment FWD pass counter AND Restart Heartbeat Timer Waiting for response 2 Response check Waiting for response 1 Response check Waiting for response 0 Response check FWD error : Wrong response2.) Decrement FWD pass counter Correct response Response check 1.)change value = sum of decrement and increment value 2.) wrong response event is also input for the error check statemachine 3.) only active if bit FWDKQ=1 , for FWDKQ=0 transition of „No WD error“ is executed WWD error: minimum one of the bits WWDSCE or WWDTO in register WDDiag is high; FWDRespC md OR FWDRespSy nchCmd receive d FWDRespCmd OR FWDRespSynchCmd received FWDRespSynchCmd received FWDRespCmd received FWD error: Wrong response2.) FWD error: WDHBPSynchCmd received No WWD error 3.) No WWD error3.) WWD error3.) W W D error3.)

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 38 Rev. 1.1, 2014-08-20 The definition of the next question is done with a pseudo random algorithm. With the bit FWDQG in the configuration register WDConfig1 the generation algorithm for the questions is defined. There are two settings:

• question pattern length 16: 16 question repeated ev ery 16th watchdog sequence with a minimum hamming distance of 3
• question pattern length 256: every 256 question the orde r of the 16 questions is repeated, minimum hamming distance is 1

6.3 Total Error Counter Module

The total error module is used to count the errors of the window watchdog and the functional watchdog. In Figure 10 the error check state machine is shown. If a watc hdog error of the functional or the window watchdog occurs the state machine enters the state “error occurred” and with the next heartbeat event (definition see Chapter 6.2) the total error counter is incremented. The counter is also incremented if a functional watchdog error or at the same time a window watchdog error occurs by using the FWDRespSyncCmd. With the WDHBTPSyncCmd always an increment of the total error counter is done. A decrement of the total error counter is only possible by using the FWDRespSyncCmd and no errors are occurred. The decrement and increment value of the total erro r counter can be set with the configuration register TECConfig. The status of the total error counter is available in the status register TECStat. Table 11 Questions and related Response QUEST[3:0] RESP3 RESP2 RESP1 RESP0 0F F0 FF 00 0 1B 04 0 B F4 F 2E 91 9 E 61 6 3A 65 6 A 95 9 47 5 8 5 7 A8 A

53 AC A3 5 C 5

72 CD C 2 3 D 3

99 D6 D9 2 6 2

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 39 Rev. 1.1, 2014-08-20 Figure 10 State diagram of the Error check State machine for the Total Error Counter Module

6.4 Watchdog Reset Counter

The watchdog reset counter is a three bit counter (bits RESC in WdStat0) and is triggered by an overflow of one of the three counters of the monitoring functions (see Figure 11). The reset counter can only be incremented by 1. Each time the watchdog reset counter changes the va lue a watchdog reset occurs depending on the status of watchdog reset enable bit WDREN in the configuration register WDConfig1. The counter stops counting if WDREN = “0” or at full scale. There are no further resets if full scale is reached. The behavior at the different reset conditions is defined in Chapter 5.2 Table 6 and Table 7.

6.5 Power Down Counter

There are three power down counters with three bits implemented. The window watchdog power down counter (bits WWDPDC in status register WdStat0) is triggered by an overflow of the window watchdog error counter, the functional watchdog power down counter (bits FWDPDC in status register WdStat1) is triggered by an overflow of the functional watchdog pass counter a nd the total error power down counter (bits TECPDC in status register WdStat1) is triggered by an overflow of the total error counter (see Figure 11). If a trigger occurs the dedicated power down counter is incremented by 1. Additionally all three power down counters are incremented by 1 if a software reset occurs. The power down counters are reset if the ready state is reached (see Table 12 and Table 13). With an overflow of minimum one of the three power down counters a power down of the TLE8888-1QK is performed if KEY is “low” (see Chapter 5.1). This function can not be disabled. The behavior at the different reset conditions is defined in Chapter 5.2 Table 6 and Table 7.

6.6 Secure Shut Off Timer

The secure shut off timer (SSOT) is reset with KEY = 1 and the timer starts with an overflow of one of the three counters of the monitoring functions (see Figure 11) if it is enabled with KEY = 0. If the timer is expired after the Secure shut off time a power down of the TLE8888-1QK is performed (see Chapter 5.1).The behavior at the different reset conditions is defined in Chapter 5.2 Table 6 and Table 7. Error occured Reset WWD or FWD error Wait for error Increment Total error counter Heartbeat event Decrement Total error counter Error Check Statemachine FWDRespSy ncCmd received and (funct iona l check failed orWWD error) orWDHB TPSyncC md FWDRespSyncCmd received and (functional check passed and no W WD error)

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 40 Rev. 1.1, 2014-08-20

6.7 Operation State Defini tion and Reset Generation

The values of the three counter of the monitoring modul e are affecting the operation state of the TLE8888-1QK. There are three states defined:

• the safe state: this is the reset state. The bits O1E to O24E and IGN1E to IGN4E in the configuration register OEConfig0 to OEConfig3 are set to “0” to ensure that all actuators are switched off.
• ready state: the device can be operated without restrictions.
• watchdog reset: a reset is performed according the definition in Table 6 and Table 7. The definition of the three states is shown in Table 12. The states are affecting the status of the pins MON and RST, the power down counter, the secure shut off timer and the reset counter (definition see Table 13). Table 12 Definition of Reset, Safe and Ready State Safe State WWDEC>32 D OR FWDPC >32D OR TEC>32D Ready State WWDEC<33 D AND FWDPC<33D AND TEC<33D Watchdog Reset WWDEC overflow OR FWDPC overflow OR TEC overflow (for all counters >63D) Table 13 System Reaction to the watchdog status Ready State Safe State Watchdog Reset RST 11 0 1) 1) occurs for the defined reset time if watchdog reset is enabled MON 10 0 Power stages no influence of normal operation disabled disabled O1E to O24E, IGN1E to IGN4E X0 0 WWD error counter FWD pass counter Total error counter no effect no effect reset 1) Reset counter no effect no effect increment by 1 Window watchdog power down counter Total error power down counter Functional watchdog power down reset no effect increment by 1 regarding the overflow source Secure shut off timer no effect no effect start of timer with the first overflow if KEY = 0

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 41 Rev. 1.1, 2014-08-20 Figure 11 Block diagram of the Reset Generation Behavior of the WWD error counter, the FWD pass counters and the total error counter in case of over and underflow: The counters are designed to keep the same value:

• at incrementation if the new counter value is hi gher than the full scale value of the counter and
• at decrementation if the new counter value is lower than zero. In Figure 12 an example is shown. Ready Safe Overflow Reset Value=48 Ready Safe Overflow Reset Value=48 Window Watchdog Error Counter Functional Watchdog Pass Counter Reset Generation Total Error Power Down Counter Power Down Reset Counter RST MON Total Error Counter Ready Safe Overflow Reset Value=48 counter reset Functional Watchdog Power Down Counter Window Watchdog Power Down Counter

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 42 Rev. 1.1, 2014-08-20 Figure 12 Example of WWD error counter behavior with decrement and increment value of 14d

6.8 Synchronisation of Window Watchdog Sequence and Heartbeat

In Figure 13 the relation between the heartbeat clock generation, the total error counter and the window watchdog sequence generation is shown. The window watchdog sequence generation and the heartbeat period generation have the same clock base with the accuracy of tw,a. The value of the pre-divider and the heartbeat ti mer can be read out with the status registers WDHBT0 and WDHBT1. This can be used to measure the actual internal clock frequency. Therefore the value of the pre-divider and the heartbeat period counter must be sampled by sending a Cmd0 command with an activated WDHBTS bit. With this command the value of the two registers are stored in the related status registers and the readout can be done. With two sampled values the micro controller can correct the time information by the value of the actual frequency of the TLE8888-1QK. With such a correction of the micro controller timing check it is possible to use smaller open window times to improve the performance of the timing check. Additional it is possible to use this information for synchronization purpose for the check of the monitoring function of the TLE8888-1QK inside the micro controller. Restart of window watchdog period Safe State Ready State WWD Error Counter Full scale 63d 1 23456 78 Reset Value 48d 40d 32d 24d 16d 56d Overflow Underflow 62d 34d 20d Decrement Value = Increment Value = 14d WDREN=0

Monitoring Watchdog Module (Signature Watchdog) Data Sheet 43 Rev. 1.1, 2014-08-20 Figure 13 Clock Generation for the Watchdog Module

6.9 Electrical Characteristi cs Monitoring Watchdog Module

Table 14 Electrical Characteristic s: Monitoring Watchdog Module VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Window watchdog closed window time tWWD,ct 1.6 – 100.8 ms 63 values P_6.8.1 Window watchdog closed window time step tWWD,ct –1 . 6 –m s – P_6.8.2 Window watchdog open window time 1 tWWD,ot1 –3 . 2 –m s P_6.9.1 Window watchdog open window time 2 tWWD,ot2 –6 . 4 –m s P_6.9.2 Window watchdog open window time 3 tWWD,ot3 –9 . 6 –m s P_6.9.3 Window watchdog open window time 4 tWWD,ot4 – 12.8 – ms – P_6.8.3 Clock frequency accuracy for window watchdog sequence and heartbeat Heartbeat time period tHBT,pt 1.6 – 203.2 ms 127 values P_6.9.4 Secure shut off time tSSOT 18 20 22 min – P_6.8.5 Window Watchdog Pre Divider Functional Watchdog Pass Counter Increment Decrement fclk fclk/16 fclk used for watchdog sequence Heartbeat for Functional Watchdog Functional Watchdog Setting 7 bit counter Error Check Statemachine

Wake Up Detection and Main Relay Driver Data Sheet 44 Rev. 1.1, 2014-08-20

7 Wake Up Detection an d Main Relay Driver

The TLE8888-1QK integrates a complex wake up functionality with two wake up pins (KEY and WK), engine off timer, CAN wake up and the main relay driver. There are several possibilities to initiate the start up of the device:

• a positive voltage at the pin KEY or at the pin WK
• a dominant pulse at the CAN inputs CANH and CANL for the wake up time (description see Chapter 12)
• after expiration of the defined time of the engine off timer in comparator mode With minimum one valid wake up signal the pre regulator and the main supply start the ramping up due to voltage at the battery supply pin BAT and the drain of the external MOSFET of the pre regulator. The switch on of the main relay depends on the wake up signal and the voltage level at the pin BAT. For a wake signal from the pin KEY the main relay is always switched on. For the other cases the main rela y is only switched on if the voltage of the pin BAT is below the detection threshold. With the bit WKCLR in the command register Cmd0 the internal status of the detection at pin WK, engine off timer engine off timer and the CAN wake receiver is V5VSTBY. Figure 14 Block Diagram of the Key Detection, Wake Up Detection and Main Relay Driver Main Relay DriverKey Detection Wake Up Pin Detection Internal Supply Key On Wake Up MR MR KEY WK BAT Wake Up Supply Supply Engine Off Timer EOTEN Digital Block Battery Detection Logic WK_High EOTWK BAT_High CAN Wake Receiver CANWKENCANWK Digital block KOFFDO Main Relay Supply Standby Supply BAT STBYV5VSTBY MSC/SPI InterfaceSDO SIN WKCLR MR On/Off connection to VDDIO or V5V

Wake Up Detection and Main Relay Driver Data Sheet 45 Rev. 1.1, 2014-08-20

7.1 Wake Up Detection by Pin KEY and Key Off Delay

The input pin KEY is implemented to detect the status of the key switch in the car. With a high signal the start up of the TLE8888-1QK is initiated. During start up the implemented circuitry provides also the supply for switching the main relay. A deglitch filt er is implemented to be robust against disturbances (see Figure 16). After ramp up the supply of the main relay is provided by the internal supply. To provide a direct access from the KEY signal to actuators a key off delay function is implemented. Figure 15 Block Diagram of the Key Detection In Figure 16 the effect of the filter time is shown. The status of the pin KEY including the filter time is reflected in bit KEY in the status register OpStat0. Table 15 Switching Behavior of Main Relay at Star t Up (Transition ECU Sleep to Supply Ramp Up Mode) KEY = 0, WK = EOTWK = CANWK= 0 - MR is switched off Supply is off KEY = 1, WK = EOTWK = CANWK= X - MR is switched on Supply is switched on KEY = 0, WK or EOTWK or CANWK = 1 BAT < VBAT,th MR is switched on KEY = 0, WK or EOTWK or CANWK= 1 BAT > VBAT,th MR is switched off Key Detection Key On KOFFDO KEY Supply Main Relay Key Off Delay Register Internal Supply connection to VDDIO or V5V

Wake Up Detection and Main Relay Driver Data Sheet 46 Rev. 1.1, 2014-08-20 Figure 16 Function of Key detection filter time The key off delay function provides the KEY signal at the open drain output KOFFDO. The positive edge is delayed by the Key Detection Filter Time and the negative edge by the Key Off Delay Time 1 to Key Off Delay Time 4 (according setup of the bits KOD in register OpConfig0) if the supply is available. Figure 17 Timing Diagram of the Key Off Delay

7.2 Wake Up Detection by Pin WK

The pin WK is used e.g. for an external CAN device with wake up function on the ECU. With a high signal the start up of the TLE8888-1QK is initiated. During ramp up the supply for the main relay circuit is provided by the active wake up pin WK. After ramp up the supply of the main relay circuit is provided by the internal supply. In Figure 18 the block diagram of the wake up detection by pin WK is shown. KEY t Wake Up by Signal at Pin KEY ; WK = EOTWK = CANWK = 0; AE=0 ECU Sleep Supply Ramp Up Normal operationRamp UP/Down Statemachine ECU Sleep tKEY,f tKEY,f V5V KOFFDO t ttKEY,f tKoff,d KEY VDDIO

Wake Up Detection and Main Relay Driver Data Sheet 49 Rev. 1.1, 2014-08-20 Figure 22 Functional Diagram of Detect ion of Two Internal Wake Signals

7.3 Main Relay Driver

The main relay driver is designed to switch on the main relay of engine management applications. It integrates a reverse protected low side switch with active clamping freewheeling. The output is protected against overload with an over-temperature detection and an over-current protection circuit. At low battery voltage (V5V main supply is below under voltage detection threshold e.g. during cranking) the main relay stays on. The on resistance is related to the supply voltage at pin BAT and is defined down to 4.5V. The main relay is automatica lly switched on with a wake up signal according to Table 15. The main relay is normally switched off automatically according the power down procedure defined in Chapter 5. With write access to the command bit MRON of the command register Cmd0 the main relay can be switched additionally by MSC/SPI control according to the status of KEY, WK, EOTWK and CANWK (see Table 16). The status of the main relay is available in the status register OpStat0 bit MR. The main relay driver is protected aga inst over-current and over-temperature . In the case of over-current and/or over-temperature the output is switched off and is swit ched on again after release of the failure condition. This leads to a repetitive switching. A minimum off time tMR,off is implemented to ensure no destruction due to repetitive switching.

7.4 Engine Off Timer

The engine off timer is integrated to measure the time in ECU sleep mode. Additionally the comparator mode is implemented to wake up the TLE8888-1QK after a defined time. It is internally supplied out of the standby supply pin V5VSTBY. With the pin EOTEN the function is enabled with a connection to V5VSTBY and disabled with a connection to AGND. It consists of an oscillator optimized fo r low current operatio n, a counter and a comparator. The counter counts up to 36 hours and if the counter value reaches the comparator threshold an internal wake up signal is generated. The activation of the comparator mode is done with a definition of a Table 16 Effect of MSC/SPI Write Command Bit MRON KEY = 0, WK = EOTWK = CANWK= X MR is switched according to write command KEY = 1, WK = EOTWK = CANWK= X MR is always switched on WK t WKINT1) t wake t Set WKCLR=“1“ Wake Up by Signal at Pin WK ; KEY = EOTWK = CANWK = 0, AE=1 1)Wake Up detection Filter Time is not shown in the diagram

Wake Up Detection and Main Relay Driver Data Sheet 50 Rev. 1.1, 2014-08-20 comparator threshold greater than 0000H in configuration registers EOTConfig0 and EOTConfig1. There are two operation modes implemented:

• Counter Mode: only counter is working, no wake up with comparator threshold
• Comparator Mode: counter operation like counter mode, additional wake up with comparator threshold In comparator mode the internal EOTWK flag is set if the counter is equal to compare value in the configuration registers EOTConfig0 and EOTConfig1. The reset of the EOTWK flag is done with the bit WKCLR in the command register Cmd0 if the counter value is not equal to the compare value. Figure 23 Block Diagram Engine Off Timer The start of the counter can be configured with the bit EOTCONF in the configuration register OpConfig0 to
• s t a r t b y KEY signal (reset value) and
• start by MSC command With the falling edge of the KEY signal or with the execution of the MSC command the counter is reset and starts counting (see Figure 24). The start command is performed with setting the bit EOTS to “1” in the command register Cmd0. The status bit EOTRES (register OpStat1) is implemented to highlight that a standby reset has happened. With the start of the counter this bit is reset. Therefore the status of this bit must be readout before the start of the engine off timer. The 24 bits of the counter are available in the status register EOTStat0, EOTStat1 and EOTStat2. For easier access to the engine off timer status the multiple read command MSCReadDiag0EOT is implemented. After wake up the counter doesn’t stop counting. A readout of the counter value doesn’t stop counting. With this behavior it is possible to measure the counting time with the micro controller (see Figure 25). With a read out of two counter values in a defined time a correction factor can be calculated (difference of counter values divided by the time between the two read outs). Wi th this measurement of the correction factor only the variation caused by the temperature of the timer are effective. The absolute variations are corrected by the correction factor. There are no restrictions for the meas urement time but due to the resolution of the counter a minimum measurement time ∆ t of 1s is recommended. After power up of the engine off timer circuit with a supply ramp up at pin V5VSTBY the counter value and the comparator threshold are reset to the reset value. Additionally the bit EOTRES in the status register OpStat1 is set to “1”. Any other resets like ECU power on reset have no im pact to the engine off timer counter. The compare configuration register EOTConfig0 and EOTConfig1 are cleared with an ECU power on reset. The counter stops counting at full scale. If a standby suppl y reset occurs the counter stops counting and is reset to “0”. Oscillator Counter Comparator V5VSTBY KEY KEY Detection Digital Block Start EOTWKEOTEN MSC/SPI Interface SDO SIN EOTWK flag WKCLR EOTRES

Wake Up Detection and Main Relay Driver Data Sheet 52 Rev. 1.1, 2014-08-20 In comparator mode there is no difference in the be havior of the counter as described above. Additionally a comparator threshold different to 0000 H for wake up is defined in the configuration register EOTConfig0 and EOTConfig1. The comparator mode is enabled with a threshold value different to 0000 H. If the counter value is equal to the comparator threshold the internal wake up signal EOTWK (status see bit EOTWK in the status register OpStat0) of the TLE8888-1QK is active (see Figure 26). With a wake up clear command (set bit WKCLR to “1” in command register Cmd0) the internal EOTWK signal is reset. Figure 26 Function Diagram Engine Off Timer Comparator Mode Table 17 Counter Definition EOTC[23:0] 000000H reset value 000001H to FFFFFFH 1/128s to 131071s = 36h + 24min + 31s time resolution 1/128s Table 18 Comparator Threshold Definition EOTTH[15:0] 0000H reset value comparator mode disabled 0001H to FFFFH 2s to 131070s = 36h + 24min + 30s comparator mode enabled, time resolution 2s KEY EOT Counter Value full scale CSN MSC Communication readout counter value command start counter t t t EOTWK t comparator threshold set WKCLR = “1" readout counter value ECU Sleep ECU Sleep ECU Sleep

Wake Up Detection and Main Relay Driver Data Sheet 53 Rev. 1.1, 2014-08-20

7.5 Electrical Characteristics Key Detection, Wake Up Detection and Main Relay

Table 19 Electrical Characteristics Key Detection VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Key On Detection Threshold VKEY,th 3.6 – 4.5 V rising edge P_7.5.1 Key On Detection Hysteresis VKEY,h 140 250 400 mV – P_7.5.2 Input Current during wake up IKEY – – 0.55 mA VKEY=5V1) 1) not subject to production test, specified for design P_7.5.3 Input Current after wake up IKEY –– 0 . 7 m A VKEY=VBAT =4.5V P_7.5.31 Key Detection Filter Time tKEY,f 7.5 16 24 ms VKEY=5V P_7.5.4 Key Off Delay Time 1 tKEYoff,d,1 100 – 200 ms – P_7.5.5 Key Off Delay Time 2 tKEYoff,d,2 200 – 400 ms – P_7.5.6 Key Off Delay Time 3 tKEYoff,d,3 400 – 800 ms – P_7.5.7 Key Off Delay Time 4 tKEYoff,d,4 800 – 1600 ms – P_7.5.8 Output KOFFDO Output Current Capability IKOFFDO 152) 2) Application must ensure t hat current into this pin does not exceed this value. –– m A VKOFFDO=5V P_7.5.9 KOFFDO Output Low Level VKOFFDO,low –– 0 . 4 V IKOFFDO<1mA P_7.5.30 Table 20 Electrical Characteristics Wake Up Detection VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Wake Up Detection Threshold VWK,th 3.6 – 4.5 V rising edge P_7.5.10 Wake Up Detection Hysteresis VWK,h 140 250 400 mV – P_7.5.11 Input Current during Wake Up IWK – – 0.55 mA VWK=5V1) 1) not subject to production test, specified by design P_7.5.12 Wake Up Detection Filter Time tWK,f 12 3 . 5 m s VWK=5V P_7.5.13 Battery Detection Threshold VBat,th 3.5 – 5 V VWK=5V P_7.5.14

Wake Up Detection and Main Relay Driver Data Sheet 54 Rev. 1.1, 2014-08-20 Table 21 Electrical Characteristics Main Relay Driver VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. MR Operation Current IMR –– 0 . 8 A – P_7.5.15 MR Over Current Limitation IMR,oc 0.8 – 1.5 A – P_7.5.16 MR On Voltage VMR –– 1 . 3 5 V IMR=0.3A P_7.5.17 MR switch off time in failure case tMR,off 16 27 – ms in case of over- current and/or over-temperature P_7.5.32 MR On Voltage at Low Battery Voltage, low temperature VMR,l,LT –– 1 . 1 V IMR=0.1A, VBAT=4.5V (decreasing) TJ<25°C P_7.5.18 MR On Voltage at Low Battery Voltage, high temperature VMR,l,HT – – 1.05 V IMR=0.1A, VBAT=4.5V (decreasing) TJ>25°C P_7.5.19 MR Clamping Voltage VMR,cl 40 – 60 V IMR=0.2A P_7.5.20 MR Clamping Energy1) 1) not subject to production test EMR,cl –– 6 . 5 m J IMR<0.3A, Tj=150°C, 40*106 cycles P_7.5.21 MR leakage current in off mode, positive voltage IMR.leak,pos –– 5 µ A VMR=13.5V, VKEY=0V and VWK=0V P_7.5.22 MR leakage current in off mode, negative voltage IMR.leak,neg -100 – – µA VMR=-13.5V, VKEY=0V and VWK=0V P_7.5.23 Table 22 Electrical Characteristics Engine Off Timer VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Oscillator Accuracy Δfosc,a -30 – +30 % VV5VSTBY=5V P_7.5.24 Oscillator Frequency Variation over Temperature Δfosc,T -5 – +5 % VV5VSTBY=5V, Tj=-40°C to 85°C, one single device P_7.5.25 Counter Resolution CEOT,r –1 / 1 2 8 – s – P_7.5.26 Counter Full Scale CEOT,fs – – 24 bit – P_7.5.27 – 131071 – s –

Wake Up Detection and Main Relay Driver Data Sheet 55 Rev. 1.1, 2014-08-20 Additional current consumption at pin BATSTBY for enabled engine off timer function IEOTSUP –– 1 0 µ A VV5VSTBY=5V and no wake up P_7.5.28 Additional current consumption at pin BATSTBY for enabled engine off timer function and wake up IEOTSUP,w – – 450 µA VV5VSTBY=5V and wake up P_7.5.29 1) not subject to production test, specified by design Table 22 Electrical Characteristics Engine Off Timer (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 56 Rev. 1.1, 2014-08-20

8 Power Supply

The power supply unit generates the internal supply (including supply for CAN and pre-drivers, voltage reference and current biasing), the main supply voltage for the ECU ( V5V) and sensor supplies for off- board sensors (T5V1 and T5V2). All supplies start working by the wake up signal generated by the key and wake up detection (see Chapter 7.2 for details). A linear pre-regulator with an external logic level power MOSFET is implemented to keep the power dissipation of the TLE8888-1QK low. The precise voltage supplies for the ECU and the sensor supplies are integrated inclusive the power transistor. All supplies wit h low drop functionality (main supply V5V, pre-regulator, sensor supplies T5V1/T5V2) are using an integrated charge pump to provide low drop behavior at low battery voltages. Figure 27 Block diagram of the power supply

8.1 Pre-Regulator

The pre-regulator uses an external logic level power MOSFET and regulates the voltage at pin V6V. The voltage at the pin is also the input voltage for the main supply of the ECU (V5V), the sensor supplies (T5V1, T5V2) and the internal supply. The circuit is designed for low drop operation. It's not allowed to load the external MOSFET with anything else than V6V. The function of the pre-regulator is guaranteed with the MOSFET IPD30N06S2L-23 of Infineon. V5V T5V1 VG V6V T5V2 Linear Preregulator Linear Regulator Tracker Ref Ref VV5V CPBATSTBY Standby RegulatorV5VSTBY Chargepump VDDIO Digital Outputs to Micro Controller To Micro Controller Half Bridges BATPA BATPB Key and Wake Up Detection BAT

Data Sheet 57 Rev. 1.1, 2014-08-20 8.2 5V Main Supply The 5V main supply is designed to supply the ECU includ ing micro controller and e.g. other power chips. Out of V6V a high accurate voltage is provided at the pin V5V. The pin and the circuit is protected against overload and short circuit. For stabilization and ripple reduction an external buffer capacitor is required. For low drop operation of the regulator the pins BATPA and BATPB must be supplied.

8.3 Sensor Supply

There are two sensor supplies integrated providing an output voltage based on V5V as reference. Out of V6V a high accurate voltage is provided at the pins T5V1 and T5V2. The pins and the circuits are protected against overload, short circuit and reverse supply back to V6V. For stabilization and ripple reduction external buffer capacitors are required. For low drop operation of the regulator the pins BATPA and BATPB must be supplied.

8.4 IO Supply

The TLE8888-1QK provides an IO supply pin VDDIO for 3.3V and 5V micro controller interfaces. This pin is used for the supply of the output driver and defines the output level of all logical interface pins.

8.5 Standby Supply

The TLE8888-1QK integrates a standby supply which is supplied by the pin BATSTBY and provides a 5V output supply at pin V5VSTBY. It is not allowed to connect this pin to any other supply.

8.6 Charge Pump

There is a charge pump integrated to supply the half bridges out of BATPA and BATPB. A capacitor has to be connected on the PCB (between CP and BATPA/BATPB) to buffer the voltage and reduce the ripple. It's not allowed to apply any external load to the pin CP.

8.7 Voltage Monitoring

The TLE8888-1QK provides voltage monitoring of the main ECU supply V5V, the sensor supplies T5V1 and T5V2 and the battery voltage. In Chapter 5.2 the effect to the status of t heTLE8888-1QK is described. All detection thresholds are implemented with a hysteresis and a filter time to suppress disturbances. The status of the over- and under-voltage detection of BAT, T5V1 and T5V2 are available in the diagnosis resister Diag0 and the bits BATOV, T1UV, T1OV, T2UV and T2OV. Under- and over-voltage of V5V leads to a reset of the micro controller (see Table 6 in Chapter 5.2). After release of the reset the cause of the reset is available in the status register OpStat1 (bits V5VUVR and V5VOVR).

8.8 Electrical Charact eristics Power Supply

Table 23 Electrical Characteristics Power Supply VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. current consumption at pins BATPA, BATPB, BAT and V6V IBAT,sum – – 50 mA static, all “off”, no PWM and MSC/SPI communication P_8.8.1 Pre-Regulator

Data Sheet 58 Rev. 1.1, 2014-08-20 Pre-Driver Output Voltage V6V VV6V 5.5 6 6.5 V with respect to AGND, with external MOS FET IPD30N06S2L-23 P_8.8.2 Gate Output Voltage VG ΔVVG 4– 7 . 5 V VV6V=5.5V; ΔVVG=VVG-VV6V P_8.8.3 Gate Output Voltage VG at low Supply ΔVVG,l 1.7 – – V VBATPx=4.5V, IVG=1µA; ΔVVG=VVG-VV6V P_8.8.4 Buffer Capacitor at V6V1) CV6V 12 0 1 0 0 0 µ F 2) 3) P_8.8.37 ESR of Buffer Capacitance at V6V1) ESRV6V 0.01 2 Ω for CV6V<15µF, fESR=10kHz P_8.8.38 ESR of Buffer Capacitance at V6V1) ESRV6V 0.5 2 Ω for 15µF<CV6V<20µF, fESR=10kHz P_8.8.39 ESR of Buffer Capacitance at V6V1) ESRV6V 12 Ω for 20µF<CV6V<1000µF , fESR=10kHz P_8.8.40 Buffer Capacitor at VG1) CVG –4 . 7 1 5 n F 2)3) P_8.8.41 ESR of Buffer Capacitance at VG1) ESRVG –– 1 Ω fESR=10kHz P_8.8.42 5V Main Supply V5V Output Voltage V5V VV5V 4.9 – 5.1 V -5mA < IV5V < -500mA, with respect to AGND P_8.8.5 Voltage Drop V6V-V5V at low Supply VV5V,d –– 0 . 6 V IV5V=- 500mA; VBAT=VBATPx=VKEY= VV6V=4.5V P_8.8.6 Voltage Drop V6V-V5V at low Supply and low temperature VV5V,d,CT – – 0.45 V Tj=-40°C; IV5V = -500mA; VBAT=VBATPx=VKEY= VV6V=4.5V1) P_8.8.7 Current Limitation IV5V,lim -1200 – -500 mA – P_8.8.8 Buffer Capacitor at V5V1) CV5V 0.1 10 220 µF 2)3) P_8.8.9 ESR of Buffer Capacitance at V5V1) ESRV5V 0.01 2 Ω for CV5V<10µF, fESR=10kHz P_8.8.43 ESR of Buffer Capacitance at V5V1) ESRV5V 0.1 2 Ω for 10µF<CV5V<47µF, fESR=10kHz P_8.8.44 Table 23 Electrical Characteristics Power Supply (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 59 Rev. 1.1, 2014-08-20 ESR of Buffer Capacitance at V5V1) ESRV5V 0.5 2 Ω for 47µF<CV5V<220µF, fESR=10kHz P_8.8.45 Sensor Supplies T5V1 and T5V2 Output voltage tracking accuracy ΔVT5Vx -10 – 10 mV ΔVT5Vx=VV5V-VT5Vx, 4V<VV5V<5.1V,VV6V >5.5V, VIGNx≥0V P_8.8.10 Current Limitation IT5Vx,lim -300 – -100 mA P_8.8.11 Buffer Capacitor at T5V1 and T5V21) CT5Vx –– 4 0 0 n F P_8.8.12 IO Supply VDDIO IO Supply Voltage Range VVDDIO 3– 5 . 5 V – P_8.8.13 Current Consumption at pin VDDIO IDDIO –– 2 m A VVDDIO=5V, INx=0V, CSN=LINTX=CANT X=5V, MON and RST open P_8.8.14 Standby Supply V5VSTBY Output Voltage V5VSTBY VV5VSTBY 4.75 – 5.25 V -10µA < I V5VSTBY < -15mA P_8.8.15 Total Standby Current Consumption at pins BATSTBY, BAT, V6V and MR ISTBY –– 1 2 0 µ Α ECU sleep mode, Tj=25°C, IV5VSTBY=0mA, VBATSTBY=VBAT=VMR =13.5V, EOTEN=CANW KEN= 0V P_8.8.16 Buffer Capacitor at V5VSTBY1) CV5VSTBY 27 100 270 nF 2)3) P_8.8.46 ESR of Buffer Capacitance at V5VSTBY1) ESRV5VSTBY 0.01 – 1 Ω P_8.8.47 Charge Pump Charge pump Output Voltage ΔVCP 45 7 V ΔVCP=VCP-VBAT no external load currents P_8.8.17 Charge pump Output Voltage at low supply ΔVCP 3.5 – – V VBAT=4.5V after start up, Δ VCP=VCP-VBATPx P_8.8.18 Buffer Capacitor at CP1) CCP –4 . 7 – n F P_8.8.19 Voltage Monitoring Table 23 Electrical Characteristics Power Supply (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 60 Rev. 1.1, 2014-08-20 V5V Under Voltage Detection Threshold, decreasing VUV,V5V,dec 4.45 – 4.7 V VV5V decreasing P_8.8.20 V5V Under Voltage Detection Threshold, increasing VUV,V5V,inc 4.45 – 4.8 V VV5V increasing P_8.8.21 V5V Under Voltage Detection Hysteresis VHys,UV,V5V 10 50 – mV – P_8.8.22 V5V Under Voltage Filter Time tf,UV,V5V 51 0 1 5 µ s – P_8.8.23 T5V1 and T5V2 Under Voltage Detection Threshold VUV,T5Vx,dec 4.45 – 4.7 V VT5Vx decreasing P_8.8.24 T5V1 and T5V2 Under Voltage Detection Threshold VUV,T5Vx,inc 4.45 – 4.8 V VT5Vx increasing P_8.8.25 T5V1 and T5V2 Under Voltage Detection Hysteresis VHys,UV,T5Vx 10 50 – mV – P_8.8.26 T5V1 and T5V2 Under Voltage Filter Time tf,UV,T5Vx 51 0 1 5 µ s – P_8.8.27 V5V Over Voltage Detection Threshold VOV,V5V 5.2 – 5.6 V VV5V increasing P_8.8.28 V5V Over Voltage Detection Hysteresis VHys,OV,V5V 10 – 100 mV – P_8.8.29 V5V Over Voltage Filter Time tf,OV,V5V 51 0 1 5 µ s – P_8.8.30 T5V1 and T5V2 Over Voltage Detection Threshold VOV,T5Vx 5.2 – 5.6 V VT5Vx increasing P_8.8.31 T5V1 and T5V2 Over Voltage Detection Hysteresis VHys,OV,T5Vx 10 – 100 mV – P_8.8.32 T5V1 and T5V2 Over Voltage Filter Time tf,OV,T5Vx 51 0 1 5 µ s – P_8.8.33 BAT Over Voltage Detection Threshold VOV,BAT 28 – 30.4 V VBAT increasing P_8.8.34 BAT Over Voltage Detection Hysteresis VHys,BAT 50 – 500 mV – P_8.8.35 BAT Over Voltage Filter Time tf,OV,BAT 51 0 1 5 µ s – P_8.8.36 1) not subject to production test, specified by design 2) Defined minimum value is needed for regulator stability. Application might need higher value than minimum. 3)additionally in parallel a capacitance up to 0.1*CVxV and low ESR is allowed Table 23 Electrical Characteristics Power Supply (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 61 Rev. 1.1, 2014-08-20

9 Power Stages

In the TLE8888-1QK there are 14 low side power stage s, 4 half bridges, 4 push-pull outputs for on board and external ignition driver and 6 push-pull outputs for on board MOSFETs implemented. The 14 low side power stages are designed for various inductive and resistive loads, 4 stages to drive especially injectors, 3 with a higher operating current to drive e.g. O2-heaters and 7 stages to drive relays. For the injector output stages (OUT1 to OUT4) the common enable input INJEN and for the ignition outputs the common enable input IGNEN are implemented. The half bridges can be used with high or low side load, with active or passive freewheeling or in full bridge configuration. Figure 28 Block Diagram of the Power stages digital block Protection Overtemp Overcurrent Clamping Diagnosis Open Load Short to GND Power Stage 2.2A OUT1A OUT4A OUT1B OUT4B MSC INJEN IN1 IN2 IN3 IN4 Protection Overtemp Overcurrent Clamping Diagnosis Open Load Short to GND Power Stage 4.5A OUT5A OUT7A OUT5C OUT7C Protection Overtemp Overcurrent Clamping Diagnosis Open Load Short to GND Power Stage 0.6A OUT14 OUT20 IN9 IN10 IN11 IN12 OUT21 OUT24 Protection Overtemp Overcurrent Diagnosis Open Load Short to GND Short to Bat Half Bridge 0.6A BATPB BATPA Charge- pump CP Push Pull Driver 20mA DFBx Diagnosis Ignition Driver 20mA DFB8 OUT8 DFB13 OUT13 IGN1 IGN4 IGNEN IN5 IN6 IN7 IN8 Diagnosis

Data Sheet 62 Rev. 1.1, 2014-08-20

9.1 Power Stage Control

The output stages will be controlled either by the MSC/SPI data frame or command frame and the control register Cont0 to Cont3 (see Chapter 14.6) or the direct drive inputs IN1 to IN12. The configuration which control mode is active is done in the configuration register DDConfig0 to DDConfig3 (see Chapter 14.5). A “1” in the control register/data frame bit or a “high” at the direct drive inputs switches on the corresponding output. In Table 25 the assignment of the direct drive inputs to the ou tput stages is shown. T he set up is valid for MSC and SPI operation. The status of the power stages is also affected by the operation state and conditions of the TLE8888-1QK and is described in Chapter 5. All power stages are switched off if a micr o channel time out occurs. Description of the effect to the control of the power stages see Chapter 13.1.1, Downstream Supervisory Functions. Table 24 Overview Power Stages Type maximum operation current Ron active clamping Diagnosis in on Diagnosis in off OUT1 to OUT4 Low side switch 2.2A 550mΩ yes over current (short to battery) over temperature open load short to GND over temperature OUT5 to OUT7 Low side switch 4.5A 350mΩ yes over current (short to battery) over temperature open load short to GND over temperature OUT8 to OUT13 5V push pull output 20/-20mA – no at pin DFBx: short to battery at pin OUTx: over voltage at pin DFBx: open load short to GND at pin OUTx: over voltage OUT14 to OUT20 Low side switch 0.6A 1.5Ω yes over current (short to battery) over temperature open load short to GND over temperature OUT21 to OUT24 Half bridge 0.6A 2.4Ω no over current (short to battery/short to GND) over temperature open load short to battery/short to GND over temperature IGN1 to IGN4 5V push pull output 20/-20mA – no short to battery short to GND open load short to battery

Data Sheet 63 Rev. 1.1, 2014-08-20 All direct drive inputs have implemented a pull down current source to define the input voltage. For a multiple assignment of two direct drive inputs for one output stage (wrong configuration) the output is switched off independent of the status of the direct drive inputs.

9.2 Power Stages Enable

To enable the power stages a central output enable bit OE is defined. The status of the bit is shown in the status register OpStat1 and can be set with the command register CmdOE. Additional a dedicated output enable bit for each output is defined (see register OEConfig0 to OEConfig3) to avoid uncontrolled repetitive switching in failure case. These enable bits are reset by the protection function of each channel and block switch on of the channels. The bits could not be set if a protection function is active. With setting the central enable bit to “1” all dedicated output enable bits are set to “1” (if no protection function is active) and all channels are enabled and can be controlled according their configuration. With setting the central enable bit to “0” all dedicated output enable bits are set to “0” and all channels are disabled. For the injector channels OUT1 to OUT4 the common enable input INJEN must be set to “high” and for the ignition outputs IGN1 to IGN4 the common enable input IGNEN must be set to “high” to enable the channels. Procedure to switch on after failure condition occurred:

• Read out of diagnosis bits
• Second read out to verify that the failure conditions are not remaining
• Set of the dedicated output enable bit of the affect ed channel if the diagnosis bit is not active anymore
• Switch on of the channel Switch off during battery over voltage: To protect the power stages against hi gh energy during freewheeling they are switched off for battery voltages greater than the “BAT Over Voltage Detection Threshold” (see Table 23 in Chapter 8.8).

9.3 Power Stages Configuration

The power stages can be configured according the configuration bits in the configuration registers OutConfig0 to OutConfig5, BriConfig0, BriConfig1 and IGNConfig. The direct drive input configuration is described in Table 25. Table 25 Direct Drive Input Assignment to Output Stages Input Output Note IN1 to IN4 OUT1 to OUT4 configuration for direct drive: bits O1DD to O4DD of the configuration register DDConfig0 fix assignment of the inputs to the outputs IN5 to IN8 IGN1 to IGN4 configuration for direct drive: bits IGN1DD to IGN4DD of the configuration register DDConfig3 fix assignment of the inputs to the outputs IN9 to IN12 OUT5 to OUT24 configuration for direct drive: bits O5DD to O24DD of the configuration registers DDConfig0 to DDConfig2 assignment of input pins: configuration register InConfig0 to InConfig3 only 4 of this output stages can be switched directly

Data Sheet 64 Rev. 1.1, 2014-08-20

9.4 Special Function “Del ayed Switch Off” for OUT17 and OUT21

A special set up for the control behavior of OUT17 and OUT21 is implemented. With the delayed switch off functionality the outputs are suited to drive loads (e.g. st arter relay) which must be on during very low battery voltages even if the micro controller is in reset e.g. due to under-voltage. In this operation conditions all other power stages are normally switched off. With the bits O17D in the configuration register OutConfig4 and O21D in the configuration register BriConfig1 both outputs can be configured to:

• normal control mode according description in Chapter 9.1
• delayed switch off mode Note: For delayed switch off mode OUT17 and OUT21 must be configured as controlled by MSC/SPI (bits O17DD/O21DD in configuration register DDConfig2 are set to “0”) Delayed switch off mode for OUT21 is only allowed in high or low si de switch configuration. Fullbridge configuration is not allowed. Note: The delayed switch off mode keeps the two outputs on for the time ton,del after an trigger event. With the trigger events in normal control mode the outputs are switched off. In delayed switch off mode the delayed switch off timer starts with following trigger events: Note: The channel must be on before a trigger event, switch on of all channels during the delayed switch off mode is not possible Table 26 Configuration Overview Power Stages Configuration Configuration Register OUT1 to OUT4 over current: current limitation or switch off diagnosis in off: pull down current activated/deactivated OutConfig0 OUT5 to OUT7 over current: current limitation or switch off diagnosis in off: pull down current activated/deactivated OutConfig1 OUT8 to OUT13 at pin DFBx: diagnosis in off: pull down current activated/deactivated diagnosis in on: short to battery detection thresholds OutConfig2 and OutConfig3 bits 0 to 3 OUT14 to OUT20 mode set up: delayed switch off mode for OUT17 over current: current limitation or switch off diagnosis in off: pull down current activated/deactivated ( OUT14 to OUT17) pull up and down current activated/deactivated (OUT18 to OUT20) OutConfig3 bits 4 and 5, OutConfig4, OutConfig5 OUT21 to OUT24 mode set up: active or passive freewheeling high or low side switch mode half or full bridge mode delayed switch off mode for OUT21 BriConfig0 and BriConfig1 IGN1 to IGN4 open load in activation/deactivation open load current setting open load detection time IGNConfig

Data Sheet 65 Rev. 1.1, 2014-08-20

• under-voltage of the main supply V5V is detected
• or over-voltage of the main supply V5V is detected
• or the MSC time out occurs
• or an active signal (“0”) at pin MON
• or an active signal (“0”) at pin RST With the bit RDOT in the command register Cmd0 the delayed switch off timer is restarted and the on time is increased. The delayed off mode is terminated with following events:
• overflow of delayed off timer
• O17/O21 are switched off with command CmdOE, set control register bits O17ON/O21ON or the configuration register bits O17E/O21E to “0”
• O17D/O21D are set to “0”
• Ready State is active and no trigger event is active The outputs are switched off immediately if an internal power on reset occurs. According to the definition in Chapter 5.1 if the conditions for a state change to ECU sleep mode are fulfilled the delayed off is terminated and the transition is executed. Normally the related register bits of OUT17 and OUT21 are reset during undervoltage of the main supply V5V or an active signal (“0”) at pin RST (definition see Table 6 and Table 7 in Chapter 5.2). In delayed switch off configuration following register bits are not reset:
• OE in status register OpStat1
• O17E, O21E in configuration register OEConfig2
• O17D, O17OL, O17OC in configuration register OutConfig4
• O21F, O21M in configuration register BriConfig0
• O21D in configuration register BriConfig1 For illustration in Figure 29 and Figure 30 two examples for the delayed switch off mode for are shown. Figure 29 Example for Delayed Off Behavi or: Overflow of Delayed Off Timer reset Watchdog Operation State Delayed Off Trigger Status Delayed Off Timer O17/O21 O17D/O21D Remaining Power Stages Remaining OEx Bits OE17/OE21 no trigger event e.g. V5VUV=1 Ready State Safe State reset Count up no trigger event ON „1" ON OFF OFF „1" „1" „0" „0" Delayed off timer overflow Start of delayed off mode OE „1"

Data Sheet 66 Rev. 1.1, 2014-08-20 Figure 30 Example for Delayed Off Behavior: Stop of Delayed Off Timer with Ready State

9.5 Electrical Characteris tics Direct Drive Inputs

Table 27 Electrical Characteristics Direct Drive Inputs VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Direct Drive Inputs IN1 to IN12 Low Level Input Voltage VIN,l -0.3 – 0.9 V – P_9.5.1 High Level Input Voltage VIN,h 2– VVDDIO V– P_9.5.2 Input Voltage Hysteresis VIN,hys 50 200 – mV – P_9.5.3 Pull Down Current IIN,pd 25 – 100 µA VIN=VVDDIO P_9.5.4 Pull Down Current IIN,pd 2.4 – – µA VIN=0.6V P_9.5.5 Delayed Switch Off for OUT17 and OUT21 Switch On Time in Delayed Switch Off Mode ton,del 400 – 800 ms – P_9.5.6 reset Watchdog Operation State Delayed Off Trigger Status Delayed Off Timer O17/O21 O17D/O21D Remaining Power Stages Remaining OEx Bits OE17/OE21 no trigger event e.g. V5VUV=1 Ready State Safe State reset Count up no trigger event ON „1" ON OFF „1" „1" „0" MSC time out Ready State Watchdog Error Counter <33 Start of delayed off mode OE „1"

Data Sheet 67 Rev. 1.1, 2014-08-20 Figure 31 Switching Behavior INx OUTn CSN MSC Communication Dataframe switch on t t t Dataframe switch off 0.8* Vbat 0.2* Vbat td,on td,offts,on ts,off Vbat

9.6 Low Side Switches OUT1 to OUT7 and OUT14 to OUT20

applications. The outputs are fully protected and various diagnosis functions are implemented. They are controlled and enabled like all power stages according the description in Chapter 9.1 and Chapter 9.2. To enable the low side switches OUT1 to OUT4 additionally the enable pin INJEN must be “high”. implemented. For the description of the diagnosis function see Chapter 9.6.2. power stages see Chapter 13.1.1, Downstream Supervisory Functions.

9.6.1 Protection of OUT1 to OUT7 and OUT14 to OUT20

The outputs are fully protected against over current and over temperature. For the procedure to switch on an affected channel after failure condition see Chapter 9.2.

9.6.2 Diagnosis of OUT1 to OUT7 and OUT14 to OUT20

and short to GND (SCG) in off a special circuit is implemented. Table 28. With the readout of the diagnosis register the content is updated to the actual diagnosis. occur and is deactivated. With deactivated pull down current the short to GND detection is active. O18DIAG1, O19DIAG1 and O20DIAG1 are “0”.

Data Sheet 69 Rev. 1.1, 2014-08-20 Figure 32 Output behavior with active diagnosis in off

9.6.3 Electrical Character istics Low Side Switches OUT1 to OUT7 and OUT14 to

Table 28 Description of Diagnosis Information OnDIAG[1:0] Priority (1 = highest priority) 01 1 short circuit to battery (over current) or over temperature 10 2 open load in off1) 2) 1) no open load in off detection with deactivated pull down current 2)no open load and short to GND in off signalization for OUT18 toOUT20 if pull up and down currents are switched off 11 3 short circuit to ground in off2) Table 29 Electrical Characteri stics Low Side Switches OUT1 to OUT7 and OUT14 to OUT20 VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. OUT1...4, n=1 to 4 Operation Current IOUTn –– 2 . 2 A P_9.6.1 Limitation Current in Over-current condition IOUTn,lim 2.2 – 4 A P_9.6.2 Over-current Detection Filter Time toc,f 40 – 70 µs P_9.6.3 On Resistance ROUTn,on –5 5 0 m Ω IOUTn=2.2A P_9.6.4 Clamping Voltage VOUTn,cv 50 – 60 V IOUTn=0.2A P_9.6.5 pull up and down current active pull down current switched off IOUTn Idiag,pu min VBATVOUTn_BIAS VOUTn O.K.OLSCG VolVscg Idiag,pu max Idiag,pd max Idiag,pd min pull down current switched off O.K.SCG IOUTn,l

Data Sheet 70 Rev. 1.1, 2014-08-20 Repetitive Clamping Energy EOUTn,cl –– 4 m J IOUTn<1.4A, Tj=125°C, 648*106 cycles1) P_9.6.6 Leakage Current 1 IOUTn,l,1 –– 5 µ A VOUTn=13.5V, VBAT=0V, Tj=60°C1)2) P_9.6.7 Leakage Current 2 IOUTn,l,2 –– 1 0 µ A VOUTn=28V, VBAT=0V, Tj=60°C1)2) P_9.6.8 Leakage Current 3 IOUTn,l,3 –– 2 0 µ A VOUTn<28V, VBAT=0V, Tj=150°C2) P_9.6.9 Turn On Delay Time td,on 1– 7 µ s VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.10 Turn Off Delay Time td,off 1– 8 µ s VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.11 Switch On Time ts,on 1.8 – 7 µs VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.12 Switch Off Time ts,off 1.8 – 7 µs VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.13 OUT5...7, n=5 to 7 Operation Current IOUTn –– 4 . 5 A P_9.6.14 Limitation Current in Over-current condition IOUTn,lim 4.5 – 8 A P_9.6.15 Over-current Detection Filter Time toc,f 40 – 70 µs P_9.6.16 On Resistance ROUTn,on –3 5 0 m Ω IOUTn=3A P_9.6.17 Clamping Voltage VOUTn,cv 50 – 60 V IOUTn=0.2A P_9.6.18 Repetitive Clamping Energy EOUTn,cl –– 2 2 m J IOUTn<1.05A, Tj=125°C, 1*109 cycles1) P_9.6.19 Leakage Current 1 IOUTn,l,1 –– 5 µ A VOUTn=13.5V, VBAT=0V, Tj=60°C1)2) P_9.6.20 Leakage Current 2 IOUTn,l,2 –– 1 0 µ A VOUTn=28V, VBAT=0V, Tj=60°C1)2) P_9.6.21 Leakage Current 3 IOUTn,l,3 –– 3 0 µ A VOUTn<28V, VBAT=0V, Tj=150°C2) P_9.6.22 Table 29 Electrical Characteri stics Low Side Switches OUT1 to OUT7 and OUT14 to OUT20 (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 71 Rev. 1.1, 2014-08-20 Turn On Delay Time td,on 1– 7 µ s VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.23 Turn Off Delay Time td,off 1– 7 µ s VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.24 Switch On Time ts,on 1.4 – 7 µs VOUTn=13.5V, IOUTn=2.2A, resistive load3) P_9.6.25 Switch Off Time ts,off 1.4 – 7 µs VOUTn13.5V, IOUTn=2.2A, resistive load3) P_9.6.26 OUT14...20, n=14 to 20 Operation Current IOUTn –– 0 . 6 A P_9.6.27 Limitation Current in Over-current condition IOUTn,lim 0.6 – 1.5 A P_9.6.28 Over-current Detection Filter Time toc,f 40 – 70 µs P_9.6.29 On Resistance ROUTn,on –1 . 5 Ω IOUTn=0.6A P_9.6.30 OUT17 On Resistance at Low Battery Voltage ROUT17,on,l –1 . 7 Ω IOUTn=0.1A, VBATPx=4.5V P_9.6.31 Clamping Voltage VOUTn,cv 50 – 60 V IOUTn=0.2A P_9.6.32 Repetitive Clamping Energy EOUTn,cl –– 6 . 5 m J IOUTn<0.3A, Tj=125°C, 40*106 cycles1) P_9.6.33 Leakage Current 1 IOUTn,l,1 –– 5 µ A VOUTn=13.5V, VBAT=0V, Tj=60°C1)2) P_9.6.34 Leakage Current 2 IOUTn,l,2 –– 1 5 µ A VOUTn=28V, VBAT=0V, Tj=60°C1)2) P_9.6.35 Leakage Current 3 IOUTn,l,3 –– 3 5 µ A VOUTn=28V, VBAT=0V, Tj=150°C2) P_9.6.36 Turn On Delay Time td,on 1– 7 µ s VOUTn=13.5V, IOUTn=0.3A, resistive load3) P_9.6.37 Turn Off Delay Time td,off 1– 7 µ s VOUTn=13.5V, IOUTn=0.3A, resistive load3) P_9.6.38 Switch On Time ts,on 1.1 – 5.6 µs VOUTn=13.5V, IOUTn=0.3A, resistive load3) P_9.6.39 Table 29 Electrical Characteri stics Low Side Switches OUT1 to OUT7 and OUT14 to OUT20 (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 72 Rev. 1.1, 2014-08-20 Switch Off Time ts,off 1.1 – 5.6 µs VOUTn=13.5V, IOUTn=0.3A, resistive load3) P_9.6.40 Delayed Off Time after trigger event for OUT17 toff,del 400 – 800 ms P_9.6.41 Diagnosis OUT1 to 7 and OUT14 to 20 Over Temperature Switch Off Threshold TOUTn,ot 150 – 200 °C 1) P_9.6.42 Over Temperature Hysteresis TOUTn,ot,hys –1 0 – ° C 1) P_9.6.43 Open Load in Off Detection Threshold Vol V5V- 0.15 V5V V5V + 0.15 V P_9.6.44 Short to GND in Off Detection Threshold Vscg 0.6*V 5V- 0.15 0.6* V5V 0.6*V 5V+0 .15 V P_9.6.45 Diagnosis Pull Up Current Idiag,pu -270 – -150 µA VOUTn=0V, VIGNx≥0V P_9.6.46 Diagnosis Pull Down Current Idiag,pd 280 – 500 µA V ol<VOUTn<VBAT, VIGNx≥0V P_9.6.47 Diagnosis Filter Time for open load and short to GND in off tdiag,f 60 – 135 µs P_9.6.48 Direct Drive Inputs INJEN Low Level Input Voltage VIN,l -0.3 – 0.9 V P_9.6.49 High Level Input Voltage VIN,h 2– VVDDIO V P_9.6.50 Input Voltage Hysteresis VIN,hys 50 200 – mV P_9.6.51 Pull Down Current IIN,pd 25 – 100 µA VIN=VVDDIO P_9.6.52 Pull Down Current IIN,pd 2.4 – – µA VIN=0.6V P_9.6.53 1) Parameter is not subject of production test, specified by design 2)additionally diagnosis currents are active in operation mode; exception OUT18 to OUT20 in diagnosis current switch off configuration 3) see Figure 31 Table 29 Electrical Characteri stics Low Side Switches OUT1 to OUT7 and OUT14 to OUT20 (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 73 Rev. 1.1, 2014-08-20

9.7 Half Bridges OUT21 to OUT24

The TLE8888-1QK integrates 4 half bridges which can be used as half bridge, full bridge, low side power stage or high side power stage. They are fully protected against overload and over-temperature and diagnosis fits to the chosen setup of the load. For the description of the diagnosis function see Chapter 9.7.2. They are controlled and enabled like all power stages according the description in Chapter 9.1 and Chapter 9.2. In Table 30 the effect of O21E to O24E and O21ON to O24ON to the high side and low side switch of the half bridge is shown. The half bridges can be configured via MSC/SPI for high or low side loads (setup see Figure 33) and for passive or active freewheeling (freewheeling is done with bulk di ode or actively with switching on the freewheeling path). In Table 30 the configuration is shown. With the bits O21M to O24M of the configuration register BriConfig0 the switching mode is defined. With this co nfiguration the low or the high side tr ansistor is defined to switch on the load. For low side switch mode the load is connected to the battery, for high side switch mode the load is connected to GND (see Figure 33). With the bits O21F to O24F of the configuration register BriConfig0 the freewheeling behavior is defined. The freewheeling is done for low side switch mode with the high side transistors. For passive freewheeling the bulk diode is used and the freewheeling transistor is always off. For the active freewheeling mode the freewheeling transistor is on during an off signal. This is the so called half bridge mode. The alternate switching of the high side and low side switch is done with a break before make phase. The definition of the switching mode is important for the correct diagnosis in off (see Chapter 9.7.2). The bits FB1E and FB2E (full bridge enable) are only used for the diagnosis in off for full bridge set up. FB1E = “1” is used for loads connected between OUT21 and OUT22. FB2E = “1” is used for loads connected between OUT23 and OUT24. The diagnosis in off setup is changed to the special situation of full bridge mode. The setting with O21M to O24M and O21F to O24F are valid. Note: for full bridge set up the same set up for the two half bridges is recommended! Table 30 Configuration of the Half Bridge OnM1) OnF1) OnE1) OnON=11) OnON=01) Description 0 0 0 high side =off low side = off high side =off low side = off low side switch mode and passive freewheeling at high side:2) both switches are disabled 0 0 1 high side =off low side = on high side =off low side = off low side switch mode and passive freewheeling at high side:2) high side switch always off, bulk diode of high side switch is used for passive freewheeling 0 1 0 high side =off low side = off high side =off low side= off low side switch mode and active freewheeling at high side:2) both switches are disabled 0 1 1 high side =off low side = on high side =on low side= off low side switch mode and active freewheeling at high side:2) high side switch on during freewheeling 1 0 0 high side =off low side= off high side =off low side= off high side switch mode and passive freewheeling at low side:2) both switches are disabled 1 0 1 high side =on low side= off high side =off low side= off high side switch mode and passive freewheeling at low side:2) low side switch always off, bulk diode of low side switch is used for passive freewheeling

Data Sheet 74 Rev. 1.1, 2014-08-20 Figure 33 Load setups for half and full bridge mode

9.7.1 Protection of Half Bridges OUT21 to OUT24

The half bridge outputs are fully protected against over-current and over-temperature. In failure case (e.g. short to GND) the affected transistor is switched off after the “Over-current Switch Off Filter Time” and the diagnosis bit is set. The half bridge output is high ohmic (tristate). To cover all failure conditions the over temperature prot ection is implemented. After exceeding the temperature threshold the half bridge outputs are switched of f till the temperature is decreased by the “ Over Temperature 1 1 0 high side =off low side= off high side =off low side= off high side switch mode and active freewheeling at low side:2) both switches are disabled 1 1 1 high side =on low side= off high side =off low side= on high side switch mode and active freewheeling at low side:2) low side switch on during freewheeling 1) n=21 to 24 for the selected half bridge channel 2) setup definition see Figure 33 Table 30 Configuration of the Half Bridge (cont’d) OnM1) OnF1) OnE1) OnON=11) OnON=01) Description OUT21 Protection Overtemp Overcurrent Diagnosis Open Load Short to GND Short to Bat Half Bridge 0.6A OUT22 Protection Overtemp Overcurrent Diagnosis Open Load Short to GND Short to Bat Half Bridge 0.6A OUT23 Protection Overtemp Overcurrent Diagnosis Open Load Short to GND Short to Bat Half Bridge 0.6A OUT24 Protection Overtemp Overcurrent Diagnosis Open Load Short to GND Short to Bat Half Bridge 0.6A Half Bridge Mode : Low Side Switch Mode with Freewheeling at High Side Half Bridge mode : High Side Switch Mode with Freewheeling at Low Side Full Bridge Mode

Data Sheet 75 Rev. 1.1, 2014-08-20 Hysteresis”. For the procedure to switch on an affected channel after failure condition see Chapter 9.2.

9.7.2 Diagnosis of Half Bridges OUT21 to OUT24

For the half bridge outputs various diagnosis function ar e implemented. For short to battery and short to GND in on diagnosis the protection function over current is used (diagnosis bits O21OC to O24OC in diagnosis register BriDiag1). Over temperature is signalized with the diagnosis bits B1OT and B2OT in diagnosis register BriDiag1. For open load and short to GND (SCG) in off a special circuit is implemented. The diagnosis bits O21DIA to O24DIA in diagnosis register BriDiag0 are set according the setup of the channels and according the priority shown in Table 31. Figure 34 Open Load and Short to GND/Battery Detection Circuit for Half Bridge Configuration (Low or High Side Load) Vol,high Vol,low BATPx OnDIAG0 OnDIAG1 Decoder

Data Sheet 78 Rev. 1.1, 2014-08-20 Note: For high side switch mode (low side load) after start up there will be a short to ground detection before the output is configured to high side load and the diagnosis bits are set to “11”. This detection is not right and it is recommended to read out the diagnosis registers twice after start up to avoid wrong diagnosis information.

9.7.3 Electrical Charact eristics Half Bridges

Table 31 Description of Diagnosis Information Single Switch Usage OnDIAG[1:0]1) 1) n from 21 to 24 Priority (1 = highest priority) High Side Switch Mode Low Side Switch Mode 00 3 no failure no failure 01 2 open load in off n.a. 10 2 n.a. open load in off 11 1 short circuit to battery in off short circuit to ground in off Table 32 Description of Diagnosis Information in Full Bridge Mode OnDIAG[1:0]1) 1) n = 21 and m=22 or n=23 and m=24 OmDIAG[1:0]1) Full Bridge Mode 00 00 no failure Single Failure 00 01 open load in off (or double fault open load and short to GND at OUT22 /OUT24) 10 10 short circuit to battery in off 01 01 short circuit to ground in off (or double fault open load and short to GND at OUT21 /OUT23 Double Failure 00 10 open load and short circuit to bat at OUT22 /OUT24 in off 01 10 short circuit to ground at OUT21 /OUT23 and short circuit to battery at OUT22 /OUT24 in off 10 01 short circuit to battery at OUT21 /OUT23 and short circuit to ground or open load at OUT22 /OUT24 in off Remaining Combinations 10 00 not existing or transition states after switch off xx 11 11 xx 01 00

Data Sheet 79 Rev. 1.1, 2014-08-20 Table 33 Electrical Characteristics Half Bridges VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. OUT21...24, n=21 to 24 Operation Current IOUTn –– 0 . 6 A P_9.1 Over-current Switch Off Threshold IOUTn,oc 0.6 – 1.5 A P_9.2 Over-current Switch Off Filter Time toc,f 0.5 – 2 µs P_9.3 On Resistance ROUTn,on –2 . 4 Ω IOUTn=0.3A P_9.4 OUT21 On Resistance at Low Battery Voltage, low temperature ROUT21,on,l, LT –2 . 4 Ω IOUTn=0.1A, VBAT=4.5V Tj<100°C P_9.5 OUT21 On Resistance at Low Battery Voltage, high temperature ROUT21,on,l, HT –2 . 6 Ω IOUTn=0.1A, VBAT=4.5V Tj>100°C P_9.6 Leakage Current, low side IOUTn,l,low –– 2 0 1) 1) In operation leakage current covered by open load current µA VOUTn=13.5V P_9.7 Leakage Current, high side IOUTn,l,high -201) –– µ A VOUTn=0V P_9.8 Turn On Delay Time2) 2) see Figure 31 for timing definition td,on –– 1 0 µ s I OUTn=0.3A, resistive load P_9.9 Turn Off Delay Time2) td,off 0.1 – 10 µs I OUTn=0.3A, resistive load P_9.10 Switch On Time2) ts,on 0.9 – 2.5 µs I OUTn=0.3A, resistive load P_9.11 Switch Off Time2) ts,off 0.9 – 2.5 µs I OUTn=0.3A, resistive load P_9.12 Diagnosis OUT21 to 24 Over Temperature Switch Off Threshold TOUTn,ot 150 – 200 °C 3) 3) not subject to production test, specified by design P_9.13 Over Temperature Hysteresis TOUTn,ot,hys –1 0 – ° C 3) P_9.14 Open Load in Off Detection Threshold High Limit Vol,high 0.9*V5V -0.2 0.9* V5V 0.9*V5V +0.2 V P_9.15 Open Load in Off Detection Threshold Low Limit Vol, low 0.5*V5V -0.2 0.5* V5V 0.5*V5V +0.2 V P_9.16 Diagnosis Pull Up Current Idiag,pu -980 – -220 µA P_9.17 Diagnosis Pull Down Current Idiag,pd 150 – 300 µA P_9.18 Bridge Diagnosis Activation Time tbr,diag, act 60 – 135 µs P_9.19 Bridge Diagnosis Filter Time tbr,diag, f 0.5 – 2 µs P_9.20

Data Sheet 80 Rev. 1.1, 2014-08-20

9.8 Push Pull Stages OUT8 to OUT13 and DFB8 to DFB13

These 5V push pull stages are designed for driving on -board MOSFET’s. The outputs are fully protected and various diagnosis functions are implemented. They are controlled and enabled like all power stages according the description in Chapter 9.1 and Chapter 9.2. In off (“0” in control register or “low” at the configured direct drive input pin) the low side transistor of the push/pull stage is on and forces a “low voltage level at the pin.

9.8.1 Protection of OUT8 to OUT13

There are functions implemented to detect short to battery at the external MOSFET and to protect the driver outputs. For the short to battery detection feedback pins DFB8 to DFB13 are implemented to sense the voltage at the drain of the external MOSFET. The short to battery detect ion in on is done by comparing the voltage level of the drain feedback pins with the short to bat detection threshold. A short is detected after the “ Short to Battery Detection Filter Time ”. In case of short to battery the output is switched off and the corresponding diagn osis bits in the diagnosis register OutDiag1 to OutDiag3 are set according the priority shown in Table 34. There are four diff erent thresholds, “ Short to Battery Detection Threshold in On 1 ” to “Short to Battery Detection Threshold in On 4 ”, implemented so that the detection threshold can be adapted to the used MOSFET. The diagnosis of the push pull stages can be set in three groups. The configuration is done with the bits PP0D to PP2D in the configuration register OutConfig2 and OutConfig3. The protection of the driver ou tput pins is done by comparing the output voltage on the pins OUT8 to OUT13 with the “Over Voltage Detection Threshold”. An over voltage (e.g. short to battery) is detected after the “Over Voltage Diagnosis Filter Time” and the corresponding diagnosis bits in the diagnosis register PPOVDiag is set. In case of over voltage high and low side transistors of the push pull driver are switched off (high ohmic state).

9.8.2 Diagnosis of OUT8 to OUT13

For the push pull stages OUT8 to OUT13 various diagnosis functions for the external MOSFETs are implemented. The open load, short to ground in off and sh ort to battery in on detection is done via the drain feedback DFB8 to DFB13. The diagnosis pull down current of the op en load/short to ground in off detection can be switched off (see configuration register OutConfig2). With deactivated pull down current open load in off detection is not active and the dia gnosis information of OnDIAG[1:0]=10 B will never occur. With deactivated pull down current the short to ground detection is active. In Figure 39 the behavior of the output current as a function of the output voltage is shown. Figure 39 Output behavior in off with open load and short to GND detection of DFB8 to DFB13 pull up and down current active pull down current switched off IOUTn Idiag,pu min VBATVOUTn_BIAS VOUTn O.K.OLSCG VolVscg Idiag,pu max Idiag,pd max Idiag,pd min pull down current switched off O.K.SCG IOUTn,l

Data Sheet 81 Rev. 1.1, 2014-08-20 Whenever the push pull stages are off the open load/sho rt to GND detection circui t is enabled. To suppress disturbances the output of the detection circuit is stored in the diagnosis register OutDiag1 to OutDiag3 after the Diagnosis Filter Time for Open Load and Short to GND in Off Detection tdiag,f and according the priority shown in Table 34. With the readout of the diagnosis register the content is updated to the actual diagnosis.

9.8.3 Electrical Character istics Push Pull Stages OUT8 to OUT13

Table 34 Description of Diagnosis Information ( DFB8 to DFB13) OnDIAG[1:0] Priority (1 = highest priority) 01 1 short circuit to battery 10 2 open load in off1) 1) no open load in off detection with deactivated pull down current 11 3 short circuit to ground in off Table 35 Electrical Characteristics Push Pull Stages OUT8 to OUT13 Stages on or off, VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with resp ect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. OUT8...13, n=8 to 13 High Level Output Voltage V OUTn,h 4– 5 . 5 V I OUTn=-5mA P_9.8.1 Low Level Output Voltage V OUTn,l –– 0 . 6 V I OUTn=5mA P_9.8.2 Pull up current I OUTn,pu –– - 2 0 m A V OUTn=0V, OUTn on P_9.8.3 Pull down current I OUTn,pd 20 – – mA V OUTn=5V, OUTn off P_9.8.4 Over Voltage Detection Threshold VOUTn,ov,th 5.5 – 7.7 V P_9.8.5 Over Voltage Diagnosis Filter Time tOUTn,ov,f 5– 1 0 µ s P_9.8.6 Diagnosis DFB8 to DFB13 Short to Battery Detection Threshold in On 1 VDFBn,sb,1 90 125 150 mV referred to PGND P_9.8.7 Short to Battery Detection Threshold in On 2 VDFBn,sb,2 180 225 250 mV referred to PGND P_9.8.8 Short to Battery Detection Threshold in On 3 VDFBn,sb,3 350 400 450 mV referred to PGND P_9.8.9 Short to Battery Detection Threshold in On 4 Short to Battery Detection Filter Time VDFBn,sb,fl 10 – 15 µs P_9.8.11 Open Load in Off Detection Threshold Vol V5V- 0.2 V5V V5V + 0.2 V P_9.8.12

Data Sheet 82 Rev. 1.1, 2014-08-20

9.9 Push Pull Stages IGN1 to IGN4

The IGN1 to IGN4 are 5V push pull stages for on- and off-bo ard ignition power stages (e.g. with IGBT’s, darlington transistors). For off board ignition power stages the outputs IGN1 to IGN4 are equipped with a back supply suppression (in case of a short circuit from IGN1 to IGN4 to battery there is no parasitic current flow back to 5V). They are controlled and enabled like all power stages according the description in Chapter 9.1 and Chapter 9.2. Additionally a “high” at the pin IGNEN is needed to enable the outputs. In off (“0” in control register or “low” at the configured direct drive input pin or IGNEN is “low”) the low side transistor of the push/pull stage is on and forces a “low voltage level at the pin. The outputs are fully protected and various diagnosis functions are implemented.

9.9.1 Protection of IGN1 to IGN4

The protection of the outputs is done by detecting short to battery and short to ground. This is done by comparing the output voltage level with the “ Short to Battery Detection Threshold and Short to Ground Detection Threshold”. To suppress disturbances the output signal of the short to GND and short to battery detection circuit is stored in the diagnosis register IgnDiag after the “ Diagnosis Filter Time for Short to GND and Battery Detection” tdiag,f,sc and according the priority shown in Table 36. During detected short to GND the output is switched off (l ow side transistor of push /pull stage is on), during detected short to battery the output is high ohmic (tristate). The short to battery detection is always active. The short to ground detection is enabled with the on signal of the output stage. Additionally an over temperature protection is implemented. There is one common sensor for IGN1 and IGN2 and one for IGN3 and IGN4.

9.9.2 Diagnosis of IGN1 to IGN4

An open load detection during the switch on phas e is implemented and can be enabled with the bit IOLA in the configuration register IGNConfig. In Figure 40 the detection principle is shown. When the open load detection in on is enabled, first the output is pulled up by a defined current, which is set by the bits IOLI in the configuration register IGNConfig. The output voltage, which is passed to the detection circuit, is filtered (“Diagnosis Filter Time for Open Load Detection”) to suppress disturbances. After the open load time (“ Open Load Time 1 ” to “Open Load Time 4“selected in configuration register IGNConfig bits IOLT) the filtered output is compared with the Open Load Short to GND in Off Detection Threshold Vscg 0.5*V 5V- 0.2 0.5* V5V 0.5*V 5V+0. V P_9.8.13 Diagnosis Pull Down Current in Off Idiag,pd 220 – 600 µA VDFBn=13.5V P_9.8.14 Diagnosis Pull Up Current in Off Idiag,pu -300 – -100 µA VDFBn=0V P_9.8.15 Diagnosis Filter Time for Open Load and Short to GND in Off Detection tdiag,f,off 60 – 135 µs P_9.8.16 Pull Down Current in On Idiag,pd,on –– 1 . 8 µ A VDFBn=5V P_9.8.17 Table 35 Electrical Characteristics Push Pull Stages OUT8 to OUT13 (cont’d) Stages on or off, VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with resp ect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 83 Rev. 1.1, 2014-08-20 Detection Threshold Vol. The diagnosis register IgnDiag is set if the filtered output is higher than the Open Load Detection Threshold and the output is fully switched on. The failures are stored in the diagnosis register according the priority shown in Table 36 with “1” is the highest priority. With the readout of the diagnosis register IgnDiag the content is updated to the actual diagnosis. Figure 40 Ignition Output Open Load Detection

9.9.3 Electrical Character istics Push Pull Stages IGN1 to IGN4

Table 36 Description of Diagnosis Information ( IGN1 to IGN4) IGNnDIAG[1:0]P r i o r i t y (1 = highest priority) 01 1 short circuit to battery or over temperature 10 2 open load 11 3 short circuit to ground in on Table 37 Electrical Characteristics Push Pull Stages Stages on or off, VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with resp ect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. IGN1...4, n=1 to 4 High Level Output Voltage V IGNn,h 4.35 – – V I IGNn=-15mA, P_9.9.1 Low Level Output Voltage V IGNn,l –– 0 . 6 V I IGNn=5mA P_9.9.2 Pull up current I IGNn,pu –– - 2 0 m A V IGNn=0V, IGNn on P_9.9.3 t VIGN t -IIGN tol OFF ON Vol Iol open load measurement capturing of open load measuring result

Data Sheet 84 Rev. 1.1, 2014-08-20 Pull down current I IGNn,pd 20 – – mA V IGNn=5V, IGNn off P_9.9.4 Leakage current I L_IGNn –– 1 2 0 µ A V IGNn=13.5V P_9.9.5 Leakage current to V5V IL_IGNn,V5V –– 1 µ A V IGNn=13.5V P_9.9.26 Over Temperature Switch Off Threshold TIGNx,ot 150 – 200 °C 1) P_9.9.6 Over Temperature Hysteresis TIGNx,ot,hys 10 °C 1) P_9.9.7 Diagnosis IGN1 to IGN4 Short to Battery Detection Threshold VIGNn,scb 6.4 – 7.5 V P_9.9.8 Short to Ground Detection Threshold Vscg 1.6 – 2.3 V P_9.9.9 Diagnosis Filter Time for Short to GND and Battery Detection tdiag,f,sc 5– 1 0 µ s P_9.9.10 Open Load Detection Threshold Vol 4– 4 . 5 V P_9.9.11 Open Load Switch On Current 1 Iolf,1 -120 -100 -40 µA P_9.9.12 Open Load Switch On Current 2 Iolf,2 -500 -400 -300 µA P_9.9.13 Open Load Switch On Current 3 Iolf,3 -1.2 -1 -0.4 mA P_9.9.14 Open Load Switch On Current 4 Iolf,4 -5 -4 -2.5 mA P_9.9.15 Open Load Time 1 tol,1 50 60 70 µs P_9.9.16 Open Load Time 2 tol,2 210 250 290 µs P_9.9.17 Open Load Time 3 tol,3 450 510 570 µs P_9.9.18 Open Load Time 4 tol,4 690 775 860 µs P_9.9.19 Diagnosis Filter Time for Open Load Detection tdiag,f,olf 61 0 1 4 µ s P_9.9.20 Direct Drive Inputs IGNEN Low Level Input Voltage VIN,l -0.3 – 0.9 V P_9.9.21 High Level Input Voltage VIN,h 2– VVDDIO V P_9.9.22 Input Voltage Hysteresis VIN,hys 50 200 – mV P_9.9.23 Pull Down Current IIN,pd 25 – 100 µA VIN=VVDDIO P_9.9.24 Pull Down Current IIN,pd 2.4 – – µA VIN=0.6V P_9.9.25 1) Parameter is not subject of production test, specified by design Table 37 Electrical Characteristics Push Pull Stages (cont’d) Stages on or off, VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with resp ect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

VR and Hall Sensor Interface Data Sheet 85 Rev. 1.1, 2014-08-20

10 VR and Hall Sensor Interface

The variable reluctance (VR) sensor interface converts an output signal of a VR sensor into a push-pull logic level signal suited for micro controller input ports. To achieve the best accuracy for the positive and the negative edge of the VROUT signal the switching point is the zero crossing. For robustness against disturbances the next zero crossing is enabled only if a signal peak (minimum or maximum of the signal) is detected. The amplitude of the VR sensor signal is limited by an internal clamping circ uit to avoid damage of the device due to over voltage caused by the VR sensor signal. There are three operation modes for VR sensor applications and one Hall sensor mode implemented. The manuel VR sensor mode with static setup of the detection parameter under control of the micro controller via MSC/SPI and an auto mode with an adaptive algorithm to ensure be st detection performance. The semi auto mode is less accurate then the auto mode. The diagnosis VR sensor interface setup could be done by measuring the voltage between the two input pins during diagnosis mode. Additionally three diagnosis bits for short to battery, short to GND and open load (directly at the pins) are available. Figure 41 VR Sensor Interface Block diagram

10.1 Signal Detection

The signal detection for Hall sensor mode is a comparator with the switching threshold VVRIN1,th, hall and the hysteresis VVRIN1,hys, hall. The detection of the VR signal consist of the zero crossing detection, peak detection and the output filter. At the input there is a clamping circuit between the pins VRIN1 and VRIN2 suited to clamp the maximum current of VR sensors. The zero crossing detection ensures that the influence of the input signal slope is eliminated for both edges. To avoid disturbances due to the floating input signal a middle voltage is applied with the integrated load resistance. The clamping circuit between the pins VRIN1 and VRIN2 clamps the input voltage in both direction to protect the input structures. The clamping is suited fo r VR sensors with a maximum output current of DIVR,clamp (see Table 38). The peak detection is done by measuring the voltage difference by the analog to digital converter and the detection of the slope of the input signal. If the gradient of the slope changes the sign the next zero crossing detection is enabled. The detection of the sign is done by comparing the absolute value of the signal with the peak detection Differential Amplifier Comparator Low Pass Filter Peak & Time Measurement ADC Clamping VRIN1 VRIN2 VROUT Diagnosis on Diagnosis on Vmiddle MSC/SPI Detection Output Filter Diagnosis VDDIORVR,Load/2 RVR,Load/2

VR and Hall Sensor Interface Data Sheet 87 Rev. 1.1, 2014-08-20

10.2 Detection Modes

The TLE8888-1QK integrates four detection modes:

• auto detection mode for VR sensor signals
• manual detection mode for VR sensor signals
• semi auto detection mode for VR sensor signals
• detection mode for Hall sensor signals To select the various detection modes the bits VRSM in the configuration register VRSConfig1 must be set. Auto detection mode for VR sensor signals: In the auto detection mode an algorithm is setting all parameters to the optimal values to achieve the best detection behavior. The peak detection time is set due to the actual speed value, the peak detection threshold is set due to the level of the previous peaks. The output filter time (t of,1 to tof,4) is set by the micro controller independ ently to increase the robustness agai nst short disturbances at the inputs. Write access to the registers bits of VRSPT and VRSPV are ignored in auto detection mode. Semi auto detection mode for VR sensor signals: The algorithm of the semi auto mode is based on less number of measurement information as the auto detection mode. This leads to a simpler implementation of the detection algorithm. The output filter time (tof,1 to tof,4) is set by the micro controller independently to increase the robustness against short disturbances at the inputs. Write access to the registers bits of VRSPT and VRSPV are ignored in semi auto detection mode. Manual detection mode for VR sensor signals: In the manual detection mode the micro controller has the full control of all parameters of the detection and the algorithm of the auto detection modes are disabled. The settings are done via the MSC/SPI interface. Detection mode for Hall sensor signals: For the Hall sensor mode the pin VRIN2 is forced internally to the switching threshold VVRIN1,th, hall . The detection principle is a comparator with hysteresis. Write access to the registers bits of VRSPT and VRSPV are ignored in the detection mode for Hall sensor signals. The diagnosis is disabled. With this set up the number of external devices is reduced (see Chapter 17.2). Note: Switching between the different configuration must be avoided with active signals at the inputs VRIN1 and VRIN2.

10.3 Diagnosis for VR Sensor Signal Detection Modes

The TLE8888-1QK integrates three different diagnosis modes for the VR sensor interface:

• short to GND/short to battery diagnosis mode: detection of short to GND or short to battery directly at pins VRIN1 and VRIN2
• open load diagnosis mode: detection of open load directly at pins VRIN1 and VRIN2
• ADC measurement mode: measurement of the voltage between the pins VRIN1 and VRIN2 The modes are defined in the configuration register VRSConfig1 with the bits VRSDIAGM. The diagnosis of the VR sensor is done by ac tivating the diagnosis mode with the bits VRSDIAGM in the configuration register VRSConfig1 and starting diagnosis measurement with the bit VDIAGS in the command register Cmd0. With the activation of the VRS diagnosis mode at VRIN1 a pull up current source to the internal supply and at VRIN2 a pull down current source is applied (current configuration with bits VRSI_SC for short to GND/short to battery diagnosis mode, VRSI_OL for open load diagnosis mode and VRSI_ADC for ADC measurement mode in the configuration registers VRSConfig1 and VRSConfig2).To avoid bad influence of the time constants of the external circui try the timing of the measurement is controlled by the micro controller. The sequence is shown in Figure 44. The end of the diagnosis procedure triggered by the start command is signalized by the correspondent data valid bits VRSDV_SC (short to GND and short to battery diagnosis mode), VRSDV_OL (open load diagnosis mode) in diagnosis register VRSDiag0 and VRSDV_ADC (ADC measurement mode) in the diagnosis register VRSDiag1. For the detection thresholds see parameter Short to GND detection threshold , Short to battery detection

Data Sheet 88 Rev. 1.1, 2014-08-20 TLE8888-1QK VR and Hall Sensor Interface threshold and Open load detection threshold. The output of the ADC measurement is defined by the parameter ADC measurement gain and ADC measurement offset. The result of the diagnosis is av ailable in the diagnosis register VRSDiag0 with the bits VRSG (short to GND detection), VRSB (short to battery detection) and VRSOL (open load detection directly at the pins). The digital value of the ADC measurement is available in the register VRSDiag1 with the bits VRSD. This ADC value can be used by the micro controller to define additional error de tection conditions different to the defined short to GND, short to battery and open load thresholds. The data valid bits are reset with start of the corresponding diagnosis or with the readout of the register. Note: In detection mode for Hall sensor signals the diagnosis is deactivated and the values of VRSDIAGM and VRSI_SCin the register VRSConfig1,VRSI_ADC and VRSI_OL in register VRSConfig2 and the start command VDIAGS in the register Cmd0 are ignored.

VR and Hall Sensor Interface Data Sheet 89 Rev. 1.1, 2014-08-20 Figure 44 VRS Flow Chart For the measurement the internal circuits are changed. In Figure 45, Figure 46 and Figure 47 the block diagram of the different setups are shown. Diagnosis Mode Configuration (Bits VRSDIAGM/ VRSI_SC in Reg. VRSConfig1, Bits VRSI_ADC/VRSI_OL in Reg. VRSConfig2) Wait Phase (till transisent effects can be neglected) Start of Diagnosis Measurement (Bit VDIAG in Reg. Cmd0) Read out of Results (Register VRSDiag 0, VRSDiag1) Data Valid Bits active? End No Yes

VR and Hall Sensor Interface Data Sheet 91 Rev. 1.1, 2014-08-20 Figure 47 VRS Diagnosis Block Diagram for ADC Measurement Vamp,ADC ADC Register VRSDIAG 1 Idiag Idiag Vmiddle Register VRSDIAG1 = (VRIN1-VRIN2)/VADC,LSB +VADC,offset VRIN1 VRIN2 RVR,Load/2 RVR,Load/2 VADC

Data Sheet 92 Rev. 1.1, 2014-08-20 TLE8888-1QK VR and Hall Sensor Interface

10.4 Electrical Characteris tics VR Sensor Interface

Table 38 Electrical Characteristics: VR Sensor Interface VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input Characteristics: VR Sensor Interface Detection Threshold VVR,th -30 0 30 mV P_10.4.1 minimum amplitude for peak detection 1 VVR,peak,min,1 – 50 – mV reset value P_10.4.2 minimum amplitude for peak detection 2 VVR,peak,min,2 – 150 – mV P_10.4.3 minimum amplitude for peak detection 3 VVR,peak,min,3 – 350 – mV P_10.4.4 minimum amplitude for peak detection 4 VVR,peak,min,4 – 550 – mV P_10.4.5 minimum time for peak detection 1 tVR,peak,min,1 – 10 – µs reset value 1kHz sinusoidal signal P_10.4.6 minimum time for peak detection 2 tVR,peak,min,2 – 250 – µs 1kHz sinusoidal signal P_10.4.7 VR Sensor Interface Load Resistance RVR,Load 50 75 110 k Ω P_10.4.9 VR Sensor Interface Input Clamping Current ΔIVR,clamp ––5 0 m A ΔIVR,clamp=(IVRIN1- IVRIN2)/2 P_10.4.18 VR Sensor Interface Input Clamping Voltage ΔVVR,clamp 2–3V ΔVVR,clamp=|VVRIN1- VVRIN”|, IVR,calmp= 50mA P_10.4.19 Switching threshold voltage at pin VRIN1 for Hall Sensor Mode VVRIN1,th, hall 0.9 – 2 V no load at pin VRIN21) P_10.4.20 Switching hysteresis pin VRIN1 for Hall Sensor Mode VVRIN1,hys, hall 0.35 0.5 – V no load at pin VRIN2 P_10.4.10 Middle voltage level normal mode VRS Diagnosis: Middle voltage level diagnosis mode Diagnosis measurement time tconv –78µ s P_10.4.13

VR and Hall Sensor Interface Data Sheet 93 Rev. 1.1, 2014-08-20 Diagnosis current accuracy Idiag, acc -30% – +30% VRIN1=VRIN2= Vmiddle; typ. values see register VRSConfig1 and VRSConfig2 P_10.4.14 Short to GND detection threshold Vth,scg 0.8 – 1.1 V P_10.4.15 Short to battery detection threshold Vth,scb 2.8 – 3.3 V P_10.4.16 Open load detection threshold Vth,ol 0.9 – 1.2 V P_10.4.17 ADC measurement input range VADC,r -1.5 – 1.5 V P_10.4.8 ADC measurement gain VADC,LSB – 49 – mV valid from 6 d to 70d P_10.4.31 ADC measurement offset VADC,offset –3 7 d – P_10.4.32 Output Characteristics: Low Level Output Voltage - Low Output Current VVR_OUT,L,l ––0 . 4 V IVR_OUT = 100µA P_10.4.21 Low Level Output Voltage - High Output Current VVR_OUT,L,h ––1 . 5 V IVR_OUT = 1mA P_10.4.22 High Level Output Voltage - Low Output Current VVR_OUT,H,l VDDIO -0.4 ––V IVR_OUT = -100µA P_10.4.23 High Level Output Voltage - High Output Current VVR_OUT,H,h VDDIO -1.5 ––V IVR_OUT = -1mA P_10.4.24 Transfer Characteristics: Output Filter Time 1 tof,1 123µ s r e s e t v a l u e P_10.4.25 Output Filter Time 2 tof,2 567 . 5 µ s P_10.4.26 Output Filter Time 3 tof,3 9.5 11 13 µs P_10.4.27 Output Filter Time 4 tof,4 19 21 23 µs P_10.4.28 1) external circuitry for hall mode see Chapter 17.2 Table 38 Electrical Characteristics: VR Sensor Interface (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 94 Rev. 1.1, 2014-08-20 TLE8888-1QK Local Interconnect Network (LIN)

11 Local Interconne ct Network (LIN)

The LIN interface is designed for in-vehicle networks using data transmission up to 20kbit/s. The implementation of the physical layer is according to LIN specification revision 2.1 for slave nodes and is compatible with lower versions like revision 2.0 and 1.3 1). LINTX is the transmit-data input from the micro controller, LINIO is the bidirectional LIN bus signal and LINRX is the receive-data output to the micro controller. The transmitted data stream at LINTX is converted to the LIN bus signal at LINIO. LINRX reflects the received data at LINIO with a logic signal suited for 3.3V and 5V micro controller interfaces. The detection thresholds at LINIO are related to the power supply BATPA2). The LIN interface of the TLE8888-1QK is compatible to the physical layer definition of the K-Line (ISO 9141) standard. For K-Line operation no additional settings are necessary. A flash mode for high speed operation can be selected with the communication interface (MSC or SPI). There is no bus wake up function implemented. Figure 48 Local Interconnect Network (LIN) Slave Node The LIN interface in the TLE8888-1QK is implemented a ccording the requirements of the standard for slave nodes. For master setup an external pull up resistor (typ. 1kΩ, see definition in LIN specification) and a diode must be connected to LINIO and BATPA on the ECU (see Figure 49). 1) see LIN specification revision 2.1 chapter 6.2 2) BATPA is identical to the internal supply voltage VSUP defined in LIN specification revision 2.1 optional BATPA LINRX RLIN GND LINIO LINRX LINTX Dser,int internal Logic TLE8888 - LIN 2.1 LIN Bus ECU in LIN Slave Configuration BATECU GNDECU Micro Controller

Local Interconnect Network (LIN) Data Sheet 95 Rev. 1.1, 2014-08-20 Figure 49 Local Interconnect Network (LIN) Master Node

11.1 Operation Modes

The interface can be configured for three operation modes:

• LIN/K-Line Mode: operation according LIN specification revision 2.1 with a maximum speed of 20kbit/s and K-Line standard ISO 9141
• Receive Only Mode: transmission of data is disabled
• Flash Mode: operation up to 115 kbit/s is possible, slope control and current limitation are deactivated The selection of the modes is done with setting the bits LIN in the register ComConfig1 via communication interface (MSC or SPI). The operation mode after power on reset is defined by reset value of the register.

11.2 Failure Modes in LIN/K-Line Operation

In the LIN specification a special behavior of the interface is required for some failure conditions. This behavior is also active if a K-Line node is used.

11.2.1 Performance in Non Oper ation Supply Voltage Range

For supply voltages out of operation range the interface may still operate, but communication is not guaranteed. For LINTX = ‘high’ (recessive) the interface shall not drive LINIO to dominant state and if LINIO is in recessive state the LINRX output shall provide a ‘high’ (recessive).

11.2.2 Loss of Supply Volt age and GND Connection

During loss of supply voltage or GND connection the interface shall not interfere with the communication of other LIN nodes. Upon return of connection, normal operation shall resume without any intervention on the LIN bus line (pin LINIO). optional BATPA LINRX RLIN,Slave GND LINIO LINRX LINTX Dser,int internal Logic 1kOhm TLE8888 - LIN 2.1 LIN Bus ECU in LIN Master Configuration BATECU GNDECU Micro Controller

Data Sheet 96 Rev. 1.1, 2014-08-20 TLE8888-1QK Local Interconnect Network (LIN)

11.2.3 Bus Wiring Short to Battery or GND

The LIN interface is protected against short to battery or short to GND. Upon remove of the fault, normal operation shall resume without any intervention on the LIN bus line (pin LINIO).

11.2.4 TX Time Out

The TX time out function is implemented to prevent th e bus line from being blocked by a permanent ‘low’ at the pin LINTX caused by an error at the ECU or the micro controller. If the LINTX signal is ‘low’ (dominant) for t > ttimeout the transmission of the LINTX signal to the bus is deactivated and the LIN output stage is disabled. The transmission is reactivated, after a rising edge at LINTX was detected. The implemented time out feature requires a minimum data rate of 1600 bit/s. The time out function can be disabled with the configuration bit LINTOE in the configuration register ComConfig1.

11.2.5 Over Temper ature Protection

The LIN bus output LINIO is protected against overload with an ov er temperature protection. In case of over temperature the output transistor is switched off and the diagnosis bit LINOT in the diagnosis register ComDiag is set. The configuration register is not changed.

Local Interconnect Network (LIN) Data Sheet 97 Rev. 1.1, 2014-08-20

11.3 Electrical Characteristics LIN

Table 39 Electrical Characteristics: LIN VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Supply voltage range for normal operation VBATPA,LIN 7 – 18 V acc. Param 10 LIN Spec. Rev. 2.1 P_11.3.1 Limitation Current at LINIO for driver dominant state ILINIO,lim 40 – 200 mA acc. Param 12 LIN Spec. Rev. 2.1 P_11.3.2 Leakage Current at LINIO for bus dominant state and driver off ILINIO,leak,dom -1 – – mA acc. Param 13 LIN Spec. Rev. 2.1 VLINIO=0V VBAT=12V P_11.3.3 Leakage Current at LINIO for bus recessive state ILINIO,leak,rec ––2 0 μA acc. Param 14 LIN Spec. Rev. 2.1 VLINIO>VBAT P_11.3.4 Current at LINIO during GND loss ILINIO,no_GND -1 – 1 mA acc. Param 15 LIN Spec. Rev. 2.1 GND=VS 0V<VLINIO<18V VBAT=12V P_11.3.5 Current at LINIO during power supply loss ILINIO,no_Sup ––2 0 μA acc. Param 16 LIN Spec. Rev. 2.1 GND=VS=0V 0V<VLINIO<18V P_11.3.6 Receiver Dominant State VLINIO,dom – – 0.4* VBA TPA V acc. Param 17 LIN Spec. Rev. 2.1 P_11.3.7 Receiver Recessive State VLINIO,rec 0.6*VBA TPA – – V acc. Param 18 LIN Spec. Rev. 2.1 P_11.3.8 Receiver switching threshold center voltage VLINIO,cnt 0.475* VBATPA – 0.525* VBATPA V acc. Param 19 LIN Spec. Rev. 2.1 VLINIO,cnt=(Vth, dom+Vth,rec)/2 P_11.3.9

Data Sheet 98 Rev. 1.1, 2014-08-20 TLE8888-1QK Local Interconnect Network (LIN) Hysteresis of switching threshold VHys – – 0.175* VBATPA V acc. Param 20 LIN Spec. Rev. 2.1 VHys=Vth,rec-Vth,dom P_11.3.10 voltage drop at internal serial diode Dser,int VD 0.4 – 1 V acc. Param 21 LIN Spec. Rev. 2.1 P_11.3.11 Resistance of internal slave resistor Rslave RLIN,Slave 20 – 60 k Ω acc. Param 26 LIN Spec. Rev. 2.1 P_11.3.12 Duty cycle 1 D1 0.396 – – – acc. Param 27 LIN Spec. Rev. 2.1 P_11.3.13 Duty cycle 2 D2 – – 0.581 – acc. Param 28 LIN Spec. Rev. 2.1 P_11.3.14 Duty cycle 3 D3 0.417 – – – acc. Param 29 LIN Spec. Rev. 2.1 P_11.3.15 Duty cycle 4 D4 – – 0.59 – acc. Param 30 LIN Spec. Rev. 2.1 P_11.3.16 propagation delay of receiver rising edge trx,pd,r ––6 μs acc. Param 31 LIN Spec. Rev. 2.1 P_11.3.17 propagation delay of receiver falling edge trx,pd,f ––6 μs acc. Param 31 LIN Spec. Rev. 2.1 P_11.3.18 propagation delay symmetry of receiver trx,pd,sym -2 – 2 μs acc. Param 32 LIN Spec. Rev. 2.1 P_11.3.19 TX Dominant Time Out Time ttimeout 6 12 20 ms min. data rate of 1600bit/s required P_11.3.20 Bus Recessive Output Voltage VBUS,rec 0.8*VBA TPA ––V P_11.3.21 Bus Dominant Output Voltage VBUS,do ––1 . 4 V VBATPA=7V Rpu=500Ω P_11.3.22 Bus Dominant Output Voltage VBUS,do ––2 . 2 V VBATPA=18V Rpu=500Ω P_11.3.23 LINIO Input Capacitance CLINIO –1 5 2 5 p F 1) P_11.3.24 Table 39 Electrical Characteristics: LIN (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Local Interconnect Network (LIN) Data Sheet 99 Rev. 1.1, 2014-08-20 Over Temperature Switch Off Threshold TLIN,ot 150 – 200 1) P_11.3.25 Over Temperature Hysteresis TLIN,ot,hys –1 0 – 1) P_11.3.26 LINRX Output Characteristics Low Level Output Voltage - Low Output Current VLINRX,L,l ––0 . 4 V ILINRX = 100µA P_11.3.27 Low Level Output Voltage - High Output Current VLINRX,L,h ––1 . 5 V IVR_OUT = 1mA P_11.3.28 High Level Output Voltage - Low Output Current VLINRX,H,l VDDIO -0.4 ––V ILINRX = -100µA P_11.3.29 High Level Output Voltage - High Output Current VLINRX,H,h VDDIO -1.5 ––V ILINRX = -1mA P_11.3.30 LINTX Input Characteristics Low Level Input Voltage VLINTX,l -0.3 – 0.9 V P_11.3.31 High Level Input Voltage VLINTX,h 2– VVDDIO V P_11.3.32 Input Voltage Hysteresis VIN,hys 50 200 – mV P_11.3.33 Pull Up Current ILINTX,pu -100 – -25 µA VLINTX=0V P_11.3.34 Pull Up Current ILINTX,pu ––- 2 . 4 µ A VLINTX=VDDIO- 0.6V P_11.3.35 1) Not subject to production test, specified by design Table 39 Electrical Characteristics: LIN (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 100 Rev. 1.1, 2014-08-20 TLE8888-1QK Local Interconnect Network (LIN) Figure 50 Timing Diagram of the LIN Interface VS VLINIO,rec GND t t VLINIO LINTX 0.6 * VS VLIN,cnt LINRX Vth,rec Vth,dom trx,pd,f trx.pd,r tBIT.dom tBIT tBIT tBIT VBAT t 0.4 * VS VLINIO,dom

High Speed Controller Area Network (CAN) Transceiver Data Sheet 101 Rev. 1.1, 2014-08-20

12 High Speed Controller Area Network (CAN) Transceiver

The Controller Area Network (CAN) is a serial bus system that connects micro controller, sensors and actuators for real-time control applications. The integrated CAN interface provides the physical layer of the CAN according to ISO 11898. It is suitable for high speed differential data transmission and reception. It wo rks as an interface between the CAN protocol controller and the physical bus lines. Remote wake up function with a dominant signal at the bus lines is implemented.

12.1 Functional Description

The high speed CAN is a two wire differential network whic h allows data transmission rates up to 1Mbit/s. The input CANTX and the output CANRX are connected to the micro controller of the ECU. As shown in Figure 51, the CAN has a receive unit and a out put driver stage, allowing the transceiver to send data to the bus line and monitor data from the bus lines at the same time. It conver ts the serial data stream available at the transmit data input CANTX into a differential output signal at CANH and CANL. The receiver stage monitors CANH and CANL and converts the differential voltage to a serial data stream at CANRX. The supply of the CAN transceiver is done out of V5VCAN, the wake receiver is supplied out of V5VSTBY. The pin V5VCAN must be connected directly to the 5V supply pin V5V. In order to optimize EMC performance a ceramic capacitor CV5VCAN should be connected to the pins V5VCAN and PGND (pin 50). Figure 51 High speed CAN topology

12.2 Operation Modes

Four different operation modes are available. Regardless of the supply status the CAN interface does not disturb the communication on the bus line. CANH CANL ESD RDIV CMP RxD_BUF CANRX TxD_BUF CANTXDRV DIAG analog Error Register analog filter deglitcher RL Wake Receiver CANWK V5VSTBYCANWKEN MSC/SPI Interface SDO SINWKCLR V5VCAN CAN Transceiver RL CAN node n CAN node n-1 VDDIO

Data Sheet 102 Rev. 1.1, 2014-08-20 TLE8888-1QK High Speed Controller Area Network (CAN) Transceiver

12.2.1 Normal Operation Mode

In normal operation mode the CAN transceiver send s the serial data stream available at the pin CANTX to the CAN bus while at the same time the data ava ilable at the CAN bus is monitored at the CANRX pin. In normal operation mode all functions are active:

• The driver output is active and drives data from the CANTX pin to the CAN bus.
• The receiver unit is active and provides the data from the CAN bus to the CANRX pin.
• The failure detection is active.

12.2.2 Receive Only Mode

In the receive only mode the CAN tran sceiver can still receive data from th e bus, but the driver output stage is disabled and therefore no data can be sent to the CAN bus. All other functions are active:

• The driver output is disabled and data which is available at the CANTX pin will be blocked and not communicated to the CAN bus.
• The receiver unit is active and provides the data from the CAN bus to the CANRX pin.
• The failure detection is active.

12.2.3 Power Down Mode

If the TLE8888-1QK is not supplied the bus communication is not allowed to be disturbed. Therefore the resistors of the receiver unit are switched off and the bus input pins CANH and CANL are high resistive.

12.2.4 Remote Wake Up

The wake receiver is internally supplied from the standby supply pin V5VSTBY. The wake up function is enabled by an external connection of the pin CANWKEN to the standby supply pin V5VSTBY. The wake function is disabled by an external connection to AGND and the current consumption of t he wake up circuit is reduced to leakage currents only. In “ECU Sleep” state a dominant signal at CANH and CANL for longer than the CAN Wake up filter time preceded by a recessive signal causes an inte rnal wake up and the internal wake signal CANWK is set. With a wake clear command (set bit WKCLR to “1” in command register Cmd0) CANWK is reset (status see bit CANWK in the status register OpStat0). The next wake up is only detected with a transition from recessive to dominant. With this implementation of the wake up procedure, bus line dominant clamping does not lead to permanent wake up. In Figure 52, Figure 53 and Figure 54 the behavior is shown.

Data Sheet 104 Rev. 1.1, 2014-08-20 TLE8888-1QK High Speed Controller Area Network (CAN) Transceiver Figure 54 State Transitions at CAN Remote Wake Up

12.3 Diagnostic Functions

The CAN transceiver has an implemented diagnostic unit. Bus failures and local failures can be detected.

12.3.1 CAN Bus Failure Detection

In normal operation the CAN transceiver can detect following bus failure:

• Bus line dominant clamping (bit CANBDC in diagnosis register ComDiag) Following bus failures can’t be detected (outputs are protected):
• CANH shorted to GND
• CANL shorted to GND
• CANH shorted to low voltage supply
• CANL shorted to low voltage supply
• CANH shorted to VBat
• CANL shorted to VBat
• CANH open
• CANL open
• CANH shorted to CANL

12.3.2 Local Failure Detection

In normal operation the CAN transceiver can detect following local failures:

• CAN TX dominant time-out (bit CANTXTO in diagnosis register ComDiag)
• Over temperature (bit CANOT in diagnosis register ComDiag) In case of failure detection only the corresponding di agnosis register bits are changed. No change in the configuration occurs. CAN Sleep recessive CAN Wake CAN WakeStatus CAN Wake Statemachine CANH CANL t CAN Sleep recessive CAN Sleep dominant CAN Sleep recessive Wake Up by CAN remote wake up ; KEY = EOTWK = WK = 0 CSN MSC Communication tSet WKCLR=“1“ ECU Sleep ECU Sleep ECU Sleep 1) Wake Up Filter Time is not shown in the diagram Set WKCLR=“1“

High Speed Controller Area Network (CAN) Transceiver Data Sheet 105 Rev. 1.1, 2014-08-20

12.4 Electrical Character istics CAN Transceiver

Table 40 Electrical Characte ristics: CAN Transceiver VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. CANH voltage, recessive state VCANH,rec 2 2.5 3 V no load P_12.4.1 CANL voltage, recessive state VCANL,rec 2 2.5 3 V no load P_12.4.2 CANH voltage, dominant state CANL voltage, dominant state Differential output bus voltage, dominant state Vdiff,out,dom 1.5 2 3 V 4.75V < VV5VCAN < 5.25V P_12.4.5 Common mode bus voltage, dominant and recessive state VCM -12 – 12 V 4.75V < VV5VCAN < 5.25V P_12.4.6 External Termination resistor RL 100 120 130 Ω P_12.4.7 Differential input voltage, recessive state Vdiff,n,rec -1 – 0.5 V P_12.4.8 Differential input voltage, dominant state Vdiff,in,dom 0.9 – 5 V P_12.4.9 Differential receiver hysteresis Vdiff,hys 20 100 – mV P_12.4.10 Common mode input resistance Rin 5–5 0 k Ω P_12.4.11 Bit time tB 1–– μs P_12.4.12 Propagation delay time CANTX to CANRX recessive to dominant tpd,rec,dom ––2 5 5 n s P_12.4.13 Propagation delay time CANTX to CANRX dominant to recessive tpd,dom,rec ––2 5 5 n s P_12.4.14 Propagation delay time CANTX to CANH/CANL recessive to dominant tpd,out,dom ––1 4 0 n s Tj=25°C;1) CCANH/CANL<10p F P_12.4.15 Propagation delay time CANTX to CANH/CANL dominant to recessive tpd,out,rec ––1 4 0 n s Tj=25°C1); CCANH/CANL<10p F P_12.4.16 Bus line dominant clamping detection time tbus,cl,dom 4–7 m s P_12.4.17 CANTX dominant detection time tCANTX,cl,dom 4–7 m s P_12.4.18

Data Sheet 106 Rev. 1.1, 2014-08-20 TLE8888-1QK High Speed Controller Area Network (CAN) Transceiver V5VCAN buffer capacitance1) CV5VCAN 2 – µF recommended for optimized EMC performance P_12.4.19 Over Temperature Switch Off Threshold TCAN,ot 150 – 200 °C 1) P_12.4.20 Over Temperature Hysteresis TCAN,ot,hys –1 0 – ° C 1) P_12.4.21 CANRX Output Characteristics Low Level Output Voltage - Low Output Current VCANRX,L,l ––0 . 4 V ICANRX = 100µA P_12.4.22 Low Level Output Voltage - High Output Current VCANRX,L,h ––1 . 5 V ICANRX = 1mA P_12.4.23 High Level Output Voltage - Low Output Current VCANRX,H,l VDDIO -0.4 –– V ICANRX = -100µA P_12.4.24 High Level Output Voltage - High Output Current VCANRX,H,h VDDIO -1.5 –– V ICANRX = -1mA P_12.4.25 CANTX Input Characteristics Low level input voltage VCANTX,l -0.3 – 1 V P_12.4.26 High level input voltage VCANTX,h 2– VV5VCAN V P_12.4.27 Input voltage hysteresis VCANTX,hys 50 200 – mV P_12.4.28 Pull up current ICANTX,pu -100 – -25 µA VCANTX=0V P_12.4.29 Wake Receiver Differential input voltage, recessive state, low power mode Vdiff,rec,lp -1 – 0.4 V 4.75V < VV5VSTBY < 5.25V P_12.4.30 Differential input voltage, dominant state, low power mode Vdiff,dom,lp 1.15 – 5 V 4.75V < VV5VSTBY < 5.25V P_12.4.31 Common mode bus voltage, low power mode VCM,lp -12 – 12 V 4.75V < VV5VSTBY < 5.25V P_12.4.32 CAN Wake up filter time twake,CAN 0.75 – 5 μs4 . 7 5 V < VV5VSTBY < 5.25V P_12.4.33 Additional current consumption in low power mode at pin BATSTBY ICANWK ––3 5 μA0 V ≤VCANH≤5V, 0V≤VCANL≤5V P_12.4.34 1) Not subject to production test, specified by design Table 40 Electrical Characte ristics: CAN Transceiver (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 107 Rev. 1.1, 2014-08-20

13 Micro Second Channel MSC

The bidirectional micro second channel (MSC) is a serial interface which is especially optimized to connect peripheral devices via serial link to micro controller. The serial communication link is built up by a fast synchronous downstream channel from micro controller to the devic e and an asynchronous upstream channel (referenced to downstream clock). The downstream interface can be “low voltage differential” (FCLN, FCLP, SIN, SIP, CSN) or “single ended” (FCLP, SIP, CSN). Via MSC, the micro controller controls the outputs and lo gic of the device including the diagnosis and monitoring module. Read data is requested by micro controller vi a downstream communication and returned by the device via MSC upstream channel. Multiple “power devices” with MSC for downstream operation are possible. The device is selected by CSN. The MSC logic is internally supplied and referenced to AGND. The behavior of the MSC interface during reset is described in Table 6 and Table 7 in Chapter 5.2. Figure 55 MSC Interface (not tested, overview only)

13.1 Downstream Communication

Downstream frames are synchronous serial frames with clock and data line. The physical interface for downstream communication can be “low voltage differential” or “single ended” type. Both interface types are using individual pins ( FCLN, FCLP, SIN and SIP) and common pins ( CSN and SDO). For single ended interface FCLN and SIN have to be connected to VDDIO. For low voltage differential interface both input voltage levels must be within the defined input voltage range. The frames and the behavior of the communication are the same in differential and single ended mode. Differential inputs for downstream data are SIP and SIN; the differential input signal SIP – SIN is the same logical signal as SIP alone in single ended mode and SI will be used in the description for both types of communication. The clock pins are FCLP and FCLN, the differential clock FCLP – FCLN is the same logical signal as FCLP in single ended mode and CLK will be used in the description for both types of communication. There is one input CSN for chip select, and one output SDO for upstream data. The device is always the slave in this communication link. The CSN signal enables receiver circuits automatically during a downstream frame transmission. Two types of downstream frames are defined: MSC interface Asynchronous / synchronous receive buffer Microcontroller TLE8888 Downstream Upstream Shift register

32 Bit

(low activ) Clock input Serial data output CSN FCLP FCLN Differential Downstream dataSIP SIN SDO Figures_TLE8728.vsd Single ended Differential Differential Single ended Differential

Data Sheet 108 Rev. 1.1, 2014-08-20 TLE8888-1QK Micro Second Channel MSC

• Command frames (selection bit =“1”)
• Data frames (selection bit =“0”) The device MSC uses non inverting polarity for SI and CLK: SI changes its state with the rising edge of CLK and is sampled with the falling edge; a logic ‘1’ is a ‘high level’ on SI, and a logic ‘0’ is a ‘low level’ on SI. Data at SI is latched by the device on the falling edge of CLK. The CSN input is active low during the active phases of command or data frames. An active enable signal validates the SI input signal. Outside the active phase (CSN line is at high level) data at SI is ignored. It is possible to drive multiple “power devices” with shared CLK and SI lines and individual CSN signal. Command frames and data frames may be sent in any sequence (with a passive phase of at least 2 CLK-cycles after each frame). The serial clock CLK must be active (toggling) during upstream communication even when no command frame or data frame is transmitted. The clock period of CLK is defined as tFCL, maximum downstream clock rate is fFCLmax. The active phase of a downstream frame starts with the falling edge of the signal on CSN and ends with the rising edge. CSN changes its state with the rising edge of clock CLK. Table 41 Execution of commands Event on MSC downstream upstream busy upstream idle valid read command frame ignored executed valid write command frame executed 1) 1) only after tprep,sr or tprep,mr, see also Chapter 13.2 executed valid data frame accepted accepted invalid command ignored ignored invalid data frame ignored ignored

Data Sheet 109 Rev. 1.1, 2014-08-20 Figure 56 Voltage level diagram

13.1.1 Downstream S upervisory Functions

A command- or data frame is interpreted as valid, if it has the correct number of CLK pulses (a frame has a length of 17 clock pulses). Clock pulses are counted at the falling edge of the signal. There is no parity check. If TLE8888-1QK receives no valid data frame for t > tMSC_mon, the device switches off the output stages (all output stage control bits are set to “0”), the bits O1E to O24E in the configuration registers OEConfig0 to OEConfig3 are set to “0” and the MSC time out failure bit in the register ComDiag is set to “1”. The MSC time out failure bit is reset by a readout of the register ComDiag and all output stages remain off. For switching on the stages the bits O1E to O24E in the configuration registers OEConfig0 to OEConfig3 must be set to “1” and the control bits must be set. Outputs which are configured to be driven directly with the direct drive inputs are switched according the input level of the pins IN1 to IN12 after set of the bits O1E to O24E. Drawing10_Voltage _level_diagram. vsd This figure shows SIP and SIN function but is also valid for FCLP and FCLN SIP SIN VSIN(min), VSIP(min) VSIN(max), VSIP(max) Not defined Not defined VSIx_low(min) VSIx_low(max) Logic function 101 VSIN(min), VSIP(min) VSIN(max), VSIP(max) VSINx_off(max) VSINx_off(min) SIP SIN 101 101 101 101 X XX XXX t [s] VSIN, VSIP [V] t [s] t [s] t [s] VSIN, VSIP [V] Logic function VSIx_high(min) VSIx_high(max)

Data Sheet 110 Rev. 1.1, 2014-08-20 TLE8888-1QK Micro Second Channel MSC

13.1.2 Command Frame

A command frame always starts with a high level bit (command selection bit). The number of command bits of the active phase of a command frame is fixed to 16. A command is executed only if the number of transmitted bits of an active command frame is equal to 17. The length of the command frame’s passive phase tCPP must be a minimum of 2 * tFCL (2 clock pulses). Alternatively the passive phase can consist in tCPP = tFCL (1 clock pulse) followed by a frame of wrong length (4...8 bits, with or without CSN active low) and a second tCPP = tFCL (1 clock pulse). Figure 57 MSC command frame Content of a command frame (LSB transmitted first) The least significant (LSB) bit of a command is transmitted first

13.1.3 Data Frame

A data frame always starts with a low level bit (data selection bit). The number of the data bits of the active phase of a data frame is fixed to 28 bit. A data frame is accepted if the actual length is the expected length 29. MSC Monitoring tMSC_mon is re triggered by any data frame with correct length (no other error detection mechanism is implemented). The length of the data frame’s passive phase tDPP must be a minimum of 2 * tFCL (2 clock pulses). Table 42 Command frame Bit # Description 0 (first bit) = ‘1’: command selection bit 1invalid command bits C0 ... C7 command data bits CD0 ... CD7 invalid shift sample tFCL CSN SI FCL active selection bit (1=command ) active phase Command frame passive phase tCPP Figures_TLE8728 .vsd

Data Sheet 111 Rev. 1.1, 2014-08-20 Figure 58 MSC data frame Table 43 Data frame OUTREG Bit Description 0 (first bit) = ‘0’: data selection bit

1 O14ON1)

2 O11ON1)

3 O24ON1)

4 O13ON1)

5 IGN1ON1)

6 IGN2ON1)

7 O5ON1)

8 O1ON1)

9 O15ON1)

10 IGN3ON1)

11 O2ON1)

12 O22ON1)

13 O9ON1)

14 O23ON1)

15 O19ON1)

16 O16ON1)

17 O18ON1)

18 O20ON1)

19 O8ON1)

20 O4ON1)

21 O17ON1)

22 O10ON1)

23 O21ON1)

selection bit (0=data) active phase data frame tDPP Figures_TLE 8728. vsd passive phase

Data Sheet 112 Rev. 1.1, 2014-08-20 TLE8888-1QK Micro Second Channel MSC There is no parity bit in the data frame. The data is stored in the control register Cont0 to Cont3.

13.2 Upstream Communication

The serial data output SDO is the synchronous serial data signal of the upstream c hannel and is always single ended. The polarity is ‘non inverting polarity‘– i.e. a low level bit at SDO is stored in the micro controller as a logic ‘0‘, and a high level bit at SDO is stored in the micro controller as a logic ‘1‘. The frequency for SDO is derived from CLK by an internal divider and can be configured via MSC. The output of SDO can be configured as an open drain or an push pull output. The set is done with the bit MSCO in the configuration register ComConfig0. The full range of up stream frequency divider settings in the configuration register ComConfig0 bits MSCF is valid for the push pull output configuration. Figure 59 MSC upstream communication (not tested, overview only, Single Ended) The data frame could be defined with 12 and 16 bit according the setting of MSCUF in the configuration register ComConfig0. In Figure 60 the formats are shown. The address bits A2 and A3 are used for the selection of the upstream data register in the micro controller. Definition of Address Bits A0 to A3 in 16 Bit Upstream Mode:

• Fixed A0 to A3 Value: The value of the address bits A0 to A3 is fixed according the definition of MSCA in the configuration register ComConfig1 at the rising edge of CSN of the read command. For read out with multiple read out commands the value of A0 to A3 does not change.
• Multiple Read Command Mode: This mode is especially for the multiple read commands and the configuration of the micro controller in UD3 interrupt mode. A2 and A3 are used in this mode to define the upstream data register (UD0 -UD3) and a number of n times 4 of upstream frames. A0 is defined as read overflow and A1 is defined as read busy.

24 O7ON1)

25 O6ON1)

26 O3ON1)

27 IGN4ON1)

28 O12ON1)

1) Definition see Chapter 14.6. Table 43 Data frame (cont’d) OUTREG Bit Description Downstream Channel Divider Upstream Channel Divider Shift Control TLE8888 SO FCL SDOSI Microcontroller FCL SI ENx CSN

Data Sheet 113 Rev. 1.1, 2014-08-20 Figure 60 MSC upstream frame Figure 61 MSC upstream communication flow Table 44 Definition of A0 in Multiple Read Command Mode for 16 Bit Upstream Format A0 Description

0 No read command is ignored

1 A read command was sent during upstream communication. This read command was ignored and this is signalized with A0=1 Table 45 Definition of A1 in Multiple Read Command Mode for 16 Bit Upstream Format A1 Description 0 last upstream frame; after finish of this fram e next transmitted read command will be executed

1 Upstream activities required by an multiple read commands are ongoing

Table 46 12 Bit Upstream Frame Bit description 0 start bit, always ‘0’ 1-8 upstream data bits UD0..7 9 parity bit (The parity bit is set in order to achieve an even number of ‘1’ in Bits UD0..7+Parity) 10, 11 stop bits, always ‘1’ Table 47 16 Bit Upstream Frame Bit description 0 start bit, always ‘0’ 1-4 address bits A0..3 Start bit UD0 LSB UD1 UD2 UD3 UD4 UD5 UD6 UD7 MSB Stop bit Parity Stop bit fSDO 8 bit data field UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7 MSB Stop bit Parity Stop bit fSDO 8 bit data field Figures _TLE 8728 .vsd Start bit LSB A1 A2 A3 16 bit upstream data frame 12 bit upstream data frame UD6 UD7 MSB Stop bit Parity bit Start bit UD0 LSB UD1 UD2 Upstream data frame Next Upstream Stop bit Figures_TLE 8728. vsd

Data Sheet 114 Rev. 1.1, 2014-08-20 TLE8888-1QK Micro Second Channel MSC Transmission of the registers via upstream starts within tMSC_RSP after read command has been received. During an ongoing upstream communicatio n the device will ignore further re ad commands until the upstream data transfer is finished. A new read comma nd is accepted if the rising edge CSN arrives after the last stop bit has been sent. Data frames are executed independently of ongoing read requests. Write commands are ignored during MSC upstream preparation time for single read command tprep,sr or MSC upstream preparation time for multi read command tprep,mr (see Figure 62). After that time the write commands are executed also during ongoing upstream communication. If the write command is changing the register which is in transmission, the old register content will be sent. With setting the command bit MSCUPS in the command register Cmd0 the running upstream transmission is stopped and all remaining read request of a multiple read command are cleared. Figure 62 Example MSC upstream and active downstream communication

13.3 Timing Characteristics

5-12 upstream data bits UD0..7 9 parity bit (The parity bit is set in order to achieve an even number of ‘1’ in Bits UD0..7+Parity) 10, 11 stop bits, always ‘1’ Table 47 16 Bit Upstream Frame (cont’d) Bit description FCLK SIP SDO Read Command CSN Diag0OpStat1 Preparation Phase tprep,sr or tprep,mr tMSC,RSP Execution Phase Only Data Frame executed Only Read Command ignored Only Read Command ignored CSN FCL SI t switchtsetup t hold t CSNhold 1/f FCL tCSNsetup SDO tMSC_RSP t or t prep ,mrprep,sr tFCLlowtFCLhigh

Data Sheet 115 Rev. 1.1, 2014-08-20 The downstream clock within the device must be active during an upstream data frame transmission (i.e. each answer to a READ command). The upstream response time tMSC_RSP describes the time between end of read command (rising edge of CSN) to beginning of up-stream communication (falling edge of start bit).

13.4 Electrical Characteristics

Table 48 Electrical Characteristics: Micro Second Channel VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Pin CSN Input comparator low level VCSN_low -0.3 – 0.8 P_13.4.1 Input comparator high level VCSN_high 1.6 – 5.5 V – P_13.4.2 Input comparator hysteresis VCSN_hys 0.1 – 0.5 V – P_13.4.3 Input capacitance1) CCSN 12 pF – P_13.4.4 Input current Internal pull up current source to VDDIO ICSN -25 – -3 µA 0V< VCSN<2V P_13.4.5 Pins FCLP, FCLN MSC Differential Mode Input voltage range VFCLP, VFCLN Differential input high detection level, VFCLx_high=VFCLP–VFCLN VFCLx_high – – 125 mV – P_13.4.7 Differential input low detection level, VFCLx_low=VFCLP–VFCLN VFCLx_low -125 – – mV – P_13.4.8 Differential input hysteresis VFCLx,hys 50 200 mV P_13.4.53 Input voltage offset, VFCLx_off=0.5*(VFCLP+VFCLN) VFCLx_off 1.05 – 1.4 V – P_13.4.9 Differential capacitance between; FCLP and FCLN CFCLx –– 8 p F 1) P_13.4.10 Input pull down current IFCLN 3 – 25 µA 1V< VFCLx<VVDDIO P_13.4.12 Pins FCLP Single Ended Mode Input comparator low level VFLCP_low -0.3 – 0.8 P_13.4.13 Input comparator high level VFLCP_high 1.6 – 5.5 V – P_13.4.14 Input comparator hysteresis VFLCP_hys 0.1 – 0.5 V – P_13.4.15 Input capacitance CFLCP 12 pF 1) P_13.4.16 Input pull down current IFLCP 3– 2 5 µ A 1 V < VFCLP<VVDDIO P_13.4.17 Clock Frequency FCLP, FCLN frequency fFCLx –– 2 3 M H z P_13.4.18

Data Sheet 116 Rev. 1.1, 2014-08-20 TLE8888-1QK Micro Second Channel MSC FCL frequency single ended mode fFCL – – 12.5 MHz P_13.4.19 Pins SIP, SIN MSC Differential Mode Input voltage range VSIP, VSIN 0.8 – 1.6 V – P_13.4.20 Differential input high detection level, VSIx_high=VSIP–VNSI VSIx_high – – 125 mV – P_13.4.21 Differential input low detection level, VSIx_low=VSIP–VSIN VSIx_low -125 – – mV – P_13.4.22 Differential input hysteresis VSIx,hys 50 200 mV P_13.4.54 Input voltage offset, VSIx_Off=0.5*(VSIP+VSIN) VSIx_Off 1.05 – 1.4 V – P_13.4.23 Differential capacitance between SIP and SIN CSIx –– 8 p F 1) P_13.4.24 Input pull down current ISIN 3 – 25 µA 1V< VSIx<VVDDIO P_13.4.26 Pin SIP Single Ended Mode Input comparator low level VSIP_low -0.3 – 0.8 P_13.4.27 Input comparator high level VSIP_high 1.6 – 5.5 V – P_13.4.28 Input comparator hysteresis VSIP_hys 0.1 – 0.5 V – P_13.4.29 Input capacitance CSIP 12 pF 1) P_13.4.30 Input pull down current ISIP 3– 2 5 µ A 1 V < VSIP<VVDDIO P_13.4.31 Pin SDO open drain set up SDO output low level VSDO_low; VSDO_low – – 0.8 V ISDO<4mA; P_13.4.32 –– 0 . 4 V ISDO<1mA P_13.4.33 SDO passive output high voltage VSDO_high,p VDDIO – 1.5 VDDIO – V no load P_13.4.34 Output current capability ISDO_max 152) ––m A VSDO=5V and VVDDIO=5V P_13.4.35 SDO pull-up current source ISDO_high -50 – -10 µA 0V< VSDO<2V, SDO in tristate, pull up to VDDIO P_13.4.36 SDO (high level = inactive) pin capacity CSDO – – 10 pF measured with bias voltage of 1V1) P_13.4.37 SDO frequency; maximum upstream frequency with external pull-up fSDO 500 – – kHz 2.2k Ω and CL=15pF1) P_13.4.38 Pin SDO push pull set up Table 48 Electrical Characteristics: Micro Second Channel (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 117 Rev. 1.1, 2014-08-20 SDO output low level VSDO_low; VSDO_low – – 0.8 V ISDO<4mA; P_13.4.39 –– 0 . 4 V ISDO<1mA P_13.4.40 SDO active output high voltage VSDO_high,a VDDIO – 0.4 ––V ISDO=100μA P_13.4.41 Timing Characteristics3) Data hold time thold 10 – – ns – P_13.4.42 Data Setup time tsetup 10 – – ns – P_13.4.43 Switching time tswitch –– 3 n s 1) P_13.4.44 FCL low time tFCLlow 13 – – ns – P_13.4.45 FCL high time tFCLhigh 13 – – ns – P_13.4.46 CSN setup time tCSNsetup 10 – – ns – P_13.4.47 CSN hold time tCSNhold 10 – – ns – P_13.4.48 MSC data time-out monitoring tMSC_mon 60 – 135 µs – P_13.4.49 MSC upstream preparation time for single read command tprep,sr – – 0.9 + 4*tFCL µs P_13.4.11 MSC upstream preparation time for multi read command tprep,mr – – 1.8 + 4*tFCL µs P_13.4.25 MSC upstream response time; up-stream divider independent tMSC_RSP – – 100 µs P_13.4.50 Required idle time after command tCPP 2/fFCL (2 clock pulses) ––s – P_13.4.51 Required idle time after data frame tDPP 2/fFCL (2 clock pulses) ––s – P_13.4.52 1) not subject to production test, specified by design 2) Application must ensure t hat current into this pin does not exceed this value. 3) See Figure 57, Figure 58 and Figure 63 Table 48 Electrical Characteristics: Micro Second Channel (cont’d) VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 118 Rev. 1.1, 2014-08-20 TLE8888-1QK Register and Commands

14 Register and Commands

In Chapter 14.1 to Chapter 14.6 detailed descriptions and definitions of the registers and commands are shown. General definition for all registers and commands are described below. Offset Address The offset address used for the register address is mapped to the command bits from C1 to C7. In Figure 64 an example is shown. Maximum allowed address is 7FH. Figure 64 Mapping Offset Address to the Command Bits Read Access A read access to a register is done by sending a “0” for the bit C0 of the command frame of the MSC or the SPI frame. All register bits are updated constantly. With the positive edge of CSN of a valid read command the internal register information is loaded into the output shift register. The communication via SDO to the micro controller is according the serial interface mode MSC or SPI. Therefore the read information is related to the time of the positive edge of CSN. Write Access A write access to a register is done by sending a “1” for the bit C0 of the command frame of the MSC or the SPI frame or with the data frame of the MSC communication. With the positive edge of CSN of a valid write access for read/write register the bits are set and for command registers the defined function is executed (e.g. multiple read command). Command Register These registers are write only registers. Following functions are executed:

• Main relay switching with bits MRON and MRSE in command register Cmd0: In all states where a serial communication with the TLE8888-1QK is allowed the main relay can be switched. This is done by enabling the command with a “1” for MRSE and a “0” for switch off or a ”1” for switch on for MRON. Switch off of the main relay leads for an application with supply of the ECU over the main relay path to a power down.
• VRS diagnosis start with bit VDIAGS in command register Cmd0: With a “1” the VRS diagnosis is started. A “0” leads to no action.
• Stop of a MSC upstream communication with bit MSCUPS in command register Cmd0: With a “1” the upstream communication is stopped immediately. This leads during an upstream to invalid communication. This command is implemented to stop especially multiple read communication. A “0” leads to no action. For SPI mode this command has no effect.
• Start of the engine off timer with bit EOTS in command register Cmd0: With a “1” the engine off timer is started if the configuration is set accordingly. A “0” leads to no action.
• Restart of the delayed off timer with bit RDOT in command register Cmd0: With a “1” the delayed off timer is reset and started again. A “0” leads to no action. C6 C5 C4 C3 C2 C1 C0C7 Offset Address 6BH: 6B R/W01110110 Not mapped

Data Sheet 119 Rev. 1.1, 2014-08-20

• Wake up signal clear with bit WKCLR in command register Cmd0: With a “1” all internal wake up signals (WKINT, CANWK, EOTWK) are reset. A “0” leads to no action.
• Response write command FWDRespCmd and FWDRespSyncCmd: With the write access to these registers the 8 bit response byte is sent to the TLE8888-1QK. The interpretation of the sent response byte is done according the description in Chapter 6.
• Multiple read command MSCReadWd0 to MSCReadWd1: Multiple read commands are only allowed for MSC setup of the serial interface. The number of read register is defined by a “1” in the data bits of the command. The chosen register is sent in the order MSB down to LSB (see Figure 65). In SPI setup a multiple read command is an invalid communication. During a multi read upstream read commands are ignored, write commands are allowed. To stop an upstream operation use the command MSCUPS.
• Software reset command CmdSR: With the execution of this command the software reset of the TLE8888- 1QK is performed according Table 7 in Chapter 5.
• Central output enable command CmdOE: With the execution of this command the central output enable bit is set or reset. For the description of the functionality see Chapter 9.2. The status of the central enable bit is available in register OpStat1.
• Lock command CmdLOCK: With the execution of this command the lock bit is set or reset.This bit is used to lock some configuration registers (see Table 50) to avoid a change of these register e.g. during operation. The status of the lock bit is available in register OpStat1. Figure 65 Example of a Multi read Command Diagnosis Register The diagnosis register bits are set according the asynchro nous detection circuits. The reset of the diagnosis bits is done with the read out of the registers if the failure condition is not detected anymore. Central Over-temperature Bit COT in Diagnosis Register Diag0 The central over temperature bit is an OR combination of all over temperature detection signals which leads to active diagnosis bits. With at least one active over-tempe rature diagnosis the central over-temperature bit is “1”, with no active over-temperature diagnosis this bit is “0”. All other diagnosis signals doesn’t change the status of the central over-temperature bit. e.g. MSCReadMain : C0 C1 C2 C3 C4 C5 C6 C7 CD0 CD1 CD2 CD3 CD4 CD5 CD6 CD7 111 FWDConfig WDConfig1 OpStat1 Diag0 FCLK SIP SDO MSCReadMain CSN OpStat0 TECConfig WWDConfig1 Diag0OpStat1WdConfig1WWDConfig1 FWDConfig 0BH 101110101 1001101111101000

Data Sheet 120 Rev. 1.1, 2014-08-20 TLE8888-1QK Register and Commands Central Failure Bit CF in Diagnosis Register Diag0 The central failure bit is an OR combination of diagnosis bits (see Table 49). If one or more of these diagnosis bits are active then the central failure bit is “1”. If all are inactive the central failure bit is “0”. The over-temperature diagnosis doesn’t change the status of the central failure bit. Engine Off Timer Register EOTStat0 to EOTStat2, EOTConfig0 and EOTConfig1 These register are located in the standby block and are supplied by the standby supply. They are not reset with the power on reset of the digital block. Registers affected by the Lock Bit Table 49 Overview of Diagnosis Registers an Bits affecting the Central Failure Bit Register Offset Bit(s) Note ComDiag 024 H MSCTO, COMFE, CANBDC, CANTXTO OutDiag0 to OutDiag4 026H to 029H all bits central failure bit not set if only over- temperature is detected PPOVDiag 02A H all bits BriDiag0 02B H all bits BriDiag1 02C H only over-current bits IgnDiag 02D H all bits WdDiag 02E H WWDTO, WWDSCE, FWDREL, FWDREA Table 50 Overview of Register affected by the Lock Bit Register Offset OutConfig0 040 H OutConfig1 041 H OutConfig2 042 H OutConfig3 043 H OutConfig4 044 H OutConfig5 045 H BriConfig0 046 H BriConfig1 047 H IGNConfig 048 H VRSConfig1 04A H VRSConfig2 04B H OpConfig0 04E H ComConfig0 04F H ComConfig1 050 H EOTConfig0 051 H EOTConfig1 052 H

Data Sheet 121 Rev. 1.1, 2014-08-20 InConfig0 053 H InConfig1 054 H InConfig2 055 H InConfig3 056 H DDConfig0 057 H DDConfig1 058 H DDConfig2 059 H DDConfig3 05A H WDConfig1 064 H Table 50 Overview of Register affected by the Lock Bit (cont’d) Register Offset

Data Sheet 122 Rev. 1.1, 2014-08-20

14.1 Register Table

Table 14-1 Register Overview Register Short Name Register Long Name Offset Address Reset Value Cmd0 001H 00H MSCReadWd0 003H 00H MSCReadDiag0EOT 004H 00H MSCReadDiag1 005H 00H MSCReadCont 006H 00H MSCReadConfig0 007H 00H MSCReadConfig1 008H 00H MSCReadConfig2 009H 00H MSCReadOEConfig 00AH 00H MSCReadMain 00BH 00H MSCReadWd1 00CH 00H WWDServiceCmd 015H 00H FWDRespCmd 016H 00H FWDRespSyncCmd 017H 00H WDHBTPSyncCmd 018H 00H CmdSR 01AH 00H CmdOE 01CH 00H CmdLOCK 01EH 00H Diag0 020H 00H Diag1 021H 00H VRSDiag0 022H 00H VRSDiag1 023H 00H ComDiag 024H 00H OutDiag0 025H 00H OutDiag1 026H 00H OutDiag2 027H 00H OutDiag3 028H 00H OutDiag4 029H 00H PPOVDiag 02AH 00H BriDiag0 02BH 00H BriDiag1 02CH 00H IgnDiag 02DH 00H WdDiag 02EH 00H EOTStat0 031H 00H EOTStat1 032H 00H

Data Sheet 123 Rev. 1.1, 2014-08-20 EOTStat2 033H 00H OpStat0 034H 00H OpStat1 035H 00H WWDStat 036H 30H FWDStat0 037H 30H FWDStat1 038H 30H TECStat 039H 30H WdStat0 03AH 00H WdStat1 03BH 00H WDHBT0 03CH 00H WDHBT1 03DH 00H OutConfig0 040H FFH OutConfig1 041H 3FH OutConfig2 042H 3FH OutConfig3 043H 30H OutConfig4 044H 3FH OutConfig5 045H 3FH BriConfig0 046H 00H BriConfig1 047H 00H IGNConfig 048H 00H VRSConfig0 049H 00H VRSConfig1 04AH 00H VRSConfig2 04BH 00H OpConfig0 04EH 09H ComConfig0 04FH A4H ComConfig1 050H 0DH EOTConfig0 051H 00H EOTConfig1 052H 00H InConfig0 053H 00H InConfig1 054H 00H InConfig2 055H 00H InConfig3 056H 00H DDConfig0 057H 00H DDConfig1 058H 00H DDConfig2 059H 00H DDConfig3 05AH 00H OEConfig0 05BH 00H OEConfig1 05CH 00H Table 14-1 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Reset Value

Data Sheet 124 Rev. 1.1, 2014-08-20 The registers are addressed wordwise.

14.2 Command Register

Field Bits Type Description WKCLR 7 w Wake Up Signal Clear Command: 0B no action 1B initiated clear of internal wake signals Reset: 0B Table 14-1 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Reset Value 7 6 5 4 3 2 1 0 WKCLR w RDOT w EOTS w MSCUPS w WDHBTS w VDIAGS w MRON w MRSE w

Data Sheet 125 Rev. 1.1, 2014-08-20 RDOT 6 w Restart Delayed off Timer Command: 0B no action 1B delayed off timer is restarted Reset: 0B EOTS 5 w Engine Off Timer Start Command: 0B no action 1B start counter Reset: 0B MSCUPS 4 w MSC Upstream Stop Bit Command: 0B no influence to upstream transmission 1B upstream communication is stopped Reset: 0B WDHBTS 3 w Watchdog Heartbeat Timer Sample Command: 0B no action 1B Watchdog Heartbeat Timer sampled (WDHBT0 and WDHBT1) Reset: 0B VDIAGS 2 w VRS Diagnosis Measurement Start Command: 0B no measurement 1B start of VRS diagnosis measurement Reset: 0B MRON 1 w Main Relay On Command (active if MRSE=1): 0B initiated main relay is switched off 1B initiated main relay is switched on Reset: 0B MRSE 0 w Main Relay Switching Enable: 0B main relay switching by bit MRON not enabled 1B main relay switching enabled: value of MRON executed Reset: 0B MSCReadWd0 Offset Reset Value 003H 00H Field Bits Type Description 7 6 5 4 3 2 1 0 IG0 WWDCONF w WDCONFI w WWDSTAT w WDDIAG w FWDSTAT w FWDSTAT w TECSTAT w WDSTAT0 w

Data Sheet 126 Rev. 1.1, 2014-08-20 Field Bits Type Description WWDCONFIG 7w Read Status Register WWDConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WDCONFIG0 6 w Read Status Register WDConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WWDSTAT 5 w Read Status Register WWDStat 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WDDIAG 4 w Read Configuration Register WdDiag 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B FWDSTAT1 3 w Read Configuration Register FWDStat1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B FWDSTAT0 2 w Read Diagnosis Register FWDStat0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B TECSTAT 1 w Read Diagnosis Register TECStat 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WDSTAT0 0 w Read Status Register WdStat0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadDiag0EOT Offset Reset Value 004H 00H 7 6 5 4 3 2 1 0 G PPOVDIA w DIAG1 w EOTSTAT w EOTSTAT w EOTSTAT w COMDIAG w VRSDIAG w VRSDIAG w

Data Sheet 127 Rev. 1.1, 2014-08-20 Field Bits Type Description PPOVDIAG 7 w Read Diagnosis Register PPOVDiag 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B DIAG1 6 w Read Diagnosis Register Diag1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B EOTSTAT2 5 w Read Status Register EOTStat2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B EOTSTAT1 4 w Read Status Register EOTStat1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B EOTSTAT0 3 w Read Status Register EOTStat0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B COMDIAG 2 w Read Diagnosis Register ComDiag 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B VRSDIAG1 1 w Read Diagnosis Register VRSDiag1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B VRSDIAG0 0 w Read Diagnosis Register VRSDiag0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadDiag1 Offset Reset Value 005H 00H 7 6 5 4 3 2 1 0 IGNDIAG w BRIDIAG w BRIDIAG w OUTDIAG w OUTDIAG w OUTDIAG w OUTDIAG w OUTDIAG w

Data Sheet 128 Rev. 1.1, 2014-08-20 Field Bits Type Description IGNDIAG 7 w Read Diagnosis Register IgnDiag 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B BRIDIAG1 6 w Read Diagnosis Register BriDiag1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B BRIDIAG0 5 w Read Diagnosis Register BriDiag0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTDIAG4 4 w Read Diagnosis Register OutDiag4 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTDIAG3 3 w Read Diagnosis Register OutDiag3 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTDIAG2 2 w Read Diagnosis Register OutDiag2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTDIAG1 1 w Read Diagnosis Register OutDiag1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTDIAG0 0 w Read Diagnosis Register OutDiag0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadCont Offset Reset Value 006H 00H 7 6 5 4 3 2 1 0 RES CONT3 w CONT2 w CONT1 w CONT0 w

Data Sheet 129 Rev. 1.1, 2014-08-20 Field Bits Type Description CONT3 3 w Read Control Register Cont3 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B CONT2 2 w Read Control Register Cont2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B CONT1 1 w Read Control Register Cont1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B CONT0 0 w Read Control Register Cont0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadConfig0 Offset Reset Value 007H 00H Field Bits Type Description BRICONFIG1 7 w Read Configuration Register BriConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B BRICONFIG0 6 w Read Configuration Register BriConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTCONFIG5 5 w Read Configuration Register OutConfig5 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B 7 6 5 4 3 2 1 0 IG1 BRICONF w IG0 BRICONF w IG5 OUTCONF w IG4 OUTCONF w IG3 OUTCONF w IG2 OUTCONF w IG1 OUTCONF w IG0 OUTCONF w

Data Sheet 130 Rev. 1.1, 2014-08-20 OUTCONFIG4 4 w Read Configuration Register OutConfig4 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTCONFIG3 3 w Read Configuration Register OutConfig3 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTCONFIG2 2 w Read Configuration Register OutConfig2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTCONFIG1 1 w Read Configuration Register OutConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OUTCONFIG0 0 w Read Configuration Register OutConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadConfig1 Offset Reset Value 008H 00H Field Bits Type Description EOTCONFIG1 7 w Read Configuration Register EOTConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B EOTCONFIG0 6 w Read Configuration Register EOTConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 IG1 EOTCONF w IG0 EOTCONF w IG1 VRSCONF w IG0 VRSCONF w OPCONFI w IG1 COMCONF w IG0 COMCONF w IG IGNCONF w

Data Sheet 131 Rev. 1.1, 2014-08-20 VRSCONFIG1 5 w Read Configuration Register VRSConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B VRSCONFIG0 4 w Read Configuration Register VRSConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OPCONFIG0 3 w Read Configuration Register OpConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B COMCONFIG 2w Read Configuration Register ComConfig1 B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B COMCONFIG 1w Read Configuration Register ComConfig0 B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B IGNCONFIG 0 w Read Configuration Register IGNConfig 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadConfig2 Offset Reset Value 009H 00H Field Bits Type Description INCONFIG3 7 w Read Configuration Register InConfig3 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 INCONFI w INCONFI w INCONFI w INCONFI w DDCONFI w DDCONFI w DDCONFI w DDCONFI w

Data Sheet 132 Rev. 1.1, 2014-08-20 INCONFIG2 6 w Read Configuration Register InConfig2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B INCONFIG1 5 w Read Configuration Register InConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B INCONFIG0 4 w Read Configuration Register InConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B DDCONFIG3 3 w Read Configuration Register DDConfig3 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B DDCONFIG2 2 w Read Configuration Register DDConfig2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B DDCONFIG1 1 w Read Configuration Register DDConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B DDCONFIG0 0 w Read Configuration Register DDConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadOEConfig Offset Reset Value 00AH 00H Field Bits Type Description 7 6 5 4 3 2 1 0 RES IG2 VRSCONF w OECONFI w OECONFI w OECONFI w OECONFI w

Data Sheet 133 Rev. 1.1, 2014-08-20 Field Bits Type Description VRSCONFIG2 4 w Read Configuration Register VRSConfig2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OECONFIG3 3 w Read Configuration Register OEConfig3 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OECONFIG2 2 w Read Configuration Register OEConfig2 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OECONFIG1 1 w Read Configuration Register OEConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OECONFIG0 0 w Read Configuration Register OEConfig0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadMain Offset Reset Value 00BH 00H Field Bits Type Description WWDCONFIG 6w Read Status Register WWDConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B TECCONFIG 5 w Read Status Register TECConfig 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B 7 6 5 4 3 2 1 0 RES IG1 WWDCONF w IG TECCONF w IG FWDCONF w WDCONFI w OPSTAT1 w OPSTAT0 w DIAG0 w

Data Sheet 134 Rev. 1.1, 2014-08-20 FWDCONFIG 4 w Read Status Register FWDConfig 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WDCONFIG1 3 w Read Status Register WDConfig1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OPSTAT1 2 w Read Status Register OpStat1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B OPSTAT0 1 w Read Status Register OpStat0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B DIAG0 0 w Read Diagnosis Register Diag0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B MSCReadWd1 Offset Reset Value 00CH 00H Field Bits Type Description WDSTAT1 3 w Read Status Register WdStat1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WDSTAT0 2 w Read Status Register WdStat0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 RES WDSTAT1 w WDSTAT0 w WDHBT1 w WDHBT0 w

Data Sheet 135 Rev. 1.1, 2014-08-20 WDHBT1 1 w Read Status Register WDHBT1 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WDHBT0 0 w Read Status Register WDHBT0 0B no action 1B multi read operation executed (order MSB to LSB) Reset: 0B WWDServiceCmd Offset Reset Value 015H 00H Field Bits Type Description WWDCWTC 7:2 w Window Watchdog Closed Window Time Write Command: Set WWDCWT in register WWDConfig0 000000 B no change - old setting used for open and closed window 000001B 1,6ms 111111B 100,8ms Reset: 000000B WWDOWTC 1:0 w Window Watchdog Open Window Time Write Command: Set WWDOWT in register WWDConfig0 00B 3,2ms 01B 6,4ms 10B 9,6ms 11B 12,8ms Reset: 00B FWDRespCmd Offset Reset Value 016H 00H Field Bits Type Description 7 6 5 4 3 2 1 0 WWDCWTC w WWDOWTC w

Data Sheet 136 Rev. 1.1, 2014-08-20 Field Bits Type Description FWDRESP 7:0 w Functional Watchdog Response Byte Write Command Reset: 00H FWDRespSyncCmd Offset Reset Value 017H 00H Field Bits Type Description FWDRESPS 7:0 w Functional Watchdog Response Byte Write and Heartbeat Synchronisation Command Reset: 00H WDHBTPSyncCmd Offset Reset Value 018H 00H 7 6 5 4 3 2 1 0 FWDRESP w 7 6 5 4 3 2 1 0 FWDRESPS w 7 6 5 4 3 2 1 0 RES WDHBTPC w

Data Sheet 137 Rev. 1.1, 2014-08-20 Field Bits Type Description WDHBTPC 6:0 w Heartbeat Timer Period Write and Synchronisation Command: Set WDHBTP in register WDConfig0 0000000B no change 0000001B 1,6ms 0000010B 3,2ms 1111111B 203,2ms Reset: 0000000B CmdSR Offset Reset Value 01AH 00H Field Bits Type Description CMDSR 1:0 w Software Reset Command 00B No action 01B No action 10B No action 11B Initiate software reset Reset: 00B CmdOE Offset Reset Value 01CH 00H 7 6 5 4 3 2 1 0 RES CMDSR w 7 6 5 4 3 2 1 0 RES CMDOE w

Data Sheet 138 Rev. 1.1, 2014-08-20

14.3 Diagnosis Register

Field Bits Type Description CMDOE 1:0 w Global Output Enable Command 00B No action 01B Set Bit OE to 0 10B Set Bit OE to 1 11B No action Reset: 00B CmdLOCK Offset Reset Value 01EH 00H Field Bits Type Description CMDLOCK 1:0 w Configuration Lock Command 00B No action 01B Set Bit LOCK to 0 10B Set Bit LOCK to 1 11B No action Reset: 00B Diag0 Offset Reset Value 020H 00H 7 6 5 4 3 2 1 0 RES CMDLOCK w 7 6 5 4 3 2 1 0 V6VOV r T2OV r T2UV r T1OV r T1UV r BATOV r CF r COT r

Data Sheet 139 Rev. 1.1, 2014-08-20 Field Bits Type Description V6VOV 7 r Over Voltage Diagnosis Bit of 6V Supply V6V: 0B no over voltage 1B over voltage Reset: 0B T2OV 6 r Over Voltage Diagnosis Bit of Tracker Output T5V2: 0B no over voltage 1B over voltage Reset: 0B T2UV 5 r Under Voltage Diagnosis Bit of Tracker Output T5V2: 0B no under voltage 1B under voltage Reset: 0B T1OV 4 r Over Voltage Diagnosis Bit of Tracker Output T5V1: 0B no over voltage 1B over voltage Reset: 0B T1UV 3 r Under Voltage Diagnosis Bit of Tracker Output T5V1: 0B no under voltage 1B under voltage Reset: 0B BATOV 2 r Battery Over Voltage Diagnosis Bit: 0B no battery over voltage 1B battery over voltage Reset: 0B CF 1 r Central Failure Diagnosis Bit: 0B no failure 1B failure of minimum one diagnostic detected Reset: 0B COT 0 r Central Over Temperature Diagnosis Bit: 0B no over temperature 1B over temperature of minimum one temperature sensor Reset: 0B Diag1 Offset Reset Value 021H 00H 7 6 5 4 3 2 1 0 RES T5VOT r V5VOT r MROT r

Data Sheet 140 Rev. 1.1, 2014-08-20 Field Bits Type Description T5VOT 2 r Tracker Overtemperature Diagnosis Bit: 0B no over temperature 1B over temperature Reset: 0B V5VOT 1 r V5V Regulator Overtemperature Diagnosis Bit: 0B no over temperature 1B over temperature Reset: 0B MROT 0 r Main Relay Overtemperature Diagnosis Bit: 0B no over temperature 1B over temperature Reset: 0B VRSDiag0 Offset Reset Value 022H 00H Field Bits Type Description VRSDV_OL 4 r Open Load Measurement Data Valid Bit 0B measurement data not valid 1B measurement data valid Reset: 0B VRSDV_SC 3 r Short to GND/Bat Measurement Data Valid Bit 0B measurement data not valid 1B measurement data valid Reset: 0B VRSOL 2 r VRS Open Load Diagnosis Bit: 0B no open load 1B open load Reset: 0B VRSB 1 r VRS Short to Battery Diagnosis Bit: 0B no short to battery 1B short to battery Reset: 0B 7 6 5 4 3 2 1 0 RES L VRSDV_O r C VRSDV_S r VRSOL r VRSB r VRSG r

Data Sheet 141 Rev. 1.1, 2014-08-20 VRSG 0 r VRS Short to GND Diagnosis Bit: 0B no short to GND 1B short to GND Reset: 0B VRSDiag1 Offset Reset Value 023H 00H Field Bits Type Description VRSDV_ADC 7 r ADC Measurement Data Valid Bit 0B measurement data not valid 1B measurement data valid Reset: 0B VRSD 6:0 r VRS Diagnosis Measurement Result Register Reset: 0000000B ComDiag Offset Reset Value 024H 00H Field Bits Type Description LINOT 5 r LIN Over Temperature Diagnosis Bit: 0B no over temperature 1B over temperature Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 DC VRSDV_A r VRSD r 7 6 5 4 3 2 1 0 RES LINOT r CANOT r CANTXTO r CANBDC r COMFE r MSCTO r

Data Sheet 142 Rev. 1.1, 2014-08-20 CANOT 4 r CAN Over Temperature Diagnosis Bit: 0B no over temperature 1B over temperature Reset: 0B CANTXTO 3 r CAN TX Dominant Time Out Error Diagnosis Bit: 0B no error 1B TX dominant time out error Reset: 0B CANBDC 2 r CAN Bus Line Dominant Clamp Error Diagnosis Bit: 0B no error 1B bus dominant clamp error Reset: 0B COMFE 1 r Communication Frame Error Diagnosis Bit: 0B no MSC/SPI frame error 1B MSC/SPI frame error Reset: 0B MSCTO 0 r MSC Time Out Failure Diagnosis Bit: 0B no failure 1B MSC time out Reset: 0B OutDiag0 Offset Reset Value 025H 00H Field Bits Type Description O4DIA 7:6 r Output4 Diagnosis Bits: see below Reset: 00B O3DIA 5:4 r Output3 Diagnosis Bits: see below Reset: 00B O2DIA 3:2 r Output2 Diagnosis Bits: see below Reset: 00B Field Bits Type Description 7 6 5 4 3 2 1 0 O4DIA r O3DIA r O2DIA r O1DIA r

Data Sheet 143 Rev. 1.1, 2014-08-20 O1DIA 1:0 r Output1 Diagnosis Bits: 00B no failure 01B short circuit to bat (over current) or over temperature 10B open load in off 11B short circuit to ground in off Reset: 00B OutDiag1 Offset Reset Value 026H 00H Field Bits Type Description O8DIA 7:6 r Output8 (DFB8) Diagnosis Bit: 00B no failure 01B short circuit to bat 10B open load in off 11B short circuit to ground in off Reset: 00B O7DIA 5:4 r Output7 Diagnosis Bits: see below Reset: 00B O6DIA 3:2 r Output6 Diagnosis Bits: see below Reset: 00B O5DIA 1:0 r Output5 Diagnosis Bits: 00B no failure 01B short circuit to bat (over current) or over temperature 10B open load in off 11B short circuit to ground in off Reset: 00B OutDiag2 Offset Reset Value 027H 00H Field Bits Type Description 7 6 5 4 3 2 1 0 O8DIA r O7DIA r O6DIA r O5DIA r

Data Sheet 144 Rev. 1.1, 2014-08-20 Field Bits Type Description O12DIA 7:6 r Output12 (DFB12) Diagnosis Bit: see below Reset: 00B O11DIA 5:4 r Output11 (DFB11) Diagnosis Bit: see below Reset: 00B O10DIA 3:2 r Output10 (DFB10) Diagnosis Bit: see below Reset: 00B O9DIA 1:0 r Output9 (DFB9) Diagnosis Bit: 00B no failure 01B short circuit to bat 10B open load in off 11B short circuit to ground in off Reset: 00B OutDiag3 Offset Reset Value 028H 00H Field Bits Type Description O16DIA 7:6 r Output16 Diagnosis Bit: see below Reset: 00B O15DIA 5:4 r Output15 Diagnosis Bit: see below Reset: 00B O14DIA 3:2 r Output14 Diagnosis Bit: 00B no failure 01B short circuit to bat (over current) or over temperature 10B open load in off 11B short circuit to ground in off Reset: 00B 7 6 5 4 3 2 1 0 O12DIA r O11DIA r O10DIA r O9DIA r 7 6 5 4 3 2 1 0 O16DIA r O15DIA r O14DIA r O13DIA r

Data Sheet 145 Rev. 1.1, 2014-08-20 O13DIA 1:0 r Output13 (DFB13) Diagnosis Bit: 00B no failure 01B short circuit to bat 10B open load in off 11B short circuit to ground in off Reset: 00B OutDiag4 Offset Reset Value 029H 00H Field Bits Type Description O20DIA 7:6 r Output20 Diagnosis Bits: see below Reset: 00B O19DIA 5:4 r Output19 Diagnosis Bits: see below Reset: 00B O18DIA 3:2 r Output18 Diagnosis Bits: see below Reset: 00B O17DIA 1:0 r Output17 Diagnosis Bits: 00B no failure 01B short circuit to bat (over current) or over temperature 10B open load in off 11B short circuit to ground in off Reset: 00B PPOVDiag Offset Reset Value 02AH 00H Field Bits Type Description 7 6 5 4 3 2 1 0 O20DIA r O19DIA r O18DIA r O17DIA r 7 6 5 4 3 2 1 0 RES O13OV r O12OV r O11OV r O10OV r O9OV r O8OV r

Data Sheet 146 Rev. 1.1, 2014-08-20 Field Bits Type Description O13OV 5 r Output13 Overvoltage Diagnosis Bit: 0B no overvoltage 1B overvoltage Reset: 0B O12OV 4 r Output12 Overvoltage Diagnosis Bit: 0B no overvoltage 1B overvoltage Reset: 0B O11OV 3 r Output11 Overvoltage Diagnosis Bit: 0B no overvoltage 1B overvoltage Reset: 0B O10OV 2 r Output10 Overvoltage Diagnosis Bit: 0B no overvoltage 1B overvoltage Reset: 0B O9OV 1 r Output9 Overvoltage Diagnosis Bit: 0B no overvoltage 1B overvoltage Reset: 0B O8OV 0 r Output8 Overvoltage Diagnosis Bit: 0B no overvoltage 1B overvoltage Reset: 0B BriDiag0 Offset Reset Value 02BH 00H Field Bits Type Description O24DIA 7:6 r Output24 Diagnosis Bits (in off) Reset: 00B O23DIA 5:4 r Output23 Diagnosis Bits (in off) Reset: 00B 7 6 5 4 3 2 1 0 O24DIA r O23DIA r O22DIA r O21DIA r

Data Sheet 147 Rev. 1.1, 2014-08-20 O22DIA 3:2 r Output22 Diagnosis Bits (in off) Reset: 00B O21DIA 1:0 r Output21 Diagnosis Bits (in off) Reset: 00B BriDiag1 Offset Reset Value 02CH 00H Field Bits Type Description B2OT 5 r Output23,24 Overtemperature Diagnosis Bit 0B no over temperature 1B over temperature Reset: 0B B1OT 4 r Output21,22 Overtemperature Diagnosis Bit 0B no over temperature 1B over temperature Reset: 0B O24OC 3 r Output24 Over Current Diagnosis Bit 0B no over current 1B over current Reset: 0B O23OC 2 r Output23 Over Current Diagnosis Bit 0B no over current 1B over current Reset: 0B O22OC 1 r Output22 Over Current Diagnosis Bit 0B no over current 1B over current Reset: 0B O21OC 0 r Output21 Over Current Diagnosis Bit 0B no over current 1B over current Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 RES B2OT r B1OT r O24OC r O23OC r O22OC r O21OC r

Data Sheet 148 Rev. 1.1, 2014-08-20 IgnDiag Offset Reset Value 02DH 00H Field Bits Type Description IGN4DIA 7:6 r Ignition 4 Output Diagnosis Bits: see below Reset: 00B IGN3DIA 5:4 r Ignition 3 Output Diagnosis Bits: see below Reset: 00B IGN2DIA 3:2 r Ignition 2 Output Diagnosis Bits: see below Reset: 00B IGN1DIA 1:0 r Ignition 1 Output Diagnosis Bits: 00B no failure 01B short circuit to bat or over temperature 10B open load 11B short circuit to ground in on Reset: 00B WdDiag Offset Reset Value 02EH 00H Field Bits Type Description TECRES 6 r Reset caused by TEC: 0B no reset (caused by TEC) happened 1B reset (caused by TEC) happened Reset: 0B 7 6 5 4 3 2 1 0 IGN4DIA r IGN3DIA r IGN2DIA r IGN1DIA r 7 6 5 4 3 2 1 0 RES TECRES r FWDRES r WWDRES r FWDREA r FWDREL r WWDSCE r WWDTO r

Data Sheet 149 Rev. 1.1, 2014-08-20

14.4 Status Register

FWDRES 5 r Reset caused by Functional Watchdog: 0B no functional watchdog reset happened 1B functional watchdog reset happened Reset: 0B WWDRES 4 r Reset caused by Window Watchdog: 0B no window watchdog reset happened 1B window watchdog reset happened Reset: 0B FWDREA 3 r Functional Watchdog Response Error of Actual Running Sequence Diagnosis Bit: 0B no error 1B error Reset: 0B FWDREL 2 r Functional Watchdog Response Error of Last Sequence Diagnosis Bit: 0B no error 1B error Reset: 0B WWDSCE 1 r Window Watchdog Service Command too Early Diagnosis Bit: 0B service command in time 1B service command too early Reset: 0B WWDTO 0 r Window Watchdog Time Out Diagnosis Bit: 0B no time out 1B time out Reset: 0B EOTStat0 Offset Reset Value 031H 00H Field Bits Type Description 7 6 5 4 3 2 1 0 EOTC0 r

Data Sheet 150 Rev. 1.1, 2014-08-20 Field Bits Type Description EOTC0 7:0 r Engine Off Timer Counter Value Bits: (Bit 7 - 0) Reset: 00H EOTStat1 Offset Reset Value 032H 00H Field Bits Type Description EOTC1 7:0 r Engine Off Timer Counter Value Bits: (Bit 15 - 8) Reset: 00H EOTStat2 Offset Reset Value 033H 00H Field Bits Type Description EOTC2 7:0 r Engine Off Timer Counter Value Bits: (Bit 23 - 16) Reset: 00H OpStat0 Offset Reset Value 034H 00H 7 6 5 4 3 2 1 0 EOTC1 r 7 6 5 4 3 2 1 0 EOTC2 r

Data Sheet 151 Rev. 1.1, 2014-08-20 Field Bits Type Description EOTWK 7 r Status of internal EOTWK signal: 0B EOTWK is inactive 1B EOTWK is active Reset: 0B CANWK 6 r Status of internal CANWK signal: 0B CANWK is inactive 1B CANWK is active Reset: 0B WKINT 5 r Status of internal WKINT signal: 0B WKINT is inactive 1B WKINT is active Reset: 0B MON 4 r MON Pin Status Bit: 0B active (low) 1B inactive (high) Reset: 0B MR 3 r Main Relay Switch On Status Bit: 0B off 1B on Reset: 0B OM 2 r Operation Mode Bit: 0B normal operation 1B afterrun mode Reset: 0B WK 1 r WK Status Bit (filtered): 0B WK=0 1B WK=1 Reset: 0B KEY 0 r KEY Status Bit (filtered): 0B KEY=0 1B KEY=1 Reset: 0B OpStat1 Offset Reset Value 035H 00H 7 6 5 4 3 2 1 0 EOTWK r CANWK r WKINT r MON r MR r OM r WK r KEY r

Data Sheet 152 Rev. 1.1, 2014-08-20 Field Bits Type Description LOCK 7 r Configuration Lock Status Bit: 0B Configuration registers unlocked 1B Configuration registers locked Reset: 0B OE 6 r Global Output Enable Status Bit: 0B outputs disabled and control register are reset 1B outputs enabled Reset: 0B EOTRES 5 r Engine Off Timer Reset Status Bit: 0B no EOT reset happened 1B EOT reset happened Reset: 0B RSTR 4 r Reset caused by external RST Reset: (only valid if no internal power on reset occurs) B no external RST reset happened 1B external RST reset happened Reset: 0B V5VOVR 3 r Reset caused by V5V Over Voltage Reset: (only valid if no internal power on reset occurs) 0B no V5V over voltage reset happened 1B V5V over voltage reset happened Reset: 0B V5VUVR 2 r Reset caused by V5V Under Voltage Reset: (only valid if no internal power on reset occurs) 0B no V5V under voltage reset happened 1B V5V under voltage reset happened Reset: 0B WDRES 1 r Reset caused by Watchdog Reset: (only valid if no internal power on reset occurs) B no watchdog reset happened 1B watchdog reset happened Reset: 0B ARES 0 r Reset caused by Afterrun Reset: (only valid if no internal power on reset occurs) B no afterrun reset happened 1B afterrun reset happened Reset: 0B 7 6 5 4 3 2 1 0 LOCK r OE r EOTRES r RSTR r V5VOVR r V5VUVR r WDRES r ARES r

Data Sheet 153 Rev. 1.1, 2014-08-20 WWDStat Offset Reset Value 036H 30H Field Bits Type Description WWDEC 5:0 r Window Watchdog Error Counter Value Reset: 110000B FWDStat0 Offset Reset Value 037H 30H Field Bits Type Description FWDPC 5:0 r Functional Watchdog Pass Counter Value Reset: 110000B FWDStat1 Offset Reset Value 038H 30H 7 6 5 4 3 2 1 0 RES WWDEC r 7 6 5 4 3 2 1 0 RES FWDPC r 7 6 5 4 3 2 1 0 RES FWDRESPC r FWDQUEST r

Data Sheet 154 Rev. 1.1, 2014-08-20 Field Bits Type Description FWDRESPC 5:4 r Functional Watchdog Response Counter Value Reset: 11B FWDQUEST 3:0 r Functional Watchdog Question Reset: 0000B TECStat Offset Reset Value 039H 30H Field Bits Type Description TEC 5:0 r Total Error Counter Value Reset: 110000B WdStat0 Offset Reset Value 03AH 00H Field Bits Type Description WWDSCR 7 r Window Watchdog Service Command received 0B No Service Command received 1B Service Command received Reset: 0B 7 6 5 4 3 2 1 0 RES TEC r 7 6 5 4 3 2 1 0 WWDSCR r SSOTS r WWDPDC r RESC r

Data Sheet 155 Rev. 1.1, 2014-08-20 SSOTS 6 r Secure Shut Off Timer Start Status Bit: 0B timer reset 1B timer started Reset: 0B WWDPDC 5:3 r Window Watchdog Power Down Counter Value Reset: 000B RESC 2:0 r Reset Counter Value Reset: 000B WdStat1 Offset Reset Value 03BH 00H Field Bits Type Description TECPDC 5:3 r Total Error Power Down Counter Value Reset: 000B FWDPDC 2:0 r Functional Watchdog Power Down Counter Value Reset: 000B WDHBT0 Offset Reset Value 03CH 00H Field Bits Type Description WDHBTPRE 3:0 r Sampled Watchdog Heartbeat Timer Predivider Value Reset: 0000B Field Bits Type Description 7 6 5 4 3 2 1 0 RES TECPDC r FWDPDC r 7 6 5 4 3 2 1 0 RES WDHBTPRE r

Data Sheet 156 Rev. 1.1, 2014-08-20

14.5 Configuration Register

OutConfig0 locked with LOCK=1 WDHBT1 Offset Reset Value 03DH 00H Field Bits Type Description WDHBT 6:0 r Sampled Watchdog Heartbeat Timer Value Reset: 0000000B OutConfig0 Offset Reset Value 040H FFH Field Bits Type Description O4OL 7 rw Output4 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O4OC 6 rw Output4 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O3OL 5 rw Output3 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B 7 6 5 4 3 2 1 0 RES WDHBT r 7 6 5 4 3 2 1 0 O4OL rw O4OC rw O3OL rw O3OC rw O2OL rw O2OC rw O1OL rw O1OC rw

Data Sheet 157 Rev. 1.1, 2014-08-20 OutConfig1 locked with LOCK=1 O3OC 4 rw Output3 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O2OL 3 rw Output2 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O2OC 2 rw Output2 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O1OL 1 rw Output1 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O1OC 0 rw Output1 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B OutConfig1 Offset Reset Value 041H 3FH Field Bits Type Description O7OL 5 rw Output7 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O7OC 4 rw Output7 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B Field Bits Type Description 7 6 5 4 3 2 1 0 RES O7OL rw O7OC rw O6OL rw O6OC rw O5OL rw O5OC rw

Data Sheet 158 Rev. 1.1, 2014-08-20 OutConfig2 locked with LOCK=1 O6OL 3 rw Output6 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O6OC 2 rw Output6 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O5OL 1 rw Output5 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O5OC 0 rw Output5 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B OutConfig2 Offset Reset Value 042H 3FH Field Bits Type Description PP0D 7:6 rw Diagnosis in On Set Up for OUT8 and OUT9: 00B typ. 125mV short to bat in on threshold 01B typ. 225mV short to bat in on threshold 10B typ. 400mV short to bat in on threshold 11B typ. 0.8V short to bat in on threshold Reset: 00B O13OL 5 rw Output13 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O12OL 4 rw Output12 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B Field Bits Type Description 7 6 5 4 3 2 1 0 PP0D rw O13OL rw O12OL rw O11OL rw O10OL rw O9OL rw O8OL rw

Data Sheet 159 Rev. 1.1, 2014-08-20 OutConfig3 locked with LOCK=1 O11OL 3 rw Output11 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O10OL 2 rw Output10 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O9OL 1 rw Output9 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O8OL 0 rw Output8 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B OutConfig3 Offset Reset Value 043H 30H Field Bits Type Description O14OL 5 rw Output14 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O14OC 4 rw Output14 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B PP2D 3:2 rw Diagnosis in On Set Up for OUT12 and OUT13: 00B typ. 125mV short to bat in on threshold 01B typ. 225mV short to bat in on threshold 10B typ. 400mV short to bat in on threshold 11B typ. 0.8V short to bat in on threshold Reset: 00B Field Bits Type Description 7 6 5 4 3 2 1 0 RES O14OL rw O14OC rw PP2D rw PP1D rw

Data Sheet 160 Rev. 1.1, 2014-08-20 OutConfig4 locked with LOCK=1 PP1D 1:0 rw Diagnosis in On Set Up for OUT10 and OUT11: 00B typ. 125mV short to bat in on threshold 01B typ. 225mV short to bat in on threshold 10B typ. 400mV short to bat in on threshold 11B typ. 0.8V short to bat in on threshold Reset: 00B OutConfig4 Offset Reset Value 044H 3FH Field Bits Type Description O17D 6 rw Output17 Delayed Off Set Up: 0B no delayed off function 1B delayed off function activated Reset: 0B O17OL 5 rw Output17 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O17OC 4 rw Output17 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O16OL 3 rw Output16 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B O16OC 2 rw Output16 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O15OL 1 rw Output15 Open Load Set Up: 0B pull down current deactivated 1B fully functional Reset: 1B Field Bits Type Description 7 6 5 4 3 2 1 0 RES O17D rw O17OL rw O17OC rw O16OL rw O16OC rw O15OL rw O15OC rw

Data Sheet 161 Rev. 1.1, 2014-08-20 OutConfig5 locked with LOCK=1 BriConfig0 locked with LOCK=1 O15OC 0 rw Output15 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B OutConfig5 Offset Reset Value 045H 3FH Field Bits Type Description O20OL 5 rw Output20 Open Load Set Up: 0B pull down and pull up current deactivated 1B fully functional Reset: 1B O20OC 4 rw Output20 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O19OL 3 rw Output19 Open Load Set Up: 0B pull down and pull up current deactivated 1B fully functional Reset: 1B O19OC 2 rw Output19 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B O18OL 1 rw Output18 Open Load Set Up: 0B pull down and pull up current deactivated 1B fully functional Reset: 1B O18OC 0 rw Output18 Over Current Protection Set Up: 0B current limitation in case of over current 1B switch off in case of over current Reset: 1B Field Bits Type Description 7 6 5 4 3 2 1 0 RES O20OL rw O20OC rw O19OL rw O19OC rw O18OL rw O18OC rw

Data Sheet 162 Rev. 1.1, 2014-08-20 BriConfig1 locked with LOCK=1 BriConfig0 Offset Reset Value 046H 00H Field Bits Type Description O24F 7 rw Output24 Freewheeling Mode Set Up: 0B passive freewheeling mode 1B active freewheeling mode Reset: 0B O24M 6 rw Output24 Mode Set Up: 0B low side switch mode 1B high side switch mode Reset: 0B O23F 5 rw Output23 Freewheeling Mode Set Up: 0B passive freewheeling mode 1B active freewheeling mode Reset: 0B O23M 4 rw Output23 Mode Set Up: 0B low side switch mode 1B high side switch mode Reset: 0B O22F 3 rw Output22 Freewheeling Mode Set Up: 0B passive freewheeling mode 1B active freewheeling mode Reset: 0B O22M 2 rw Output22 Mode Set Up: 0B low side switch mode 1B high side switch mode Reset: 0B O21F 1 rw Output21 Freewheeling Mode Set Up: 0B passive freewheeling mode 1B active freewheeling mode Reset: 0B O21M 0 rw Output21 Mode Set Up: 0B low side switch mode 1B high side switch mode Reset: 0B 7 6 5 4 3 2 1 0 O24F rw O24M rw O23F rw O23M rw O22F rw O22M rw O21F rw O21M rw

Data Sheet 163 Rev. 1.1, 2014-08-20 IGNConfig locked with LOCK=1 BriConfig1 Offset Reset Value 047H 00H Field Bits Type Description FB2E 2 rw Full Bridge 2 Enable Bit: 0B Output 23 and 24 are not used in full bridge configuration 1B Output 23 and 24 are used in full bridge configuration Reset: 0B FB1E 1 rw Full Bridge 1 Enable Bit: 0B Output 21 and 22 are not used in full bridge configuration 1B Output 21 and 22 are used in full bridge configuration Reset: 0B O21D 0 rw Output21 Delayed Off Set Up: 0B no delayed off function 1B delayed off function activated Reset: 0B IGNConfig Offset Reset Value 048H 00H Field Bits Type Description IOLT 4:3 rw Ignition Time Setting for Open Load Detection: 00B 64μs 01B 256μs 10B 512μs 11B 768μs Reset: 00B 7 6 5 4 3 2 1 0 RES FB2E rw FB1E rw O21D rw 7 6 5 4 3 2 1 0 RES IOLT rw IOLI rw IOLA rw

Data Sheet 164 Rev. 1.1, 2014-08-20 VRSConfig1 locked with LOCK=1 IOLI 2:1 rw Ignition Current Setting for Open Load Detection: 00B -100μA 01B -400μA 10B -1 mA 11B -4 mA Reset: 00B IOLA 0 rw Ignition Open Load Detection Activation: 0B no open load detection 1B open load detection active Reset: 0B VRSConfig0 Offset Reset Value 049H 00H Field Bits Type Description VRSPV 7:6 rw VRS Peak Voltage Detection Set Up: 00B 50mV 01B 150mV 10B 350mV 11B 550mV Reset: 00B VRSF 2:1 rw VRS Output Filter Time Set Up: 00B 1μs, reset value 01B 5μs 10B 10μs 11B 20μs Reset: 00B VRSPT 0 rw VRS Peak Time Set Up: 0B 10μs, reset value 1B 250μs Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 VRSPV rw RES VRSF rw VRSPT rw

Data Sheet 165 Rev. 1.1, 2014-08-20 VRSConfig2 locked with LOCK=1 VRSConfig1 Offset Reset Value 04AH 00H Field Bits Type Description VRSI_SC 7:4 rw Current setting for short to GND/Bat measurement 0000B 10μA 0001B 20μA 0010B 30μA 0011B 40μA 0100B 50μA 0101B 60μA 0110B 70μA 0111B 80μA 1000B 100μA 1001B 120μA 1010B 140μA 1011B 160μA 1100B to full scale (0b1111) 160μA Reset: 0000B VRSM 3:2 rw VRS/Hall Sensor Mode Set Up: 00B auto detection mode for VR sensor signals (reset value) 01B semi auto detection mode for VR sensor signals 10B manuel detection mode for VR sensor signals 11B Hall sensor mode Reset: 00B VRSDIAGM 1:0 rw VRS Diagnosis Mode Set Up: 00B normal detection mode 01B short to GND/Bat diagnosis mode 10B open load diagnosis mode 11B ADC diagnosis mode Reset: 00B VRSConfig2 Offset Reset Value 04BH 00H 7 6 5 4 3 2 1 0 VRSI_SC rw VRSM rw VRSDIAGM rw

Data Sheet 166 Rev. 1.1, 2014-08-20 OpConfig0 locked with LOCK=1 Field Bits Type Description VRSI_ADC 7:4 rw Current setting for ADC measurement 0000B 10μA 0001B 20μA 0010B 30μA 0011B 40μA 0100B 50μA 0101B 60μA 0110B 70μA 0111B 80μA 1000B 100μA 1001B 120μA 1010B 140μA 1011B 160μA 1100B to full scale (0b1111) 160μA Reset: 0000B VRSI_OL 3:0 rw Current setting for open load measurement 0000B 10μA 0001B 20μA 0010B 30μA 0011B 40μA 0100B 50μA 0101B 60μA 0110B 70μA 0111B 80μA 1000B 100μA 1001B 120μA 1010B 140μA 1011B 160μA 1100B to full scale (0b1111) 160μA Reset: 0000B OpConfig0 Offset Reset Value 04EH 09H 7 6 5 4 3 2 1 0 VRSI_ADC rw VRSI_OL rw

Data Sheet 167 Rev. 1.1, 2014-08-20 ComConfig0 locked with LOCK=1 Field Bits Type Description KOD 6:5 rw Key Off Delay Set Up: 00B 100ms 01B 200ms 10B 400ms 11B 800ms Reset: 00B EOTCONF 4 rw Engine Off Timer Configuration: 0B timer start with negative edge of KEY signal 1B timer start with command EOTS in register Cmd0 Reset: 0B AR 3 rw Afterrun Reset Behavior Set Up: 0B no afterrun reset 1B afterrun reset Reset: 1B AE 2 rw Afterrun Enable: 0B no afterrun mode 1B afterrun mode Reset: 0B PDT 1:0 rw Power Down Time Set Up: 00B 100ms 01B 200ms 10B 300ms 11B 400ms Reset: 01B ComConfig0 Offset Reset Value 04FH A4H 7 6 5 4 3 2 1 0 RES KOD rw EOTCONF rw AR rw AE rw PDT rw 7 6 5 4 3 2 1 0 MSCF rw MSCO rw MSCAD rw MSCP rw MSCUF rw

Data Sheet 168 Rev. 1.1, 2014-08-20 ComConfig1 locked with LOCK=1 Field Bits Type Description MSCF 7:5 rw MSC Upstream Frequency Divider Set Up: 000B Division by 64 001B Division by 4 010B Division by 8 011B Division by 16 100B Division by 32 101B Division by 64 110B Division by 128 111B Division by 256 Reset: 101B MSCO 4 rw MSC SDO Definition: 0B open drain 1B push pull Reset: 0B MSCAD 3 rw MSC Address Definition A0 to A3: 0B value of A2 to A3 are incremented with each read command 1B A0 to A3 values are fixed to the values of MSCA[3:0] Reset: 0B MSCP 2 rw MSC Upstream Parity Format Set Up: 0B odd parity 1B even parity Reset: 1B MSCUF 1:0 rw MSC Upstream Address Format Setup: 00B upstream format without address 01B upstream format with address 10B upstream format with address 11B upstream format with address Reset: 00B ComConfig1 Offset Reset Value 050H 0DH Field Bits Type Description MSCA 7:4 rw MSC Upstream Address for MSCAD=1 Reset: 0000B 7 6 5 4 3 2 1 0 MSCA rw LINTOE rw LIN rw CAN rw

Data Sheet 169 Rev. 1.1, 2014-08-20 EOTConfig0 locked with LOCK=1 EOTConfig1 locked with LOCK=1 LINTOE 3 rw LIN TX Time OUT Function Enable: 0B TX time out function disabled 1B TX time out function enabled Reset: 1B LIN 2:1 rw Operation Mode: 00B receive only mode 01B LIN/K-line operation 10B flash mode 11B receive only mode Reset: 10B CAN 0 rw CAN Operation Mode: 0B receive only mode 1B high speed CAN mode Reset: 1B EOTConfig0 Offset Reset Value 051H 00H Field Bits Type Description EOTTH0 7:0 rw Engine Off Timer Comparator Threshold: (Bit 7 - 0) Reset: 00H EOTConfig1 Offset Reset Value 052H 00H Field Bits Type Description 7 6 5 4 3 2 1 0 EOTTH0 rw 7 6 5 4 3 2 1 0 EOTTH1 rw

Data Sheet 170 Rev. 1.1, 2014-08-20 InConfig0 locked with LOCK=1 Additional Table with Constants This table describes more than 16 constants. Field Bits Type Description EOTTH1 7:0 rw Engine Off Timer Comparator Threshold: (Bit 15 - 8) Reset: 00H InConfig0 Offset Reset Value 053H 00H Field Bits Type Description IN9O 4:0 rw Direct control Input9 Assignment: See Table 14-2 Reset: 00000B Table 14-2 Constant Values Name and Description Value output5 00000B output6 00001B output7 00010B output8 00011B output9 00100B output10 00101B output11 00110B output12 00111B 7 6 5 4 3 2 1 0 RES IN9O rw

Data Sheet 171 Rev. 1.1, 2014-08-20 InConfig1 locked with LOCK=1 output13 01000B output14 01001B output15 01010B output16 01011B output17 01100B output18 01101B output19 01110B output20 01111B output21 10000B output22 10001B output23 10010B output24 10011B InConfig1 Offset Reset Value 054H 00H Field Bits Type Description IN10O 4:0 rw Direct control Input10 Assignment: See Table 14-3 Reset: 00000B Table 14-2 Constant Values (cont’d) Name and Description Value 7 6 5 4 3 2 1 0 RES IN10O rw

Data Sheet 172 Rev. 1.1, 2014-08-20 Additional Table with Constants This table describes more than 16 constants. Table 14-3 Constant Values Name and Description Value output5 00000B output6 00001B output7 00010B output8 00011B output9 00100B output10 00101B output11 00110B output12 00111B output13 01000B output14 01001B output15 01010B output16 01011B output17 01100B output18 01101B output19 01110B output20 01111B output21 10000B output22 10001B output23 10010B output24 10011B

Data Sheet 173 Rev. 1.1, 2014-08-20 InConfig2 locked with LOCK=1 Additional Table with Constants This table describes more than 16 constants. InConfig2 Offset Reset Value 055H 00H Field Bits Type Description IN11O 4:0 rw Direct control Input11 Assignment: See Table 14-4 Reset: 00000B Table 14-4 Constant Values Name and Description Value output5 00000B output6 00001B output7 00010B output8 00011B output9 00100B output10 00101B output11 00110B output12 00111B output13 01000B output14 01001B output15 01010B 7 6 5 4 3 2 1 0 RES IN11O rw

Data Sheet 174 Rev. 1.1, 2014-08-20 InConfig3 locked with LOCK=1 Additional Table with Constants This table describes more than 16 constants. output16 01011B output17 01100B output18 01101B output19 01110B output20 01111B output21 10000B output22 10001B output23 10010B output24 10011B InConfig3 Offset Reset Value 056H 00H Field Bits Type Description IN12O 4:0 rw Direct control Input12 Assignment: See Table 14-5 Reset: 00000B Table 14-4 Constant Values (cont’d) Name and Description Value 7 6 5 4 3 2 1 0 RES IN12O rw

Data Sheet 175 Rev. 1.1, 2014-08-20 DDConfig0 locked with LOCK=1 Table 14-5 Constant Values Name and Description Value output5 00000B output6 00001B output7 00010B output8 00011B output9 00100B output10 00101B output11 00110B output12 00111B output13 01000B output14 01001B output15 01010B output16 01011B output17 01100B output18 01101B output19 01110B output20 01111B output21 10000B output22 10001B output23 10010B output24 10011B

Data Sheet 176 Rev. 1.1, 2014-08-20 DDConfig1 locked with LOCK=1 DDConfig0 Offset Reset Value 057H 00H Field Bits Type Description O8DD 7 rw Output8 Direct Drive Control: see below Reset: 0B O7DD 6 rw Output7 Direct Drive Control: see below Reset: 0B O6DD 5 rw Output6 Direct Drive Control: see below Reset: 0B O5DD 4 rw Output5 Direct Drive Control: see below Reset: 0B O4DD 3 rw Output4 Direct Drive Control: see below Reset: 0B O3DD 2 rw Output3 Direct Drive Control: see below Reset: 0B O2DD 1 rw Output2 Direct Drive Control: see below Reset: 0B O1DD 0 rw Output1 Direct Drive Control: 0B controlled by MSC/SPI interface 1B controlled by Direct Drive Input Reset: 0B DDConfig1 Offset Reset Value 058H 00H 7 6 5 4 3 2 1 0 O8DD rw O7DD rw O6DD rw O5DD rw O4DD rw O3DD rw O2DD rw O1DD rw 7 6 5 4 3 2 1 0 O16DD rw O15DD rw O14DD rw O13DD rw O12DD rw O11DD rw O10DD rw O9DD rw

Data Sheet 177 Rev. 1.1, 2014-08-20 DDConfig2 locked with LOCK=1 Field Bits Type Description O16DD 7 rw Output16 Direct Drive Control: see below Reset: 0B O15DD 6 rw Output15 Direct Drive Control: see below Reset: 0B O14DD 5 rw Output14 Direct Drive Control: see below Reset: 0B O13DD 4 rw Output13 Direct Drive Control: see below Reset: 0B O12DD 3 rw Output12 Direct Drive Control: see below Reset: 0B O11DD 2 rw Output11 Direct Drive Control: see below Reset: 0B O10DD 1 rw Output10 Direct Drive Control: see below Reset: 0B O9DD 0 rw Output9 Direct Drive Control: 0B controlled by MSC/SPI interface 1B controlled by Direct Drive Input Reset: 0B DDConfig2 Offset Reset Value 059H 00H Field Bits Type Description O24DD 7 rw Output24 Direct Drive Control: see below Reset: 0B O23DD 6 rw Output23 Direct Drive Control: see below Reset: 0B O22DD 5 rw Output22 Direct Drive Control: see below Reset: 0B O21DD 4 rw Output21 Direct Drive Control: see below Reset: 0B O20DD 3 rw Output20 Direct Drive Control: see below Reset: 0B 7 6 5 4 3 2 1 0 O24DD rw O23DD rw O22DD rw O21DD rw O20DD rw O19DD rw O18DD rw O17DD rw

Data Sheet 178 Rev. 1.1, 2014-08-20 DDConfig3 locked with LOCK=1 O19DD 2 rw Output19 Direct Drive Control: see below Reset: 0B O18DD 1 rw Output18 Direct Drive Control: see below Reset: 0B O17DD 0 rw Output17 Direct Drive Control: 0B controlled by MSC/SPI interface 1B controlled by Direct Drive Input Reset: 0B DDConfig3 Offset Reset Value 05AH 00H Field Bits Type Description IGN4DD 3 rw Ignition Output4 Direct Drive Control: see below Reset: 0B IGN3DD 2 rw Ignition Output3 Direct Drive Control: see below Reset: 0B IGN2DD 1 rw Ignition Output2 Direct Drive Control: see below Reset: 0B IGN1DD 0 rw Ignition Output1 Direct Drive Control: 0B controlled by MSC/SPI interface 1B controlled by Direct Drive Input Reset: 0B OEConfig0 Offset Reset Value 05BH 00H Field Bits Type Description 7 6 5 4 3 2 1 0 RES IGN4DD rw IGN3DD rw IGN2DD rw IGN1DD rw

Data Sheet 179 Rev. 1.1, 2014-08-20 Field Bits Type Description O8E 7 rw Output8 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O7E 6 rw Output7 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O6E 5 rw Output6 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O5E 4 rw Output5 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O4E 3 rw Output4 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O3E 2 rw Output3 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O2E 1 rw Output2 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O1E 0 rw Output1 Enable Bit: 0B output disabled 1B output enabled Reset: 0B OEConfig1 Offset Reset Value 05CH 00H 7 6 5 4 3 2 1 0 O8E rw O7E rw O6E rw O5E rw O4E rw O3E rw O2E rw O1E rw

Data Sheet 180 Rev. 1.1, 2014-08-20 Field Bits Type Description O16E 7 rw Output16 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O15E 6 rw Output15 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O14E 5 rw Output14 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O13E 4 rw Output13 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O12E 3 rw Output12 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O11E 2 rw Output11 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O10E 1 rw Output10 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O9E 0 rw Output9 Enable Bit: 0B output disabled 1B output enabled Reset: 0B OEConfig2 Offset Reset Value 05DH 00H 7 6 5 4 3 2 1 0 O16E rw O15E rw O14E rw O13E rw O12E rw O11E rw O10E rw O9E rw

Data Sheet 181 Rev. 1.1, 2014-08-20 Field Bits Type Description O24E 7 rw Output24 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O23E 6 rw Output23 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O22E 5 rw Output22 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O21E 4 rw Output21 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O20E 3 rw Output20 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O19E 2 rw Output19 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O18E 1 rw Output18 Enable Bit: 0B output disabled 1B output enabled Reset: 0B O17E 0 rw Output17 Enable Bit: 0B output disabled 1B output enabled Reset: 0B OEConfig3 Offset Reset Value 05EH 00H 7 6 5 4 3 2 1 0 O24E rw O23E rw O22E rw O21E rw O20E rw O19E rw O18E rw O17E rw

Data Sheet 182 Rev. 1.1, 2014-08-20 Field Bits Type Description IGN4E 3 rw Ignition 4 Output Enable Bit: 0B output disabled 1B output enabled Reset: 0B IGN3E 2 rw Ignition 3 Output Enable Bit: 0B output disabled 1B output enabled Reset: 0B IGN2E 1 rw Ignition 2 Output Enable Bit: 0B output disabled 1B output enabled Reset: 0B IGN1E 0 rw Ignition 1 Output Enable Bit: 0B output disabled 1B output enabled Reset: 0B WWDConfig0 Offset Reset Value 05FH FFH Field Bits Type Description WWDCWT 7:2 rw Window Watchdog Closed Window Time: 000000B no change - old setting used for open and closed window 000001B 1,6ms 111111B 100,8ms Reset: 111111B 7 6 5 4 3 2 1 0 RES IGN4E rw IGN3E rw IGN2E rw IGN1E rw 7 6 5 4 3 2 1 0 WWDCWT rw WWDOWT rw

Data Sheet 183 Rev. 1.1, 2014-08-20 WWDOWT 1:0 rw Window Watchdog Open Window Time: 00B 3,2ms 01B 6,4ms 10B 9,6ms 11B 12,8ms Reset: 11B WWDConfig1 Offset Reset Value 060H 77H Field Bits Type Description WWDECD 7:4 rw Window Watchdog Error Counter Decrement: 0000B -1 0001B -2 1111B -16 Reset: 0111B WWDECI 3:0 rw Window Watchdog Error Counter Increment: 0000B +1 0001B +2 1111B +16 Reset: 0111B FWDConfig Offset Reset Value 061H F7H Field Bits Type Description 7 6 5 4 3 2 1 0 WWDECD rw WWDECI rw 7 6 5 4 3 2 1 0 FWDPCD rw FWDPCI rw

Data Sheet 184 Rev. 1.1, 2014-08-20 Field Bits Type Description FWDPCD 7:4 rw Functional Watchdog Pass Counter Decrement: 0000B -1 0001B -2 1111B -16 Reset: 1111B FWDPCI 3:0 rw Functional Watchdog Pass Counter Increment: 0000B +1 0001B +2 1111B +16 Reset: 0111B TECConfig Offset Reset Value 062H 77H Field Bits Type Description TECD 7:4 rw Total Error Counter Decrement: 0000B -1 0001B -2 1111B -16 Reset: 0111B TECI 3:0 rw Total Error Counter Increment: 0000B +1 0001B +2 1111B +16 Reset: 0111B WDConfig0 Offset Reset Value 063H 47H 7 6 5 4 3 2 1 0 TECD rw TECI rw

Data Sheet 185 Rev. 1.1, 2014-08-20 WDConfig1 locked with LOCK=1 Field Bits Type Description WDHBTP 6:0 rw Watchdog Heartbeat Timer Period: 0000000B no change 0000001B 1,6ms 0000010B 3,2ms 1111111B 203,2ms Reset: 1000111B WDConfig1 Offset Reset Value 064H 03H Field Bits Type Description FWDKQ 4 rw Functional Watchdog Keep Question Setup: 0B No influence to question generation in case of window watchdog error 1B Keep question in case of window watchdog error Reset: 0B FWDQG 3 rw Functional Watchdog Question Generation: 0B Question period 16 1B Question period 256 Reset: 0B WDREN 2 rw Watchdog Reset Enable Bit: 0B reset disabled 1B reset enabled Reset: 0B LINWE 1 rw LIN Operation Mode during Watchdog Error Setup: 0B receive only mode 1B according ComConfig1.LIN Reset: 1B 7 6 5 4 3 2 1 0 RES WDHBTP rw 7 6 5 4 3 2 1 0 RES FWDKQ rw FWDQG rw WDREN rw LINWE rw CANWE rw

Data Sheet 186 Rev. 1.1, 2014-08-20

14.6 Control Register

CANWE 0 rw CAN Operation Mode during Watchdog Error Setup: 0B receive only mode 1B according ComConfig1.CAN Reset: 1B Cont0 Offset Reset Value 07BH 00H Field Bits Type Description O8ON 7 rw Output8 Switch on Control Bit: 0B off 1B on Reset: 0B O7ON 6 rw Output7 Switch on Control Bit: 0B off 1B on Reset: 0B O6ON 5 rw Output6 Switch on Control Bit: 0B off 1B on Reset: 0B O5ON 4 rw Output5 Switch on Control Bit: 0B off 1B on Reset: 0B O4ON 3 rw Output4 Switch on Control Bit: 0B off 1B on Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 O8ON rw O7ON rw O6ON rw O5ON rw O4ON rw O3ON rw O2ON rw O1ON rw

Data Sheet 187 Rev. 1.1, 2014-08-20 O3ON 2 rw Output3 Switch on Control Bit: 0B off 1B on Reset: 0B O2ON 1 rw Output2 Switch on Control Bit: 0B off 1B on Reset: 0B O1ON 0 rw Output1 Switch on Control Bit: 0B off 1B on Reset: 0B Cont1 Offset Reset Value 07CH 00H Field Bits Type Description O16ON 7 rw Output16 Switch on Control Bit: 0B off 1B on Reset: 0B O15ON 6 rw Output15 Switch on Control Bit: 0B off 1B on Reset: 0B O14ON 5 rw Output14 Switch on Control Bit: 0B off 1B on Reset: 0B O13ON 4 rw Output13 Switch on Control Bit: 0B off 1B on Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 O16ON rw O15ON rw O14ON rw O13ON rw O12ON rw O11ON rw O10ON rw O9ON rw

Data Sheet 188 Rev. 1.1, 2014-08-20 O12ON 3 rw Output12 Switch on Control Bit: 0B off 1B on Reset: 0B O11ON 2 rw Output11 Switch on Control Bit: 0B off 1B on Reset: 0B O10ON 1 rw Output10 Switch on Control Bit: 0B off 1B on Reset: 0B O9ON 0 rw Output9 Switch on Control Bit: 0B off 1B on Reset: 0B Cont2 Offset Reset Value 07DH 00H Field Bits Type Description O24ON 7 rw Output24 Switch on Control Bit: 0B off 1B on Reset: 0B O23ON 6 rw Output23 Switch on Control Bit: 0B off 1B on Reset: 0B O22ON 5 rw Output22 Switch on Control Bit: 0B off 1B on Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 O24ON rw O23ON rw O22ON rw O21ON rw O20ON rw O19ON rw O18ON rw O17ON rw

Data Sheet 189 Rev. 1.1, 2014-08-20 O21ON 4 rw Output21 Switch on Control Bit: 0B off 1B on Reset: 0B O20ON 3 rw Output20 Switch on Control Bit: 0B off 1B on Reset: 0B O19ON 2 rw Output19 Switch on Control Bit: 0B off 1B on Reset: 0B O18ON 1 rw Output18 Switch on Control Bit: 0B off 1B on Reset: 0B O17ON 0 rw Output17 Switch on Control Bit: 0B off 1B on Reset: 0B Cont3 Offset Reset Value 07EH 00H Field Bits Type Description IGN4ON 3 rw Ignition Output4 Switch on Control Bit: 0B off 1B on Reset: 0B IGN3ON 2 rw Ignition Output3 Switch on Control Bit: 0B off 1B on Reset: 0B Field Bits Type Description 7 6 5 4 3 2 1 0 RES IGN4ON rw IGN3ON rw IGN2ON rw IGN1ON rw

Data Sheet 190 Rev. 1.1, 2014-08-20 IGN2ON 1 rw Ignition Output2 Switch on Control Bit: 0B off 1B on Reset: 0B IGN1ON 0 rw Ignition Output1 Switch on Control Bit: 0B off 1B on Reset: 0B Field Bits Type Description

Data Sheet 191 Rev. 1.1, 2014-08-20

15 SPI

Alternatively to the MSC communication interface a SPI interface is available. It uses the pins SIP, SDO, CSN and FCLP. The configuration is done via the pins FCLN and SIN. FCLN must be connected to VDDIO and SIN must be connected to AGND. In SPI mode the output stage of the pin SDO is set to push pull operation (definition and description see Chapter 13.2 and Chapter 13.4). The definition of the registers is the same as for the MSC communication (see Chapter 14), only the frame is SPI specific (see Figure 67 and Chapter 15.1). Multiple read commands are not allowed. There is no monitoring of valid transmissions implemented (like MSC monitoring, see Chapter 13.1.1). Figure 66 Block diagram of the SPI interface

15.1 SPI Protocol

The principle of the SPI communication is shown in Figure 67. The message from the micro controller must be sent LSB first. The data from the SDO pin is sent LSB first. The TLE8888-1QK samples data from the SIP pin on the falling edge of FCLP and shifts data out of the SDO pin on the rising edge of FCLP. Each access must be terminated by a rising edge of CSN. All SPI messages must be exactly 16-bits long, ot herwise the SPI message is discarded and the bit COMFE in diagnosis register ComDiag is set to “1”. There is one message delay in the response to each message (i.e. the response for message N will be returned during message N+1). There are two valid access possible:

• Write access to registers with write permission: the answer is 1 for the R /W bit, the address and the content of the register
• Read access to register with read permission: the answer is 0 for the R /W bit, the address and the content of the register Everything else is not executed. Note: Write access to multiple read commands are also not valid in SPI mode. M S C S P I REF SDO FCLN SIP SIN CSN FCLP VDDIO

Data Sheet 192 Rev. 1.1, 2014-08-20 Status Flag Indication: after the falling edge of CSN and before the first rising edge of FCLP the level of the SDO indicates an OR combination of the status of the central failure bit CF and the central overtemperature bit COT of the diagnosis register Diag0. With this feature during every SPI communication a check of the diagnosis status can be done without additional read access of the diagnosis register. Figure 67 SPI Protocol SPI Answers:

• during power on reset: SPI commands are ignored, SDO is always tristate
• after power on reset: the address and the content of the status register OpStat0 is transmitted with the next SPI transmission
• during watchdog reset: SPI commands are ignored, SDO has the value of the status flag
• after watchd og reset: the address and the content of the diagnosis register FWDStat1 is transmitted with the first SPI transmission after the low to high transition of RST
• after a read or write command: the address and content of the selected register is transmitted with the next SPI transmission (for not existing addresses or wrong access mode the data is always “0”)
• after an invalid communication frame: the address and the content of the diagnosis register Diag0 is transmitted with the next SPI transmission and the bit COMFE in diagnosis register ComDiag is set to “1” Bit 0 LSB Bit 15MS B don’t care don’t care clock clock clock clock clock Bit 1 Bit 2 Bit 14 don’t care Bit 15 MSB Bit 0 LSB Bit 1 tristatetristate time time time time don’t care Bit 15Bit 2 FCLP SIP SDO CSN Status Flag ) active clock edge for reading data at SI

Data Sheet 193 Rev. 1.1, 2014-08-20

15.2 SPI Frame Definition

1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 C7 C6 C5 C4 C3 C2 C1 C0 Field Bits Type Description C0 0 R/W Bit: defines the access to the register C[7:1] [7:1] Address Bits, definition see Chapter 14 CD[7:0] [15:8] Data Bits, definition see Chapter 14

Data Sheet 194 Rev. 1.1, 2014-08-20

15.3 Electrical Characteristics SPI

Table 51 Electrical Characteristics Communication VS=13.5V, VV5V=5V, Tj=-40 to 150°C, all voltages with respect to GND, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. SPI detection threshold for SIN VFCLN_SPI 0.3 – 0.7 V P_15.1 Single ended mode detection threshold for FCLN VFCLN_single 2– 3 V P_15.2 SDO see Chapter 13.4 P_15.3 Input low level (SIP, FCLP, CSN) VINn_L -0.3 – 0.8 V P_15.4 Input high level (SIP, FCLP, CSN) VINn_H 1.6 – 5.5 V P_15.5 Input hysteresis (SIP, FCLP, CSN) VINn_Hys 0.1 – 0.5 V P_15.6 Clock frequency f SPI –– 5 M H z P_15.7

Data Sheet 195 Rev. 1.1, 2014-08-20 TLE8888-1QK EMC Requirements

16 EMC Requirements

16.1 ISO Pulse Tests

Definitions for all ISO pulse test on application incl uding the TLE8888-1QK are regarding standard ISO 7637- 2:2011. Following amplitude definition for the tests are required:

• Pulse 3a: VS= -140V, all outputs available on ECU connector
• Pulse 3b: VS= 140V, all outputs available on ECU connector
• Pulse 5: VS= +38.5V (clamped), td=4 00ms (ECU reset is permitted under this test, outputs will be switched off) The tests are performed only on application level.

Application Information

Data Sheet 196 Rev. 1.1, 2014-08-20 Note: The information in this chapter is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Note: These are very simplified examples of application circuits. The functions must be verified in the real application. Figure 68 Application Diagram Push Pull Driver 20mA DFBx Diagnosis Power Stage 0.6A Half Bridge Power Stage 4.5A Power Stage 2.2A Linear Regulator (Tracker) V5V T5V1 BAT VG V6V T5V2 Linear Pre-regulator Linear Regulator Linear Regulator (Tracker) Vref V5V Vref Key Off Delay KOFFDO to internal supply Main Relay Driver Key and WK Detection KEY WK MR Voltage Monitoring ChargepumpCP BATPA BATPB OUT21 OUT24 OUT22 OUT23 Power Stage 2.2A OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B OUT5A OUT5B Power Stage 4.5A OUT5C OUT6A OUT6B OUT6C OUT7A OUT7B OUT7C Half Bridge OUT14 OUT15 OUT17 OUT18 Power Stage 0.6A OUT16 OUT19 OUT20 VR Sensor Interface VRIN1 VRIN2 VROUT LIN Interface LINIO LINTX LINRX DFB8 OUT8 DFB9 OUT9 DFB10 OUT10 DFB11 OUT11 DFB12 OUT12 DFB13 OUT13 Push Pull Driver 20mA DFBx Diagnosis Monitoring Watchdog VDDIO MON RST IN12 IN1 SIP SIN FCLP FCLN CSN SDO MSC/SPI InterfaceDirect Drive Inputs AGND PGND Exposed Pad Control Logic Standby Supply BATSTBY V5VSTBY Ignition Driver Ignition Driver 20mA IGN1 IGN3 IGN4 IGN2 Engine Off Timer EOTEN INJEN from micro controller I/O supply from/to micro controller from/to micro controller to micro controller to VR Sensor to Sensors 5V ECU supply nd wake input Battery to DFBx Ignition Battery Battery M high side or low side or motor configuration connection to standby supply or AGND IGNEN Battery CAN Interface Wake Receiver CANH CANTX CANRX CANL CANWKEN from/to micro controller connection to standby supply or AGND V5VCANconnection to V5V connection to VDDIO connection to VDDIO connection to V5V Optional connection to INJEN and IGNEN

Data Sheet 197 Rev. 1.1, 2014-08-20

17.1 Supply Systems

Figure 69 Application Diagram Supply Systems In Figure 69 three setups for connecting the battery supply to the TLE8888-1QK are shown. With non permanent battery supply there is no standby supply available and a ll functions related to this supply (e.g. engine off timer) are not active. Wake up could be done by a signal at the pins KEY and WK. In a permanent supply system the standby supply is permanently connected to the battery and all functions related to this supply can be enabled (e.g. CAN remote wake up). The pins BATPA and BATPB must be connected to the switched battery supply because there is no special mode to reduce the current consumption in standby mode. The pin BAT and the external MOSFET of the pre regulator are allowed to be connected permanently to the battery. VG V6V BATSTBY V5VSTBY BATPA BATPB BAT WK KEY MR to all other loads External Wake Up Circuit Permanent Supply System 1 ECU TLE8888 VG V6V BATSTBY V5VSTBY BATPA BATPB BAT WK KEY MR to all other loads External Wake Up Circuit Permanent Supply System 2 ECU TLE8888 VG V6V BATSTBY V5VSTBY BATPA BATPB BAT WK KEY MR to all other loads Non Permanent Supply System ECU TLE8888

Data Sheet 198 Rev. 1.1, 2014-08-20

17.2 VR Sensor Interface

For Hall sensor signal detection in Figure 70 and Figure 71 different proposals for the external devices are shown. For the description of the set ups see Chapter 10 Figure 70 Application Circuit for VR Sensor Interface used for Hall Sensor in Hall Mode Set Up VROUT VR Sensor Interface VRIN1 VRIN2 Hall Sensor Sensor Supply 2-2,5V internaly generated 3 wire Hall Sensor VR Sensor Interface VRIN1 VRIN2 Hall Sensor Sensor Supply VROUT 2 wire Hall Sensor 2-2,5V internaly generated

Data Sheet 199 Rev. 1.1, 2014-08-20 Figure 71 Application Circuit for VR Sensor Interface used for Hall Sensor in Auto, Semi Auto and Manual Detection Mode Set Up VR Sensor Interface VRIN1 VRIN2 Hall Sensor Sensor Supply 2-2,5V VROUT 2 wire Hall Sensor VROUT VR Sensor Interface VRIN1 VRIN2 Hall Sensor Sensor Supply 3 wire Hall Sensor 2-2,5V

Doc_Preliminary Data Sheet 200 Rev. 1.1, 2014-08-20 Figure 72 LQFP-100 For the LQFP-100 package the lead frame version C66065-A6837-C029 with an exposed pad size of 8.5mm*8.5mm is used. Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Data Sheet 201 Rev. 1.1, 2014-08-20 TLE8888-1QK

Revision History

V1.1 2014-08-20 on all pages: general name changed to “TLE8888-1QK” and date and revision V1.1 2014-08-20 page 5 and 6: 2 device types added V1.1 2014-08-20 page 29: parameter P_5.3.24 min/max changed definiton improved V1.1 2014-08-20 page 58: parameter P_8.8.45 definiton improved V1.1 2014-08-20 page 62: table 25 corrected V1.1 2014-08-20 page 100: PGND reference pin changed V1.1 2014-08-20 page 2, 9, 10, 11, 17, 18, 20, 21, 22 , 26, 38, 39, 43, 44, 45, 48, 49, 52, 56, 58, 196: missing variable names added V1.0 2014-03-13 Data Sheet

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