TC364DP64F300FAAKXUMA1

TC36X INFINEON | Alldatasheet

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V 1.0, 2020-04 TC36x 32-Bit Single-Chip Microcontroller AA-Step 32-Bit Single-Chip Microcontroller 32-Bit Microcontroller OPEN MARKET VERSION

81726 Munich, Germany

© 2020 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be reg arded as a guarantee of conditions or characteristics. With respect to any examples or hints given he rein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and condi tions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com) Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support de vices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety o r effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human bo dy or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. OPEN MARKET VERSION

Data Sheet 3 V 1.0, 2020-04

Revision History

Page or Item Subjects (major c hanges since previous revision) V 0.4, 2018-08 The history is documented in the last chapter V 0.6, 2019-02 The history is documented in the last chapter V 0.7, 2019-11 The history is documented in the last chapter V 1.0, 2020-04 The history is documented in the last chapter OPEN MARKET VERSION

Data Sheet 4 V 1.0 2020-04 Trademarks of Infineon Technologies AG AURIX™, C166™, C anPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, C o o l S E T ™ , CORECONTROL™, CROSSAVE™ , DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™ , EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER ™, eupec™, FCOS™, HITFET™, Hyb ridPACK™, I²RF™, ISOFACE™, IsoPACK™, MI PAQ™, ModSTACK™, my-d ™, NovalithIC™, Opti MOS™, ORIGA™, POWERCODE™; PRIMARION™ , PrimePACK™, PrimeSTA CK™, PRO-SIL™, PROF ET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, AR M™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetoot h™ of Bluetooth SIG Inc. CAT-i q™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Lt d. EMV™ of EMVCo, LLC (Visa H oldings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexR ay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Int ernationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICRO TEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Allianc e, Inc. MIPS™ of MIPS Technol ogies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Rese arch Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. R ED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of S irius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIY O YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 OPEN MARKET VERSION

Data Sheet 5 V 1.0, 2020-04 Table of Contents OPEN MARKET VERSION

Data Sheet 6 V 1.0 2020-04 OPEN MARKET VERSION

Data Sheet 7 V 1.0, 2020-04

1 Summary of Features

The TC36x product family has the following features:

• High Performance Microcon troller with two CPU cores
• Two 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having t he following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate u nit able to sustain 2 MAC operations per cycle – Fully pipelined Floating point unit (FPU) – up to 300 MHz operation at full temperature range – up to 192 Kbyte Data S cratch-Pad RAM (DSPR) – up to 32 Kbyte Instructio n Scratch-Pad RAM (PSPR) – up to 64 Kbyte Data RAM (DLMU) – 32 Kbyte Instruction Cache (ICACHE) – 16 Kbyte Data Cache (DCACHE)
• Lockstepped shadow cores for all TC1.6.2P
• Multiple on-chip memories – All embedded NVM and S RAM are ECC protected – up to 4 Mbyte Program Flash Memory (PFLASH) – up to 128 kbyte Data Flash Mem ory (DFLASH) usable for EEPROM emulation – BootROM (BROM)
• 64-Channel DMA Controller with safe data transfer
• Sophisticated interrupt system (ECC protected)
• High performance on -chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel acces s between bus masters, CPUs and memories – 32-bit System Peripheral Bus ( SPB) for on-chip peripheral and functional units – SRI to SPB bus br idges (SFI Bridge)
• Optional Hardware Security Module (HSM) on some variants
• Safety Management Unit (SMU) handling safety monitor alarms
• Memory Test Unit with ECC, Memor y Initialization and MBIST functions (MTU)
• Hardware I/O Monitor (IOM) for checking of digital I/O
• Versatile On-chip Peripheral Units – 12 Asynchronous/Synchronous Serial Channels (ASCLIN) with hard ware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – 4 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s – 1 High Speed Serial Link (HSSL) for serial inter-processor com munication up to 320 Mbit/s – 1 serial Micro Second Bus int erfaces (MSC) for serial port expansion to external power devices – 2 MCMCAN Modules with 4 CAN node s for high efficiency data handling via FIFO buffering – 10 Single Edge Nibble Transmissi on (SENT) channels for connection to sensors –1 F l e x R a yTM module with 2 channels (E-Ray) supporting V2.1 – One Generic Timer Module (GTM) p roviding a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management OPEN MARKET VERSION

Data Sheet 8 V 1.0, 2020-04 – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) – One General Purpose 12 Timer Unit (GPT120) – 2 channel Peripheral Sensor Inte rface conforming to V1.3 (PSI5) – 1 Peripheral Sensor Interface with Serial PHY (PSI5-S) – 1 Inter-Integrated Cir cuit Bus Interface (I2C) conforming to V2.1 – 1 IEEE802.3 Ethernet MAC with RG MII, RMII and MII interfaces (ETH)

• Versatile Successive Approximation ADC (VADC) – Cluster of 8 indep endent ADC kernels – Input voltage range from 0 V to 5.5V (ADC supply)
• Delta-Sigma ADC (DSADC) – 4 channels
• Digital programmable I/O ports
• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
• multi-core debugging, real time tracing, and calibration
• four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
• Power Management System and on-chip regulators
• Clock Generation Unit with Sy stem PLL and Peripheral PLL
• Embedded Voltage Regulator OPEN MARKET VERSION

Data Sheet 9 V 1.0, 2020-04

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• The package and the type of delivery. Table 1-1 Platform Feature Overview Feature TC36x CPUs Type TC1.6.2 Cores / Checker Cores 2 / 2 Max. Freq. 300 MHz Cache per CPU Program 32 KB Data 16 KB SRAM per CPU PSPR 32 KB DSPR 192 KB DLMU 64 KB Program Flash Size 4 MB Banks 2 x 2 MB Data Flash Size (single-ended) 128 kB DMA Channels 64 CONVCTRL Modules 1 EVADC Primary Groups/Channels 4 / 32 Secondary Groups/Channels 2 / 32 Fast Compare Channels 2 EDSADC Channels 4 GTM Clusters 4 @ 200MHz TIM (8 ch) 3 TOM (16 ch) 2 ATOM (8 ch) 4 MCS (8 ch) 3 CMU / ICM 1 / 1 PSM 1 TBU channels1) 4 (TBU0-3) SPE 2 CMP / MON 1 / 1 BRC / DPLL 1 / 1 CDTM modules 4 DTM modules 12 (4 on TOM, 8 on ATOM) Timer GPT12 1 CCU6 1 STM Modules 2 OPEN MARKET VERSION

Data Sheet 10 V 1.0, 2020-04 FlexRay Modules 1 Channels 2 CAN Modules 2 Nodes 2 x 4 of which support TT-CAN 1 QSPI Modules 4 HSCI Channels 0 ASCLIN Modules 12 I2C Interfaces 1 SENT Channels 10 PSI5 Modules 2 PSI5-S Modules 1 HSSL Channels 1 MSC Channels 1 EBU External Bus 0 SDMMC eMMC/SD Interface 0 Ethernet (10/100Mbit/1Gbit) Modules 1 FCE Modules 1 Safety Support SMU yes IOM yes SPU Modules 0 RIF Modules 0 HSPDM Modules 0 Security HSM+ 1 Debug OCDS yes MCDS no miniMCDS no miniMCDS TRAM - AGBT no Low Power Features Standby RAM DLMU0&1 SCR yes Packages Type LFBGA-292 / LFBGA-180 / LQFP-176 /LQFP-144 / TQFP- 144 I/O Type 5 V CMOS / 3.3 V CMOS / LVDS Tambient Range −40 … +150°C 1) TBU3 has special purpose as angle clock. Table 1-1 Platform Feature Overview (cont’d) Feature TC36x OPEN MARKET VERSION

TC36x Pin Definition and Functions: Data Sheet 11 V 1.0, 2020-04

2 TC36x Pin Definition and Functions:

The following figures are showing the TC36x Logic Symbols for the package variants:

• LFBGA-292 ( Figure 2-1)
• LFBGA-180 ( Figure 2-2)
• LQFP-176 ( Figure 2-3)
• LQFP-144 ( Figure 2-4)
• TQFP-144 ( Figure 2-5) Figure 2-1 TC36x Logic Symbol for the package variant LFBGA-292 P15.0 P15.1 P15.2 P15.3 P15.4 P15.5 P15.6 P15.7P15.8 P14.0 P14.2 P14.3 P14.4 P14.5 P14.6 P14.7 P14.8 P14.9P14.10 P13.0 P13.1 P13.2 P13.3 P12.0P12.1 P11.14 P11.13 P11.15 P11.0P11.1 P11.2 P11.4 P11.3 P11.6P11.5 P11.7 P11.9 P11.8 P11.10 P11.11 P11.12 P10.0 P10.1 P10.2 P10.3 P10.4P10.5 P10.7 P10.6 P10.8P02.0 P02.1P02.2 P02.3P02.4 P02.5P02.6 P02.7P02.8 P00.0 P33.8 P32.2 P32.3 P32.4 P23.0 P23.1 P23.3 P23.2 P23.5 P23.4 P22.0P22.1 P22.2P22.3 P21.0 P21.1 P21.2 P21.3 P21.4 P21.5 P21.6 / TDI P21.7 / TDO P20.0 P20.1 P20.2 P20.3 P20.6 P20.7 P20.8 P20.9 P20.10 P20.12 P20.11 P20.13 P20.14 VDDM VFLEX VDDP3 VDDP3 VSSM P32.0 / VGATE VAREF VAGND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC1 NC1 NC1 VEVRS B P32.1 / VGATE P33.0 P33.1 P33.2 P33.3 P33.4 P33.5 P33.6 P33.7 P33.9 P33.10 P33.11 P33.12 P33.13 P14.1 TMS TRST TCK ESR1 PORST ESR0 P00.1 P00.2 P00.3 P00.4 P00.5 P00.6 P00.7 P00.8P00.9 P00.10 P00.11 P00.12 AN43 AN42 AN47AN46 AN45AN44 AN39 / P40.9 AN38 / P40.8 AN37 / P40.7 AN36 / P40.6 AN35 AN34 AN33 / P40.5 AN32 / P40.4 AN29 AN28 AN27 / P40.3 AN26 / P40.2 AN25 / P40.1 AN24 / P40.0 AN23 AN22 AN41 AN21 AN40 AN20 AN31 AN19 AN30 AN18 AN17 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 XTAL1XTAL2 VDD VDD VDD VDD VDD VDD VDD VDDVDD VDD VEXT VEXT VEXT VEXT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VEXT A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V W W Y Y TC36xpd - (top view) OPEN MARKET VERSION

TC36x Pin Definition and Functions: Data Sheet 12 V 1.0, 2020-04 Figure 2-2 TC36x Logic Symbol for the package variant LFBGA-180 P15.0P15.1 P15.2 P15.3 P15.4 P15.5 P15.6 P15.7P15.8 P14.0 P14.2 P14.3P14.4 P14.5 P14.6P14.8 P14.10 P13.0 P13.1 P13.2 P13.3 P11.2 P11.3 P11.6 P11.9 P11.8 P11.10 P11.11 P11.12 P10.0 P10.1 P10.2P10.3 P10.4 P10.5 P10.6 P02.0 P02.1 P02.2 P02.3P02.4P02.5 P02.6 P02.7 P02.8 P00.0 P33.8 P32.4 P23.1 P23.3 P22.0 P22.1 P22.2 P22.3 P21.0 P21.2 P21.3P21.4 P21.5 P21.6 / TDI P21.7 / TDO P20.0 P20.2P20.3 P20.6 P20.7 P20.8 P20.9 P20.10 P20.12 P20.11 P20.13 P20.14 VDDM VFLEX VDDP3 P32.0 / VGATE VAREF NC NC NC NC NC NC NC NC VEVRS B P32.1 / VGATE P33.0P33.1 P33.2 P33.3 P33.4 P33.5 P33.6 P33.7 P33.9 P33.10P33.11 P33.12 P33.13 P14.1 VSSM / VAGND TMS TRST TCK ESR1 PORST ESR0 P00.1 P00.2P00.3P00.4 P00.5 P00.6P00.7P00.8 P00.9P00.12 AN39 / P40.9 AN38 / P40.8 AN37 / P40.7 AN36 / P40.6 AN35AN34AN33 / P40.5 AN32 / P40.4 AN25 / P40.1 AN24 / P40.0 AN17AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 XTAL1XTAL2 VDD VDD VDD VDD VDD VEXT VEXT VEXT VEXT VEXT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VEXT A A B B C C D D E E F F G G H H J J K K L L M M N N P P TC36xpd - (top view) OPEN MARKET VERSION

TC36x Pin Definition and Functions: Data Sheet 13 V 1.0, 2020-04 Figure 2-3 TC36x Logic Symbol for the package variant LQFP-176 133 P15.0 134 P15.1 135 P15.2 136 P15.3 137 P15.4 138 P15.5 139 P15.6 140 P15.7 141 P15.8 142 P14.0 144 P14.2 145 P14.3 146 P14.4 147 P14.5 148 P14.6 149 P14.7 150 P14.8 151 P14.9 152 P14.10 156 P13.0 157 P13.1 158 P13.2 159 P13.3 160 P11.2 161 P11.3 162 P11.6 163 P11.9 165 P11.10 166 P11.11 167 P11.12 168 P10.0 169 P10.1 170 P10.2 171 P10.3 172 P10.4 173 P10.5 175 P10.7 174 P10.6 176 P10.8 1P02.0 2P02.1 3P02.2 4P02.3 5P02.4 6P02.5 7P02.6 8P02.7 9P02.8 11P00.0 78P33.8 86P32.2 87P32.3 88P32.4 89 P23.0 90 P23.1 92 P23.3 91 P23.2 94 P23.5 93 P23.4 95 P22.0 96 P22.1 97 P22.2 98 P22.3 105 P21.0 106 P21.1 107 P21.2 108 P21.3 109 P21.4 110 P21.5 111 P21.6 / TDI 113 P21.7 / TDO 116 P20.0 117 P20.1 118 P20.2 119 P20.3 124 P20.6 125 P20.7 126 P20.8 127 P20.9 128 P20.10 130 P20.12 129 P20.11 131 P20.13 132 P20.14 54VDDM

164 VFLEX

154 VDDP3

84P32.0 / VGATE1N 52VAREF1 69VEVRSB 85P32.1 / VGATE1P

155 VDD

100 VDD

123 VDD

153 VEXT

99 VEXT

70P33.0 71P33.1 72P33.2 73P33.3 74P33.4 75P33.5 76P33.6 77P33.7 79P33.9 80P33.10 81P33.11 82P33.12 83P33.13 143 P14.1 53VSSM 51VAGND1

101 VSS

104 VEXT

112 TMS

114 TRST

115 TCK

120 ESR1

121 PORST

122 ESR0

12P00.1 13P00.2 14P00.3 15P00.4 16P00.5 17P00.6 18P00.7 19P00.8 20P00.9 21P00.10 22P00.11 23P00.12 26AN43 27AN42 28AN47 29AN46 30AN45 31AN44 32AN39 / P40.9 33AN38 / P40.8 34AN37 / P40.7 35AN36 / P40.6 36AN35 37AN33 / P40.5 38AN32 / P40.4 39AN29 40AN28 41AN27 / P40.3 42AN26 / P40.2 43AN25 / P40.1 44AN24 / P40.0 45AN21 46AN20 47AN19 48AN18 49AN17 50AN16 55AN13 56AN12 57AN11 58AN10 59AN8 60AN7 61AN6 62AN5 63AN4 64AN3 65AN2 66AN1 67AN0

102 XTAL1

103 XTAL2

(Top View) OPEN MARKET VERSION

TC36x Pin Definition and Functions: Data Sheet 14 V 1.0, 2020-04 Figure 2-4 TC36x Logic Symbol for the package variant LQFP-144 109 P15.0 110 P15.1 111 P15.2 112 P15.3 113 P15.4 114 P15.5 115 P15.6 116 P15.7 117 P15.8 118 P14.0 120 P14.2 121 P14.3 122 P14.4 123 P14.5 124 P14.6 128 P13.0 129 P13.1 130 P13.2 131 P13.3 132 P11.2 133 P11.3 134 P11.6 135 P11.9 137 P11.10 138 P11.11 139 P11.12 140 P10.1 141 P10.2 142 P10.3 143 P10.5 144 P10.6 1P02.0 2P02.1 3P02.2 4P02.3 5P02.4 6P02.5 7P02.6 8P02.7 9P02.8 11P00.0 64P33.8 72P32.4 73 P23.1 74 P22.0 75 P22.1 76 P22.2 77 P22.3 84 P21.2 85 P21.3 86 P21.4 87 P21.5 88 P21.6 / TDI 90 P21.7 / TDO 93 P20.0 94 P20.2 95 P20.3 100 P20.6 101 P20.7 102 P20.8 103 P20.9 104 P20.10 106 P20.12 105 P20.11 107 P20.13 108 P20.14 44VDDM

136 VFLEX

126 VDDP3

70P32.0 / VGATE1N 42VAREF1 59VEVRSB 71P32.1 / VGATE1P 10VDD

125 VEXT

78 VEXT

127 VDD

79 VDD

99 VDD

60P33.4 61P33.5 62P33.6 63P33.7 65P33.9 66P33.10 67P33.11 68P33.12 69P33.13 119 P14.1 43VSSM 41VAGND1

80 VSS

83 VEXT

89 TMS

91 TRST

92 TCK

96 ESR1

97 PORST

98 ESR0

12P00.1 13P00.2 14P00.3 15P00.4 16P00.5 17P00.6 18P00.7 19P00.8 20P00.9 21P00.12 24AN43 25AN42 26AN47 27AN46 28AN45 29AN44 30AN39 / P40.9 31AN38 / P40.8 32AN37 / P40.7 33AN36 / P40.6 34AN35 35AN25 / P40.1 36AN24 / P40.0 37AN21 38AN20 39AN17 40AN16 45AN13 46AN12 47AN11 48AN10 49AN8 50AN7 51AN6 52AN5 53AN4 54AN3 55AN2 56AN1 57AN0

81 XTAL1

82 XTAL2

(Top View) OPEN MARKET VERSION

TC36x Pin Definition and Functions: Data Sheet 15 V 1.0, 2020-04 Figure 2-5 TC36x Logic Symbol for the package variant TQFP-144 109 P15.0 110 P15.1 111 P15.2 112 P15.3 113 P15.4 114 P15.5 115 P15.6 116 P15.7 117 P15.8 118 P14.0 120 P14.2 121 P14.3 122 P14.4 123 P14.5 124 P14.6 128 P13.0 129 P13.1 130 P13.2 131 P13.3 132 P11.2 133 P11.3 134 P11.6 135 P11.9 136 P11.8 137 P11.10 138 P11.11 139 P11.12 140 P10.1 141 P10.2 142 P10.3 143 P10.5 144 P10.6 1P02.0 2P02.1 3P02.2 4P02.3 5P02.4 6P02.5 7P02.6 8P02.7 9P02.8 11P00.0 64P33.8 73 P23.1 74 P22.0 75 P22.1 76 P22.2 77 P22.3 84 P21.2 85 P21.3 86 P21.4 87 P21.5 88 P21.6 / TDI 90 P21.7 / TDO 93 P20.0 94 P20.2 95 P20.3 100 P20.6 101 P20.7 102 P20.8 103 P20.9 104 P20.10 106 P20.12 105 P20.11 107 P20.13 108 P20.14 44VDDM 70P32.0 / VGATE1N 42VAREF1 53NC 54NC 55NC 52VEVRSB 71P32.1 / VGATE1P 10VDD 56P33.0 57P33.1 58P33.2 59P33.3 60P33.4 61P33.5 62P33.6 63P33.7 65P33.9 66P33.10 67P33.11 68P33.12 119 P14.1 43VSSM 41VAGND1 12P00.1 13P00.2 14P00.3 15P00.4 16P00.5 17P00.6 18P00.7 19P00.8 20P00.9 21P00.12 24AN39 / P40.9 25AN38 / P40.8 26AN37 / P40.7 27AN36 / P40.6 28AN35 29AN34 30AN33 / P40.5 31AN32 / P40.4 32AN28 33AN27 / P40.3 34AN26 / P40.2 35AN25 / P40.1 36AN24 / P40.0 37AN21 38AN20 39AN17 40AN16 45AN11 46AN5 47AN4 48AN3 49AN2 50AN1 51AN0 (Top View) OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 16 V 1.0, 2020-04

2.1 LFBGA-292 Packag e Variant Pin Configuration of TC36x

Table 2-1 Port 00 Functions Ball Symbol Ctrl. Buffer Type Function G1 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 17 V 1.0, 2020-04 G2 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI Analog input channel 11, group 9 P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 18 V 1.0, 2020-04 H1 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 19 V 1.0, 2020-04 H2 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI Analog input channel 9, group 9 P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 20 V 1.0, 2020-04 J1 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input EVADC_G9CH8 AI Analog input channel 8, group 9 P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 21 V 1.0, 2020-04 J2 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 J4 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 22 V 1.0, 2020-04 K1 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 K4 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 23 V 1.0, 2020-04 K2 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI Analog input channel 3, group 9 P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 K5 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN1_1 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 24 V 1.0, 2020-04 L1 P00.11 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN2_1 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 EVADC_G9CH1 AI Analog input channel 1, group 9 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT0 O4 Modulator clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved L2 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input EVADC_G9CH0 AI Analog input channel 0, group 9 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 25 V 1.0, 2020-04 Table 2-2 Port 02 Functions Ball Symbol Ctrl. Buffer Type Function B1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 26 V 1.0, 2020-04 C2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 —O 2 Reserved QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 27 V 1.0, 2020-04 C1 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 28 V 1.0, 2020-04 D2 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input PSI5_RX0B RXD inputs (receive data) channel 0 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 29 V 1.0, 2020-04 D1 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 30 V 1.0, 2020-04 E2 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 31 V 1.0, 2020-04 E1 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 32 V 1.0, 2020-04 F2 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 33 V 1.0, 2020-04 F1 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output —O 4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-2 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 34 V 1.0, 2020-04 Table 2-3 Port 10 Functions Ball Symbol Ctrl. Buffer Type Function A7 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_2 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_2 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B7 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 35 V 1.0, 2020-04 A5 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select —O 5 Reserved —O 6 Reserved —O 7 Reserved A6 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved Table 2-3 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 36 V 1.0, 2020-04 B6 P10.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_2 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_2 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 —O 2 Reserved QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved B5 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output —O 7 Reserved Table 2-3 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 37 V 1.0, 2020-04 A4 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 —O 5 Reserved QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved A3 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_3 Mux input channel 0 of TIM module 0 GPT120_T3EUDB Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 —O 2 Reserved QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved CAN12_TXD O6 CAN transmit output node 2 —O 7 Reserved Table 2-3 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 38 V 1.0, 2020-04 B4 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_2 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_2 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-4 Port 11 Functions Ball Symbol Ctrl. Buffer Type Function E10 P11.0 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN0_7 Mux input channel 0 of TIM module 2 ASCLIN3_ARXB Receive input GTM_DTMA2_1 CDTM2_DTM4 P11.0 O0 General-purpose output GTM_TOUT119 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved CAN11_TXD O5 CAN transmit output node 1 GETH_TXD3 O6 Transmit Data —O 7 Reserved Table 2-3 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 39 V 1.0, 2020-04 E9 P11.1 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN1_6 Mux input channel 1 of TIM module 2 P11.1 O0 General-purpose output GTM_TOUT120 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 GETH_TXD2 O6 Transmit Data —O 7 Reserved A10 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 40 V 1.0, 2020-04 B10 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 D10 P11.4 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN2_6 Mux input channel 2 of TIM module 2 GETH_RXCLKB Receive Clock MII P11.4 O0 General-purpose output GTM_TOUT121 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved CAN13_TXD O5 CAN transmit output node 3 GETH_TXER O6 Transmit Error MII GETH_TXCLK O7 Transmit Clock Output for RGMII Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 41 V 1.0, 2020-04 D8 P11.5 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN3_8 Mux input channel 3 of TIM module 2 GETH_TXCLKA Transmit Clock Input for MII GETH_GREFCLK Gigabit Reference Clock input for RGMII (125 MHz high precission) P11.5 O0 General-purpose output GTM_TOUT122 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved D9 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 42 V 1.0, 2020-04 E8 P11.7 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN4_7 Mux input channel 4 of TIM module 2 GETH_RXD3A Receive Data 3 MII and RGMII (RGMII can use RXD3A only) CAN11_RXDD CAN receive input node 1 P11.7 O0 General-purpose output GTM_TOUT123 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved E7 P11.8 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_8 Mux input channel 5 of TIM module 2 GETH_RXD2A Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN12_RXDD CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 43 V 1.0, 2020-04 A9 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 B9 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 44 V 1.0, 2020-04 A8 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 B8 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 45 V 1.0, 2020-04 E6 P11.13 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN6_7 Mux input channel 6 of TIM module 2 GETH_RXERA Receive Error MII CAN13_RXDD CAN receive input node 3 P11.13 O0 General-purpose output GTM_TOUT125 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved D7 P11.14 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN7_8 Mux input channel 7 of TIM module 2 GETH_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVB Receive Data Valid MII GETH_CRSA Carrier Sense MII P11.14 O0 General-purpose output GTM_TOUT126 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved D6 P11.15 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM0_IN7_8 Mux input channel 7 of TIM module 0 GETH_COLA Collision MII P11.15 O0 General-purpose output GTM_TOUT127 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-4 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 46 V 1.0, 2020-04 Table 2-5 Port 12 Functions Ball Symbol Ctrl. Buffer Type Function E12 P12.0 I SLOW / PU1 / VFLEX / ES General-purpose input CAN00_RXDC CAN receive input node 0 GETH_RXCLKC Receive Clock MII P12.0 O0 General-purpose output GTM_TOUT128 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_MDC O6 MDIO clock —O 7 Reserved E11 P12.1 I SLOW / PU1 / VFLEX / ES General-purpose input GETH_MDIOC MDIO Input P12.1 O0 General-purpose output GTM_TOUT129 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 47 V 1.0, 2020-04 Table 2-6 Port 13 Functions Ball Symbol Ctrl. Buffer Type Function B12 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 A12 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved B11 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 48 V 1.0, 2020-04 A11 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-7 Port 14 Functions Ball Symbol Ctrl. Buffer Type Function B16 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-6 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 49 V 1.0, 2020-04 A15 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 E13 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-7 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 50 V 1.0, 2020-04 B14 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved B15 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-7 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 51 V 1.0, 2020-04 A14 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B —O 7 Reserved B13 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B —O 7 Reserved Table 2-7 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 52 V 1.0, 2020-04 D13 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_5 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_5 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved A13 P14.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_3 Mux input channel 2 of TIM module 2 ERAY0_RXDA0 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-7 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 53 V 1.0, 2020-04 D12 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_3 Mux input channel 3 of TIM module 2 ASCLIN0_ACTSA Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output —O 2 Reserved MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A —O 7 Reserved D11 P14.10 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_3 Mux input channel 4 of TIM module 2 QSPI2_MRSTFP Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output —O 2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A —O 7 Reserved Table 2-7 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 54 V 1.0, 2020-04 Table 2-8 Port 15 Functions Ball Symbol Ctrl. Buffer Type Function B20 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved A18 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 55 V 1.0, 2020-04 C19 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved B17 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-8 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 56 V 1.0, 2020-04 A17 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-8 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 57 V 1.0, 2020-04 E14 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 A16 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-8 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 58 V 1.0, 2020-04 D15 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 D14 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-8 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 59 V 1.0, 2020-04 Table 2-9 Port 20 Functions Ball Symbol Ctrl. Buffer Type Function H20 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output G19 P20.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_5 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved CBS_TGO1 O Trigger output H19 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 60 V 1.0, 2020-04 G20 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved F17 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-9 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 61 V 1.0, 2020-04 F19 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 F20 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-9 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 62 V 1.0, 2020-04 E17 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 E19 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-9 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 63 V 1.0, 2020-04 E20 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 D19 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-9 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 64 V 1.0, 2020-04 D20 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 C20 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-9 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 65 V 1.0, 2020-04 Table 2-10 Port 21 Functions Ball Symbol Ctrl. Buffer Type Function K17 P21.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_6 Mux input channel 4 of TIM module 2 ASCLIN11_ARXC Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM1 O Pin Output Value J17 P21.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_6 Mux input channel 5 of TIM module 2 ASCLIN11_ARXD Receive input P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM2 O Pin Output Value OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 66 V 1.0, 2020-04 K19 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved J19 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output Table 2-10 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 67 V 1.0, 2020-04 K20 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data J20 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data Table 2-10 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 68 V 1.0, 2020-04 H17 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-10 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 69 V 1.0, 2020-04 H16 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-10 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 70 V 1.0, 2020-04 Table 2-11 Port 22 Functions Ball Symbol Ctrl. Buffer Type Function P20 P22.0 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 ASCLIN6_ARXE Receive input QSPI3_MTSRD Slave SPI data input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN6_ATX O7 Transmit output P19 P22.1 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 ASCLIN7_ARXE Receive input QSPI3_MRSTD Master SPI data input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN7_ATX O7 Transmit output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 71 V 1.0, 2020-04 R20 P22.2 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI3_SLSO12 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved R19 P22.3 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 ASCLIN5_ARXC Receive input QSPI3_SCLKD Slave SPI clock inputs P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-11 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 72 V 1.0, 2020-04 Table 2-12 Port 23 Functions Ball Symbol Ctrl. Buffer Type Function V20 P23.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_4 Mux input channel 5 of TIM module 0 CAN10_RXDC CAN receive input node 0 P23.0 O0 General-purpose output GTM_TOUT41 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved U19 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output —O 3 Reserved GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output U20 P23.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_5 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_5 Mux input channel 6 of TIM module 0 ASCLIN7_ARXC Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 73 V 1.0, 2020-04 T19 P23.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_4 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_4 Mux input channel 7 of TIM module 0 ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved T20 P23.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_5 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_5 Mux input channel 7 of TIM module 0 P23.4 O0 General-purpose output GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved T17 P23.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_7 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_7 Mux input channel 2 of TIM module 0 P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-12 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 74 V 1.0, 2020-04 Table 2-13 Port 32 Functions Ball Symbol Ctrl. Buffer Type Function Y17 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved W17 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Y18 P32.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_8 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_8 Mux input channel 3 of TIM module 0 CAN03_RXDB CAN receive input node 3 ASCLIN3_ARXD Receive input P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 75 V 1.0, 2020-04 Y19 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_5 Mux input channel 4 of TIM module 0 P32.3 O0 General-purpose output GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved W18 P32.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_5 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_5 Mux input channel 5 of TIM module 0 ASCLIN1_ACTSB Clear to send input P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output —O 2 Reserved —O 3 Reserved GTM_CLK1 O4 CGM generated clock —O 5 Reserved CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO O DC-DC synchronization output Table 2-13 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 76 V 1.0, 2020-04 Table 2-14 Port 33 Functions Ball Symbol Ctrl. Buffer Type Function W10 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN4_6 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_6 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Y10 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN5_6 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_6 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 77 V 1.0, 2020-04 W11 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN6_6 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_6 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Y11 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN7_6 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_6 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output —O 3 Reserved EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 78 V 1.0, 2020-04 W12 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 79 V 1.0, 2020-04 Y12 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 —O 6 Reserved ASCLIN5_ASLSO O7 Slave select signal output Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 80 V 1.0, 2020-04 W13 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 81 V 1.0, 2020-04 Y13 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) IOM_PIN_7 GPIO pad input to FPC P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output —O 3 Reserved ASCLIN8_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 82 V 1.0, 2020-04 W14 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 83 V 1.0, 2020-04 Y14 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 84 V 1.0, 2020-04 W15 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output —O 3 Reserved ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core Y15 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 85 V 1.0, 2020-04 W16 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved ASCLIN1_ASCLK O4 Shift clock output —O 5 Reserved EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Y16 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN1_5 Mux input channel 1 of TIM module 2 ASCLIN1_ARXF Receive input EDSADC_SGNB Carrier sign signal input P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-14 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 86 V 1.0, 2020-04 Table 2-15 Analog Inputs Ball Symbol Ctrl. Buffer Type Function T10 AN0 I D / HighZ / VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A U10 AN1 I D / HighZ / VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A W9 AN2 I D / HighZ / VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A U9 AN3 I D / HighZ / VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A T9 AN4 I D / HighZ / VDDM Analog Input 4 EVADC_G0CH4 Analog input channel 4, group 0 Y9 AN5 I D / HighZ / VDDM Analog Input 5 EVADC_G0CH5 Analog input channel 5, group 0 T8 AN6 I D / HighZ / VDDM Analog Input 6 EVADC_G0CH6 Analog input channel 6, group 0 U8 AN7 I D / HighZ / VDDM Analog Input 7 EVADC_G0CH7 Analog input channel 7, group 0 W8 AN8 I D / HighZ / VDDM Analog Input 8 EVADC_G1CH0 Analog input channel 0, group 1 U7 AN9 I D / HighZ / VDDM Analog Input 9 EVADC_G1CH1 Analog input channel 1, group 1 Y8 AN10 I D / HighZ / VDDM Analog Input 10 EVADC_G1CH2 Analog input channel 2, group 1 W7 AN11 I D / HighZ / VDDM Analog Input 11 EVADC_G1CH3 Analog input channel 3, group 1 T7 AN12 I D / HighZ / VDDM Analog Input 12 EVADC_G1CH4 Analog input channel 4, group 1 EDSADC_EDS0PB Positive analog input channel 0, pin B W6 AN13 I D / HighZ / VDDM Analog Input 13 EVADC_G1CH5 Analog input channel 5, group 1 EDSADC_EDS0NB Negative analog input channel 0, pin B U6 AN14 I D / HighZ / VDDM Analog Input 14 EVADC_G1CH6 Analog input channel 6, group 1 EDSADC_EDS3PB Positive analog input channel 3, pin B OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 87 V 1.0, 2020-04 T6 AN15 I D / HighZ / VDDM Analog Input 15 EVADC_G1CH7 Analog input channel 7, group 1 EDSADC_EDS3NB Negative analog input channel 3, pin N W5 AN16 I D / HighZ / VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 U5 AN17 I D / HighZ / VDDM Analog Input 17 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 W4 AN18 I D / HighZ / VDDM Analog Input 18 EVADC_G2CH2 Analog input channel 2, group 2 W3 AN19 I D / HighZ / VDDM Analog Input 19 EVADC_G2CH3 Analog input channel 3, group 2 Y3 AN20 I D / HighZ / VDDM Analog Input 20 EVADC_G2CH4 Analog input channel 4, group 2 EDSADC_EDS2PA Positive analog input channel 2, pin A Y2 AN21 I D / HighZ / VDDM Analog Input 21 EVADC_G2CH5 Analog input channel 5, group 2 EDSADC_EDS2NA Negative analog input channel 2, pin A T5 AN22 I D / HighZ / VDDM Analog Input 22 EVADC_G2CH6 Analog input channel 6, group 2 R5 AN23 I D / HighZ / VDDM Analog Input 23 EVADC_G2CH7 Analog input channel 7, group 2 W2 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B W1 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B V2 AN26/P40.2 I S / HighZ / VDDM Analog Input 26 SENT_SENT2A Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 Table 2-15 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 88 V 1.0, 2020-04 V1 AN27/P40.3 I S / HighZ / VDDM Analog Input 27 SENT_SENT3A Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2 U2 AN28 I D / HighZ / VDDM Analog Input 28 EVADC_G3CH4 Analog input channel 4, group 3 U1 AN29 I D / HighZ / VDDM Analog Input 29 EVADC_G3CH5 Analog input channel 5, group 3 T4 AN30 I D / HighZ / VDDM Analog Input 30 EVADC_G3CH6 Analog input channel 6, group 3 R4 AN31 I D / HighZ / VDDM Analog Input 31 EVADC_G3CH7 Analog input channel 7, group 3 P4 AN32/P40.4 I S / HighZ / VDDM Analog Input 32 SENT_SENT4A Receive input channel 4 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 R1 AN33/P40.5 I S / HighZ / VDDM Analog Input 33 SENT_SENT5A Receive input channel 5 EVADC_G8CH1 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 P5 AN34 I D / HighZ / VDDM Analog Input 34 EVADC_G8CH2 Analog input channel 2, group 8 R2 AN35 I D / HighZ / VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 N4 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A P2 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A Table 2-15 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 89 V 1.0, 2020-04 N5 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B P1 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B M5 AN40 I D / HighZ / VDDM Analog Input 40 EVADC_G8CH8 Analog input channel 8, group 8 M4 AN41 I D / HighZ / VDDM Analog Input 41 EVADC_G8CH9 Analog input channel 9, group 8 L5 AN42 I D / HighZ / VDDM Analog Input 42 EVADC_G8CH10 Analog input channel 10, group 8 L4 AN43 I D / HighZ / VDDM Analog Input 43 EVADC_G8CH11 Analog input channel 11, group 8 N1 AN44 I D / HighZ / VDDM Analog Input 44 EVADC_G8CH12 Analog input channel 12, group 8 EDSADC_EDS1PC Positive analog input channel 1, pin C N2 AN45 I D / HighZ / VDDM Analog Input 45 EVADC_G8CH13 Analog input channel 13, group 8 EDSADC_EDS1NC Negative analog input channel 1, pin C M1 AN46 I D / HighZ / VDDM Analog Input 46 EVADC_G8CH14 Analog input channel 14, group 8 EDSADC_EDS1PD Positive analog input channel 1, pin D M2 AN47 I D / HighZ / VDDM Analog Input 47 EVADC_G8CH15 Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D Table 2-15 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 90 V 1.0, 2020-04 Table 2-16 System I/O Ball Symbol Ctrl. Buffer Type Function Y17 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC W17 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC M20 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. M19 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT K16 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O L19 TRST I FAST / PU2 / VEXT JTAG Module Reset/Enable Input J16 TCK I FAST / PD2 / VEXT JTAG Module Clock Input DAP0 I DAP: DAP0 Clock Input G16 ESR1 I/O FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input G17 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. F16 ESR0 I/O FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 91 V 1.0, 2020-04 Table 2-17 Supply Ball Symbol Ctrl. Buffer Type Function Y5 VDDM I — ADC Analog Power Supply (5V / 3.3V) D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) P8, P13, N7, N14, E15, H14, D16, G13, G8, H7 VDD I — Digital Core Power Supply (1.25V) A2, B3, V19, W20 VEXT I — External Power Supply (5V / 3.3V) B18, A19 VDDP3 I — Flash Power Supply (3.3V) B2, D4, E5, T16, U17, W19, Y20, E16, D17, B19, A20 VSS I — Digital Ground Y4 VSSM I — Analog Ground for VDDM P9, P12, N9, N10, N11, N12, M7, M8, M10, M11, M13, M14, L8, L9, L10, L11, L12, L13, K8, K9, K10, K11, K12, K13, J7, J8, J10, J11, J13, J14, H9, H10, H11, H12, G9, G10, G11, G12, L14, P10, P11, K7, L7 VSS I — Digital Ground L20 VSS I — Oscillator Ground Y6 VAREF1 I — Positive Analog Reference Voltage 1 Y7 VAGND1 I — Negative Analog Reference Voltage 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-292 Package Variant Pin Data Sheet 92 V 1.0, 2020-04 E4, F4, F5, G4, G5, H4, H5, J5, K14, L16, L17, M16, M17, N16, N17, P16, P17, R16, R17, T1, T2, T12, T13, T14, T15, U11, U12, U13, U14, U15, U16 NC I — Not connected. These pins are reserved for future extensions and shall not be connected externally A1, Y1, U4 NC1 I — Not connected. These pins are not connected on package level and will not be used for future extensions T11 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM N19 VDD I — Digital Power Supply for Oscillator (1.25V) N20 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT) Table 2-17 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 93 V 1.0, 2020-04

2.2 LFBGA-180 Packag e Variant Pin Configuration of TC36x

Table 2-18 Port 00 Functions Ball Symbol Ctrl. Buffer Type Function G4 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 94 V 1.0, 2020-04 H4 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI Analog input channel 11, group 9 P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 95 V 1.0, 2020-04 F3 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 96 V 1.0, 2020-04 F2 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI Analog input channel 9, group 9 P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 97 V 1.0, 2020-04 F1 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input EVADC_G9CH8 AI Analog input channel 8, group 9 P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 98 V 1.0, 2020-04 H3 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 G3 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 99 V 1.0, 2020-04 G2 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 G1 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 100 V 1.0, 2020-04 H2 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI Analog input channel 3, group 9 P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 101 V 1.0, 2020-04 H1 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input EVADC_G9CH0 AI Analog input channel 0, group 9 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-18 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 102 V 1.0, 2020-04 Table 2-19 Port 02 Functions Ball Symbol Ctrl. Buffer Type Function B1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 103 V 1.0, 2020-04 C1 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 —O 2 Reserved QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 104 V 1.0, 2020-04 C2 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 105 V 1.0, 2020-04 D3 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input PSI5_RX0B RXD inputs (receive data) channel 0 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 106 V 1.0, 2020-04 D2 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 107 V 1.0, 2020-04 D1 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 108 V 1.0, 2020-04 E1 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 109 V 1.0, 2020-04 E2 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 110 V 1.0, 2020-04 E3 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output —O 4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-19 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 111 V 1.0, 2020-04 Table 2-20 Port 10 Functions Ball Symbol Ctrl. Buffer Type Function C4 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_2 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_2 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B3 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 112 V 1.0, 2020-04 A3 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select —O 5 Reserved —O 6 Reserved —O 7 Reserved A2 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved Table 2-20 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 113 V 1.0, 2020-04 B4 P10.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_2 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_2 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 —O 2 Reserved QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved F4 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output —O 7 Reserved Table 2-20 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 114 V 1.0, 2020-04 E4 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 —O 5 Reserved QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved Table 2-21 Port 11 Functions Ball Symbol Ctrl. Buffer Type Function A6 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-20 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 115 V 1.0, 2020-04 B6 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 C6 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-21 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 116 V 1.0, 2020-04 D6 P11.8 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_8 Mux input channel 5 of TIM module 2 GETH_RXD2A Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN12_RXDD CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A5 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-21 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 117 V 1.0, 2020-04 B5 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 C5 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-21 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 118 V 1.0, 2020-04 A4 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-22 Port 13 Functions Ball Symbol Ctrl. Buffer Type Function A7 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 Table 2-21 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 119 V 1.0, 2020-04 B7 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved A8 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output —O 7 Reserved B8 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-22 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 120 V 1.0, 2020-04 Table 2-23 Port 14 Functions Ball Symbol Ctrl. Buffer Type Function A9 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 121 V 1.0, 2020-04 B10 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 D9 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-23 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 122 V 1.0, 2020-04 C11 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved C10 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-23 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 123 V 1.0, 2020-04 B9 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B —O 7 Reserved C9 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B —O 7 Reserved C7 P14.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_3 Mux input channel 2 of TIM module 2 ERAY0_RXDA0 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-23 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 124 V 1.0, 2020-04 C8 P14.10 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_3 Mux input channel 4 of TIM module 2 QSPI2_MRSTFP Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output —O 2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A —O 7 Reserved Table 2-24 Port 15 Functions Ball Symbol Ctrl. Buffer Type Function A13 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved Table 2-23 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 125 V 1.0, 2020-04 A12 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B12 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved Table 2-24 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 126 V 1.0, 2020-04 A10 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved B11 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-24 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 127 V 1.0, 2020-04 D10 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 A11 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-24 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 128 V 1.0, 2020-04 D8 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 D7 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-24 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 129 V 1.0, 2020-04 Table 2-25 Port 20 Functions Ball Symbol Ctrl. Buffer Type Function H13 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output G13 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 130 V 1.0, 2020-04 G12 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved F11 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-25 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 131 V 1.0, 2020-04 E12 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 F12 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-25 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 132 V 1.0, 2020-04 D12 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 C14 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-25 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 133 V 1.0, 2020-04 D14 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 D13 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-25 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 134 V 1.0, 2020-04 C13 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 B14 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-25 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 135 V 1.0, 2020-04 Table 2-26 Port 21 Functions Ball Symbol Ctrl. Buffer Type Function H12 P21.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_6 Mux input channel 4 of TIM module 2 ASCLIN11_ARXC Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM1 O Pin Output Value K13 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 136 V 1.0, 2020-04 J14 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output J13 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data Table 2-26 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 137 V 1.0, 2020-04 H14 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data F13 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-26 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 138 V 1.0, 2020-04 F14 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-26 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 139 V 1.0, 2020-04 Table 2-27 Port 22 Functions Ball Symbol Ctrl. Buffer Type Function J11 P22.0 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 ASCLIN6_ARXE Receive input QSPI3_MTSRD Slave SPI data input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN6_ATX O7 Transmit output L12 P22.1 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 ASCLIN7_ARXE Receive input QSPI3_MRSTD Master SPI data input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN7_ATX O7 Transmit output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 140 V 1.0, 2020-04 H11 P22.2 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI3_SLSO12 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved J12 P22.3 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 ASCLIN5_ARXC Receive input QSPI3_SCLKD Slave SPI clock inputs P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-27 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 141 V 1.0, 2020-04 Table 2-28 Port 23 Functions Ball Symbol Ctrl. Buffer Type Function N14 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output —O 3 Reserved GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output K11 P23.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_4 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_4 Mux input channel 7 of TIM module 0 ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 142 V 1.0, 2020-04 Table 2-29 Port 32 Functions Ball Symbol Ctrl. Buffer Type Function P12 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved N12 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved P13 P32.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_5 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_5 Mux input channel 5 of TIM module 0 ASCLIN1_ACTSB Clear to send input P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output —O 2 Reserved —O 3 Reserved GTM_CLK1 O4 CGM generated clock —O 5 Reserved CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO O DC-DC synchronization output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 143 V 1.0, 2020-04 Table 2-30 Port 33 Functions Ball Symbol Ctrl. Buffer Type Function M9 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN4_6 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_6 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved M8 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN5_6 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_6 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 144 V 1.0, 2020-04 P8 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN6_6 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_6 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved N8 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN7_6 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_6 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output —O 3 Reserved EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 145 V 1.0, 2020-04 L8 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 146 V 1.0, 2020-04 N9 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 —O 6 Reserved ASCLIN5_ASLSO O7 Slave select signal output Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 147 V 1.0, 2020-04 P9 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 148 V 1.0, 2020-04 L10 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) IOM_PIN_7 GPIO pad input to FPC P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output —O 3 Reserved ASCLIN8_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 149 V 1.0, 2020-04 L9 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 150 V 1.0, 2020-04 P10 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 151 V 1.0, 2020-04 N11 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output —O 3 Reserved ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core N10 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 152 V 1.0, 2020-04 M10 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved ASCLIN1_ASCLK O4 Shift clock output —O 5 Reserved EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 M11 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN1_5 Mux input channel 1 of TIM module 2 ASCLIN1_ARXF Receive input EDSADC_SGNB Carrier sign signal input P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-30 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 153 V 1.0, 2020-04 Table 2-31 Analog Inputs Ball Symbol Ctrl. Buffer Type Function L7 AN0 I D / HighZ / VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A P6 AN1 I D / HighZ / VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A L6 AN2 I D / HighZ / VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A M6 AN3 I D / HighZ / VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A N6 AN4 I D / HighZ / VDDM Analog Input 4 EVADC_G0CH4 Analog input channel 4, group 0 L5 AN5 I D / HighZ / VDDM Analog Input 5 EVADC_G0CH5 Analog input channel 5, group 0 M5 AN6 I D / HighZ / VDDM Analog Input 6 EVADC_G0CH6 Analog input channel 6, group 0 P5 AN7 I D / HighZ / VDDM Analog Input 7 EVADC_G0CH7 Analog input channel 7, group 0 N5 AN8 I D / HighZ / VDDM Analog Input 8 EVADC_G1CH0 Analog input channel 0, group 1 N3 AN9 I D / HighZ / VDDM Analog Input 9 EVADC_G1CH1 Analog input channel 1, group 1 M4 AN10 I D / HighZ / VDDM Analog Input 10 EVADC_G1CH2 Analog input channel 2, group 1 N4 AN11 I D / HighZ / VDDM Analog Input 11 EVADC_G1CH3 Analog input channel 3, group 1 M3 AN12 I D / HighZ / VDDM Analog Input 12 EVADC_G1CH4 Analog input channel 4, group 1 EDSADC_EDS0PB Positive analog input channel 0, pin B N2 AN13 I D / HighZ / VDDM Analog Input 13 EVADC_G1CH5 Analog input channel 5, group 1 EDSADC_EDS0NB Negative analog input channel 0, pin B L4 AN14 I D / HighZ / VDDM Analog Input 14 EVADC_G1CH6 Analog input channel 6, group 1 EDSADC_EDS3PB Positive analog input channel 3, pin B OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 154 V 1.0, 2020-04 N1 AN15 I D / HighZ / VDDM Analog Input 15 EVADC_G1CH7 Analog input channel 7, group 1 EDSADC_EDS3NB Negative analog input channel 3, pin N M1 AN16 I D / HighZ / VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 M2 AN17 I D / HighZ / VDDM Analog Input 17 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 L1 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B L2 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B K1 AN32/P40.4 I S / HighZ / VDDM Analog Input 32 SENT_SENT4A Receive input channel 4 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 K2 AN33/P40.5 I S / HighZ / VDDM Analog Input 33 SENT_SENT5A Receive input channel 5 EVADC_G8CH1 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 K3 AN34 I D / HighZ / VDDM Analog Input 34 EVADC_G8CH2 Analog input channel 2, group 8 K4 AN35 I D / HighZ / VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 J1 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A Table 2-31 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 155 V 1.0, 2020-04 J2 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A J3 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B J4 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B Table 2-32 System I/O Ball Symbol Ctrl. Buffer Type Function P12 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC N12 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC L14 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. L13 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT G11 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O K12 TRST I FAST / PU2 / VEXT JTAG Module Reset/Enable Input G14 TCK I FAST / PD2 / VEXT JTAG Module Clock Input DAP0 I DAP: DAP0 Clock Input Table 2-31 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 156 V 1.0, 2020-04 E11 ESR1 I/O FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input E13 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. E14 ESR0 I/O FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input Table 2-33 Supply Ball Symbol Ctrl. Buffer Type Function P3 VDDM I — ADC Analog Power Supply (5V / 3.3V) D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) F9, G9, H6, J7, J8 VDD I — Digital Core Power Supply (1.25V) F6, F8, G6, J9, P11 VEXT I — External Power Supply (5V / 3.3V) F7 VDDP3 I — Flash Power Supply (3.3V) B2, C3, D4, E5, K10, L11, M12, N13 VSS I — Digital Ground B13, C12, D11, E10, G7, G8, H7, H8, J6, K5 VSS I — Digital Ground K14 VSS I — Oscillator Ground P4 VAREF1 I — Positive Analog Reference Voltage 1 Table 2-32 System I/O (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LFBGA-180 Package Variant Pin Data Sheet 157 V 1.0, 2020-04 A1, A14, L3, M7, N7, P1, P7, P14 NC I — Not connected. These pins are reserved for future extensions and shall not be connected externally H9 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM M13 VDD I — Digital Power Supply for Oscillator (1.25V) M14 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT) P2 VSSM/VAGND1 I — Analog Ground for VDDM / Negative Analog Reference Voltage 1 Table 2-33 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 158 V 1.0, 2020-04

2.3 LQFP-176 Package Variant Pin Configuration of TC36x

Table 2-34 Port 00 Functions Pin Symbol Ctrl. Buffer Type Function 11 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 159 V 1.0, 2020-04 12 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI Analog input channel 11, group 9 P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 160 V 1.0, 2020-04 13 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 161 V 1.0, 2020-04 14 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI Analog input channel 9, group 9 P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 162 V 1.0, 2020-04 15 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input EVADC_G9CH8 AI Analog input channel 8, group 9 P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 163 V 1.0, 2020-04 16 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 17 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 164 V 1.0, 2020-04 18 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 19 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 165 V 1.0, 2020-04 20 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI Analog input channel 3, group 9 P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 21 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN1_1 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 166 V 1.0, 2020-04 22 P00.11 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN2_1 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 EVADC_G9CH1 AI Analog input channel 1, group 9 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT0 O4 Modulator clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved 23 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input EVADC_G9CH0 AI Analog input channel 0, group 9 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-34 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 167 V 1.0, 2020-04 Table 2-35 Port 02 Functions Pin Symbol Ctrl. Buffer Type Function 1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 168 V 1.0, 2020-04 2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 —O 2 Reserved QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 169 V 1.0, 2020-04 3 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 170 V 1.0, 2020-04 4 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input PSI5_RX0B RXD inputs (receive data) channel 0 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 171 V 1.0, 2020-04 5 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 172 V 1.0, 2020-04 6 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 173 V 1.0, 2020-04 7 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 174 V 1.0, 2020-04 8 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 175 V 1.0, 2020-04 9 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output —O 4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-35 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 176 V 1.0, 2020-04 Table 2-36 Port 10 Functions Pin Symbol Ctrl. Buffer Type Function 168 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_2 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_2 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 169 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 177 V 1.0, 2020-04 170 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select —O 5 Reserved —O 6 Reserved —O 7 Reserved 171 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved Table 2-36 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 178 V 1.0, 2020-04 172 P10.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_2 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_2 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 —O 2 Reserved QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved 173 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output —O 7 Reserved Table 2-36 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 179 V 1.0, 2020-04 174 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 —O 5 Reserved QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved 175 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_3 Mux input channel 0 of TIM module 0 GPT120_T3EUDB Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 —O 2 Reserved QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved CAN12_TXD O6 CAN transmit output node 2 —O 7 Reserved Table 2-36 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 180 V 1.0, 2020-04 176 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_2 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_2 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-37 Port 11 Functions Pin Symbol Ctrl. Buffer Type Function 160 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-36 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 181 V 1.0, 2020-04 161 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 162 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-37 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 182 V 1.0, 2020-04 163 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 165 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-37 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 183 V 1.0, 2020-04 166 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 167 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-37 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 184 V 1.0, 2020-04 Table 2-38 Port 13 Functions Pin Symbol Ctrl. Buffer Type Function 156 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 157 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved 158 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 185 V 1.0, 2020-04 159 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-39 Port 14 Functions Pin Symbol Ctrl. Buffer Type Function 142 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-38 Port 13 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 186 V 1.0, 2020-04 143 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 144 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-39 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 187 V 1.0, 2020-04 145 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved 146 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-39 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 188 V 1.0, 2020-04 147 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B —O 7 Reserved 148 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B —O 7 Reserved Table 2-39 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 189 V 1.0, 2020-04 149 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_5 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_5 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved 150 P14.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_3 Mux input channel 2 of TIM module 2 ERAY0_RXDA0 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-39 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 190 V 1.0, 2020-04 151 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_3 Mux input channel 3 of TIM module 2 ASCLIN0_ACTSA Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output —O 2 Reserved MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A —O 7 Reserved 152 P14.10 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_3 Mux input channel 4 of TIM module 2 QSPI2_MRSTFP Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output —O 2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A —O 7 Reserved Table 2-39 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 191 V 1.0, 2020-04 Table 2-40 Port 15 Functions Pin Symbol Ctrl. Buffer Type Function 133 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved 134 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 192 V 1.0, 2020-04 135 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved 136 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-40 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 193 V 1.0, 2020-04 137 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-40 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 194 V 1.0, 2020-04 138 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 139 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-40 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 195 V 1.0, 2020-04 140 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 141 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-40 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 196 V 1.0, 2020-04 Table 2-41 Port 20 Functions Pin Symbol Ctrl. Buffer Type Function 116 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output 117 P20.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_5 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved CBS_TGO1 O Trigger output 118 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 197 V 1.0, 2020-04 119 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved 124 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-41 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 198 V 1.0, 2020-04 125 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 126 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-41 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 199 V 1.0, 2020-04 127 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 128 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-41 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 200 V 1.0, 2020-04 129 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 130 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-41 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 201 V 1.0, 2020-04 131 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 132 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-41 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 202 V 1.0, 2020-04 Table 2-42 Port 21 Functions Pin Symbol Ctrl. Buffer Type Function 105 P21.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_6 Mux input channel 4 of TIM module 2 ASCLIN11_ARXC Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM1 O Pin Output Value 106 P21.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_6 Mux input channel 5 of TIM module 2 ASCLIN11_ARXD Receive input P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM2 O Pin Output Value OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 203 V 1.0, 2020-04 107 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved 108 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output Table 2-42 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 204 V 1.0, 2020-04 109 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data 110 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data Table 2-42 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 205 V 1.0, 2020-04 111 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-42 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 206 V 1.0, 2020-04 113 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-42 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 207 V 1.0, 2020-04 Table 2-43 Port 22 Functions Pin Symbol Ctrl. Buffer Type Function 95 P22.0 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 ASCLIN6_ARXE Receive input QSPI3_MTSRD Slave SPI data input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN6_ATX O7 Transmit output 96 P22.1 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 ASCLIN7_ARXE Receive input QSPI3_MRSTD Master SPI data input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN7_ATX O7 Transmit output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 208 V 1.0, 2020-04 97 P22.2 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI3_SLSO12 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 98 P22.3 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 ASCLIN5_ARXC Receive input QSPI3_SCLKD Slave SPI clock inputs P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-43 Port 22 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 209 V 1.0, 2020-04 Table 2-44 Port 23 Functions Pin Symbol Ctrl. Buffer Type Function 89 P23.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_4 Mux input channel 5 of TIM module 0 CAN10_RXDC CAN receive input node 0 P23.0 O0 General-purpose output GTM_TOUT41 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 90 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output —O 3 Reserved GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output 91 P23.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_5 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_5 Mux input channel 6 of TIM module 0 ASCLIN7_ARXC Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 210 V 1.0, 2020-04 92 P23.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_4 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_4 Mux input channel 7 of TIM module 0 ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 93 P23.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_5 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_5 Mux input channel 7 of TIM module 0 P23.4 O0 General-purpose output GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 94 P23.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_7 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_7 Mux input channel 2 of TIM module 0 P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-44 Port 23 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 211 V 1.0, 2020-04 Table 2-45 Port 32 Functions Pin Symbol Ctrl. Buffer Type Function 84 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 85 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 86 P32.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_8 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_8 Mux input channel 3 of TIM module 0 CAN03_RXDB CAN receive input node 3 ASCLIN3_ARXD Receive input P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 212 V 1.0, 2020-04 87 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_5 Mux input channel 4 of TIM module 0 P32.3 O0 General-purpose output GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved 88 P32.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_5 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_5 Mux input channel 5 of TIM module 0 ASCLIN1_ACTSB Clear to send input P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output —O 2 Reserved —O 3 Reserved GTM_CLK1 O4 CGM generated clock —O 5 Reserved CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO O DC-DC synchronization output Table 2-45 Port 32 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 213 V 1.0, 2020-04 Table 2-46 Port 33 Functions Pin Symbol Ctrl. Buffer Type Function 70 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN4_6 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_6 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 71 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN5_6 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_6 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 214 V 1.0, 2020-04 72 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN6_6 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_6 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved 73 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN7_6 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_6 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output —O 3 Reserved EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 215 V 1.0, 2020-04 74 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 216 V 1.0, 2020-04 75 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 —O 6 Reserved ASCLIN5_ASLSO O7 Slave select signal output Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 217 V 1.0, 2020-04 76 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 218 V 1.0, 2020-04 77 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) IOM_PIN_7 GPIO pad input to FPC P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output —O 3 Reserved ASCLIN8_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 219 V 1.0, 2020-04 78 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 220 V 1.0, 2020-04 79 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 221 V 1.0, 2020-04 80 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output —O 3 Reserved ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core 81 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 222 V 1.0, 2020-04 82 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved ASCLIN1_ASCLK O4 Shift clock output —O 5 Reserved EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 83 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN1_5 Mux input channel 1 of TIM module 2 ASCLIN1_ARXF Receive input EDSADC_SGNB Carrier sign signal input P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 223 V 1.0, 2020-04 Table 2-47 Analog Inputs Pin Symbol Ctrl. Buffer Type Function

67 AN0 I D / HighZ

/ VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A

66 AN1 I D / HighZ

/ VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A

65 AN2 I D / HighZ

/ VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A

64 AN3 I D / HighZ

/ VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A

63 AN4 I D / HighZ

/ VDDM Analog Input 4 EVADC_G0CH4 Analog input channel 4, group 0

62 AN5 I D / HighZ

/ VDDM Analog Input 5 EVADC_G0CH5 Analog input channel 5, group 0

61 AN6 I D / HighZ

/ VDDM Analog Input 6 EVADC_G0CH6 Analog input channel 6, group 0

60 AN7 I D / HighZ

/ VDDM Analog Input 7 EVADC_G0CH7 Analog input channel 7, group 0

59 AN8 I D / HighZ

/ VDDM Analog Input 8 EVADC_G1CH0 Analog input channel 0, group 1

58 AN10 I D / HighZ

/ VDDM Analog Input 10 EVADC_G1CH2 Analog input channel 2, group 1

57 AN11 I D / HighZ

/ VDDM Analog Input 11 EVADC_G1CH3 Analog input channel 3, group 1

56 AN12 I D / HighZ

/ VDDM Analog Input 12 EVADC_G1CH4 Analog input channel 4, group 1 EDSADC_EDS0PB Positive analog input channel 0, pin B

55 AN13 I D / HighZ

/ VDDM Analog Input 13 EVADC_G1CH5 Analog input channel 5, group 1 EDSADC_EDS0NB Negative analog input channel 0, pin B

50 AN16 I D / HighZ

/ VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 224 V 1.0, 2020-04

49 AN17 I D / HighZ

/ VDDM Analog Input 17 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1

48 AN18 I D / HighZ

/ VDDM Analog Input 18 EVADC_G2CH2 Analog input channel 2, group 2

47 AN19 I D / HighZ

/ VDDM Analog Input 19 EVADC_G2CH3 Analog input channel 3, group 2

46 AN20 I D / HighZ

/ VDDM Analog Input 20 EVADC_G2CH4 Analog input channel 4, group 2 EDSADC_EDS2PA Positive analog input channel 2, pin A

45 AN21 I D / HighZ

/ VDDM Analog Input 21 EVADC_G2CH5 Analog input channel 5, group 2 EDSADC_EDS2NA Negative analog input channel 2, pin A 44 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B 43 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B 42 AN26/P40.2 I S / HighZ / VDDM Analog Input 26 SENT_SENT2A Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 41 AN27/P40.3 I S / HighZ / VDDM Analog Input 27 SENT_SENT3A Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2

40 AN28 I D / HighZ

/ VDDM Analog Input 28 EVADC_G3CH4 Analog input channel 4, group 3

39 AN29 I D / HighZ

/ VDDM Analog Input 29 EVADC_G3CH5 Analog input channel 5, group 3 Table 2-47 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 225 V 1.0, 2020-04 38 AN32/P40.4 I S / HighZ / VDDM Analog Input 32 SENT_SENT4A Receive input channel 4 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 37 AN33/P40.5 I S / HighZ / VDDM Analog Input 33 SENT_SENT5A Receive input channel 5 EVADC_G8CH1 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0

36 AN35 I D / HighZ

/ VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 35 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A 34 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A 33 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B 32 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B

27 AN42 I D / HighZ

/ VDDM Analog Input 42 EVADC_G8CH10 Analog input channel 10, group 8

26 AN43 I D / HighZ

/ VDDM Analog Input 43 EVADC_G8CH11 Analog input channel 11, group 8

31 AN44 I D / HighZ

/ VDDM Analog Input 44 EVADC_G8CH12 Analog input channel 12, group 8 EDSADC_EDS1PC Positive analog input channel 1, pin C Table 2-47 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 226 V 1.0, 2020-04

30 AN45 I D / HighZ

/ VDDM Analog Input 45 EVADC_G8CH13 Analog input channel 13, group 8 EDSADC_EDS1NC Negative analog input channel 1, pin C

29 AN46 I D / HighZ

/ VDDM Analog Input 46 EVADC_G8CH14 Analog input channel 14, group 8 EDSADC_EDS1PD Positive analog input channel 1, pin D

28 AN47 I D / HighZ

/ VDDM Analog Input 47 EVADC_G8CH15 Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D Table 2-48 System I/O Pin Symbol Ctrl. Buffer Type Function 84 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC 85 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC

102 XTAL1 I XTAL /

XTAL1. Main Oscillator/PLL/Clock Generator Input.

103 XTAL2 O XTAL /

XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT

112 TMS I FAST /

JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O

114 TRST I FAST /

JTAG Module Reset/Enable Input

115 TCK I FAST /

DAP0 I DAP: DAP0 Clock Input

120 ESR1 I/O FAST /

ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input

121 PORST I/O PORST /

Power On Reset Input. Additional strong PD in case of power fail. Table 2-47 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-176 Package Variant Pin Data Sheet 227 V 1.0, 2020-04

122 ESR0 I/O FAST /

ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input Table 2-49 Supply Pin Symbol Ctrl. Buffer Type Function 54 VDDM I — ADC Analog Power Supply (5V / 3.3V) 164 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) 154 VDDP3 I — Flash Power Supply (3.3V)

52 VAREF1 I — Positive Analog Reference Voltage 1

69 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM 155 VDD I — Digital Core Power Supply (1.25V) 10 VDD I — Digital Core Power Supply (1.25V) 24 VDD I — Digital Core Power Supply (1.25V) 68 VDD I — Digital Core Power Supply (1.25V) 100 VDD I — Digital Core Power Supply (1.25V) 123 VDD I — Digital Core Power Supply (1.25V) 153 VEXT I — External Power Supply (5V / 3.3V) 25 VEXT I — External Power Supply (5V / 3.3V) 99 VEXT I — External Power Supply (5V / 3.3V) E-PAD VSS I — Digital Ground (Exposed PAD), VSS

53 VSSM I — Analog Ground for VDDM

51 VAGND1 I — Negative Analog Reference Voltage 1

101 VSS I — Oscillator Ground, VSS(OSC)

104 VEXT I — Digital Power Supply for Oscillator (shall be supplied

with same level as used for VEXT), VEXT(OSC) Table 2-48 System I/O (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 228 V 1.0, 2020-04

2.4 LQFP-144 Package Variant Pin Configuration of TC36x

Table 2-50 Port 00 Functions Pin Symbol Ctrl. Buffer Type Function 11 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 229 V 1.0, 2020-04 12 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI Analog input channel 11, group 9 P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 230 V 1.0, 2020-04 13 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 231 V 1.0, 2020-04 14 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI Analog input channel 9, group 9 P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 232 V 1.0, 2020-04 15 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input EVADC_G9CH8 AI Analog input channel 8, group 9 P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 233 V 1.0, 2020-04 16 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 17 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 234 V 1.0, 2020-04 18 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 19 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 235 V 1.0, 2020-04 20 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI Analog input channel 3, group 9 P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 236 V 1.0, 2020-04 21 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input EVADC_G9CH0 AI Analog input channel 0, group 9 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-50 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 237 V 1.0, 2020-04 Table 2-51 Port 02 Functions Pin Symbol Ctrl. Buffer Type Function 1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 238 V 1.0, 2020-04 2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 —O 2 Reserved QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 239 V 1.0, 2020-04 3 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 240 V 1.0, 2020-04 4 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input PSI5_RX0B RXD inputs (receive data) channel 0 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 241 V 1.0, 2020-04 5 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 242 V 1.0, 2020-04 6 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 243 V 1.0, 2020-04 7 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 244 V 1.0, 2020-04 8 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 245 V 1.0, 2020-04 9 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output —O 4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-51 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 246 V 1.0, 2020-04 Table 2-52 Port 10 Functions Pin Symbol Ctrl. Buffer Type Function 140 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved 141 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 247 V 1.0, 2020-04 142 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved 143 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output —O 7 Reserved Table 2-52 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 248 V 1.0, 2020-04 144 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 —O 5 Reserved QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved Table 2-53 Port 11 Functions Pin Symbol Ctrl. Buffer Type Function 132 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-52 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 249 V 1.0, 2020-04 133 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 134 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-53 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 250 V 1.0, 2020-04 135 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 137 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-53 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 251 V 1.0, 2020-04 138 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 139 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-53 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 252 V 1.0, 2020-04 Table 2-54 Port 13 Functions Pin Symbol Ctrl. Buffer Type Function 128 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 129 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved 130 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 253 V 1.0, 2020-04 131 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-55 Port 14 Functions Pin Symbol Ctrl. Buffer Type Function 118 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-54 Port 13 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 254 V 1.0, 2020-04 119 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 120 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-55 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 255 V 1.0, 2020-04 121 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved 122 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-55 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 256 V 1.0, 2020-04 123 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B —O 7 Reserved 124 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B —O 7 Reserved Table 2-55 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 257 V 1.0, 2020-04 Table 2-56 Port 15 Functions Pin Symbol Ctrl. Buffer Type Function 109 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved 110 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 258 V 1.0, 2020-04 111 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved 112 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-56 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 259 V 1.0, 2020-04 113 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-56 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 260 V 1.0, 2020-04 114 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 115 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-56 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 261 V 1.0, 2020-04 116 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 117 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-56 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 262 V 1.0, 2020-04 Table 2-57 Port 20 Functions Pin Symbol Ctrl. Buffer Type Function 93 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output 94 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 263 V 1.0, 2020-04 95 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved 100 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-57 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 264 V 1.0, 2020-04 101 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 102 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-57 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 265 V 1.0, 2020-04 103 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 104 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-57 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 266 V 1.0, 2020-04 105 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 106 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-57 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 267 V 1.0, 2020-04 107 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 108 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-57 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 268 V 1.0, 2020-04 Table 2-58 Port 21 Functions Pin Symbol Ctrl. Buffer Type Function 84 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved 85 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 269 V 1.0, 2020-04 86 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data 87 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data Table 2-58 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 270 V 1.0, 2020-04 88 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-58 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 271 V 1.0, 2020-04 90 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-58 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 272 V 1.0, 2020-04 Table 2-59 Port 22 Functions Pin Symbol Ctrl. Buffer Type Function 74 P22.0 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 ASCLIN6_ARXE Receive input QSPI3_MTSRD Slave SPI data input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN6_ATX O7 Transmit output 75 P22.1 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 ASCLIN7_ARXE Receive input QSPI3_MRSTD Master SPI data input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN7_ATX O7 Transmit output OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 273 V 1.0, 2020-04 76 P22.2 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI3_SLSO12 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 77 P22.3 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 ASCLIN5_ARXC Receive input QSPI3_SCLKD Slave SPI clock inputs P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-59 Port 22 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 274 V 1.0, 2020-04 Table 2-60 Port 23 Functions Pin Symbol Ctrl. Buffer Type Function 73 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output —O 3 Reserved GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output Table 2-61 Port 32 Functions Pin Symbol Ctrl. Buffer Type Function 70 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 71 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 275 V 1.0, 2020-04 72 P32.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_5 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_5 Mux input channel 5 of TIM module 0 ASCLIN1_ACTSB Clear to send input P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output —O 2 Reserved —O 3 Reserved GTM_CLK1 O4 CGM generated clock —O 5 Reserved CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 PMS_DCDCSYNCO O DC-DC synchronization output Table 2-61 Port 32 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 276 V 1.0, 2020-04 Table 2-62 Port 33 Functions Pin Symbol Ctrl. Buffer Type Function 60 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 277 V 1.0, 2020-04 61 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 —O 6 Reserved ASCLIN5_ASLSO O7 Slave select signal output Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 278 V 1.0, 2020-04 62 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 279 V 1.0, 2020-04 63 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) IOM_PIN_7 GPIO pad input to FPC P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output —O 3 Reserved ASCLIN8_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 280 V 1.0, 2020-04 64 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 281 V 1.0, 2020-04 65 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 282 V 1.0, 2020-04 66 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output —O 3 Reserved ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core 67 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 283 V 1.0, 2020-04 68 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved ASCLIN1_ASCLK O4 Shift clock output —O 5 Reserved EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 69 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN1_5 Mux input channel 1 of TIM module 2 ASCLIN1_ARXF Receive input EDSADC_SGNB Carrier sign signal input P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-62 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 284 V 1.0, 2020-04 Table 2-63 Analog Inputs Pin Symbol Ctrl. Buffer Type Function

57 AN0 I D / HighZ

/ VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A

56 AN1 I D / HighZ

/ VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A

55 AN2 I D / HighZ

/ VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A

54 AN3 I D / HighZ

/ VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A

53 AN4 I D / HighZ

/ VDDM Analog Input 4 EVADC_G0CH4 Analog input channel 4, group 0

52 AN5 I D / HighZ

/ VDDM Analog Input 5 EVADC_G0CH5 Analog input channel 5, group 0

51 AN6 I D / HighZ

/ VDDM Analog Input 6 EVADC_G0CH6 Analog input channel 6, group 0

50 AN7 I D / HighZ

/ VDDM Analog Input 7 EVADC_G0CH7 Analog input channel 7, group 0

49 AN8 I D / HighZ

/ VDDM Analog Input 8 EVADC_G1CH0 Analog input channel 0, group 1

48 AN10 I D / HighZ

/ VDDM Analog Input 10 EVADC_G1CH2 Analog input channel 2, group 1

47 AN11 I D / HighZ

/ VDDM Analog Input 11 EVADC_G1CH3 Analog input channel 3, group 1

46 AN12 I D / HighZ

/ VDDM Analog Input 12 EVADC_G1CH4 Analog input channel 4, group 1 EDSADC_EDS0PB Positive analog input channel 0, pin B

45 AN13 I D / HighZ

/ VDDM Analog Input 13 EVADC_G1CH5 Analog input channel 5, group 1 EDSADC_EDS0NB Negative analog input channel 0, pin B

40 AN16 I D / HighZ

/ VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 285 V 1.0, 2020-04

39 AN17 I D / HighZ

/ VDDM Analog Input 17 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1

38 AN20 I D / HighZ

/ VDDM Analog Input 20 EVADC_G2CH4 Analog input channel 4, group 2 EDSADC_EDS2PA Positive analog input channel 2, pin A

37 AN21 I D / HighZ

/ VDDM Analog Input 21 EVADC_G2CH5 Analog input channel 5, group 2 EDSADC_EDS2NA Negative analog input channel 2, pin A 36 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B 35 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B

34 AN35 I D / HighZ

/ VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 33 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A 32 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A 31 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B Table 2-63 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 286 V 1.0, 2020-04 30 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B

25 AN42 I D / HighZ

/ VDDM Analog Input 42 EVADC_G8CH10 Analog input channel 10, group 8

24 AN43 I D / HighZ

/ VDDM Analog Input 43 EVADC_G8CH11 Analog input channel 11, group 8

29 AN44 I D / HighZ

/ VDDM Analog Input 44 EVADC_G8CH12 Analog input channel 12, group 8 EDSADC_EDS1PC Positive analog input channel 1, pin C

28 AN45 I D / HighZ

/ VDDM Analog Input 45 EVADC_G8CH13 Analog input channel 13, group 8 EDSADC_EDS1NC Negative analog input channel 1, pin C

27 AN46 I D / HighZ

/ VDDM Analog Input 46 EVADC_G8CH14 Analog input channel 14, group 8 EDSADC_EDS1PD Positive analog input channel 1, pin D

26 AN47 I D / HighZ

/ VDDM Analog Input 47 EVADC_G8CH15 Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D Table 2-64 System I/O Pin Symbol Ctrl. Buffer Type Function 70 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC 71 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC

81 XTAL1 I XTAL /

XTAL1. Main Oscillator/PLL/Clock Generator Input.

82 XTAL2 O XTAL /

XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT

89 TMS I FAST /

JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O

91 TRST I FAST /

JTAG Module Reset/Enable Input Table 2-63 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 287 V 1.0, 2020-04

92 TCK I FAST /

DAP0 I DAP: DAP0 Clock Input

96 ESR1 I/O FAST /

ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input

97 PORST I/O PORST /

Power On Reset Input. Additional strong PD in case of power fail.

98 ESR0 I/O FAST /

ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input Table 2-65 Supply Pin Symbol Ctrl. Buffer Type Function 44 VDDM I — ADC Analog Power Supply (5V / 3.3V) 136 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) 126 VDDP3 I — Flash Power Supply (3.3V)

42 VAREF1 I — Positive Analog Reference Voltage 1

59 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM 10 VDD I — Digital Core Power Supply (1.25V) 125 VEXT I — External Power Supply (5V / 3.3V) 23 VEXT I — External Power Supply (5V / 3.3V) 78 VEXT I — External Power Supply (5V / 3.3V) 127 VDD I — Digital Core Power Supply (1.25V) 22 VDD I — Digital Core Power Supply (1.25V) 58 VDD I — Digital Core Power Supply (1.25V) Table 2-64 System I/O (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:LQFP-144 Package Variant Pin Data Sheet 288 V 1.0, 2020-04 79 VDD I — Digital Core Power Supply (1.25V) 99 VDD I — Digital Core Power Supply (1.25V) E-PAD VSS I — Digital Ground (Exposed PAD), VSS

43 VSSM I — Analog Ground for VDDM

41 VAGND1 I — Negative Analog Reference Voltage 1

80 VSS I — Oscillator Ground, VSS(OSC)

83 VEXT I — Digital Power Supply for Oscillator (shall be supplied

with same level as used for VEXT), VEXT(OSC) Table 2-65 Supply (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 289 V 1.0, 2020-04

2.5 TQFP-144 Package Variant Pin Configuration of TC36x

Table 2-66 Port 00 Functions Pin Symbol Ctrl. Buffer Type Function 11 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 290 V 1.0, 2020-04 12 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EVADC_G9CH11 AI Analog input channel 11, group 9 P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 291 V 1.0, 2020-04 13 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 292 V 1.0, 2020-04 14 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 EVADC_G9CH9 AI Analog input channel 9, group 9 P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 293 V 1.0, 2020-04 15 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input EVADC_G9CH8 AI Analog input channel 8, group 9 P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 294 V 1.0, 2020-04 16 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 17 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 295 V 1.0, 2020-04 18 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 19 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 296 V 1.0, 2020-04 20 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 EVADC_G9CH3 AI Analog input channel 3, group 9 P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 297 V 1.0, 2020-04 21 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input EVADC_G9CH0 AI Analog input channel 0, group 9 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-66 Port 00 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 298 V 1.0, 2020-04 Table 2-67 Port 02 Functions Pin Symbol Ctrl. Buffer Type Function 1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 299 V 1.0, 2020-04 2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 —O 2 Reserved QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 300 V 1.0, 2020-04 3 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 301 V 1.0, 2020-04 4 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input PSI5_RX0B RXD inputs (receive data) channel 0 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 302 V 1.0, 2020-04 5 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 303 V 1.0, 2020-04 6 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 304 V 1.0, 2020-04 7 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 305 V 1.0, 2020-04 8 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 GPT120_T3EUDA Count direction control input of core timer T3 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 306 V 1.0, 2020-04 9 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output —O 4 Reserved EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-67 Port 02 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 307 V 1.0, 2020-04 Table 2-68 Port 10 Functions Pin Symbol Ctrl. Buffer Type Function 140 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved 141 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 308 V 1.0, 2020-04 142 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved 143 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input MSC0_INJ1 Injection signal from port P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output —O 7 Reserved Table 2-68 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 309 V 1.0, 2020-04 144 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 —O 5 Reserved QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved Table 2-69 Port 11 Functions Pin Symbol Ctrl. Buffer Type Function 132 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-68 Port 10 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 310 V 1.0, 2020-04 133 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 134 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-69 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 311 V 1.0, 2020-04 136 P11.8 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_8 Mux input channel 5 of TIM module 2 GETH_RXD2A Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN12_RXDD CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 135 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-69 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 312 V 1.0, 2020-04 137 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 138 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-69 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 313 V 1.0, 2020-04 139 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-70 Port 13 Functions Pin Symbol Ctrl. Buffer Type Function 128 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 Table 2-69 Port 11 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 314 V 1.0, 2020-04 129 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved 130 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output —O 7 Reserved 131 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-70 Port 13 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 315 V 1.0, 2020-04 Table 2-71 Port 14 Functions Pin Symbol Ctrl. Buffer Type Function 118 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 316 V 1.0, 2020-04 119 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 120 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-71 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 317 V 1.0, 2020-04 121 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved 122 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-71 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 318 V 1.0, 2020-04 123 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B —O 7 Reserved 124 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B —O 7 Reserved Table 2-71 Port 14 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 319 V 1.0, 2020-04 Table 2-72 Port 15 Functions Pin Symbol Ctrl. Buffer Type Function 109 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved 110 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 320 V 1.0, 2020-04 111 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved 112 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-72 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 321 V 1.0, 2020-04 113 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-72 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 322 V 1.0, 2020-04 114 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 115 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-72 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 323 V 1.0, 2020-04 116 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 117 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-72 Port 15 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 324 V 1.0, 2020-04 Table 2-73 Port 20 Functions Pin Symbol Ctrl. Buffer Type Function 93 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output 94 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 325 V 1.0, 2020-04 95 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 6 Reserved —O 7 Reserved 100 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-73 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 326 V 1.0, 2020-04 101 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 102 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-73 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 327 V 1.0, 2020-04 103 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 104 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-73 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 328 V 1.0, 2020-04 105 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 106 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-73 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 329 V 1.0, 2020-04 107 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 108 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC DMU_FDEST Enter destructive debug mode P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-73 Port 20 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 330 V 1.0, 2020-04 Table 2-74 Port 21 Functions Pin Symbol Ctrl. Buffer Type Function 84 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved 85 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 331 V 1.0, 2020-04 86 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data 87 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data Table 2-74 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 332 V 1.0, 2020-04 88 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-74 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 333 V 1.0, 2020-04 90 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-74 Port 21 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 334 V 1.0, 2020-04 Table 2-75 Port 22 Functions Pin Symbol Ctrl. Buffer Type Function 74 P22.0 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 ASCLIN6_ARXE Receive input QSPI3_MTSRD Slave SPI data input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN6_ATX O7 Transmit output 75 P22.1 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 ASCLIN7_ARXE Receive input QSPI3_MRSTD Master SPI data input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN7_ATX O7 Transmit output OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 335 V 1.0, 2020-04 76 P22.2 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI3_SLSO12 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 77 P22.3 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 ASCLIN5_ARXC Receive input QSPI3_SCLKD Slave SPI clock inputs P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-75 Port 22 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 336 V 1.0, 2020-04 Table 2-76 Port 23 Functions Pin Symbol Ctrl. Buffer Type Function 73 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output —O 3 Reserved GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output Table 2-77 Port 32 Functions Pin Symbol Ctrl. Buffer Type Function 70 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 71 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 337 V 1.0, 2020-04 Table 2-78 Port 33 Functions Pin Symbol Ctrl. Buffer Type Function 56 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN4_6 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_6 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved 57 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN5_6 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_6 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 338 V 1.0, 2020-04 58 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN6_6 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_6 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved 59 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN7_6 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_6 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 IOM_PIN_3 GPIO pad input to FPC P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output —O 3 Reserved EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 339 V 1.0, 2020-04 60 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 340 V 1.0, 2020-04 61 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 —O 6 Reserved ASCLIN5_ASLSO O7 Slave select signal output Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 341 V 1.0, 2020-04 62 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 342 V 1.0, 2020-04 63 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) IOM_PIN_7 GPIO pad input to FPC P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output —O 3 Reserved ASCLIN8_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 343 V 1.0, 2020-04 64 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 344 V 1.0, 2020-04 65 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 345 V 1.0, 2020-04 66 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output —O 3 Reserved ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core 67 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 346 V 1.0, 2020-04 68 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved ASCLIN1_ASCLK O4 Shift clock output —O 5 Reserved EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-79 Analog Inputs Pin Symbol Ctrl. Buffer Type Function

51 AN0 I D / HighZ

/ VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A

50 AN1 I D / HighZ

/ VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A

49 AN2 I D / HighZ

/ VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A

48 AN3 I D / HighZ

/ VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A

47 AN4 I D / HighZ

/ VDDM Analog Input 4 EVADC_G0CH4 Analog input channel 4, group 0

46 AN5 I D / HighZ

/ VDDM Analog Input 5 EVADC_G0CH5 Analog input channel 5, group 0 Table 2-78 Port 33 Functions (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 347 V 1.0, 2020-04

45 AN11 I D / HighZ

/ VDDM Analog Input 11 EVADC_G1CH3 Analog input channel 3, group 1 / VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 / VDDM Analog Input 17 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 / VDDM Analog Input 20 EVADC_G2CH4 Analog input channel 4, group 2 EDSADC_EDS2PA Positive analog input channel 2, pin A / VDDM Analog Input 21 EVADC_G2CH5 Analog input channel 5, group 2 EDSADC_EDS2NA Negative analog input channel 2, pin A 36 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B 35 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B 34 AN26/P40.2 I S / HighZ / VDDM Analog Input 26 SENT_SENT2A Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 33 AN27/P40.3 I S / HighZ / VDDM Analog Input 27 SENT_SENT3A Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2

32 AN28 I D / HighZ

/ VDDM Analog Input 28 EVADC_G3CH4 Analog input channel 4, group 3 31 AN32/P40.4 I S / HighZ / VDDM Analog Input 32 SENT_SENT4A Receive input channel 4 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 Table 2-79 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 348 V 1.0, 2020-04 30 AN33/P40.5 I S / HighZ / VDDM Analog Input 33 SENT_SENT5A Receive input channel 5 EVADC_G8CH1 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0

29 AN34 I D / HighZ

/ VDDM Analog Input 34 EVADC_G8CH2 Analog input channel 2, group 8

28 AN35 I D / HighZ

/ VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 27 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A 26 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A 25 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B 24 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B Table 2-80 System I/O Pin Symbol Ctrl. Buffer Type Function 70 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC 71 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC XTAL1. Main Oscillator/PLL/Clock Generator Input. Table 2-79 Analog Inputs (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 349 V 1.0, 2020-04 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O JTAG Module Reset/Enable Input DAP0 I DAP: DAP0 Clock Input ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input Power On Reset Input. Additional strong PD in case of power fail. ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input Table 2-81 Supply Pin Symbol Ctrl. Buffer Type Function 44 VDDM I — ADC Analog Power Supply (5V / 3.3V) 126 VDDP3 I — Flash Power Supply (3.3V) 53, 54, 55 NC I — Not connected. These pins are reserved for future extensions and shall not be connected externally Table 2-80 System I/O (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:TQFP-144 Package Variant Pin Data Sheet 350 V 1.0, 2020-04 52 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM 10 VDD I — Digital Core Power Supply (1.25V) 125 VEXT I — External Power Supply (5V / 3.3V) 23 VEXT I — External Power Supply (5V / 3.3V) 78 VEXT I — External Power Supply (5V / 3.3V) 69 VEXT I — External Power Supply (5V / 3.3V) 127 VDD I — Digital Core Power Supply (1.25V) 22 VDD I — Digital Core Power Supply (1.25V) 79 VDD I — Digital Core Power Supply (1.25V) 99 VDD I — Digital Core Power Supply (1.25V) 72 VDD I — Digital Core Power Supply (1.25V) E-PAD VSS I — Digital Ground (Exposed PAD), VSS with same level as used for VEXT), VEXT(OSC) Table 2-81 Supply (cont’d) Pin Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 351 V 1.0, 2020-04

2.6 Bare Die Variant Pin Configuration of TC36x

Number Pad Name Pad Type X Y Comment 1 P15.0 FAST / PU1 / VEXT / ES 291978 185148 General-purpose I/O 2 P15.1 FAST / PU1 / VEXT / ES 392976 185148 General-purpose I/O 3 P15.2 FAST / PU1 / VEXT / ES 495972 185148 General-purpose I/O 4 P15.3 FAST / PU1 / VEXT / ES 600930 362646 General-purpose I/O 5 P15.4 FAST / PU1 / VEXT / ES 650934 185148 General-purpose I/O 6 P15.5 FAST / PU1 / VEXT / ES 700938 362646 General-purpose I/O

7 VSS Vx 750942 185148 Supply Voltage

8 VEXT Vx 802980 362646 Supply Voltage

9 P15.6 FAST / PU1 / VEXT / ES 852984 185148 General-purpose I/O 10 P15.7 FAST / PU1 / VEXT / ES 902988 362646 General-purpose I/O

11 VSS Vx 978948 185148 Supply Voltage

12 VDD Vx 1054494 362646 Supply Voltage

13 P15.8 FAST / PU1 / VEXT / ES 1106532 185148 General-purpose I/O

14 VDDP3 Vx 1158570 362646 Supply Voltage

15 P14.0 FAST / PU1 / VEXT / ES2 1210608 185148 General-purpose I/O 16 P14.1 FAST / PU1 / VEXT / ES2 1262646 362646 General-purpose I/O 17 P14.2 SLOW / PU2 / VEXT / ES 1314684 185148 General-purpose I/O 18 P14.3 SLOW / PU2 / VEXT / ES 1366722 362646 General-purpose I/O 19 P14.4 SLOW / PU2 / VEXT / ES 1418760 185148 General-purpose I/O 20 P14.5 FAST / PU2 / VEXT / ES 1470798 362646 General-purpose I/O 21 P14.6 FAST / PU1 / VEXT / ES 1522836 185148 General-purpose I/O 22 P14.7 SLOW / PU1 / VEXT / ES 1572840 362646 General-purpose I/O OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 352 V 1.0, 2020-04 23 P14.8 SLOW / PU1 / VEXT / ES 1624293 185148 General-purpose I/O 24 P14.9 LVDS_RX / FAST / PU1 / VEXT / ES 1694340 362646 General-purpose I/O 25 P14.10 LVDS_RX / FAST / PU1 / VEXT / ES 1793340 362646 General-purpose I/O

26 VSS Vx 1868391 185148 Supply Voltage

27 VEXT Vx 1924389 362646 Supply Voltage

28 VSS Vx 1976427 185148 Supply Voltage

29 VEXT Vx 2028465 362646 Supply Voltage

30 VEXT Vx 2080503 185148 Supply Voltage

31 VDDP3 Vx 2262501 185148 Supply Voltage

32 VDDP3 Vx 2312505 362646 Supply Voltage

33 VDDP3 Vx 2362509 185148 Supply Voltage

34 VDD Vx 2442267 362646 Supply Voltage

35 VSS Vx 2516445 185148 Supply Voltage

36 VDD Vx 2586627 362646 Supply Voltage

37 VSS Vx 2654505 185148 Supply Voltage

38 VDD Vx 2720385 362646 Supply Voltage

39 VSS Vx 2778876 185148 Supply Voltage

40 P13.0 LVDS_TX / FAST / PU1 / VEXT / ES6 2878884 185148 General-purpose I/O 41 P13.1 LVDS_TX / FAST / PU1 / VEXT / ES6 2977884 185148 General-purpose I/O 42 P13.2 LVDS_TX / FAST / PU1 / VEXT / ES6 3148884 362646 General-purpose I/O 43 P13.3 LVDS_TX / FAST / PU1 / VEXT / ES6 3247884 362646 General-purpose I/O 44 P12.0 SLOW / PU1 / VFLEX / ES 3381597 179145 General-purpose I/O 45 P12.1 SLOW / PU1 / VFLEX / ES 3428595 348147 General-purpose I/O 46 P11.14 SLOW / PU1 / VFLEX / ES 3531933 179145 General-purpose I/O 47 P11.13 SLOW / PU1 / VFLEX / ES 3580191 348147 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 353 V 1.0, 2020-04 48 P11.15 SLOW / PU1 / VFLEX / ES 3627189 179145 General-purpose I/O 49 P11.0 RFAST / PU1 / VFLEX / ES 3700593 356643 General-purpose I/O

50 VFLEX Vx 3749391 185148 Supply Voltage

51 P11.1 RFAST / PU1 / VFLEX / ES 3822795 356643 General-purpose I/O

52 VSS Vx 3871593 185148 Supply Voltage

53 P11.2 RFAST / PU1 / VFLEX / ES 3944997 362646 General-purpose I/O

54 VDD Vx 3993795 185148 Supply Voltage

55 P11.4 RFAST / PU1 / VFLEX / ES 4109499 348147 General-purpose I/O

56 VSS Vx 4196997 185148 Supply Voltage

57 P11.3 RFAST / PU1 / VFLEX / ES 4270401 362646 General-purpose I/O

58 VFLEX Vx 4319199 185148 Supply Voltage

59 P11.6 RFAST / PU1 / VFLEX / ES 4390803 362646 General-purpose I/O

60 VSS Vx 4441401 185148 Supply Voltage

61 P11.5 SLOW / RGMII_Input / PU1 / VFLEX / ES 4491099 356643 General-purpose I/O 62 P11.7 SLOW / RGMII_Input / PU1 / VFLEX / ES 4554387 179145 General-purpose I/O 63 P11.9 FAST / RGMII_Input / PU1 / VFLEX / ES 4602285 362646 General-purpose I/O

64 VFLEX Vx 4652883 185148 Supply Voltage

65 P11.8 SLOW / RGMII_Input / PU1 / VFLEX / ES 4702581 362646 General-purpose I/O 66 P11.10 FAST / RGMII_Input / PU1 / VFLEX / ES 4753179 185148 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 354 V 1.0, 2020-04 67 P11.11 FAST / RGMII_Input / PU1 / VFLEX / ES 4803777 362646 General-purpose I/O

68 VSS Vx 4854375 185148 Supply Voltage

69 P11.12 FAST / RGMII_Input / PU1 / VFLEX / ES 4903173 362646 General-purpose I/O 70 P10.0 SLOW / PU1 / VEXT / ES 4979187 185148 General-purpose I/O 71 P10.1 FAST / PU1 / VEXT / ES 5029191 362646 General-purpose I/O 72 P10.2 FAST / PU1 / VEXT / ES 5079195 185148 General-purpose I/O 73 P10.3 FAST / PU1 / VEXT / ES 5129199 362646 General-purpose I/O

74 VSS Vx 5179203 185148 Supply Voltage

75 VEXT Vx 5231241 362646 Supply Voltage

76 P10.4 FAST / PU1 / VEXT / ES 5281245 185148 General-purpose I/O

77 VDD Vx 5331249 362646 Supply Voltage

78 P10.5 SLOW / PU2 / VEXT / ES 5383287 185148 General-purpose I/O 79 P10.7 SLOW / PU1 / VEXT / ES 5435325 362646 General-purpose I/O

80 VSS Vx 5494005 185148 Supply Voltage

81 P10.6 SLOW / PU2 / VEXT / ES 5595003 185148 General-purpose I/O 82 P10.8 SLOW / PU1 / VEXT / ES 5697999 185148 General-purpose I/O 83 P02.0 FAST / PU1 / VEXT / ES 5801292 291978 General-purpose I/O 84 P02.1 SLOW / PU1 / VEXT / ES 5801292 392976 General-purpose I/O 85 P02.2 FAST / PU1 / VEXT / ES 5801292 495972 General-purpose I/O 86 P02.3 SLOW / PU1 / VEXT / ES 5801292 600966 General-purpose I/O 87 P02.4 FAST / PU1 / VEXT / ES 5801292 700974 General-purpose I/O

88 VSS Vx 5801292 800982 Supply Voltage

Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 355 V 1.0, 2020-04 89 P02.5 FAST / PU1 / VEXT / ES 5801292 900990 General-purpose I/O 90 P02.6 FAST / PU1 / VEXT / ES 5801292 1000998 General-purpose I/O 91 P02.7 FAST / PU1 / VEXT / ES 5801292 1101006 General-purpose I/O 92 P02.8 SLOW / PU1 / VEXT / ES 5801292 1201014 General-purpose I/O

93 VEXT Vx 5801292 1301022 Supply Voltage

94 VSS Vx 5801292 1401030 Supply Voltage

95 VDD Vx 5801292 1501038 Supply Voltage

96 VDD Vx 5801292 1601046 Supply Voltage

97 VSS Vx 5801292 1701054 Supply Voltage

98 VDD Vx 5801292 1801062 Supply Voltage

99 VSS Vx 5801292 1902060 Supply Voltage

100 VSS Vx 5801292 2005056 Supply Voltage

101 VDD Vx 5623794 2108052 Supply Voltage

102 P00.0 FAST / PU1 / VEXT / ES 5801292 2165049 General-purpose I/O 103 P00.1 SLOW / PU1 / VEXT / ES 5801292 2273540 General-purpose I/O 104 P00.2 SLOW / PU1 / VEXT / ES1 5623794 2328538 General-purpose I/O 105 P00.3 SLOW / PU1 / VEXT / ES1 5801292 2383538 General-purpose I/O 106 P00.4 SLOW / PU1 / VEXT / ES1 5623794 2438536 General-purpose I/O 107 P00.5 SLOW / PU1 / VEXT / ES1 5801292 2493536 General-purpose I/O 108 P00.6 SLOW / PU1 / VEXT / ES1 5623794 2548534 General-purpose I/O 109 P00.7 SLOW / PU1 / VEXT / ES1 5801292 2603534 General-purpose I/O 110 P00.8 SLOW / PU1 / VEXT / ES1 5623794 2658532 General-purpose I/O 111 P00.9 SLOW / PU1 / VEXT / ES1 5801292 2713532 General-purpose I/O 112 P00.10 SLOW / PU1 / VEXT / ES1 5623794 2768530 General-purpose I/O 113 P00.11 SLOW / PU1 / VEXT / ES1 5801292 2823530 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 356 V 1.0, 2020-04 114 P00.12 SLOW / PU1 / VEXT / ES1 5623794 2878528 General-purpose I/O

115 VSS Vx 5801292 2933528 Supply Voltage

116 VSS Vx 5801292 3032626 Supply Voltage

117 VDD Vx 5801292 3131726 Supply Voltage

118 VDD Vx 5623794 3186724 Supply Voltage

119 VEXT Vx 5801292 3285824 Supply Voltage

120 VEXT Vx 5623794 3340822 Supply Voltage

121 AN43 D / HighZ /

5801292 3439922 Analog Input 43

122 AN42 D / HighZ /

5623794 3494920 Analog Input 42

123 AN47 D / HighZ /

5801292 3549920 Analog Input 47

124 AN46 D / HighZ /

5623794 3604918 Analog Input 46

125 AN45 D / HighZ /

5801292 3659918 Analog Input 45

126 AN44 D / HighZ /

5623794 3714916 Analog Input 44 127 AN39/P40.9 S / HighZ / VDDM 5801292 3879914 Analog Input 39 128 AN38/P40.8 S / HighZ / VDDM 5623794 3934912 Analog Input 38 129 AN37/P40.7 S / HighZ / VDDM 5801292 3989912 Analog Input 37 130 AN36/P40.6 S / HighZ / VDDM 5623794 4044910 Analog Input 36

131 AN35 D / HighZ /

5801292 4099910 Analog Input 35

132 AN34 D / HighZ /

5623794 4154908 Analog Input 34 133 AN33/P40.5 S / HighZ / VDDM 5801292 4209908 Analog Input 33 134 AN32/P40.4 S / HighZ / VDDM 5623794 4264906 Analog Input 32

135 AN29 D / HighZ /

5801292 4319906 Analog Input 29

136 AN28 D / HighZ /

5623794 4374904 Analog Input 28 137 AN27/P40.3 S / HighZ / VDDM 5801292 4429904 Analog Input 27 Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 357 V 1.0, 2020-04 138 AN26/P40.2 S / HighZ / VDDM 5623794 4484902 Analog Input 26 139 AN25/P40.1 S / HighZ / VDDM 5801292 4539902 Analog Input 25 140 AN24/P40.0 S / HighZ / VDDM 5801292 4663300 Analog Input 24

141 AN23 D / HighZ /

5716440 4748292 Analog Input 23

142 AN22 D / HighZ /

5593140 4748292 Analog Input 22

143 AN41 D / HighZ /

5538141 4570794 Analog Input 41

144 AN21 D / HighZ /

5483142 4748292 Analog Input 21

145 AN40 D / HighZ /

5428143 4570794 Analog Input 40

146 AN20 D / HighZ /

5373144 4748292 Analog Input 20

147 AN31 D / HighZ /

5318145 4570794 Analog Input 31

148 AN19 D / HighZ /

5263146 4748292 Analog Input 19

149 AN30 D / HighZ /

5208147 4570794 Analog Input 30

150 AN18 D / HighZ /

5153148 4748292 Analog Input 18

151 AN17 D / HighZ /

5098149 4570794 Analog Input 17

152 AN16 D / HighZ /

5043150 4748292 Analog Input 16

153 AN15 D / HighZ /

4988151 4570794 Analog Input 15

154 VAGND1 Vx 4933152 4748292 Supply Voltage

155 VAREF1 Vx 4878153 4570794 Supply Voltage

156 VAGND0 Vx 4823154 4748292 Supply Voltage

157 VAREF0 Vx 4768155 4570794 Supply Voltage

158 VSSM Vx 4713156 4748292 Supply Voltage

159 VDDM Vx 4658157 4570794 Supply Voltage

160 VSSM Vx 4603158 4748292 Supply Voltage

161 VDDM Vx 4548159 4570794 Supply Voltage

162 VSSM Vx 4369514 4748292 Supply Voltage

163 VDDM Vx 4314514 4570794 Supply Voltage

Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 358 V 1.0, 2020-04

164 AN14 D / HighZ /

4259516 4748292 Analog Input 14

165 AN13 D / HighZ /

4204516 4570794 Analog Input 13

166 AN12 D / HighZ /

4149518 4748292 Analog Input 12

167 AN11 D / HighZ /

4094518 4570794 Analog Input 11

168 AN10 D / HighZ /

4039520 4748292 Analog Input 10

169 AN9 D / HighZ /

3984520 4570794 Analog Input 9

170 AN8 D / HighZ /

3929522 4748292 Analog Input 8

171 AN7 D / HighZ /

3874522 4570794 Analog Input 7

172 AN6 D / HighZ /

3819524 4748292 Analog Input 6

173 AN5 D / HighZ /

3764524 4570794 Analog Input 5

174 AN4 D / HighZ /

3709526 4748292 Analog Input 4

175 AN3 D / HighZ /

3654526 4570794 Analog Input 3

176 AN2 D / HighZ /

3599528 4748292 Analog Input 2

177 AN1 D / HighZ /

3544528 4570794 Analog Input 1

178 AN0 D / HighZ /

3489530 4748292 Analog Input 0

179 VSS Vx 3371427 4748292 Supply Voltage

180 VDD Vx 3293469 4570794 Supply Voltage

181 VSS Vx 3219507 4748292 Supply Voltage

182 VDD Vx 3141549 4570794 Supply Voltage

183 VSS Vx 3067587 4748292 Supply Voltage

184 VDD Vx 2991789 4570794 Supply Voltage

185 VEVRSB Vx 2910159 4748292 Supply Voltage

186 VEVRSB Vx 2858121 4570794 Supply Voltage

187 VSS Vx 2806083 4748292 Supply Voltage

188 P33.0 SLOW / PU1 / VEVRSB / ES5 2683107 4748292 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 359 V 1.0, 2020-04 189 P33.1 SLOW / PU1 / VEVRSB / ES5 2627109 4570794 General-purpose I/O 190 P33.2 SLOW / PU1 / VEVRSB / ES5 2577105 4748292 General-purpose I/O 191 P33.3 SLOW / PU1 / VEVRSB / ES5 2527101 4570794 General-purpose I/O 192 P33.4 SLOW / PU1 / VEVRSB / ES5 2477097 4748292 General-purpose I/O 193 P33.5 SLOW / PU1 / VEVRSB / ES5 2422107 4570794 General-purpose I/O

194 VSS Vx 2334015 4748292 Supply Voltage

195 VDD Vx 2258217 4570794 Supply Voltage

196 P33.6 SLOW / PU1 / VEVRSB / ES5 2208519 4748292 General-purpose I/O 197 P33.8 FAST / HighZ / VEVRSB 2158515 4570794 General-purpose I/O 198 P33.7 SLOW / PU1 / VEVRSB / ES5 2108511 4748292 General-purpose I/O

199 VDD Vx 2059173 4570794 Supply Voltage

200 VSS Vx 2009475 4748292 Supply Voltage

201 P33.10 FAST / PU1 / VEVRSB / ES5 1954179 4570794 General-purpose I/O 202 P33.9 SLOW / PU1 / VEVRSB / ES5 1903185 4748292 General-purpose I/O 203 P33.11 FAST / PU1 / VEVRSB / ES5 1853181 4570794 General-purpose I/O 204 P33.12 FAST / PU1 / VEVRSB / ES5 1803177 4748292 General-purpose I/O

205 VDD Vx 1752309 4570794 Supply Voltage

206 VSS Vx 1684044 4748292 Supply Voltage

207 VEVRSB Vx 1584036 4748292 Supply Voltage

208 VSS Vx 1484028 4748292 Supply Voltage

Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 360 V 1.0, 2020-04 209 P33.13 FAST / PU1 / VEVRSB / ES5 1379034 4748292 General-purpose I/O

210 VSS Vx 1278036 4748292 Supply Voltage

211 VDD Vx 1178028 4748292 Supply Voltage

212 VEXT Vx 1078020 4748292 Supply Voltage

213 P32.0 SLOW / PU1 / VEXT / ES 978012 4748292 General-purpose I/O 214 VGATE1N Vx 878004 4748292 DCDC N ch. MOSFET gate driver output 215 P32.1 SLOW / PU1 / VEXT / ES 777996 4748292 General-purpose I/O 216 VGATE1P Vx 677988 4748292 DCDC P ch. MOSFET gate driver output

217 VSS Vx 577980 4748292 Supply Voltage

218 P32.2 SLOW / PU1 / VEXT / ES 477972 4748292 General-purpose I/O 219 P32.3 SLOW / PU1 / VEXT / ES 372978 4748292 General-purpose I/O 220 P32.4 FAST / PU1 / VEXT / ES 269982 4748292 General-purpose I/O 221 P23.0 SLOW / PU1 / VEXT / ES 185148 4596759 General-purpose I/O 222 P23.1 FAST / PU1 / VEXT / ES 185148 4493763 General-purpose I/O

223 VEXT Vx 362646 4441725 Supply Voltage

224 P23.3 SLOW / PU1 / VEXT / ES 185148 4364199 General-purpose I/O 225 P23.2 SLOW / PU1 / VEXT / ES 362646 4312161 General-purpose I/O 226 P23.5 FAST / PU1 / VEXT / ES 185148 4260123 General-purpose I/O 227 P23.4 FAST / PU1 / VEXT / ES 362646 4208085 General-purpose I/O 228 P22.0 FAST / PU1 / VEXT / ES6 185148 4156047 General-purpose I/O 229 P22.1 FAST / PU1 / VEXT / ES6 362646 4104009 General-purpose I/O 230 P22.2 FAST / PU1 / VEXT / ES6 185148 4048011 General-purpose I/O 231 P22.3 FAST / PU1 / VEXT / ES6 362646 3995973 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 361 V 1.0, 2020-04

232 RESERVED Vx 1851 48 3943935 Must be bonded to VSS

233 VEXT Vx 362646 3891897 Supply Voltage

234 VSS Vx 185148 3839859 Supply Voltage

235 VEXT Vx 362646 3787821 Supply Voltage

236 VSS Vx 185148 3735783 Supply Voltage

237 VDD Vx 362646 3683745 Supply Voltage

238 VSS Vx 185148 3604815 Supply Voltage

239 VDD Vx 362646 3523887 Supply Voltage

240 VSS Vx 185148 3446955 Supply Voltage

241 VDD Vx 362646 3356172 Supply Voltage

242 VSS Vx 185148 3306762 Supply Voltage

243 XTAL1 XTAL / VEXT 1 85148 3149613 XTAL pad1

XTAL1. Main Oscillator/PLL/Clock Generator Input.

244 XTAL2 XTAL / VEXT 1 85148 3050613 XTAL pad2

XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT

245 VSS Vx 185148 2893464 Supply Voltage

246 VEXT Vx 362646 2844054 Supply Voltage

247 VEXT Vx 362646 2709414 Supply Voltage

248 VSS Vx 185148 2659374 Supply Voltage

249 P21.0 FAST / PU1 / VEXT / ES 362646 2605338 General-purpose I/O 250 P21.1 FAST / PU1 / VEXT / ES 185148 2551338 General-purpose I/O 251 P21.2 LVDS_RX / FAST / PU1 / VEXT / ES 362646 2476287 General-purpose I/O 252 P21.3 LVDS_RX / FAST / PU1 / VEXT / ES 362646 2377287 General-purpose I/O 253 P21.4 LVDS_TX / FAST / PU1 / VEXT / ES6 362646 2247741 General-purpose I/O 254 P21.5 LVDS_TX / FAST / PU1 / VEXT / ES6 362646 2148741 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 362 V 1.0, 2020-04 255 P21.6/TDI FAST / PD / PU2 / VEXT / ES3 185148 2037240 General-purpose I/O PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ.

256 TMS FAST / PD2 /

362646 1987236 JTAG Module State Machine Control Input 257 P21.7/TDO FAST / PU2 / VEXT / ES4 185148 1937232 General-purpose I/O

258 TRST FAST / PU2 /

362646 1887228 JTAG Module Reset/Enable Input

259 TCK FAST / PD2 /

185148 1837224 JTAG Module Clock Input 260 P20.0 FAST / PU1 / VEXT / ES 362646 1787220 General-purpose I/O

261 VSS Vx 185148 1737216 Supply Voltage

262 VEXT Vx 362646 1685178 Supply Voltage

263 P20.1 SLOW / PU1 / VEXT / ES 185148 1635174 General-purpose I/O 264 P20.2 S / PU / VEXT 362646 1585170 General-purpose I/O This pin is latched at power on reset release to enter test mode. 265 P20.3 SLOW / PU1 / VEXT / ES 185148 1535166 General-purpose I/O

266 ESR1 FAST / PU1 /

362646 1485162 ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin

267 PORST PORST / PD /

Power On Reset Input. Additional strong PD in case of power fail. Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 363 V 1.0, 2020-04

268 ESR0 FAST / OD /

362646 1385154 ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin

269 VSS Vx 185148 1312974 Supply Voltage

270 VDD Vx 362646 1240794 Supply Voltage

271 VSS Vx 185148 1168614 Supply Voltage

272 VDD Vx 362646 1096434 Supply Voltage

273 VSS Vx 185148 1024254 Supply Voltage

274 VDD Vx 362646 952074 Supply Voltage

275 P20.6 SLOW / PU1 / VEXT / ES 185148 900036 General-purpose I/O 276 P20.7 FAST / PU1 / VEXT / ES 362646 847998 General-purpose I/O 277 P20.8 FAST / PU1 / VEXT / ES 185148 797994 General-purpose I/O 278 P20.9 FAST / PU1 / VEXT / ES 362646 747990 General-purpose I/O

279 VEXT Vx 185148 697986 Supply Voltage

280 P20.10 FAST / PU1 / VEXT / ES 362646 647982 General-purpose I/O

281 VSS Vx 185148 597978 Supply Voltage

282 P20.12 FAST / PU1 / VEXT / ES 362646 547974 General-purpose I/O 283 P20.11 FAST / PU1 / VEXT / ES 185148 497970 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Bare Die Variant Pin Configuration of Data Sheet 364 V 1.0, 2020-04 Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is provided by Figure 2-82. This statement is also valid for next/nearest neighbor pads. In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads (ACNP) has to be defined. Finding close-neighbor pads. The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends. Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one neighbor. Similarly, each pad has two indirect (second) neighbo rs unless it or its first neighbor is located at the end of the edge. These first and second neighbors we will colle ctively call Close-Neighbor pads. Therefore each pad has 2 to 4 close-neighbor pads. Finding close-neighbors can be done with the following sequence: 1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-82. 2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-82 is sorted by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might end up with less than 4 close-neighbors). Defining active pads: Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name. Figuring out number of active close-neighbor pads follow next rules: - If the first neighbor is active, then we count it and also ch eck if second neighbor (on the same side of selected pad) is active. - If the first neighbor is not active, then we do not check the second on the same side. 284 P20.13 FAST / PU1 / VEXT / ES 185148 392976 General-purpose I/O 285 P20.14 FAST / PU1 / VEXT / ES 185148 289980 General-purpose I/O Table 2-82 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

TC36x Pin Definition and Functions:Legend Data Sheet 365 V 1.0, 2020-04

2.7 Legend

Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB) O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function) O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column “Buffer Type”: FAST = Pad class FAST (5V/3.3V) RFAST = Pad class RFAST (5V/3.3V) SLOW = Pad class SLOW (5V/3.3V) LVDS_TX = Pad class LVDS Transmit LVDS_RX = Pad class LVDS Receive RGMII_Input = Pad implemented with controllable RGMII input buffer. Chapter -> ´General Purpose Ports and I/O´ S = Pad class S (Analog Input overlayed with General Purpose Input) D = Pad class D (Analog Input) Porst = Porst input Pad XTAL1 = XTAL1 input Pad XTAL2 = XTAL2 input Pad PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) PU2 = with pull-up device connected during reset and startup, HighZ in Standby mode PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) PD2 = with pull-down device connected during reset and startup, HighZ in Standby mode OD = open drain during reset (PORST = 0) ES = Supports Emergency Stop ES1 = ES. ES can be overruled by VADC, control via P00_PCSR ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over CAN message ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter PMS, HWCFG[6]. OPEN MARKET VERSION

TC36x Pin Definition and Functions:Legend Data Sheet 366 V 1.0, 2020-04 ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via the control register P33_PCSR and P34_PCSR ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event. OPEN MARKET VERSION

Electrical Specification Parameter Interpretation Data Sheet 367 V 1.0, 2020-04

3 Electrical Specification

3.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC36x and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC36x and must be regarded for a system design.
• SR Such parameters indicate System Requirements which must be provided by the microcontroller system in which the TC36x designed in. OPEN MARKET VERSION

Electrical Specification Absolute Maximum Ratings Data Sheet 368 V 1.0, 2020-04

3.2 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the de vice at these or any ot her conditions above those indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3-1 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Storage Temperature TST SR -65 - 150 °C upto 65h @ TJ = 150°C Voltage at VDD power supply pins with respect to VSS 1) 2) 1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise and fall times are related to the system capacities and coils. 2) Due to EVRC output voltage oscillation during switch off phase VDD can drop down to -0.72V. For VDD an input level down to -0.72V during switch off phase will not cause any damage or reliability problem. VDD SR - - 1.65 V upto 2.8h - - 1.45 V upto 72h Voltage at VDDP3 power supply pins with respect to VSS VDDP3 S R --4 . 4 3 V Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS VDDM SR - - 6.75 V upto 2.8h - - 5.6 V upto 72h Voltage on all analog and class S input pins with respect to VSS 3) Voltages below VINmin have no Impact to the device reliability as Long as the times and currents defined in section Pin Reliability in Overload for the affected pad(s) are not violated. VIN SR -0.7 - 6.75 V Voltage on all other input pins with respect to VSS 3) VIN SR -0.7 - 6.75 V Input current on any pin during overload condition 4) 5) 4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may damage the device. 5) The specified min. and max. va lues represent the current limits, which have to be maintained, in case of a short circuit condition on the output of any Fast, RFast, Slow and Class S pad, not being used during operation. This cover also output currents due to switching in operation for CL=200pF. IIN SR -10 - 10 mA Absolute maximum sum of all input circuit currents during overload condition. 4) ΣIIN SR -100 - 100 mA OPEN MARKET VERSION

Electrical Specification Pin Reliability in Overload Data Sheet 369 V 1.0, 2020-04

3.3 Pin Reliability in Overload

When receiving signals from highe r voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. The following table defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• allowed time interval (defined in Note column) for overload co ndition is not exceeded. If no time limit is defined the allowed time includes both ‘Operation Lifetime hours’ and ‘Inactive Lifetime hours’. The number of hours in Table 3-66 and Table 3-67 are examples only and the applicable numbers are defined by the customer profiles accepted by Infineon.
• Operating Conditions are met for – pad supply levels – temperature If a pin current is out of the Operating Conditions but within the overload par ameters, then the parameters functionality of this pin as sta ted in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Table 3-2 Overload Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input current on any digital pin during overload condition IIN -5 - 5 mA except LVDS pins -15 1) - 1 5 1) mA except LVDS pins; limited to max. 20 pulses with 1ms pulse length Input current on LVDS pin during overload condition IINLVDS -3 - 3 mA Input current on analog input pin during overload condition IINANA -3 - 3 mA -5 - 5 mA limited to 60h over lifetime Absolute sum of all analog input currents for analog inputs during overload condition IINSA -20 - 20 mA Absolute maximum sum of all input circuit currents during overload condition (digital and analog combined) ΣIINS -100 - 100 mA Signal voltage over/undershoot at GPIOs VOUS VSS - 2 - VEXT/FLEX + 2 V limited to 60h over lifetime; Valid for non LVDS and analoge pads Sum of all inactive device pin currents IIDS -100 - 100 mA Static pin output current IOUT CC - - 2.5 mA 100% duty cycle; output driver = medium - - 5 mA 100% duty cycle; output driver = strong OPEN MARKET VERSION

Electrical Specification Pin Reliability in Overload Data Sheet 370 V 1.0, 2020-04 Overload coupling factor for digital inputs, negative KOVDN C C --3 * 1 0 -4 Overload injected on GPIO non LVDS pad and affecting neighbor fast pads; -5mA < IIN < 0mA --2 * 1 0 -3 Overload injected on GPIO non LVDS pad and affecting neighbor slow pads VGASTE1N and VGATE1P; -5mA < IIN < 0mA --1 * 1 0 -4 Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -5mA < IIN < 0mA - - 0.8 Overload injected on LVDS RX pad and affecting neighbor LVDS pads - - 0.5 Overload injected on LVDS TX pad and affecting neighbor LVDS pads Overload coupling factor for digital inputs, positive KOVDP C C --1 . 5 * 1 0 -3 Overload injected on GPIO non LVDS pad and affecting neighbor GPIO non LVDS pads - - 1 Overload injected on LVDS RX pad and affecting neighbor LVDS pads --5 * 1 0 -3 Overload injected on LVDS TX pad and affecting neighbor LVDS pads Overload coupling factor for analog inputs, negative 2) KOVAN C C --1 * 1 0 -4 Analog inputs overlaid with slow pads or pull down diagnostics; - 5mA < IIN < 0mA --1 * 1 0 -5 else; -5mA < IIN < 0mA Table 3-2 Overload Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Pin Reliability in Overload Data Sheet 371 V 1.0, 2020-04 Overload coupling factor for analog inputs, positive 2) KOVAP C C --2 * 1 0 -4 Analoge inputs overlaid with slow pads or pull down diagnostics; 0mA < IIN < 5mA --2 * 1 0 -5 else; 0mA < IIN < 5mA 1) Reduced VADC / DSADC result accu racy and / or GPIO input levels (VIL and VIH) can differ from specified parameters. 2) Overload coupling on analog i nputs is caused by parasitic effects between pads, input multiplexers and surrounding structures. The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to several channels. Table 3-2 Overload Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Operating Conditions Data Sheet 372 V 1.0, 2020-04

3.4 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC36x. All parameters specified in the following tables refer t o these operating conditions, unless otherwise noticed. Digital supply voltages applied to the TC36x must be static regulated voltages. All parameters specified in the following tables refer to these operating conditions (see table below), unless otherwise noticed in the Note / Test Condition column. Table 3-3 Operating Conditions Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SRI frequency fSRI S R --3 0 0 M H z CPU Frequency (All CPUs) fCPUx S R --3 0 0 M H z PLL0 output frequency fPLL0 SR 20 - 300 MHz SPB frequency fSPB S R --1 0 0 M H z FSI2 frequency fFSI2 S R --3 0 0 M H z FSI frequency fFSI SR 20 - 100 MHz GTM frequency fGTM S R --2 0 0 M H z STM frequency fSTM S R --1 0 0 M H z ERAY frequency fERAY SR - 80 - MHz BBB frequency fBBB S R --1 5 0 M H z VADC frequency fADC S R --1 6 0 M H z ASCLIN Operating Frequency fASCLINx S R --2 0 0 M H z CAN frequency fCAN S R --8 0 M H z I2C frequency fI2C S R --1 0 0 M H z Operating MSC Frequency fMSC S R --2 0 0 M H z PLL1 output frequency from PER PLL fPLL1 SR 20 - 320 MHz PLL2 output frequency from PER PLL fPLL2 SR 20 - 200 MHz QSPI Frequency fQSPI S R --2 0 0 M H z MCANH frequency fMCANH C C --1 0 0 M H z GETH frequency fGETH CC 100 - 150 MHz Ambient Temperature TA SR -40 - 125 °C valid for all SAK products -40 - 150 °C valid for all SAL products with package -40 - 170 °C valid for all SAL products without package OPEN MARKET VERSION

Electrical Specification Operating Conditions Data Sheet 373 V 1.0, 2020-04 Junction Temperature TJ SR -40 - 150 °C valid for all SAK products -40 - 170 °C valid for all SAL products Core Supply Voltage VDD SR 1.125 1) 1 . 2 5 1 . 3 7 5 2) V ADC analog supply voltage VDDM SR 2.97 5.0 5.5 3) V Digital external supply voltage for pads and EVR VEXT SR 4.5 5.0 5.5 3) V Nominal 5V Pad / Port Pin supply range. 5V pad parameters are valid. 2.97 3.3 3.63 V Nominal 3.3V Pad / Port Pin supply range with VDDP3 supplied externally and EVR33 inactive. 3.3V pad parameters are valid. 3.6 - 4.5 V Flash configured in cranking mode; Flash read operation with reduced performance. EVR33 active in low voltage mode. 3.3V pad parameters are valid. 2.97 - 3.6 V Incase EVR33 is active, Flash configured in sleep mode and execution switched to RAM. 3.3V pad parameters are valid. Digital supply voltage for Flex port VFLEX SR 2.97 - 4.0 V 3.3V pad parameters are valid 4.5 5.0 5.5 3) V 5V pad parameters are valid Digital supply voltage for Flash VDDP3 SR 2.97 3.3 3.63 4) V 2.6 - 3.63 V Flash configured in cranking mode; Flash read operation with reduced performance. Digital ground voltage VSS SR 0 - - V Analog ground voltage for VDDM VSSM CC -0.1 0 0.1 V Table 3-3 Operating Conditions (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Operating Conditions Data Sheet 374 V 1.0, 2020-04 Limitation of Supply Voltage over Time The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime. The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. The maximum operation voltage for VDD supply rails is limited over the complete lifetime. The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. Digital external supply voltage for EVR and during Standby mode VEVRSB SR 2.97 5) - 5.5 V Voltage to ensure defined pad states VDDPPA CC 1.3 6) - - V 1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters. 2) Voltage overshoot to 1.69V i s permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 3) Voltage overshoot to 6.5V is p ermissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 4) Voltage overshoot to 4.29V i s permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB supply pin. 6) HWCFG[6] pin is latched and pu ll-up or tristate is activated at Port pins when VEXT has reached this level. Table 3-4 Example Voltage Profile VEXT/FLEX/DDM= Duration [h] 5.4 V < VEXT/FLEX/DDM ≤ 5.5 V ≤ 5% of lifetime 5.15 V < VEXT/FLEX/DDM ≤ 5.4 V ≤ 15% of lifetime 4.85 V < VEXT/FLEX/DDM ≤ 5.15 V ≤ 60% of lifetime 4.6 V < VEXT/FLEX/DDM ≤ 4.85 V ≤ 15% of lifetime 4.5 V < VEXT/FLEX/DDM ≤ 4.6 V ≤ 5% of lifetime Table 3-5 Example Voltage Profile VDD= Duration [h] 1.325 V < VDD ≤ 1.375 V ≤ 5% of lifetime 1.275 V < VDD ≤ 1.325 V ≤ 15% of lifetime 1.225 V < VDD ≤ 1.275 V ≤ 60% of lifetime 1.175 V < VDD ≤ 1.225 V ≤ 15% of lifetime 1.125 V < VDD ≤ 1.175V ≤ 5% of lifetime Table 3-3 Operating Conditions (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 375 V 1.0, 2020-04 3.5 5 V / 3.3 V switchable Pads Pad classes slow GPIO and fast GP I O s u p p o r t b o t h A u t o m o t i v e L e ve l ( A L ) o r T T L l e v e l ( T T L ) o p e r a t i o n . Parameters are defined for AL operation and degrade in TTL operation. Table 3-6 PORST Pad Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. PORST pad Output current IPORST CC 13 - - mA VEXT = 2.97V; VPORST = 0.9V Spike filter always blocked pulse duration tSF1 C C --8 0 n s Spike filter pass-through blocked pulse duration tSF2 CC 260 - - ns without additional PORST Digtial Filter active (PORSTDF = 0). Input hysteresis 1) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. HYS CC 0.055 * VEXT - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) Pull-down current 2) 2) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. IPDL CC - - |130| µA VIH; TTL (degraded, used for CIF) |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -450 - 450 nA TJ≤150°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT) -500 - 500 nA TJ≤150°C ;else -900 - 900 nA TJ≤170°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT) -950 - 950 nA TJ≤170°C ; else Input high voltage level VIH SR 1.4 - - V TTL (degraded, used for CIF); VEXT = 2.97V 2.0 - - V TTL; VEXT = 4.5V Input low voltage level VIL SR - - 0.5 V TTL (degraded, used for CIF); VEXT = 2.97V --0 . 8 V T T L ; VEXT = 4.5V Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 376 V 1.0, 2020-04 Table 3-7 Fast 5V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Rise / Fall time 1) 2) tRF CC 1.6 - 3.2 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX/EVRSB to 0.8 * VEXT/FLEX/EVRSB 4+0.55*C L 4+0.75*C L 12+1.0*C L ns driver = medium; CL≤200pF 1.0+0.18* CL 2.5+0.27* CL 5.0+0.35* CL ns driver = strong edge = medium; CL≤200pF 0.5+0.08* CL 0.5+0.11* CL 1.0+0.17* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns CL; valid for all data rates excluding clock tolerance Input frequency fIN C C --1 6 0 M H z Input hysteresis 3) HYS CC 0.09 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; AL 0.075 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |30| - - µA VIH; AL or TTL --| 1 3 0 | µ A VIL; AL or TTL Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 377 V 1.0, 2020-04 Input leakage current IOZ CC -1100 - 1100 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -2500 - 2500 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX / Fast pad type ; else -3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX / Fast pad type ; else -1500 - 1500 nA TJ ≤ 150°C ; else -2000 - 2000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -4000 - 4000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX / Fast pad type ; else -5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX / Fast pad type ; else -2500 - 2500 nA TJ ≤ 170°C ; else Input high voltage level VIH SR 0.7 * VEXT/FLEX/ EVRSB --V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VEXT/FLEX/ EVRSB VA L --0 . 8 V T T L Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . Table 3-7 Fast 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 378 V 1.0, 2020-04 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-8 Fast 3.3V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Rise / Fall time 1) 2) tRF CC 1.6 - 4.5 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX/EVRSB to 0.8 * VEXT/FLEX/EVRSB --5 n s CL = 25pF; driver = strong sharp edge; from 0.8V to 2.0V (RMII) 2+0.57*C L 5.5+0.75* CL 10+1.25* CL ns driver = medium; CL≤200pF 1.5+0.18* CL 1.5+0.28* CL 8+0.4*CL ns driver = strong edge = medium; CL≤200pF 0.75+0.08 *CL 0.75+0.11 *CL 2.5+0.21* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns CL; valid for all data rates excluding clock tolerance Input frequency fIN C C --1 6 0 M H z Input hysteresis 3) HYS CC 0.055 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; AL 0.09 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; TTL 0.055 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 379 V 1.0, 2020-04 Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF) |11| - - µA VIH; TTL --| 8 0 | µ A VIL; AL and TTL and TTL (degraded, used for CIF) Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) --| 1 1 5 | µ A VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -1100 - 1100 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -2500 - 2500 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX / Fast pad type ; else -3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX / Fast pad type ; else -1500 - 1500 nA TJ ≤ 150°C ; else -2000 - 2000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -4000 - 4000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX / Fast pad type ; else -5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX / Fast pad type ; else -2500 - 2500 nA TJ ≤ 170°C ; else Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 380 V 1.0, 2020-04 Input high voltage level VIH SR 0.7 * VEXT/FLEX/ EVRSB --V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Input low voltage level VIL SR - - 0.42 * VEXT/FLEX/ EVRSB VA L --0 . 8 V T T L - - 0.5 V TTL (degraded, used for CIF) Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis available Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-9 Slow 5V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA Rise / Fall time 1) 2) tRF CC 4+0.55* C L 4+0.75*C L 12+1*CL ns driver = medium edge = medium ; CL≤200pF 1.5+0.25* CL 2.5+0.40* CL 7+0.55*C L ns driver = medium edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns CL; valid for all data rates excluding clock tolerance Input frequency fIN C C --1 6 0 M H z Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 381 V 1.0, 2020-04 Input hysteresis 3) HYS CC 0.09 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; AL 0.075 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |30| - - µA VIH;AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C --| 1 3 0 | µ A VIL; AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Input leakage current IOZ CC -300 - 300 nA TJ ≤ 150°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -400 - 400 nA TJ ≤ 150°C; else -600 - 600 nA TJ ≤ 170°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -750 - 750 nA TJ ≤ 170°C; else -18000 - 18000 nA P32.0 and P32.1;TJ≤150°C -38000 - 38000 nA P32.0 and P32.1;TJ≤170°C Input high voltage level VIH SR 0.7 * VEXT/FLEX/ EVRSB --V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VEXT/FLEX/ EVRSB VA L --0 . 8 V T T L Table 3-9 Slow 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 382 V 1.0, 2020-04 Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-10 Slow 3.3V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA Rise / Fall time 1) 2) tRF CC 2+0.57* C L 5.5+0.75* CL 10+1.25* CL ns driver = medium edge = medium ; CL≤200pF 2+0.30*C L 3.5+0.50* CL 5+0.70*C L ns driver = medium edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns CL; valid for all data rates excluding clock tolerance Input frequency fIN C C --1 6 0 M H z Input hysteresis 3) HYS CC 0.055 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; AL 0.09 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output; TTL 0.055 * VEXT/FLEX/ EVRSB - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Table 3-9 Slow 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 383 V 1.0, 2020-04 Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C |11| - - µA VIH; TTL; exept VGATE1P; except VGATE1N and TJ > 150°C --| 8 0 | µ A VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) --| 1 1 5 | µ A VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -300 - 300 nA TJ ≤ 150°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -400 - 400 nA TJ ≤ 150°C; else -600 - 600 nA TJ ≤ 170°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -750 - 750 nA TJ ≤ 170°C; else -18000 - 18000 nA P32.0 and P32.1;TJ≤150°C -38000 - 38000 nA P32.0 and P32.1;TJ≤170°C Input high voltage level VIH SR 0.7 * VEXT/FLEX/ EVRSB --V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Table 3-10 Slow 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 384 V 1.0, 2020-04 Input low voltage level VIL SR - - 0.42 * VEXT/FLEX/ EVRSB VA L --0 . 8 V T T L - - 0.5 V TTL (degraded, used for CIF) Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis available Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-11 RFast 5V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Rise / Fall time 1) 2) tRF CC 1.6 - 3.2 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX 4+0.55*C L 4+0.75*C L 12+1.0*C L ns driver = medium; CL≤200pF 1.0+0.18* CL 2.5+0.27* CL 5.0+0.35* CL ns driver = strong edge = medium; CL≤200pF 0.5+0.08* CL 0.5+0.11* CL 1.0+0.17* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -0.5 - 0.5 ns CL; valid for all data rates excluding clock tolerance Table 3-10 Slow 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 385 V 1.0, 2020-04 Input frequency fIN C C --1 6 0 M H z Input hysteresis 3) HYS CC 0.09 * VFLEX - - V non of the neighbor pads are used as output; AL 0.075 * VFLEX - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |30| - - µA VIH; AL or TTL --| 1 3 0 | µ A VIL; AL or TTL Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Input leakage current IOZ CC -1700 - 1700 nA TJ ≤ 150°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -2100 - 2100 nA TJ ≤ 150°C ; else -3000 - 3000 nA TJ ≤ 170°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -4000 - 4000 nA TJ ≤ 170°C ; else Input high voltage level VIH SR 0.7 * VFLEX --V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VFLEX VA L --0 . 8 V T T L Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VFLEX = constant; AL Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. Table 3-11 RFast 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 386 V 1.0, 2020-04 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-12 RFast 3.3V pad Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 8 20 30 Ohm Driver = RGMII; IOH / OL = 8mA 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Input Duty Cycle fD SR 47.5 50 52.5 Rise / Fall time 1) 2) tRF CC 1.6 - 4.5 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX --5 n s CL = 25pF; driver = strong sharp edge; from 0.8V to 2.0V (RMII) - - 1 ns Driver = RGMII; from 20%V to 80%V; CL=15pF 2+0.57*C L 5.5+0.75* CL 10+1.25* CL ns driver = medium; CL≤200pF 1.5+0.18* CL 1.5+0.28* CL 8+0.4*CL ns driver = strong edge = medium; CL≤200pF 0.75+0.08 *CL 0.75+0.11 *CL 2.5+0.21* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -0.4 - 0.4 ns CL; valid for all data rates excluding clock tolerance Input frequency fIN C C --1 6 0 M H z OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 387 V 1.0, 2020-04 Input hysteresis 3) HYS CC 0.055 * VFLEX - - V non of the neighbor pads are used as output; AL 0.09 * VFLEX - - V non of the neighbor pads are used as output; TTL 0.055 * VFLEX - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF) |11| - - µA VIH; TTL --| 8 0 | µ A VIL; AL and TTL and TTL (degraded, used for CIF) Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) --| 1 1 5 | µ A VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -1700 - 1700 nA TJ ≤ 150°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -2100 - 2100 nA TJ ≤ 150°C ; else -3000 - 3000 nA TJ ≤ 170°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -4000 - 4000 nA TJ ≤ 170°C ; else Input high voltage level VIH SR 0.7 * VFLEX --V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Table 3-12 RFast 3.3V pad (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 388 V 1.0, 2020-04 Input low voltage level VIL SR - - 0.42 * VFLEX VA L --0 . 8 V T T L - - 0.5 V TTL (degraded, used for CIF) Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VFLEX = constant; AL Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-13 Class S 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input frequency fIN C C --1 6 0 M H z Input hysteresis 1) HYS CC 0.09 * VDDM - - V non of the neighbor pads are used as output; AL 0.075 * VDDM - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 2) IPUH CC |30| - - µA VIH; AL or TTL --| 1 3 0 | µ A VIL; AL or TTL Pull-down current 3) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Table 3-12 RFast 3.3V pad (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 389 V 1.0, 2020-04 Input leakage current IOZ CC -150 - 150 nA TJ ≤ 150°C; else -300 - 300 nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected -300 - 300 nA TJ ≤ 170°C; else -600 - 600 nA TJ ≤ 170°C; PDD option available, or AltRef option available and EDSADC channel connected Input high voltage level VIH SR 0.7 * VDDM - - V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VDDM VA L --0 . 8 V T T L Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VDDM = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET C C --1 0 0 n s 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 3) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-13 Class S 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 390 V 1.0, 2020-04 Table 3-14 Class D Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input leakage current IOZ CC -150 - 150 nA TJ ≤ 150°C; else -300 1) 1) For AN11, 100 nA need to be added. -3 0 0 1) nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected -300 - 300 nA TJ ≤ 170°C; else -600 2) 2) For AN11, 200 nA need to be added . -6 0 0 2) nA TJ ≤ 170°C; PDD option available, or AltRef option available and EDSADC channel connected Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Table 3-15 ADC Reference Pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input leakage current for VAREF IOZ2 CC -1 - 1 µA TJ ≤ 150°C; VAREF < VDDM; used for EVADC -2 - 2 µA TJ ≤ 170°C; VAREF < VDDM; used for EVADC -3.5 - 3.5 µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EVADC -7 - 7 µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EVADC -2 - 2 µA TJ ≤ 150°C; VAREF < VDDM; used for EDSADC -4 - 4 µA TJ ≤ 170°C; VAREF < VDDM; used for EDSADC -6 - 6 µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EDSADC -12 - 12 µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EDSADC OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 391 V 1.0, 2020-04 Table 3-16 Driver Mode Selection for Slow Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X X 0 Speed grade 1 medium sharp edge (sm) X X 1 Speed grade 2 medium medium edge (m) Table 3-17 Driver Mode Selection for Fast Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (ss) X 0 1 Speed grade 2 Strong medium edge (sm) X 1 0 Speed grade 3 medium (m) X 1 1 Speed grade 4 Reserved, do not use this combination Table 3-18 Driver Mode Selection for RFast Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (ss) X 0 1 Speed grade 2 Strong medium edge (sm) X 1 0 Speed grade 3 medium (m) X 1 1 Speed grade 4 RGMII function is active OPEN MARKET VERSION

Electrical Specification High performance LVDS Pads Data Sheet 392 V 1.0, 2020-04

3.6 High performance LVDS Pads

This LVDS pad type is used for the high speed chip to chip communication interface of the new TC36x. It compose out of a LVDS pad and a fast pad. CL = 2.5 pF for all LVDS parameters. Table 3-19 LVDS - IEEE standard LVDS general purpose link (GPL) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Output impedance R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V Rise time (20% - 80%) trise20 CC - - 0.75 1) n s ZL = 100 Ohm ±20% @2pF external load Output differential voltage 2) VOD CC 240 - 330 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=00 280 - 370 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=01 320 - 410 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=10 380 - 500 mV RT = 100 Ohm ± 1%; LPCRx.VDIFFADJ=11 ; Multi slave operation Output voltage high VOH CC - - 1475 mV RT = 100 Ohm +/- 1% VDIFFADJ=00 and 01 - - 1500 mV RT = 100 Ohm ± 1% VDIFFADJ=10 and 11 Output voltage low VOL CC 925 - - mV RT = 100 Ohm ± 1% VDIFFADJ=00 and 01 900 - - mV RT = 100 Ohm +/- 1% VDIFFADJ=10 and 11 Output offset (Common mode) voltage VOS CC 1125 - 1275 mV RT = 100 Ohm ± 1% Input voltage range VI SR 0 - 1600 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±10% 0 - 2400 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±20% Input differential threshold Vidth SR -100 - 100 mV Driver ground potential difference < 900 mV; VDIFFADJ=10 and 11 -100 - - mV Driver ground potential difference < 925 mV; VDIFFADJ=00 and 01 Receiver differential input impedance Rin CC 80 - 120 Ohm VI ≤ 2400 mV OPEN MARKET VERSION

Electrical Specification High performance LVDS Pads Data Sheet 393 V 1.0, 2020-04 Note: Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted signal. Note: RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by RIN or by RT=100Ohm but not both. default after start-up = CMOS function Output differential voltage Sleep Mode 3) VODSM CC -5 - 20 mV RT = 100 Ohm ± 20%; LPCRx.VDIFFADJ=xx Delta output impedance dR0 S R --1 0 % Vcm = 1.0 V and 1.4 V Change in VOS between 0 and dVOS C C --2 5 m V RT = 100 Ohm ±1% Change in Vod between 0 and dVod C C --2 5 m V RT = 100 Ohm ±1% Pad set-up time tSET_LVDS CC -1 0 1 3 µ s Duty cycle tduty CC 45 - 55 % 1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load. 2) Potencial violati ons of the IEEE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE Std 1596.3 LPCRx.VDIFFADJ has to be configure to 01. 3) Common Mode voltage of Tx is maintained. Table 3-19 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification High performance LVDS Pads Data Sheet 394 V 1.0, 2020-04 Figure 3-1 LVDS pad Input model Ctotal=3.5pF LVDS_Input_Pad_Model.vsd Htotal=5nH LVDS IN P N RT=100Ohm Ctotal=3.5pF Rin Cext=2pF Cext=2pF Htotal=5nH OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 395 V 1.0, 2020-04

3.7 VADC Parameters

The accuracy of the converter results depends on the reference voltage range. The parameters in the table below are valid for a reference voltage range of ( VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V Noise on supply voltage VDDM influences the conversion. The accuracy (error) parameters are defined for a supply voltage ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10M H z ) . Digital functions overlapping analog inputs influence accuracy. The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS (depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional peak-peak noise error is ±(4 × 1.0) = 8 LSB12. Fast compare operations are executed with 10-bit values. The noise reduction feature improv es the result by adding addit ional conversion steps. The conversion times, therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps). Table 3-20 VADC 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. EVADC IVR output voltage VDDK CC 1.15 - 1.35 V Measured at low temperature. Deviation of IVR output voltage VDDK dVDDK CC -2 - 2 % Based on device- specific value Analog reference voltage 1) VAREF SR 4.5 5.0 VDDM + 0.05 V 4.5 V ≤ VDDM ≤ 5.5 V 2.97 3.3 VDDM + 0.05 V2 . 9 7 V ≤ VDDM < 4.5 V Analog reference ground VAGND SR VSSM VSSM VSSM V VSSM and VAGND are connected together Analog input voltage range VAIN SR VAGND - VAREF V VAIN is limited by the respective pad supply voltage; see pin configuration (buffer type) Converter reference clock fADCI SR 16 40 53.33 MHz 4.5 V ≤ VDDM ≤ 5.5 V 16 20 26.67 MHz 2.97 V ≤ VDDM < 4.5 V Total Unadjusted Error 2) 3) TUE CC -4 - 4 LSB 12-bit resolution for primary/secondary groups, 10-bit resolution for fast compare channels INL Error 2) EAINL CC -3 - 3 LSB DNL error 2)4) EADNL CC -1 - 3 LSB Gain Error 2) EAGAIN CC -3.5 - 3.5 LSB Offset Error 2)3) EAOFF CC -4 - 4 LSB RMS Noise 2)5) 6) ENRMS CC - 0.5 0.8 LSB Noise reduction level 3 - 0.5 1.0 LSB Standard conversion OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 396 V 1.0, 2020-04 Reference input charge consumption per conversion (from VAREF) 7) 8) 9) QCONV C C --2 0 p C VAIN = 0 V (worst case), precharging disabled --1 0 p C VAIN = 0 V (worst case), precharging enabled, VDDM - 5% < VAREF < VDDM + 50 mV Switched capacitance of an analog input CAINS CC - 2.5 3.4 pF Input buffer disabled Analog input charge consumption 10) QAINS CC - - 3.5 pC Primary groups and fast compare channels; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ ≤ 150°C - - 3.8 pC Primary groups and fast compare channels; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ > 150°C - - 4.4 pC Secondary groups; VAIN = VAREF; VDDM =

5.0 V; input buffer

enabled; TJ ≤ 150 °C - - 4.8 pC Secondary groups; VAIN = VAREF; VDDM = enabled; TJ > 150°C Table 3-20 VADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 397 V 1.0, 2020-04 Sampling time tS SR 100 - - ns Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled 300 - - ns Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled 500 - - ns Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled 700 - - ns Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled 200 - - ns Primary Group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled 400 - - ns Primary group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled 1000 - - ns Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled 1200 - - ns Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled Sampling time for calibration tSCAL SR 50 - - ns 4.5 V ≤ VDDM ≤ 5.5 V 100 - - ns 2.97 V ≤ VDDM < 4.5 V Input buffer switch-on time tBUF CC - 0.4 1 µs Wakeup time tWU CC - 0.1 0.2 µs Fast standby mode - 1.6 3 µs Slow standby mode Broken wire detection delay against VAREF tBWR CC - 100 - cycles Result above 80% of full scale range, analog input buffer disabled Broken wire detection delay against VAGND tBWG CC - 100 - cycles Result below 10% of full scale range, analog input buffer disabled Converter diagnostics unit resistance 11) RCSD CC 45 - 75 kOhm Converter diagnostics voltage accuracy dVCSD CC -10 - 10 % Percentage refers to VDDM Table 3-20 VADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 398 V 1.0, 2020-04 Figure 3-2 Equivalent Circuitry for Analog Inputs Resistance of the multiplexer diagnostics pull-up device RMDU CC 30 - 42 kOhm 0 V ≤ VIN ≤ 0.9* VDDM, Automotive Levels 56 - 78 kOhm 0 V ≤ VIN ≤ 0.9* VDDM, TTL Levels Resistance of the multiplexer diagnostics pull-down device RMDD CC 43 - 58 kOhm 0.1* VDDM ≤ VIN ≤ VDDM, Automotive level 18 - 25 kOhm 0.1* VDDM ≤ VIN ≤ VDDM, TTL level Resistance of the pull-down test device RPDD CC - - 0.3 kOhm Measured at pad input voltage VIN = VDDM / 2. 1) These limits apply t o the standard reference input as well as to the alternate reference input. 2) Parameter depends on reference voltage range and supply ripple, see introduction. Resulting worst case combined error is arithmetic combination of TUE and ENRMS. Tests are done with postcalibration disabled, after completing the startup calibration. 3) Digital functions on analog i nputs influence accuracy. The values for this parameter increase by 3 LSB12. 4) Monotonic characteristic, no missing codes when calibrated. 5) Parameter EN RMS refers to a 1 sigma distribution. 6) For analog inputs with overla id digital GPIOs the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC enabled). 7) For reduced reference voltages VAREF < 3.375V, the consumed charge QCONV is reduced by the factor of k2 = VAREF 8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active. 9) Fast compare channels only cons ume 1/3 of the charge for a primary/secondary group. 10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC. 11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage. Table 3-20 VADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification DSADC Parameters Data Sheet 399 V 1.0, 2020-04

3.8 DSADC Parameters

The DSADC parameters are valid only for voltage range 4.5 V <= VDDM <= 5.5 V. These parameters describe the product properties and do not inc lude external circuitry. The values are valid for junction temperatures TJ <= 150°C if not defined explicitly. Calibration is specified for gain factors 1 and 2, calibrated values refer to these settings. The signal-noise ratio (SNR) is specified for differential inpu ts. For single ended operation the resulting signal- noise ratio is reduced by 6 dB. For quasi-differential mode (i.e. using VCM) it is reduced by 6 dB for gain = 1 and by 3 dB for gain= 2. Table 3-21 DSADC 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Common mode voltage bias resistance RBIAS CC 105 130 155 kOhm On-chip variation ≤ ±2.5%. Positive reference voltage VAREF SR 4.5 - VDDM + 0.05 V Reference ground voltage VAGND SR VSSM - VSSM V VSSM and VAGND are connected together Reference load current IREF CC - 10 12 µA Per modulator - - 14 µA Per modulator, TJ>150°C Common mode voltage accuracy 1) dVCM CC -100 - 100 mV Deviation from selected voltage Analog input voltage range VDSIN SR VSSM - 2 * VDDM V Differential; VDSxP - VDSxN VSSM - VDDM V Single ended Input current 2) IRMS CC 7 10 15 µA Exact value (±1%) available in UCB; valid for gain = 1 and fMOD =

26.7 MHz

Gain error 3) 4) EDGAIN CC -0.2 5) ± 0 . 1 5) 0.2 5) % TJ≤150°C; Target, calibrated, VAREF constant after calibration; fMOD =

26.67 MHz

• ±0.25 - % TJ>150°C; VAREF constant after calibration; fMOD =

-1 - 1 % Calibrated once; fMOD = 26.67 MHz -2.5 - 2.5 % Uncalibrated; fMOD =

Electrical Specification DSADC Parameters Data Sheet 400 V 1.0, 2020-04 DC offset error 3) EDOFF CC -5 5) -5 5) mV Calibrated; fMOD = -10 - 10 mV Calibrated once; fMOD = 26.67 MHz -30 - 30 mV Uncalibrated; fMOD = differential input signals 2)6) 7) SNR CC 80 - - dB TJ≤150°C; fPB = 30 kHz; fMOD = 26.67 MHz 78 - - dB TJ≤150°C; fPB = 50 kHz; fMOD = 26.67 MHz 74 - - dB TJ≤150°C; fPB = 100 kHz; fMOD = 26.67 MHz Signal-Noise Ratio degradation DSNR C C --3 d B TJ>150°C; Resulting Signal-Noise Ratio value is SNR - DSNR Spurious-free dynamic range 3) SFDR CC 60 - - dB fMOD = 26.67 MHz Output sampling rate fD CC 3.906 - 300 kHz 16 MHz / 4096, without integrator Pass band fPB CC 1.302 - 100 kHz Output data rate: fD = fPB * 3; without integrator 1.302 - 10 kHz Output data rate: fD = fPB * 6; without integrator Pass band ripple dfPB CC -0.08 - 0.08 dB FIR filters enabled 60 - - dB 2.5 fD ... OSR/2 fD DC compensation factor DCF CC -3 - - dB 10 -5 fD, offset compensation filter enabled (FCFGMx.OCEN = 001B) Modulator settling time tMSET CC - - 20 µs After switching on, voltage regulator already running 1) On pins with overlaid GPIO func tion the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C. 2) For detailed information, refer to the User Manual chapter. 3) This parameter is valid w ithin the defined range of fMOD. 4) Gain mismatch error between t he different EDSADC channels is within ±0.5%. Table 3-21 DSADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification DSADC Parameters Data Sheet 401 V 1.0, 2020-04 5) Recalibration needed in case of a temperature change >20ºC 6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor. 7) For single ended input signals and gain1, the SNR is reduced by 6 dB. OPEN MARKET VERSION

Electrical Specification MHz Oscillator Data Sheet 402 V 1.0, 2020-04

3.9 MHz Oscillator

OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external outside of the device. Support of ceramic resonators is also provided. Table 3-22 OSC_XTAL Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input current at XTAL1 IIX1 CC -70 - 70 µA VIN>0V ; VIN<VEXT Oscillator frequency fOSC SR 4 - 40 MHz Direct Input Mode selected, if shaper is not bypassed 16 - 40 MHz External Crystal Mode selected Oscillator start-up time tOSCS C C --3 1) 1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an amplitude at XTAL1 of 0.3 * VEXT. This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease. ms 20MHz ≤ fOSC and 8pF load capacitance Input voltage at XTAL1 2) 2) For Supply ( VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause a damage or a reliability problem operating with an external crystal. VIX SR -0.7 - VEXT + 0.5 V If shaper is not bypassed Input amplitude (peak to peak) at XTAL1 VPPX SR 0.3* VEXT - VEXT + 1.0 V If shaper is not bypassed; fOSC > 25MHz 0.35*VEXT - VEXT + 1.0 V If shaper is not bypassed; fOSC ≤ 25MHz Internal load capacitor CL0 CC 1.30 1.40 1.55 pF enabled via bit OSCCON.CAP0EN Internal load capacitor CL1 CC 3.05 3.35 3.70 pF enabled via bit OSCCON.CAP1EN Internal load capacitor CL2 CC 7.85 8.70 9.55 pF enabled via bit OSCCON.CAP2EN Internal load capacitor CL3 CC 12.05 13.35 14.65 pF enabled via bit OSCCON.CAP3EN Internal load stray capacitor between XTAL1 and XTAL2 CXINTS CC 1.15 1.20 1.25 pF Internal load stray capacitor between XTAL1 and ground CXTAL1 CC - 2.5 4 pF Duty cycle at XTAL1 3) DCX1 SR 35 - 65 % VXTAL1 = 0.5*VPPX Slew rate at XTAL1 3) SRXTAL1 SR 0.3 - - V/ns Maximum 30% difference between rising and falling slew rate OPEN MARKET VERSION

Electrical Specification MHz Oscillator Data Sheet 403 V 1.0, 2020-04 Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. 3) Square wave input signal for XTAL1. OPEN MARKET VERSION

Electrical Specification Back-up Clock Data Sheet 404 V 1.0, 2020-04

3.10 Back-up Clock

The back-up clock provides an alternative clock source. Table 3-23 Back-up Clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Back-up clock accuracy before trimming fBACKUT CC 70 100 130 MHz VEXT≥2.97V Back-up clock accuracy after trimming 1) 1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for temperature and voltage drifts up to temperatures of 125 celcius fBACKT CC 98 100 102 MHz VEXT≥2.97V Standby clock fSB CC 25 70 110 kHz VEXT≥2.97V OPEN MARKET VERSION

Electrical Specification Temperature Sensor Data Sheet 405 V 1.0, 2020-04

3.11 Temperature Sensor

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Measurement time for each conversion 1) 1) After warm reset tM is not restarted and is measured from last conversion. tM CC - - 2.7 ms Measured from cold power-on reset release Calibration reference accuracy TCALACC CC -1 - 1 °C calibration points @ TJ=-40°C and TJ=127°C Accuracy over temperature range TNL CC -2 - 2 °C TCALACC has to be added in addition DTS temperature range TSR SR -40 - 170 °C Table 3-25 DTS Core Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Measurement time for each conversion 1) 1) After warm reset tM is not restarted and is measured from last conversion. tM CC - - 2.7 ms Measured from cold power-on reset release Temperature difference between on chip temperature sensors ΔT CC -3 - 3 °C Calibration reference accuracy TCALACC CC -2 - 2 °C calibration points @ TJ=-40°C and TJ=127°C Accuracy over temperature range TNL CC -2 - 2 °C TCALACC has to be added in addition DTS temperature range TSR SR -40 - 170 °C OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 406 V 1.0, 2020-04

3.12 Power Supply Current

The total power supply current defined below consists of leakage and switching component. Application relevant values are typically lower than those given in the following table and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: The real (realistic) power pattern defines the following conditions:

• TJ = 150 °C
• fSRI = fCPUx =3 0 0M H z
• fGTM = 200 MHz
• fSPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx =1 0 0 M H z
• VDD =1 . 2 7 5V
• VDDP3 / FLEX = 3.366 V
• VEXT / EVRSB / M = VDDM =5 . 1V
• all cores are active including t wo lockstep cores at IPC = 0.6
• the following periphe rals are inactive: HSM, Ethernet, PSI5, I2C, FCE, and MTU The max (maximum) power pattern defines the following conditions:
• TJ = 150 °C
• fSRI = fCPUx =3 0 0M H z
• fGTM = 200 MHz
• fSPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx =1 0 0 M H z
• VDD =1 . 3 7 5V
• VDDP3 / FLEX = 3.63 V
• VEXT / EVRSB / M = VDDM =5 . 5V
• all cores are active including t wo lockstep cores at IPC = 1.2
• the following periphe rals are inactive: GETH, FCE, and MTU Table 3-26 Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ∑ Sum of IDD core and peripheral supply currents (incl. IDDPORST+ ∑ IDDCx0+ ∑ IDDCxx+ IDDGTM+IDDSB) IDDRAIL CC - - 650 mA max power pattern - - 500 mA real power pattern IDD core current during active power-on reset (PORST pin held low). Leakage current of core domain. 1) IDDPORST CC --9 5 m A VDD = 1.275V; TJ=125°C --1 6 6 m A VDD = 1.275V; TJ=150°C --2 3 0 m A VDD = 1.275V; TJ=165°C OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 407 V 1.0, 2020-04 ∑ Sum of IDDP3 3.3 V supply currents IDDP3RAIL CC - - 45 mA max power pattern incl. Flash read current and Dflash programming current. --3 6 2) mA real power pattern incl. Flash read current and Dflash programming current. ∑ Sum of external IEXT supply currents (incl. IEXTFLEX+IEVRSB+IEXTLVDS) IEXTRAIL CC - - 44 mA max power pattern - - 34 mA real power pattern IEXT and IFLEX supply current IEXTFLEX C C --1 8 3) mA real power pattern with port activity absent; PORST output inactive. IEVRSB supply current 1) IEVRSB CC - - 8.5 mA real power pattern; PMS/EVR module current considered without SCR and Standby RAM during RUN mode. ∑ Sum of external IDDM supply currents (incl. IDDMEVADC+IDDMEDSADC) IDDM CC - - 27 mA real power pattern; sum of currents of EDSADC and EVADC modules ∑ Sum of all currents (incl. IEXTRAIL+IDDMRAIL+IDDx3RAIL+IDD) IDDTOT CC - - 597 mA real power pattern; TJ=150°C ∑ Sum of all currents with DC- DC EVRC regulator active 4) IDDTOTDC3 CC - - 380 mA real power pattern; EVRC reset settings with 72% efficiency; VEXT = 3.3V ∑ Sum of all currents with DC- DC EVRC regulator active 4) IDDTOTDC5 CC - - 280 mA real power pattern; EVRC reset settings with 72% efficiency; VEXT = 5V ∑ Sum of all currents (SLEEP mode) 1) ISLEEP CC - - 25 mA All CPUs in idle, All peripherals in sleep, fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C Table 3-26 Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 408 V 1.0, 2020-04 ∑ Sum of all currents (STANDBY mode) drawn at VEVRSB supply pin 5) ISTANDBY C C --1 3 0 6) µA 32 kB Standby RAM block active. SCR inactive. Power to remaining domains switched off. TJ = 25°C; VEVRSB = 5V Maximum power dissipation PD SR - - 1495 mW max power pattern - - 1080 mW real power pattern 1) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22. 2) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to x mA for maximum x us which is handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal considerations. 3) The current consumption inclu des only minimal port activity. 4) The total current drawn from e xternal regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and IDDM. 5) The same current limits apply also for the other power pattern. 6) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current + ISCRSB if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby SRAM contributes less than 10uA to ISTANDBY current. Table 3-27 Module Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. IDDP3 supply current for programming of a Pflash or Dflash bank 1) IDDP3PROG CC - - 25 mA Pflash 3.3V programming current adder when using external 3.3V supply. --9 2) mA Pflash 3.3V programming current adder when using external 5V supply. IEXT supply current added by LVDS pads in LVDS mode 1) IEXTLVDS CC - - 3 mA real power pattern; 2 pairs of LVDS pins active with receive function - - 12 mA real power pattern; 3 pairs of LVDS pins active with transmit function Table 3-26 Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 409 V 1.0, 2020-04 ∑ Sum of external IDDM supply currents (incl. IDDMEVADC+IDDMEDSADC) IDDM CC - - 14 mA real power pattern; current for EDSADC modules only and EVADC modules are inactive; 11 EDSADC channels active continuously. --2 2 3) mA max power pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active continuously. - - 13 mA real power pattern; current for EVADC modules only and EDSADC modules are inactive; 12 EVADC modules active. --1 5 4) mA max power pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active. IDDP3 supply current for erasing of a Pflash or Dflash bank IDDP3ERASE CC - - 25 mA Pflash 3.3V erasing current adder when using external 3.3V supply. SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin ISCRSB CC - - 7.5 mA SCR p ower pattern incl. PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C - 0.150 - mA SCR power pattern incl. PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C SCR 8-bit Standby Controller CPU in IDLE mode 5) ISCRIDLE CC - - 3.5 mA real power pattern. CPU set into idle mode. Table 3-27 Module Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 410 V 1.0, 2020-04

3.13 Power Supply Infrastru cture and Supply Start-up

1) The same current limits apply also for the other power pattern. 2) During Pflash programming at 5V , additional 2 mA is drawn at VEXT supply rail. 3) A single DS channel in stance consumes 4 mA. 4) A single VADC unit consumes 1.3 mA. 5) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22. Table 3-28 Module Core Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. IDD core current of CPUx main core with CPUx lockstep core inactive IDDCx0 CC - - 70 mA max power pattern; IPC=1.2 - - 45 mA real power pattern; IPC=0.6 IDD core current of CPUx main core with CPUx lockstep core active IDDCxx CC - - IDDCx0 + mA max power pattern; IPC=1.2 -- IDDCx0 + mA real power pattern; IPC=0.6 IDD core current added by GTM IDDGTM CC - - 90 mA max power pattern - - 75 mA real power pattern; TIMx, TOMx, ATOMx , MCSx active. 2 clusters at 200 MHz. - - 50 mA TIMx, TO Mx active at 100MHz. ATOMx , MCSx, DPLL inactive. 2 clusters at 100 MHz. IDD core current added by HSM IDDHSM C C --2 0 1) 1) The current consumption inclu des basic HSM activity incl. AES module. mA max power pattern; HSM running at 100MHz. IDD core dynamic current added by LBIST IDDLBIST C C --2 0 0 2) 2) LBIST is executed either durin g start-up phase or can be triggered by application software. Secondary voltage monitors are inactive during the LBIST execution time (tLBIST). During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static accuracy. If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit. mA LBIST Configuration A; 1.2V ≤ VDD IDD core dynamic current added by MBIST IDDMBIST CC - - 200 mA fMBIST = 300MHz; tMBIST < 6ms. MTU Ganging procedure for SRAM test and initialization; VDD = 1.375V. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 411 V 1.0, 2020-04

3.13.1 Supply Ramp-up a nd Ramp-down Behavior

3.13.1.1 Single S upply mode (a)

Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply VEXT (externally supplied) EVRC & EVR33 Ramp-up Phase 0 V 5.0 V VRST5 Firmware ExecutionBasic Supply & Clock Infrastructure User Code Execution 0 V 1.25 V VDD (internally generated by EVRC) VRSTC Primary Reset Threshold 5.5 V 4.5 V 1.375 V Power Ramp-down phase fCPU0 =100MHz default on firmware exit Startup_Diag_2 v 0.3 0 V 3.30 V 3.63 V VRST33 VDDP3 (internally generated by EVR33) Primary Reset Threshold PORST (output driven by PMS) PORST (input driven by external regulator) VLVDRST5 tBP (incl. tEVRstartup) tEVRstartup (incl. tSTR) PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds EVR33 is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD PORST input deasserted by external regulator when all input voltages have reached their minimum operational level EVR33_tSTR EVRC_tSTR Primary cold PORST Reset Threshold LVD Reset release HWCFG[1,2] latch VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 412 V 1.0, 2020-04 VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal regulators.

• The rate at which current is dr awn from the external regulator (dIEXT /dt) is limited during the basic infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification.
• Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA (dIDD) is expected.
• The power sequence as shown in Figure 3-3 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal pre-regulator VDDPD voltage has reached VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated. PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up. PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 413 V 1.0, 2020-04

3.13.1.2 Single S upply mode (e)

Figure 3-4 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator.

• The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA (dIDD) is expected. EV RC Ra mp-up Phase 0 4 Firmware ExecutionBasic Supply & Clock Infrastructure User Code Execution 0 V 1.25 V VDD (internally generated by EVRC) VRSTC Primary Reset Threshold 1.375 V Power Ramp-down phase fCPU0 =100MH z defaul t on firmware exit Startup_Diag_4 v 0.3 PORST (output driven by PMS) PORST (input driven by external regulator) 0 V 3.30 V 3.63 V VRST5/ VRST33 VEXT/VDDP3 (externally supplied) VLVDRST5 tBP (incl. tEVRstartup) tEVRstartup (incl. tSTR) PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds EVRC is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD PORST input deasserted by external regulator when all input voltages have reached their minimum operational level EVRC_tSTR Primary cold PORST Reset T hreshold LVD Reset release HWCFG[1,2] latch VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 414 V 1.0, 2020-04

• The power sequence as shown in Figure 3-4 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal pre-regulator VDDPD voltage has reached VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input) does not have any affect on EVRC output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is de- asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 415 V 1.0, 2020-04

3.13.1.3 External Supply mode (d)

Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.

• External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. In case VDD VEXT (externally supplied) EVR33 Ramp-up Phase POR ST (output dri ven by PMS) 0 V 5.0 V VRST5 Primary cold PORST Reset Threshold Firmware ExecutionBasic Supply & Clock Infrastructure PORST (input driven by external regulator) User Code Execution 0 V 1.25 V VDD (externally supplied) VRSTC Primary Reset Threshold 5.5 V 4.5 V 1.375 V Power Ramp-down phase fCPU0 =100MHz default on firmware exit Startup_Diag_1 v 0.3 0 V 3.30 V 3.63 V VRST33 VDDP3 (internally generated by EVR33) Primary Reset Threshold LVD Reset release HWCFG[1,2] latch VLVDRST5 tBP (incl. tEVRstartup) tEVRstartup (incl. tSTR) PORST output deasserted when VDD, VDDP3 and VEXT voltage above re spective prim ar y r eset th resholds EVR33 is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD PORST input deasserted by external regulator when all input voltages have reached their minimum operational level EVR33_tSTR VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 416 V 1.0, 2020-04 voltage rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the operational voltage range.

• The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds. The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA (dIDD) is expected.
• The power sequence as shown in Figure 3-5 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal pre-regulator VDDPD voltage has reached VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input) does not have any affect on EVR33 output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is de- asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 417 V 1.0, 2020-04

3.13.1.4 External Supply mode (h)

Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied All supplies, namely VEXT, VDDP3 & VDD are externally supplied.

• External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to (datasheet parameter) SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails. In case smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall be limited within the operational voltage ranges of the respective rails. VEXT (externally supplied) 0 V 5.0 V VRST5 Firmware ExecutionBasic Supply & Clock Infrastructure User Code Execution 0 V 1.25 V VDD (externally supplied) VRSTC Primary Reset Threshold 5.5 V 4.5 V 1.375 V Power Ramp-down phase fCPU0 =100MH z defaul t on firmware exit Startup_Diag_3 v 0.4 0 V 3.30 V 3.63 V VRST33 VDDP3 (externally supplied) Primary Reset Threshold PORST (input driven by external regulator) POR ST (output driven by PMS) tPOA time to ensure adequate ti me between reset releases VLVDRST5 tBP PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds Primary cold PORST Reset T hreshold LVD Reset release HWCFG[1,2] latch VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 418 V 1.0, 2020-04

• The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA (dIDD) is expected.
• The power sequence as shown in Figure 3-6 is enumerated below – T1 up to T3 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal pre-regulator VDDPD voltage has reached VLVDRSTC level. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Reset Timing Data Sheet 419 V 1.0, 2020-04

3.14 Reset Timing

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Application Reset Boot Time tB CC - - 400 µs operating with max. frequencies, with valid BMI header System Reset Boot Time tBS CC - - 1.1 ms RAM initialization and HSM boot time are not included, with valid BMI header Cold Power on Reset Boot Time 1) tBP C C --3 . 1 m s dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time after Cold PORST including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot time are not included. - - 1.6 ms Firmware execution time after PORST release without EVR ramp-up; RAM initialization and HSM boot time is not included Minimum cold PORST reset hold time in case of power fail event issued by EVR primary monitors tEVRPOR CC 10 2) - - µ s PMS Infrastructure, EVRC and EVR33 overall start-up time till cold PORST reset release tEVRstartup CC --1 m s dV/dT=1V/ms. EVRC and EVR33 active Minimum PORST active hold time externally after power supplies are stable at operating levels after start-up tPOA SR 1 3) - - m s Configurable PORST digital filter delay in addition to analog pad filter delay tPORSTDF CC 600 - 1200 ns Warm Reset Sequencing Delay tWARMRSTSEQ CC --1 8 0 µ s HWCFG pins hold time from ESR0 rising edge tHDH CC 16 / fSPB - - n s OPEN MARKET VERSION

Electrical Specification Reset Timing Data Sheet 420 V 1.0, 2020-04 HWCFG pins setup time to ESR0 rising edge tHDS CC 0 - - ns Ports inactive after ESR0 reset active tPI CC 8000/ fBAC KT - 18000/ fBA CKT s Ports inactive after PORST reset active tPIP C C --1 6 0 n s Hold time from PORST rising edge tPOH SR 150 - - ns Setup time to PORST rising edge tPOS SR 0 - - ns Warm PORST reset boot time tBWP CC - - 1.5 ms without RAM initalization LBIST execution time extending the boot time tLBIST CC - - 6 ms LBIST Configuration A; 1.2V ≤ VDD SCR reset boot time tSCR CC - - 5 µs User Mode 0 - - 16 µs User Mode 1 - 13.3 - µs WDT double bit ECC, soft reset Minimum external supplies hold time after warm reset assertion tSUPHOLD CC - - 250 µs external supplies are VEVRSB, VEXT, VFLEX, VDDM, VDDP3 and VDD 1) RAM initialization add 500µs in addition. 2) Cold PORST reset is driven b y uC and maintained in an extended voltage range between VDDPPA limit and absolute maximum rating voltage limits. 3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. Table 3-29 Reset (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Reset Timing Data Sheet 421 V 1.0, 2020-04 Figure 3-7 Power, Pad and Reset Timing reset_beh_aurix VDDP PORST Pads Pad- state undefined VDD VDDPPA VDDPPA Pad- state undefined VDDPR Programmed Z / HTristate Z / pullup H tPOA tPOA HWCFG ESR 0 tPI P Z / H Cold Warm tHDH TESTMODE tPOS tPOH tPOS tPOHTRST t PI Programmed Programmed tPI power -on config tHDA tHDH config tHDA tHDH config OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 422 V 1.0, 2020-04

3.15 EVR

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input voltage range VIN SR 3.60 1) - 5.50 V Normal RUN mode 2.97 2) - 5.50 V Low voltage cranking mode Output voltage operational range including load/line regulation and aging 3) VOUT CC 2.97 3.3 3.63 V Normal RUN mode 2.60 3.3 3.63 V Low voltage cranking mode; IDDP3=50mA Output VDDx3 static voltage accuracy after trimming and aging without dynamic load/line regulation. VOUTT CC 3.225 3.3 3.375 V Normal RUN mode 2.78 3.3 3.375 V Low voltage cranking mode; IDDP3=50mA Output buffer capacitance on VOUT COUT SR 1.45 2.2 3 µF Output buffer capacitor ESR COUTESR S R --1 0 0 4) mOhm f > 0.5MHz; f < 10MHz Maximum output current of the regulator IMAX CC 60 5) - - mA Normal RUN mode Startup time tSTR CC - 500 1000 µs Normal RUN mode External VIN supply ramp 6) dVin/dt SR - 1 - V/ms Ripple on Output Voltage Δ VOUTTC CC --3 3 m V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IOUTTC ≥ 10mA ; IOUTTC ≤ 60mA; ΔVOUTTC = (peak to peak ripple / 2) Load step response 7) dVout/dIout CC -165 - - mV Normal RUN mode; dI=10 to 60mA; dt=20ns; Tsettle=20us - - 165 mV Normal RUN mode; dI=60 to 10mA; dt=20ns; Tsettle=20us -180 - - mV Low voltage cranking mode; dI=10 to 50 mA; dt=20ns; Tsettle=20us - - 180 mV Low voltage cranking mode; dI=50 to 10mA; dt=20ns; Tsettle=20us OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 423 V 1.0, 2020-04 Line step response dVout/dVin CC --4 0 m V dVin/dT=1V/ms; dV= 3.6 to 5V; IMAX=60mA -40 - - mV dVin/dT=1V/ms; dV= 5 to 3.6V; IMAX=60mA --2 8 0 m V dVin/dT=50V/ms; dV= 3.6 to 5V; IMAX=60mA -165 - - mV dVin/dT=50V/ms; dV= 5 to 3.6V; IMAX=60mA 1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device performance during normal operation. 2) VEXT Input voltage drop up to 2.97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched before to low performance mode. 3) No external inductive load permissible if EVR33 is used. 4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm. An additional decoupling capacitor of 100nF shall be located close to the pin before Cout. 5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator. 6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid overshoots. 7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device. Table 3-30 EVR33 LDO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 424 V 1.0, 2020-04 Table 3-31 Supply Monitors Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Primary Undervoltage Reset threshold for VDDP3 before trimming 1) VRST33 CC - - 3.00 V by reset release before EVR trimming on supply ramp-up Primary undervoltage reset threshold for VDD before trimming VRSTC CC - - 1.138 V by reset release before trimming on supply ramp-up including 2 LSB voltage Hysteresis VEXT primary undervoltage monitor accuracy after trimming 2) VEXTPRIUV CC 2.86 2.92 2.97 V VEXT = Undervoltage cold PORST Primary Monitor Threshold VDDP3 primary undervoltage monitor accuracy after trimming 2) VDDP3PRIUV CC 2.86 3) 2.90 2.97 V VDDP3 = Undervoltage cold PORST Primary Monitor Threshold VDD primary undervoltage monitor accuracy after trimming 2) VDDPRIUV CC 1.08 3) 1.105 1.125 V VDD = Undervoltage cold PORST Primary Monitor Threshold EVR primary monitor measurement latency for a new supply value tPRIUV CC - - 300 ns The supply ramp / line jump slope is limited to 50V/ms for VEXT, VDDP3 and VDD rails. VEXT, VDDM & VEVRSB secondary supply monitor accuracy after trimming 4) 5) VEXTMON CC 3.2 3.3 3.4 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=3.3V=90h( OV,UV). For BGA packages: EVRMONFILT.SWDFI L=1. 3.2 3.3 3.4 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=3.3V=90h( OV,UV). For QFP packages: EVRMONFILT.SWDFI L=2 OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 425 V 1.0, 2020-04 4.5 4.6 4.7 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=4.6V=C8h( UV)/C9h(OV). For BGA packages: EVRMONFILT.SWDFI L=1 4.5 4.6 4.7 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=4.6V=C8h( UV)/C9h(OV). For QFP packages: EVRMONFILT.SWDFI L=2 5.3 5.4 5.5 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5.4V=EAh( UV)/ECh(OV). For BGA packages: EVRMONFILT.SWDFI L=1 5.3 5.4 5.5 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5.4V=EAh( UV)/ECh(OV). For QFP packages: EVRMONFILT.SWDFI L=2 4.9 5.0 5.1 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5V=D9h(UV )/DAh(OV). For BGA packages: EVRMONFILT.SWDFI L=1 Table 3-31 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 426 V 1.0, 2020-04 4.9 5.0 5.1 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5V=D9h(UV )/DAh(OV). For QFP packages: EVRMONFILT.SWDFI L=2 VDDP3 secondary supply monitor accuracy after trimming 5) VDDP3MON CC 2.97 3.035 3.1 V EVR33xxVAL monitoring threshold=3.035V=CB h(UV)/CCh(OV). EVRMONFILT.EVR33 FIL = 3. 3.235 3.30 3.365 V EVR33xxVAL monitoring threshold=3.3V=DDh( OV,UV). EVRMONFILT.EVR33 FIL = 3. 3.5 3.565 3.63 V EVR33xxVAL monitoring threshold=3.565V=EE h(UV)/EFh(OV). EVRMONFILT.EVR33 FIL = 3. VDD & VDDPD secondary supply monitor accuracy after trimming 5) VDDMON CC 1.125 1.15 1.175 V EVRCxxVAL & PRExxVAL monitoring threshold=1.15V=C7h( UV)/C8h(OV). EVRMONFILT.EVRC FIL = 1. 1.225 1.25 1.275 V EVRCxxVAL & PRExxVAL monitoring threshold=1.25V=D9h( OV,UV). EVRMONFILT.EVRC FIL = 1. 1.325 1.35 1.375 V EVRCxxVAL & PRExxVAL monitoring threshold=1.35V=EAh (UV)/EBh(OV). EVRMONFILT.EVRC FIL = 1. Table 3-31 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 427 V 1.0, 2020-04 VEXT LVD Primary undervoltage reset Monitor threshold VLVDRST5 CC 2.3 - 2.72 V Power-down 2.4 - 2.75 V Power-up VEVRSB LVD Primary undervoltage reset Monitor threshold VLVDRSTSB CC 2.18 - 2.47 V Power-down 2.21 - 2.5 V Power-up VEXT and VEVRSB PBIST primary overvoltage Monitor threshold VPBIST5 C C 5 . 6 3 --V Primary undervoltage reset threshold for VEXT before trimming VRST5 CC - - 3.0 V by last cold PORST release on supply ramp-up including voltage hysteresis. EVR secondary monitor measurement latency for all 6 supply rails tMON CC - - 3.2 µs HPOSC and SHPBG bandgap trimmed. Filter inactive. 1) The reset release on supply ramp-up is delayed by a time dura tion 20-40 us after reaching undervoltage reset threshold and by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin. 2) The monitor tolerances constit ute the inherent variation of the band gap and ADC over process, voltage and temperature operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the VxxPRIUV limits. All voltages are measured on pins. 3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware and reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a voltage hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior. 4) In case the application is using 3.3V single supply (Single S upply mode (e), i.e. VEXT and VDDP3 are shorted together), it is recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter VDDP3MON. 5) To monitor voltage level not p rovided in conditions the values for OV and UV thresholds can be generated by a linear interpolation or extrapolation based on the given points. Table 3-32 Supply Ramp Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. External VEXT & VEVRSB supply ramp-up and ramp-down slope 1) 2) 3) dVEXT/dt SR 8.3E-6 1 100 V/ms External VDDP3 supply ramp-up and ramp-down slope 1)3) dVDDP3/dt SR 8.3E-6 1 100 V/ms External VDD supply ramp-up and ramp-down slope 1)3) dVDD/dt SR 8.3E-6 1 100 V/ms External VDDM supply ramp-up and ramp-down slope 1)3) dVDDM/dt SR 8.3E-6 1 100 V/ms Table 3-31 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 428 V 1.0, 2020-04 Up to 1,000,000 power cycles, matching the limits defined in table ‘Supply Ramp’, are allowed for TC36x without any restriction to reliability. 1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation. 2) Also valid in case EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid overshoots. 3) The slope is defined as the ma ximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. Table 3-33 EVRC SMPS Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input VEXT Voltage range VIN SR 2.97 - 5.5 V Start-up VEXT voltage > 2.6 V SMPS regulator output voltage range including load/line regulation and aging VDDDC CC 1.125 - 1.375 V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 1mA ; IDDDC ≤ 500mA ; untrimmed SMPS regulator static voltage output accuracy after trimming without dynamic load/line regulation. VDDDCT CC 1.225 1.25 1.275 V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 1mA ; IDDDC ≤ 500mA Programmable switching frequency fDCDC SR 1.6 1.82 2.0 MHz Start-up frequency switches from 500 KHz in open loop operation to 1.82 MHz in closed loop Operation. - 0.8 - MHz Start-up frequency switches from 500 KHz in open loop operation to 1.82 MHz in closed loop Operation. 0.8 MHz to be set in SW. Startup time tSTRDC CC - - 900 µs SMPS Start-up Mode. It is is defined beween VEXTPRIUV reset threshold till PORST release, on condition that all other PORST requirements were released before. ISTART < 350mA. Switching frequency modulation spread ΔfDCSPR CC - 1.8% - MHz OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 429 V 1.0, 2020-04 Maximum ripple at IMAX Δ VDDDC C C --1 6 m V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 300mA ; IDDDC ≤ 500mA ; ΔVDDDC = (Peak to Peak ripple / 2) No load current consumption of SMPS regulator IDCNL CC - 15 19 mA fDCDC=1.82MHz; IDDDC=ISLEEP; VEXT >

2.97 V; TJ=25°C

• 5 - mA LPM mode; IDDDC=ISLEEP; VEXT >

SMPS regulator load transient response dVDDDCT / dlOUT CC -50 - 75 mV dI < -250mA ; IDDDC=280-500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=100 us -26 - 26 mV dI < 100mA ; IDDDC=50-500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=20us; Maximum output current IMAX CC 100 - - mA LPM mode. Typical current in LPM Mode = ISLEEP 500 - - mA limited by thermal constraints and component choice SMPS regulator line transient response dVDDDCT / dVIN CC -75 - 75 mV dV/dT=120V/ms; dV < 2.97 - 5.5V ; IDDDC=50- 500mA; -12.5 - 12.5 mV dV/dT=1V/ms; dV < 2.97 - 5.5V ; IDDDC=50- 500mA; SMPS regulator efficiency nDC CC - 80 - % VIN=3.3V; IDDDC=500mA; fDCDC=1.82MHz -7 5 -% VIN=5V; IDDDC=500mA; fDCDC=1.82MHz Input Synchronisation frequency fDCDCSYNC SR 1.6 1.82 2.0 MHz fDCDC =1.82MHz 0.66 0.8 0.94 MHz fDCDC=0.8MHz Table 3-33 EVRC SMPS (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification EVR Data Sheet 430 V 1.0, 2020-04 Table 3-34 EVRC SMPS External components Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. External output capacitor value 1) Capacitor min-max range represent typical +-35% tolerance inc luding DC bias effect. The trace resistance from the capacitor to the supply or ground rail should be limited to 25 mOhm. COUT SR 13 20 27 µF IDDDC=500 mA; fDDDC = 0.8MHz 9.6 14.7 19.8 µF IDDDC=500mA; fDDDC = 1.82MHz External output capacitor ESR COUT_ESR SR - - 50 mOhm f≥0.5MHz ; f≤10MHz - - 100 Ohm f=10Hz External input capacitor value 1) CIN SR 4.42 6.8 9.18 µF IDDDC=500mA External input capacitor ESR CIN_ESR SR - - 50 mOhm f≥0.5MHz ; f≤10MHz - - 100 Ohm f=100Hz External inductor value LDC SR 3.29 4.7 6.11 fDCDC=0.8MHz 2.31 3.3 4.29 µH fDCDC=1.82MHz External inductor DCR LDC_DCR SR - - 0.2 Ohm P + N-channel MOSFET logic level VLL S R --2 . 5 V P + N-channel MOSFET drain source breakdown voltage |VBR_DS| SR +7 - - V NMOS - VGS = 0. - - -7 V PMOS - VGS = 0. P + N-channel MOSFET drain source ON-state resistance RON SR - - 200 mOhm IDDDC=500mA; |VGS|=2.5V ; TA=25°C P + N-channel MOSFET Gate Charge QG S R --4 n C IDDDC=500mA; NMOS- |VGS|=5V; 0.5A pulsed drain current -4 - - nC IDDDC=500mA; PMOS- |VGS|=5V; 0.5A pulsed drain current External Inductor Saturation Current Margin ΔISAT SR 400 - - mA The saturation current of the coil must be larger than IDDDC + ΔISAT P + N-channel MOSFET Gate threshold voltage VGSTH SR - 1 - V NMOS -- 1 -V P M O S N-channel MOSFET reverse diode forward voltage VRDN SR - 0.8 - V OPEN MARKET VERSION

Electrical Specification System Phase Locked Loop (SYS_PLL) Data Sheet 431 V 1.0, 2020-04

3.16 System Phase Locked Loop (SYS_PLL)

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Table 3-35 PLL System Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DCO Input frequency range fREF CC 10 - 40 MHz Modulation Amplitude MA CC 0 - 2 % Peak Period jitter DP CC -200 - 200 ps without modulation (PLL output frequency) Peak Accumulated Jitter DPP CC -5 - 5 ns without modulation Total long term jitter JTOT CC - - 11.5 ns including modulation; MA 1.25%; fREF 20MHz System frequency deviation fSYSD CC - - 0.01 % with active modulation DCO frequency range fDCO CC 400 - 800 MHz PLL lock-in time tL CC 4 - 100 µs OPEN MARKET VERSION

Electrical Specification Peripheral Phase Locked Loop (PER_PLL) Data Sheet 432 V 1.0, 2020-04

3.17 Peripheral Phase Locked Loop (PER_PLL)

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Table 3-36 PLL Peripheral Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Peak Accumulated jitter at SYSCLK pin DPP CC -1000 - 1000 ps Peak only Peak accumulated jitter DPPI CC -700 - 700 ps Peak only RMS Accumulated jitter DRMS CC -100 - 100 ps measured over 1 µs; fREF = 20 MHz and fDCO = 640 MHz or fREF = 25 MHz and fDCO = 800 MHz Peak Period jitter DP CC -200 - 200 ps fDCO = 640 MHz or fDCO = 800 MHz

640 MHz

800 MHz

DCO frequency range fDCO CC 400 - 800 MHz DCO input frequency range fREF CC 10 - 40 MHz PLL lock-in time tL CC 4 - 100 µs OPEN MARKET VERSION

Electrical Specification AC Specifications Data Sheet 433 V 1.0, 2020-04

3.18 AC Specifications

All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted in column Note / Test Condition. Unless otherwise noted in the figures the timings are defined with the following guidelines: Figure 3-8 Definition of rise / fall times Figure 3-9 Time Reference Point Definition 10% 90% 10% 90% VSS VEXT/FLEX /V DDP 3 tr rise_fall tf timing _reference VEXT/FLEX /VDDP3 Timing Reference Points VEXT /FLEX /V DDP 3 VSS VEXT/FLEX /V DDP 3 OPEN MARKET VERSION

Electrical Specification JTAG Parameters Data Sheet 434 V 1.0, 2020-04

3.19 JTAG Parameters

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Figure 3-10 Test Clock Timing (TCK) Table 3-37 JTAG Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. TCK clock period t1 SR 50 - - ns TCK high time t2 SR 10 - - ns TCK low time t3 SR 10 - - ns TCK clock rise time t4 S R --4 n s TCK clock fall time t5 S R --4 n s TDI/TMS setup to TCK rising edge t6 SR 6.0 - - ns TDI/TMS hold after TCK rising edge t7 SR 6.0 - - ns TDO valid after TCK falling edge (propagation delay) t8 CC 3.0 - - ns CL≤20pF --2 5 n s CL≤50pF TDO hold after TCK falling edge t18 CC 2 - - ns TDO high impedance to valid from TCK falling edge t9 C C --2 5 n s CL≤50pF TDO valid output to high impedance from TCK falling edge t10 C C --2 5 n s CL≤50pF MC_JTAG_TCK

0.9 VEXT

0.5 VEXT

0.1 VEXT

Electrical Specification JTAG Parameters Data Sheet 435 V 1.0, 2020-04 Figure 3-11 JTAG Timing t6 t7 t6 t7 t9 t8 t10 TCK TMS TDI TDO MC_JTAG t18 OPEN MARKET VERSION

Electrical Specification DAP Parameters Data Sheet 436 V 1.0, 2020-04

3.20 DAP Parameters

The following parameters are applicable for communication through the DAP debug interface. Table 3-38 DAP Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DAP0 clock rise time t14 S R --1 n s f = 1 6 0 M H z - - 4 ns f=40MHz - - 2 ns f=80MHz DAP0 clock fall time t15 S R --1 n s f = 1 6 0 M H z - - 4 ns f=40MHz - - 2 ns f=80MHz DAP1 setup to DAP0 rising edge t16 SR 4 - - ns 5 - - ns f=40MHz DAP1 hold after DAP0 rising edge t17 SR 2 - - ns DAP1 valid per DAP0 clock period t19 CC 4 - - ns CL=20pF ; f=160MHz 8 - - ns CL=20pF ; f=80MHz 10 - - ns CL=50pF ; f=40MHz DAP0 high time t12 SR 2 - - ns DAP0 low time t13 SR 2 - - ns DAP0 clock period t11 SR 6.25 - - ns Table 3-39 SCR DAP Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DAP0 clock rise time t14 SR - - 8 ns f=20MHz DAP0 clock fall time t15 SR - - 8 ns f=20MHz DAP1 setup to DAP0 rising edge t16 SR 10 - - ns DAP1 hold after DAP0 rising edge t17 SR 10 - - ns DAP1 valid per DAP0 clock period t19 CC 30 - - ns CL=20pF ; f=20MHz DAP0 high time t12 SR 15 - - ns DAP0 low time t13 SR 15 - - ns DAP0 clock period t11 SR 50 - - ns OPEN MARKET VERSION

Electrical Specification DAP Parameters Data Sheet 437 V 1.0, 2020-04 Figure 3-12 DAP Timing Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. (Host to Device) DAP11),2) (Device to Host) 1) The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. 2) No explicite setup and hold times are given for DAP1 for the direction Device to Host. Only t11 and t19 are guaranteed and the tool may set the sample point freely. OPEN MARKET VERSION

Electrical Specification ASCLIN SPI Master Timing Data Sheet 438 V 1.0, 2020-04

3.21 ASCLIN SPI Master Timing

This section defines the timings for the ASCLIN in the TC36x. Note: Pad asymmetry is already included in the following timings. Table 3-40 Master Mode strong sharp (ss) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLKO clock period t50 CC 20 - - ns CL=25pF Deviation from ideal duty cycle t500 CC -2 - 2 ns CL=25pF MTSR delay from ASCLKO shifting edge t51 CC -3.5 - 3.5 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC -3 - 3.5 ns CL=25pF MRST setup to ASCLKO latching edge t52 SR 25 - - ns CL=25pF MRST hold from ASCLKO latching edge t53 SR -2 - - ns CL=25pF Table 3-41 Master Mode strong medium (sm) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLKO clock period t50 CC 50 - - ns CL=50pF Deviation from ideal duty cycle t500 CC -5 - 5 ns CL=50pF MTSR delay from ASCLKO shifting edge t51 CC -7 - 7 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -7 - 7 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 35 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=50pF Table 3-42 Master Mode medium (m) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLKO clock period t50 CC 160 - - ns CL=50pF Deviation from ideal duty cycle t500 CC -10 - 10 ns CL=50pF MTSR delay from ASCLKO shifting edge t51 CC -20 - 20 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -20 - 20 ns CL=50pF OPEN MARKET VERSION

Electrical Specification ASCLIN SPI Master Timing Data Sheet 439 V 1.0, 2020-04 Figure 3-13 ASCLIN SPI Master Timing MRST setup to ASCLKO latching edge t52 SR 80 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -15 - - ns CL=50pF Table 3-42 Master Mode medium (m) output pads (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLIN_TmgMM.vsd ASCLKO MTSR t51 t51 MRST t53 Data valid ASLSO t510 t50 t500 t52 Data valid OPEN MARKET VERSION

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 440 V 1.0, 2020-04

3.22 QSPI Timings, Master and Slave Mode

This section defines the timings for the QSPI in the TC36x. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings: Note: Pad asymmetry is already included in the following timings. Table 3-43 Master Mode Timing, LVDS output pads for data and clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 20 1) 1) The load ( CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to add an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply. - - ns CL=25pF Deviation from the ideal duty cycle t500 CC -1 1) -1 1) ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -3 1) -4 1) ns CL=25pF SLSOn deviation from the ideal programmed position t510 CC -4 1) -5 . 5 1) ns CL=25pF, driver strength ss -10 1) -1 0 1) ns CL=25pF, driver strength sm -30 1) -3 0 1) ns CL=25pF, driver strength m MRST setup to SCLK latching edge t52 SR 18 1) - - ns CL=25pF; valid for LVDS Input pads of QSPI2 only 19.5 1) - - ns CL=25pF; valid for LVDS Input pads of QSPI4 only MRST hold from SCLK latching edge t53 SR -1 1) - - ns CL=25pF; valid for LVDS Input pads only Table 3-44 Master Mode Strong Sharp (ss) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 50 - - ns CL=25pF Deviation from the ideal duty cycle t500 CC -2 - 2 ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -4 - 5 ns CL=25pF SLSOn deviation from the ideal programmed position t510 CC -4 - 5 ns CL=25pF MRST setup to SCLK latching edge t52 SR 25 1) 2) - - n s C L = 2 5 p F MRST hold from SCLK latching edge t53 SR -2 1)2) - - ns CL=25pF OPEN MARKET VERSION

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 441 V 1.0, 2020-04 1) For compensation of the avera ge on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are va lid for both settings of the input pads thresholds: TTL and AL. Table 3-45 Master Mode Strong Medium (sm) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 50 - - ns CL=50pF Deviation from the ideal duty cycle t500 CC -5 - 5 ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC -7 - 7 ns CL=50pF SLSOn deviation from the ideal programmed position t510 CC -7 - 7 ns CL=50pF MRST setup to SCLK latching edge t52 SR 35 1) 2) 1) For compensation of the avera ge on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are va lid for both settings of the input pads thresholds: TTL and AL. - - ns CL=50pF MRST hold from SCLK latching edge t53 SR -5 1)2) - - ns CL=50pF Table 3-46 Master Mode Medium (m) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 160 - - ns CL=50pF Deviation from the ideal duty cycle t500 CC -10 - 10 ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC -20 - 20 ns CL=50pF SLSOn deviation from the ideal programmed position t510 CC -20 - 20 ns CL=50pF MRST setup to SCLK latching edge t52 SR 80 1) 2) 1) For compensation of the avera ge on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are va lid for both settings of the input pads thresholds: TTL and AL. - - ns CL=50pF MRST hold from SCLK latching edge t53 SR -15 1)2) - - ns CL=50pF -13 1)2) - - ns CL=50pF; SCR SSC Table 3-47 Slave mode timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLK clock period t54 SR 4 x TMAX - - n s SCLK duty cycle t55/t54 SR 40 - 60 % OPEN MARKET VERSION

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 442 V 1.0, 2020-04 Figure 3-14 Master Mode Timing MTSR setup to SCLK latching edge t56 SR 6 - - ns Input Level AL 6 - - ns Input Level TTL MTSR hold from SCLK latching edge t57 SR 4 - - ns Input Level AL 6 - - ns Input Level TTL SLSI setup to first SCLK shift edge t58 SR 4 - - ns Input Level AL 6 - - ns Input Level TTL SLSI hold from last SCLK latching edge t59 SR 3 - - ns Input Level AL 6 - - ns Input Level TTL MRST delay from SCLK shift edge t60 CC 5 - 35 ns driver = strong edge = medium ; CL=50pF 2 - 24 ns driver = strong edge = sharp ; CL=50pF 15 - 80 ns medium driver ; CL=50pF 14 - - ns medium driver ; CL=50pF; SCR SSC Table 3-47 Slave mode timing (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. QSPI_TmgMM.vsd SCLK1)2) MTSR1) t51 MRST1) t53 Data valid SLSOn2) 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0. t50 t500 t52 Data valid SAMPLING POINT t510

0.5 VEXT/FLEX

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 443 V 1.0, 2020-04 Figure 3-15 Slave Mode Timing QSPI_TmgSM.vsd SCLKI1) t55 MTSR1) t57 Data valid t56 SLSI 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. t54 t55 t59 Last latching SCLK edge First latching SCLK edge t57 Data valid t56 MRST1) t60 First shift SCLK edge t60 t61 t58

Electrical Specification MSC Timing 5 V Operation Data Sheet 444 V 1.0, 2020-04

3.23 MSC Timing 5 V Operation

The following section defines the timings. Note: Pad asymmetry is already included in the following timings. Note: Load for LVDS pads are defined as differential loads in the following timings. Table 3-48 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA 1) 2) 1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC. 2) The capacitive load on the LVDS pins is differential, the cap acitive load on the CMOS pins is single ended. 3) The load ( CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply. - - ns LVDS; CL=50pF Deviation from ideal duty cycle t400 CC -1 3) -1 3) ns LVDS; 0 < CL < 50pF SOPx output delay t44 CC -3 3) -3 3) ns CL=50pF ENx output delay t45 CC -4 3) -5 3) ns ss; CL=50pF; ABRA block bypassed -4 3) -4 3) ns ss; CL=50pF; ABRA block used -2 3) -1 0 3) ns sm; CL=50pF -30 3) -3 0 3) ns m; CL=50pF Table 3-49 Strong sharp (ss) driver for clock/data valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA - - n s C L = 5 0 p F Deviation from ideal duty cycle t400 CC -2 - 2 ns CL=50pF SOPx output delay t44 CC -4 - 3.5 ns CL=50pF ENx output delay t45 CC -4 - 3.5 ns CL=50pF Table 3-50 Strong medium (sm) driver for clock/data valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA - - n s C L = 5 0 p F Deviation from ideal duty cycle t400 CC -5 - 5 ns CL=50pF SOPx output delay t44 CC -7 - 7 ns CL=50pF ENx output delay t45 CC -7 - 7 ns CL=50pF OPEN MARKET VERSION

Electrical Specification MSC Timing 5 V Operation Data Sheet 445 V 1.0, 2020-04 Figure 3-16 MSC Interface Timing Note: The SOP data signal is sampled with the falling edge of FCLP in the target device. Table 3-51 Medium (m) driver for clock/data valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA - - n s C L = 5 0 p F Deviation from ideal duty cycle t400 CC -10 - 10 ns CL=50pF SOPx output delay t44 CC -20 - 20 ns CL=50pF ENx output delay t45 CC -20 - 20 ns CL=50pF Table 3-52 Upstream Interface Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SDI bit time t46 SR 8 * tMSC - - n s SDI rise time t48 S R --2 0 0 n s SDI fall time t49 S R --2 0 0 n s MSC_Timing_A.vsd t44 t44 t40 SOP FCLP SDI t46 t48

0.1 VEXT/FLEX

0.9 VEXT/FLEX

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 446 V 1.0, 2020-04

3.24 Ethernet Interface (ETH) Characteristics

3.24.1 ETH Measurement Reference Points

Figure 3-17 ETH Measurement Reference Points ETH_Testpoints.vsd ETH Clock 1.4 V 1.4 V 2.0 V 0.8 V 2.0 V 0.8 V tR tF ETH I/O OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 447 V 1.0, 2020-04

3.24.2 ETH Management Signal Pa rameters (ETH_MDC, ETH_MDIO)

Figure 3-18 ETH Management Signal Timing Table 3-53 ETH Management Signal Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ETH_MDC period t1 CC 400 - - ns CL=25pF ETH_MDC high time t2 CC 160 - - ns CL=25pF ETH_MDC low time t3 CC 160 - - ns CL=25pF ETH_MDIO setup time (output) t4 CC 10 - - ns CL=25pF ETH_MDIO hold time (output) t5 CC 10 - - ns CL=25pF ETH_MDIO data valid (input) t6 SR 0 - 300 ns CL=25pF ETH_Timing-Mgmt.vsd ETH_MDC ETH_MDIO (output ) Valid Data Valid Data ETH_MDIO (input ) ETH_MDC ETH_MDIO sourced by controller : ETH_MDIO sourced by PHY: ETH_MDC t3 t2 OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 448 V 1.0, 2020-04

3.24.3 ETH MII Parameters

In the following, the parameters of the MII (Media Independent Interface) are described. Figure 3-19 ETH MII Signal Timing Table 3-54 ETH MII Signal Timing Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Clock period t7 SR 40 - - ns CL=25pF ; baudrate=100Mbps 400 - - ns CL=25pF ; baudrate=10Mbps Clock high time t8 SR 14 - 26 ns CL=25pF ; baudrate=100Mbps 140 1) 1) Defined by 35% of clock period. -2 6 0 2) 2) Defined by 65% of clock period. ns CL=25pF ; baudrate=10Mbps Clock low time t9 SR 14 - 26 ns CL=25pF ; baudrate=100Mbps 140 1) -2 6 0 2) ns CL=25pF ; baudrate=10Mbps Input setup time t10 SR 10 - - ns CL=25pF Input hold time t11 SR 10 - - ns CL=25pF Output valid time t12 CC 0 - 25 ns CL=25pF ETH_Timing-MII.vsd ETH _MII_RX_CLK ETH_MII_TXD [3:0] ETH_MII_TXEN ETH_MII_RXD[3:0] ETH_MII_RX_DV ETH_MII_RX_ER ETH_MII_TX_CLK t11 Valid Data t10 Valid Data t12 (sourced by controller ) (sourced by PHY ) t9 t8 ETH _MII_RX_CLK ETH_MII_TX_CLK OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 449 V 1.0, 2020-04

3.24.4 ETH RMII Parameters

In the following, the parameters of the RMII (Reduced Media Independent Interface) are described. Figure 3-20 ETH RMII Signal Timing Table 3-55 ETH RMII Signal Timing Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ETH_RMII_REF_CL clock period t13 CC 20 - - ns 50ppm ; CL=25pF ETH_RMII_REF_CL clock high time t14 CC 7 1) 1) Defined by 35% of clock period. -1 3 2) 2) Defined by 65% of clock period. ns CL=25pF ETH_RMII_REF_CL clock low time t15 CC 7 1) -1 3 2) ns CL=25pF ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time t16 CC 4 - - ns CL=25pF ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time t17 CC 2 - - ns CL=25pF ETH_Timing-RMII.vsd ETH _RMII_REF _CL t17 Valid Data t16 t13 t15 t14 ETH _RMII_REF _CL ETHTXEN , ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 450 V 1.0, 2020-04

3.24.5 ETH RGMII Parameters

In the following, the parameters of the RGMII are described. Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD)) Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS)) Table 3-56 ETH RGMII Signal Timing Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. TX Clock period t19 CC 36 40 44 ns 100Mbps 360 400 440 ns 10Mbps 7.2 8 8.8 ns Gigabit Data to Clock Output skew t20 CC -500 0 500 ps Data to Clock input skew (at receiver) t21 SR 1 1.8 2.6 ns Clock duty cycle tduty CC 40 50 60 % 10/100Mbps 45 50 55 % Gigabit GREFCLK duty cycle tduty_in SR 45 - 55 % GREFCLK Input accuracy ACC SR -0.005 - 0.005 % TXCLK at transmiter TXD[3:0],TXCTL t19 t20 RXCLK at receiver RXD[3:0],RXCTL t19 t21 OPEN MARKET VERSION

Electrical Specification E-Ray Parameters Data Sheet 451 V 1.0, 2020-04

3.25 E-Ray Parameters

The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL = 25 pF. Table 3-57 Transmit Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Rise time of TxEN tdCCTxENRise2 5 CC --9 n s CL=25pF Fall time of TxEN tdCCTxENFall25 CC --9 n s CL=25pF Sum of rise and fall time tdCCTxRise25+ dCCTxFall25 CC - - 9 ns 20% - 80% ; CL=25pF Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, rising edge of TxEN tdCCTxEN01 CC --2 5 n s Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, falling edge of TxEN tdCCTxEN10 CC --2 5 n s Asymmetry of sending ttx_asym CC -2.45 - 2.45 ns CL=25pF Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, rising edge of TxD tdCCTxD01 CC --2 5 n s Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, falling edge of TxD tdCCTxD10 CC --2 5 n s TxD signal sum of rise and fall time at TP1_BD ttxd_sum C C --9 n s Table 3-58 Receive Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Acceptance of asymmetry at receiving part tdCCTxAsymAcc ept25 SR -30.5 - 43.0 ns CL=25pF Acceptance of asymmetry at receiving part tdCCTxAsymAcc ept15 SR -31.5 - 44.0 ns CL=15pF Threshold for detecting logical high TuCCLogic1 SR 35 - 70 % Threshold for detecting logical low TuCCLogic0 SR 30 - 65 % OPEN MARKET VERSION

Electrical Specification E-Ray Parameters Data Sheet 452 V 1.0, 2020-04 Sum of delay between TP4_CC and TP4_FF and delays derived from TP4_FFi, rising edge of RxD tdCCRxD01 CC --1 0 n s Sum of delay between TP4_CC and TP4_FF and delays derived from TP4_FFi, falling edge of RxD tdCCRxD10 CC --1 0 n s Table 3-58 Receive Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification HSCT Parameters Data Sheet 453 V 1.0, 2020-04

3.26 HSCT Parameters

Table 3-59 HSCT - Rx parasitics and loads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Capacitance total budget Ctotal CC - 3.5 5 pF Total Budget for complete receiver including silicon, package, pins and bond wire Parasitic inductance budget Htotal CC - 5 - nH Table 3-60 HSCT - Rx/Tx setup timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. RX o/p duty cycle DCrx CC 40 - 60 % Disable time of the LVDS pad tLVDSDIS C C --2 0 n s Enable time of the LVDS pad tLVDSEN C C --4 0 0 n s Wakeup time from Sleep Mode tSWU C C --2 5 0 n s Maximum length of a wake-up glitch that does not wake-up the receiver tWUP CC - - 0.2 ns Bias startup time tbias CC - 5 10 µs Bias distributor waking up from power down and provide stable Bias. RX startup time trxi CC - - 600 ns Wake-up RX from power down. TX startup time ttx CC - - 280 ns Wake-up TX from power down. OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 454 V 1.0, 2020-04

3.27 Inter-IC (I2 C) Interface Timing

All I2C timing parameter are SR for Master Mode and CC for Slave Mode. Table 3-61 I2C Standard Mode Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Fall time of both SDA and SCL t1 - - 300 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Capacitive load for each bus line Cb S R --4 0 0 p F Bus free time between a STOP and ATART condition t10 4.7 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 - - 1000 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data hold time t3 0 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 250 - - ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 4.7 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 4 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Hold time for the (repeated) START condition t7 4 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 455 V 1.0, 2020-04 Set-up time for (repeated) START condition t8 4.7 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for STOP condition t9 4 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Table 3-62 I2C Fast Mode Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Fall time of both SDA and SCL t1 20+0.1* C b - 300 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Capacitive load for each bus line Cb S R --4 0 0 p F Bus free time between a STOP and ATART condition t10 1.3 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 20+0.1* C b - 300 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data hold time t3 0 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 100 - - ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 1.3 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Table 3-61 I2C Standard Mode Timing (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 456 V 1.0, 2020-04 Hold time for the (repeated) START condition t7 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for (repeated) START condition t8 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for STOP condition t9 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Table 3-63 I2C High Speed Mode Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Capacitive load for each bus line Cb S R --4 0 0 p F Fall time of SCL t11 10 1) 1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard. -4 0 1) ns bus line load of 100pF Fall time of SDA t12 10 1) -8 0 1) ns bus line load of 100pF Rise time of SCL t13 10 1) -4 0 1) ns bus line load of 100pF Rise time of SDA t14 10 1) -8 0 1) ns bus line load of 100pF Data hold time t3 0 1) -7 0 1) ns bus line load of 100pF Data set-up time t4 10 1) - - ns bus line load of 100pF Low period of SCL clock t5 160 1) - - ns bus line load of 100pF High period of SCL clock t6 60 1) - - ns bus line load of 100pF Hold time for the (repeated) START condition t7 160 1) - - ns bus line load of 100pF Set-up time for (repeated) START condition t8 160 1) - - ns bus line load of 100pF Set-up time for STOP condition t9 160 1) - - ns bus line load of 100pF Table 3-62 I2C Fast Mode Timing (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 457 V 1.0, 2020-04 Figure 3-23 I2C Standard and Fast Mode Timing SCL SDA SCL SDA t1 t2 t1 t2 t10 t9t7t8 PSSr S 70% 30% 9th clock 9th clock OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 458 V 1.0, 2020-04

3.28 Flash Target Parameters

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Program Flash Erase Time per logical sector 1) tERP CC - - 0.5 s cycle count < 1000 Program Flash Erase Time per Multi-Sector Command 1) tMERP CC - - 0.5 s For consecutive logical sectors in a physical sector with total range ≤ 512 kByte; cycle count < 1000 Program Flash program time per page in 5 V mode 1) tPRP5 C C --8 0 µ s 3 2 B y t e Program Flash program time per page in 3.3 V mode 1) tPRP3 CC - - 115 µs 32 Byte Program Flash program time per burst in 5 V mode 1) tPRPB5 CC - - 220 µs 256 Byte Program Flash program time per burst in 3.3 V mode 1) tPRPB3 CC - - 530 µs 256 Byte Program Flash program time for 1 MByte with burst programming in 3.3 V mode excluding communication 1) tPRPB3_1MB CC - - 2.2 s Derived value for documentation purpose Program Flash program time for 1 MByte with burst programming in 5 V mode excluding communication 1) tPRPB5_1MB CC --1 s D e r i v e d v a l u e f o r documentation purpose Program Flash program time for complete PFlash with burst programming in 5 V mode excluding communication 1) tPRPB5_PF CC --4 s D e r i v e d v a l u e f o r documentation purpose Write Page Once adder 1) tADD CC - - 20 µs Adder to Program Time when using Write Page Once Program Flash suspend to read latency 1) tSPNDP CC - - 120 µs For Write Burst, Verify Erased and for multi- (logical) sector erase commands Data Flash Erase Disturb Limit (single ended sensing mode) NDFD C C --5 0 c y c l e s Data Flash Erase Disturb Limit (complement sensing mode) NDFDC C C --5 0 0 c y c l e s UCB Erase Disturb Limit NUCBD C C --5 0 0 c y c l e s OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 459 V 1.0, 2020-04 Program time data flash per page 1)2) tPRD C C --7 5 µ s 8 B y t e Complete Device Flash Erase Time PFlash and DFlash 1)3) 4) tER_Dev CC - 3 5 s Valid for less than 1000 cycles, w/o UCB. Derived value for documentation purpose. Data Flash program time per burst 1)2) tPRDB CC - - 140 µs 32 Byte Data Flash suspend to read latency 1) tSPNDD C C --1 2 0 µ s Wait time after margin change tFL_MarginDel CC --2 µ s Program Flash Endurance per Logical Sector NE_P CC - - 1000 cycles Replace logical sector command shall be used if a sector fails during erase or program Number of erase operations per physical sector in program flash NERP CC - - 16000 cycles Program Flash Retention Time, Sector tRET CC 20 - - years Max. 1000 erase/program cycles UCB Retention Time tRTU CC 20 - - years Max. 100 erase/program cycles per UCB, max 500 erase/program cycles for all UCBs together Data Flash access delay tDF CC - - 100 ns see RFLASH of DMU register HF_DWAIT Data Flash ECC Delay tDFECC CC - - 20 ns see RECC of DMU register HF_DWAIT Program Flash access delay tPF CC - - 30 ns see RFLASH of DMU register HF_PWAIT Program Flash ECC delay tPFECC CC - - 10 ns see RECC and CECC of DMU register HF_PWAIT Number of erase operations on DF0 over lifetime (complement sensing mode) 6) NERD0C CC - - 4000000 cycles Number of erase operations on DF0 over lifetime (single ended sensing mode) 7) NERD0S CC - - 750000 cycles Table 3-64 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 460 V 1.0, 2020-04 Number of erase operations on DF1 over lifetime (complement sensing mode) 6) NERD1C CC - - 2000000 cycles Number of erase operations on DF1 over lifetime (single ended sensing mode) 7) NERD1S CC - - 500000 cycles Data Flash Endurance per EEPROMx sector (complement sensing mode) 8) NE_EEP10C CC - - 500000 cycles Max. data retention time 10 years DataFlash Endurance per EEPROMx sector (single ended sensing mode) 8) NE_EEP10S CC - - 125000 cycles Retention time and Tj according below example temperature profile - - 125000 cycles max data retention time 20y, Tj=110°C - - 125000 cycles max data retention time 8.2y, Tj=125°C Data Flash Endurance per HSMx sector (complement sensing mode) 8) NE_HSMC CC - - 250000 cycles Max. data retention time 10 years Data Flash Endurance per HSMx sector (single ended sensing mode) 8) NE_HSMS CC - - 125000 cycles Retention time and Tj according below example temperature profile - - 125000 cycles max data retention time 20y, Tj=110°C - - 125000 cycles max data retention time 8.2y, Tj=125°C Junction temperature limit for PFlash program/erase operations TJPFlash S R --1 5 0 ° C Data Flash Erase Time per Sector 1)3)5) tERD1 CC - - 0.5 s Max. 1000 erase/program cycles Data Flash Erase Time per Sector 1)3)5) tERDM CC - - 1.5 s Max allowed cycles, see NE_EEP10 and NE_HSM parameters DataFlash Adder on Erase Time per 32kByte erase size when using complement sensing mode 1) tER_ADDC32C CC - - 50 ms Adder per 32 kByte on erase time; applicable only when using complement mode Table 3-64 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 461 V 1.0, 2020-04 Data Flash Erase Time per Multi-Sector Command 1)3)5) tMERD1 CC - - 0.5 s Max 1000 erase/program cycles; For consecutive logical sectors ≤ 256KBytes Data Flash Erase Time per Multi-Sector Command 1)3)5) tMERDM CC - - 1.5 s Max allowed cycles, see NE_EEP10x and NE_HSMx Parameters; For consecutive logical sectors ≤ 256 kByte Program Flash Access Delay at reduced VDDP3 voltage supply during cranking tPF_low_VDDP3 CC - - 60 ns see register DMU_HF_PWAIT.CFL ASH Data Flash Erase Verify time per page (Complement Sensing) 2) tVER_PAGE_D C CC - - 10 µs Time per 8 Byte page for Verify Erased Page command Data Flash Erase Verify time per page (Single Ended Sensing) 1) tVER_PAGE_D S CC - - 10 µs Time per 8 Byte page for Verify Erased Page command Program Flash Erase Verify time per page 1) tVER_PAGE_P CC - - 10 µs Time per 32 Byte page for Verify Erased Page command Data Flash Erase Verify time per sector (Complement Sensing) 1) tVER_SEC_DC CC - - 200 µs Time per 2 KB sector for Verify Erased Logical Sector Range command Data Flash Erase Verify time per sector (Single Ended Sensing) 1) tVER_SEC_DS CC - - 360 µs Time per 4 KB sector for Verify Erased Logical Sector Range command Program Flash Erase Verify time per sector 1) tVER_SEC_P CC - - 360 µs Time per 16KB sector for Verify Erased Logical Sector Range command Data Flash Erase Verify time per wordline (Complement Sensing) 1) tVER_WL_DC CC --3 0 µ s Data Flash Erase Verify time per wordline (Single Ended Sensing) 1) tVER_WL_DS CC --5 0 µ s Program Flash Erase Verify time per wordline 1) tVER_WL_P CC --3 0 µ s 1) Only vaild for fFSI = 100MHz. 2) Time is not dependent on program mode (5V or 3.3V). Table 3-64 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 462 V 1.0, 2020-04 3) Under out-of-spec conditions (e .g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes may be increased by up to 50%. 4) Using 512 kByte / 256 kByte eras e commands (PFlash / DFlash). 5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x tER_ADDC32C 6) Allows segmentation of addressable memory into 8 logical sectors; round robin cycling must still be done to consider erase disturb limit NDFD. 7) Allows segmentation of addressable memory into 6 logical sectors; round robin cycling must still be done to consider erase disturb limit NDFD. 8) Only valid when a r obust EEPROM emulation algorithm is used. For more details see the Users Manual. OPEN MARKET VERSION

Electrical Specification Quality Declarations Data Sheet 463 V 1.0, 2020-04

3.29 Quality Declarations

Example Temperature Profile The following temperature profile is an example. Application specific temperature profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. Table 3-65 Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Moisture Sensitivity Level MSL CC - - 3 Conforming to Jedec J-STD--020C for 240C ESD susceptibility according to Charged Device Model (CDM) VCDM SR - - 500 V for all other balls/pins; conforming to JESD22-C101-C - - 750 V for corner balls/pins; conforming to JESD22-C101-C ESD susceptibility according to Human Body Model (HBM) VHBM SR - - 2000 V Conforming to JESD22-A114-B ESD susceptibility of the LVDS pins according to Human Body Model (HBM) VHBM1 SR - - 2000 V Operation Lifetime tOP CC - - 24500 hour see below temperature profile as an example Table 3-66 Example Temperature Profile TJ= Duration [h] Comment ≤ 170°C ≤ 30 ≤ 160°C ≤ 120 ≤ 150°C ≤ 220 ≤ 140°C ≤ 350 ≤ 130°C ≤ 780 ≤ 120°C ≤ 1600 ≤ 110°C ≤ 3000 ≤ 100°C ≤ 7000 ≤ 90°C ≤ 8000 ≤ 80°C ≤ 2400 ≤ 70°C ≤ 1000 ≤ 24500 total time OPEN MARKET VERSION

Electrical Specification Quality Declarations Data Sheet 464 V 1.0, 2020-04 Table 3-67 Example Inactive Lifetime Temperature Profile TJ= Duration [h] Comment ≤ 55°C ≤ 150700 OPEN MARKET VERSION

Electrical Specification Package Outline Data Sheet 465 V 1.0, 2020-04

3.30 Package Outline

Figure 3-24 Package Outlines LFBGA-292 Figure 3-25 Package Outlines LFBGA-180 OPEN MARKET VERSION

Electrical Specification Package Outline Data Sheet 467 V 1.0, 2020-04 Figure 3-28 Package Outlines TQFP-144 You can find all of our packages, sorts of packing and others i n our Infineon Internet Page “Products”: http://www.infineon.com/products.

3.30.1 Package Parameters

Table 3-68 Package Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Thermal resistance (junction to ambient) 1) RTH_JA CC - - 22 K/W LFBGA-180 - - 23 K/W LFBGA-292 --1 8 K / W Q F P - 1 4 4 --1 7 K / W Q F P - 1 7 6 Thermal resistance (junction to case bottom) 1) RTH_JCB CC - - 4.5 K/W LFBGA-180 - - 4.5 K/W LFBGA-292 - - 2 K/W QFP-144 - - 2 K/W QFP-176 Thermal resistance (junction to case top) 1) RTH_JCT CC - - 6 K/W LFBGA-180 - - 5 K/W LFBGA-292 --1 0 K / W Q F P - 1 4 4 --1 0 K / W Q F P - 1 7 6 OPEN MARKET VERSION

Electrical Specification Package Outline Data Sheet 468 V 1.0, 2020-04 1) The top and bottom thermal resi stances between the case and the ambient (RTH_CTA, RTH_CBA) are to be combined with the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate the total thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is the total thermal resistance between the junction and the ambient. Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1). OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 469 V 1.0, 2020-04

4 History

Version 0.4 is the first version of this document. 4.1 Changes from Versi on 0.4 to Version 0.6

• Changes in chapter Summary of Fe atures, table Platform Feature Overview – Corrected spelling “HSPDM” – Changed spellin g for packages – Added packages
• Changes in chapter “Pin Definition and Function” – Changed package wording from BGA292 to LFBGA-292 – Changed package wording from BGA180 to LFBGA-180 – Changed package wording from QFP176 to LQFP-176 – Changed package wording from QFP144 to LQFP-144 – Added pinning for package LFBGA-180 – Separated pinnings for pa ckage LQFP-144 and TQFP-144
• Changes in chapter 'LFBGA-292 Pa ckage Variant Pin Configuration of TC36x' P00.11, P00.12 – Changes in 'Port 10 Functions' t able; P10.2, P10.3, P10.7, P10.8 – Changes in 'Port 12 Functions' table; P12.0, P12.1 – Changes in 'Port 13 Functions' table; P13.0, P13.1, P13.2 – Changes in 'Port 23 Functions' t able; P23.0, P23.1, P23.2, P23.3 – Changes in 'Port 32 Functions' table; P32.2, P32.3, P32.4 P33.9, P33.10, P33.12, P33.13 – Changes in table “Analog Input s” - Changed function for ball W5; Changed function for ball U5 – Changes in table “System I/O” - Removed symbol and function for ball L19; Changed I/O for symbol ESR1, ball G16; Changed I/O for symbol ESR0, ball F16
• Added chapter 'LFBGA-180 Package Variant Pin Configuration of TC36x'
• Changes in chapter 'LQFP-176 Pac kage Variant Pin Configuration of TC36x' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 470 V 1.0, 2020-04 P00.11, P00.12 – Changes in 'Port 10 Functions' t able; P10.2, P10.3, P10.7, P10.8 – Changes in 'Port 11 Functions' table; P11.10, P11.12 – Changes in 'Port 13 Functions' table; P13.0, P13.1, P13.2 – Changes in 'Port 23 Functions' t able; P23.0, P23.1, P23.2, P23.3 – Changes in 'Port 32 Functions' table; P32.2, P32.3, P32.4 P33.9, P33.10, P33.12, P33.13 – Changes in table “Analog Input s” - Changed function for pin 50; Changed function for pin 49 – Changes in table “System I/O” - Removed symbol and function for pin 114; Changed I/O for symbol ESR1, pin 120; Changed I/O for symbol ESR0, pin 122 – Changes in table “Supply” - Changed symbol and function for pi n 164; Changed symbol and function for pin 54; Changed pin 177 to E-PAD

• Changes in chapter 'LQFP-144 Pac kage Variant Pin Configuration of TC36x' – Changes in 'Port 10 Functions' table; P10.2, P10.3 – Changes in 'Port 11 Functions' table; P11.10, P11.12 – Changes in 'Port 13 Functions' table; P13.0, P13.1, P13.2 – Changes in 'Port 14 Functions' table; P14.0, P14.1, P14.6 – Changes in 'Port 23 Functions' table; P23.1 – Changes in 'Port 32 Functions' table; P32.4 – Changes in table “Analog Input s” - Changed function for pin 40, symbol EVADC_FC0CH0; Changed function for pin 39, symbol EVADC_FC1CH0 – Changes in table “System I/O” - Removed symbol and function fo r pin 91; Changed I/O for symbol ESR1, ball 96; Changed I/O for symbol ESR0, ball 98 – Changes in table “Supply” - Changed symbol and function for pi n 136; Changed symbol and function for pin 44; Changed pin 145 to E-PAD
• Added chapter 'TQFP-144 Package Variant Pin Configuration of TC36x'
• Changes in chapter “Bare Die Var iant Pin Configuration of TC36x” OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 471 V 1.0, 2020-04 – Changes in table “Pad List” for different positions (Pad Names, Pad Types, X and Y values, and comments)

• Changes in chapter “Legend”
• Changes in chapter “El ectrical Specification”
• Changes in table “Absol ute Maximum Ratings” – Added footnote of parameter VDDM – Changed footnote number of parameter VIN – Changed footnote number of parameter IIN – Changed footnote number of parameter ∑ IIN – Added footnote 2) – Changed order of footnotes
• Changes in table “Overload Parameters” – Changed note for parameter KOVAN – Changed footnote number of parameter KOVAN – Changed note for parameter KOVAP – Changed footnote number of parameter KOVAP – Added footnote 2)
• Changes in table “Operating Conditions” – Deleted parameter fEBU – Added footnote number of parameter VDD – Changed footnote number of parameter VDDM – Changed footnote number of parameter VEXT – Changed footnote number of parameter VFLEX – Changed footnote number of parameter VDDP3 – Changed footnote number of parameter VEVRSB – Changed footnote number of parameter VDDPPA – Added footnote 1) – Changed order of footnotes
• Changes in table “PORST Pad” – Added footnote number of parameter IPDL – Added values and notes for parameter VIH – Added values and notes for parameter VIL – Added footnote 2)
• Changes in table “Fast 5V GPIO” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 472 V 1.0, 2020-04 – Changed and deleted values of parameter IOZ – Added footnotes 4) and 5)

• Changes in table “Fast 3.3V GPIO” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL – Changed and deleted values of parameter IOZ – Added footnotes 4) and 5)
• Changes in table “Slow 5V GPIO” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL – Changed and deleted values of parameter IOZ – Deleted footnote 4) – Added footnotes 4) and 5)
• Changes in table “Slow 3.3V GPIO” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL – Changed and deleted values of parameter IOZ – Deleted footnote 4) – Added footnotes 4) and 5)
• Changes in table “RFast 5V GPIO” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL – Added footnotes 4) and 5)
• Changes in table “RFa st 3.3V GPIO pad” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL – Added footnotes 4) and 5)
• Changes in table “Class S 5V” – Added footnote number of parameter IPUH – Added footnote number of parameter IPDL – Added footnotes 2) and 3)
• Changes in table “LVDS - IEEE s tandard LVDS general purpose link (GPL)” – Added footnote for parameter trise20 – Added footnote for parameter tfall20 – Changed footnote number of parameter VOD OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 473 V 1.0, 2020-04 – Changed value for parameter VI – Changed test conditions for parameter Vidth – Added values and test conditions for parameter Vidth – Changed test conditions for parameter Rin – Changed footnote number of parameter VODSM – Added footnotes 1) and 2) – Changed order of footnotes

• Changes in table “VADC 5V” – Added and changed values of parameter VAREF – Added footnote number of parameter VAREF – Added note for parameter VAIN – Changed footnote numbers of parameter TUE – Changed footnote number of parameter EAINL – Changed footnote numbers of parameter EADNL – Changed footnote number of parameter EAGAIN – Added footnote number of parameter EAOFF – Added and changed footnote numbers of parameter ENRMS – Added footnote number of parameter QCONV – Changed footnote number of parameter QAINS – Changed footnote number of parameter RCSD – Added footnote 1) – Changed order of footnotes
• Changes in table “DSADC 5V” – Changed value of parameter VAREF – Added value of parameter IREF – Added value of parameter IRMS – Added and changed footnote numbers of parameter EDGAIN – Changed footnote number of parameter EDOFF – Changed footnote number of parameter SNR – Added footnote 4) – Changed order of footnotes
• Changes in table “OSC_XTAL” – Added values for parameter DCX1 – Added values for parameter JABSX1 – Added values for parameter SRXTAL1 – Added footnote 3)
• Changes in table “Back-up Clock” – Changes in footnote 1) OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 474 V 1.0, 2020-04

• Changes in table “DTS PMS” – Added note for parameter TNL
• Changes in table “DTS Core” – Added note for parameter TNL
• Changes in chapter “Power Supply Current” – Changed chapter description
• Changes in table “Current Consumption” – Changed values of parameter IDDPORST – Changed value for parameter IEXTRAIL – Changed value for parameter IEXTFLEX – Changed value for parameter IDDTOT – Added value for parameter IDDTOTDC3 – Changed test condition for parameter IDDTOTDC3 – Added value for parameter IDDTOTDC5 – Changed test condition for parameter IDDTOTDC5 – Changed values for parameter PD – Deleted footnote number of parameter IEXTFLEX – Deleted footnote number of parameter IDDP3RAIL – Changed footnotes 1) and 3)
• Changes in table “Modul e Current Consumption” – Changed value of parameter of IEXTLVDS – Changed value of parameter of ISCRSB – Changed footnote 5)
• Changes in table “Module Core Current Consumption” – Added values of parameter of IDDGTM – Changed footnote 1)
• Changes in chapter “Power Supply Infrastructure and Supply Sta rt-up” – Changed wording in descriptions for sub chapter “Supply Ramp-u p and Ramp-down Behavior” – Changed numbers for HWCFG pins – Changed figure for 'Single Supply Mode (a)' – Changed figure for 'Single Supply Mode (e)' – Changed figure for 'External Supply Mode (d)' – Changed figure for 'External Supply Mode (h)'
• Changes in table “Reset” OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 475 V 1.0, 2020-04 – Added values for parameter tWARMRSTSEQ – Changed value for parameter tBWP – Changed/ added values for parameter tSCR

• Changes in table “EVR33 LDO” – Added footnote number of parameter dVOUT / dIOUT – Added footnote 7)
• Changes in table “Supply Monitors” – Changed note for parameter VRST33 – Added value for parameter VRSTC – Changed note for parameter VRSTC – Changed values of parameter VEXTMON – Added footnote number of parameter VEXTMON – Added footnote number of parameter VDDP3MON – Added footnote number of parameter VDDMON – Changed footnote 2) – Changed footnote 3) – Added footnote 5)
• Changes in table “EVRC SMPS” – Changed values of parameter VDDDC – Changed values of parameter VDDDCT – Added/ changed va lues of parameter fDCDC – Changed value of parameter tSTRDC – Changed value of parameter ∆ VDDDC – Deleted/ changed values of parameter dVDDDCT / dIOUT – Changed value for parameter IMAX – Deleted/ changed values of parameter dVDDDCT / dVIN – Changed values of parameter nDC
• Changes in table “EVRC SMPS External components” – Deleted values of parameter COUT – Deleted values of parameter CIN – Added values of parameter LDC – Deleted values of parameter RON – Deleted values of parameter QG
• Changes in table “PLL System” – Deleted values of parameter fMV
• Changes in table “Master Mode Tim ing, LVDS output pads for data and clock” OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 476 V 1.0, 2020-04 – Added footnote numbers for all parameter values – Added footnote 1)

• Changes in table “LVDS clock/data (LVDS pads in LVDS mode) valid for 5V” – Added footnote numbers for all parameter values – Added footnote 3)
• Changes in subchapter “ETH RGMII Parameters” – Added figure for “ETH RGMII TX Signal Timing (Delay on Destination (DoD))” – Added figure for “ETH RGMII RX Signal Timing (Delay on Source (DoS))”
• Changes in table “Flash” – Changed value for parameter tRTU – Changed description an d note for parameter tVER-PAGE_DC – Changed description for parameter tVER-PAGE_DS
• Changes in table “Package Parameters” – Added values for all parameters 4.2 Changes from Versi on 0.6 to Version 0.7
• Changes in chapter “Bare Die Var iant Pin Configuration of TC36x” – Added comment to “Pad List” concerning “neighbor pads”
• Changes in chapter “Legend” – Added refering IO_Spirit_file version Changes in chapter “Electrical Specification”
• Changes in table “Absol ute Maximum Ratings” – Changed description of parameter VIN – Changed description of parameter ∑ IIN – Added footnote number to parameter IIN – Added footnote 5)
• Changes in table “Slow 3.3V GPIO” – Added value and note for parameter RDSON – Changed notes of parameter IOZ
• Changes in table “LVDS - IEEE s tandard LVDS general purpose link (GPL)” – Added notes to table “LVDS - I EEE standard LVDS general purpose link (GPL)”
• Changes in table “OSC_XTAL” – Changed spelling in footnote 2)
• Changes in table “Current Consumption” – Changed wording in footnote 6) OPEN MARKET VERSION

History Changes from Version 0.7 to Version 1.0 Data Sheet 477 V 1.0, 2020-04

• Changes in table “Modul e Current Consumption” – Changed value and note of parameter TEXTLVDS – Added value and note of parameter TEXTLVDS
• Changes in table “Reset” – Changed value for parameter tPIP
• Changes in table “EVR33 LDO” – Added parameter dVOUTTC
• Changes in table “Supply Monitors” – Changed notes for all values of parameter VEXTMON – Added values to parameter VEXTMON
• Changes in table “EVRC SMPS” – Changed Controller Characterist ics (CC) to System Requirements (SR) for parameter ∆ fDCSPR – Changed Controller Characterist ics (CC) to System Requirements (SR) for parameter nDC – Added values to parameter fDCDCSYNC
• Changes in table “PLL System” – Changed value of parameter fREF
• Changes in table “Flash” – Changed value of parameter tPRPB5_PF – Changed value of parameter tER-DEV
• Changes in table “Package Parameters” – Changed value of parameter VHBM1 4.3 Changes from Versi on 0.7 to Version 1.0 Changes in chapter “Summary of Features” – Changed spelling in table "P latform Feature Overview" – Removed “ASIL” value from table “Platform Feature Overview” Changes in chapter “TC36x Pin Definition and Functions”
• Changes in sub-chapter "Bare Die Variant Pin Configuration of TC36x" – Deleted redundant sentence in explanation following table “Pad List” regarding neighbor pads Changes in chapter “Electrical Specification”
• Changes in sub-chapter “Ab solute Maximum Ratings” – Changed wording for parameter VIN – Changed spelling in footnote 3)
• Changes in sub-cha pter “Pin Reliability in Overload” – Changed spelling for parameter IINSA in table “Overload Parameters”
• Changes in sub-chapter “ Operating Conditions” – Deleted parameter fADAS in table "Operating Conditions" – Changed values for parameter fGETH in table "Operating Conditions"
• Changes in sub-chapter “5V / 3.3V switchable Pads” – Deleted value for parameter RDSON in table "Slow 5V GPIO" – Deleted value for parameter RDSON in table "Slow 3.3V GPIO" OPEN MARKET VERSION

History Changes from Version 0.7 to Version 1.0 Data Sheet 478 V 1.0, 2020-04

• Changes in sub-chapter “Hi gh performance LVDS Pads” – Deleted value for parameter tfall20 in table "LVDS - IEEE standard LVDS general purpose link (GPL)" – Deleted footnot e 2) for table "LVDS - IEEE standard LVDS general purpose link (GPL)" – Changed order of foot notes for table "LVDS - IEEE standard LVDS general purpose link (GPL)"
• Changes in sub-chapter “VADC Parameters” – Deleted footnote 9) for parameter QCONV in table "VADC 5V" – Changed spelling for parameter dVCSD in table "VADC 5V" – Changed wording for footnote 7) for table "VADC 5V" – Changed footnote numbering for table "VADC 5V" – Changed figure "Equivalent Circu itry for Analog Inputs" for table "VADC 5V"
• Changes in sub -chapter “MHz Oscillator” – Changed wording of footnote 1) for table "OSC_XTAL"
• Changes in sub-chapter “Power Supply Current” – Changed value for parameter TEXTRAIL in table "Current Consumption" – Changed value for parameter TEVRSB in table "Current Consumption" – Changed value for parameter ISRCSB in table "Module Current Consumption"
• Changes in sub-chapter “Reset Timing” – Changed spelling for parameter tEVRPOR in table "Reset" – Changed values for parameter tPI in table "Reset"
• Changes in sub-chapter “EVR” – Changed Test Conditions for parameter VDDP3MON in table "Supply Monitors" – Changed Test Conditions for parameter VDDMON in table "Supply Monitors" – Changed Test Conditions for parameter tMON in table "Supply Monitors" – Changed spelling of footnote 2) for table "Supply Ramp" – Added description at table "Supp ly Ramp" regarding power cycles – Added values for parameter COUT in table "EVRC SMPS External components"
• Changes in sub-chapter “ETH RGMII Parameters” – Deleted note for parameter t21 in table "ETH RGMII Signal Timing Parameters valid for 3.3V"
• Changes in sub-chapter “Package Parameters” – Changed notes spelling in table "Package Parameters" OPEN MARKET VERSION

Published by Infineon Technologies AG www.infineon.com OPEN MARKET VERSION