TLE9185QX

TLE9185QX INFINEON | Alldatasheet

Document overview

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• PDF pages: 193

Technical content

Features

• Low-drop voltage regulator 5 V, 250 mA for main supply
• Three half-bridge gate drivers fo r external N-channel MOSFETs
• Adaptive MOSFET gate control: – Regulation of the MOSFET switching time – Reduced switching losses in PWM mode – High efficient constant gate charge
• Control of reverse battery protection MOSFET
• One low-side capable current sense amplifier (CSA) with configurable gain for protection and diagnosis
• Configurable wake-up sources
• S i x P W M i n p u t s – High-side and low-side PWM capable – Active free-wheeling – Up to 25 kHz PWM frequency
• 32 bit serial peripheral interface (SPI) with cyclic redundancy check (CRC)
• Very low quiescent current consumption in Stop Mode and Sleep Mode
• Periodic cyclic wake in Normal Mode, Stop Mode and Sleep Mode
• Reset and interrupt output
• Drain-source monitoring and open-load detection
• Configurable time-out and window watchdog
• Overtemperature and short circuit protection features
• Leadless power package with suppor t of optical lead tip inspection
• Green Product (RoHS compliant)

Datasheet 2 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Overview Potential applications

• Auxiliary pumps (fuel, water, etc.)
• B l o w e r m o t o r
• Engine cooling fan
• S u n r o o f m o d u l e
• Transfer case Product validation Qualified for automotive applications. Product validation according to AEC-Q100.

Description

The TLE9185QX is a multifunctional IC with integrat ed power supply, multiple half-bridges and support features in an exposed pad PG-VQFN-48 power package. The device is designed for various motor control automotive applications. To support these applications, the BLDC Driver provides the main functions, such as a 5 V low-dropout voltage regulator, three half-bridges for BDLC motor contro l, one current sense amplifier and one 32 bit serial peripheral interface (SPI). The device includes diagnostic and supervision featur es, such as drain-source monitoring and open-load detection, short circuit protection, configurable time-out and window watchdog, as well as overtemperature protection. The device is intended to operate with 5.0 V microcontroller. Type Package Marking TLE9185QX PG-VQFN-48 TLE9185QX

Datasheet 3 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Table of Contents

Datasheet 4 Rev. 1.0 2021-01-21

Datasheet 5 Rev. 1.0 2021-01-21

Datasheet 6 Rev. 1.0 2021-01-21

Datasheet 7 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Block Diagram

2 Block Diagram

MUX(VSINT,VS) VS CP/VCC1 GND MUX(VSINT,VS): multiplexed VSINT & VS MUX(VSINT,VS) MUX(VSINT,VS)

Datasheet 8 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration

3.2 Pin Definitions and Functions

1V C C 1 Voltage reference for CSA, SPI and PWM inputs. Output voltage 1 2R S T N Reset Output. Active LOW, internally passive pull-up with open-drain output 3I N T N / T E S T Interrupt Output. Active LOW output, push-pull structure TEST. Connect to GND (via pull-down) to activate Software Development Mode 4S D O SPI Data Output to Microcontroller (=MISO). Push-pull structure 5S D I SPI Data Input from Microcontroller (=MOSI). Internal pull-down 6G N D Ground. Analog/digital ground 7C S A P Not Inverting input of Current Sense Amplifier.

1 VCC1

2 RSTN

3 INTN/TEST

4 SDO

5 SDI

6 GND

7 CSAP

8 CSAN

9 CSO

10 CLK

11 N.U. 12 N.U. VSINT 48 PWM6 47 PWM5 46 N.U. 45 N.U. 44 WK4/SYNC 42 N.U. 41 GL3 40 PWM4 39 N.U. 38 N.U. 37 14 N.U. 15 N.U.

16 GND

17 N.U.

18 CSN

20 GL2

21 GL1

22 PWM2

23 GH2

25 SH1

26 GH1

28 CPC2N

29 CPC2P

34 PWM3

35 GH3

24 SH2

13 N.U.

36 SH3

27 PWM1/CRC

N.U. 43

30 CPC1P

31 CPC1N

Datasheet 9 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Pin Configuration 8C S A N Inverting input of Current Sense Amplifier. 9C S O Current Sense Amplifier Output. 10 CLK SPI Clock Input. Internal passive pull-down 11 N.U. Not used. 12 N.U. Not used. 13 N.U. Not used. 14 N.U. Not used. 15 N.U. Not used.

16 GND Ground

17 N.U. Not used. 18 CSN SPI Chip Select Not input. Internal passive pull-up 19 SL Source Low Side. 20 GL2 Gate Low Side 2. 21 GL1 Gate Low Side 1. 22 PWM2 PWM input 2. Internal passive pull-up 23 GH2 Gate High Side 2. 24 SH2 Source High Side 2. 25 SH1 Source High Side 1. 26 GH1 Gate High Side 1. 27 PWM1/CRC PWM input 1. Internal passive pull-down CRC. Connect to GND (via pull-down) to activate CRC functionality 28 CPC2N Negative connection to Charge Pump Capacitor 2. 29 CPC2P Positive connection to Charge Pump Capacitor 2. 30 CPC1P Positive connection to Charge Pump Capacitor 1. 31 CPC1N Negative connection to Charge Pump Capacitor 1. 32 VS Supply voltage for Bridge Drivers and Charge pump. Connected to the battery voltage after reverse protection. 33 CP Charge Pump output voltage. 34 PWM3 PWM input 3. Internal passive pull-down 35 GH3 Gate High Side 3. 36 SH3 Source High Side 3. 37 N.U. Not used. 38 N.U. Not used. 39 PWM4 PWM input 4. Internal passive pull-down 40 GL3 Gate Low Side 3. 41 N.U. Not used. 42 WK4/SYNC Wake-up input 4/Sync. 43 N.U. Not used. 44 N.U. Not used. Pin Symbol Function

Datasheet 10 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Pin Configuration Note: The GND pin as well as the Cooling Tab mu st be connected to one common GND potential.

3.3 Hints for not functional pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI. Unused pins should be handled as follows:

• N.U.: not used; internally bonded for testing purpose; leave open except pin 17. Pin 17 to be connected to VS.
• RSVD: must be connected to GND. 45 N.U. Not used. 46 PWM5 PWM input 5. Internal passive pull-down 47 PWM6 PWM input 6. Internal passive pull-down 48 VSINT Voltage regulator and main supply voltage. Connected to the battery voltage after reverse protection Cooling Tab GND Cooling Tab - Exposed Die Pad; For cool ing purposes only, do not use as an electrical ground1) 1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the device via the PCB. The exposed die pad is not connected to any active part of the IC. However, it should be connected to GND for the best EMC performance. Pin Symbol Function

Datasheet 11 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 1 Absolute Maximum Ratings 1) Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Supply Voltage VS VS, max -0.3 – 28 V – P_4.1.1 Supply Voltage VS VS, max -0.3 – 40 V Load Dump P_4.1.2 Supply Voltage VSINT VSINT, max -0.3 – 28 V – P_4.1.3 Supply Voltage VSINT VSINT, max -0.3 – 40 V Load Dump P_4.1.4 Voltage Regulator 1 VCC1, max -0.3 – 5.5 V P_4.1.7 Charge Pump Output Pin (CP) VCP, max VS - 0.8 – VS + 17 V ICP > - 200 µA if CP is disabled P_4.1.8 CPC1P, CPC2P VCPCxP, max - 0.3 – VS + 17 V P_4.1.38 CPC1N, CPC2N VCPCxN, max - 0.3 – VS + 0.3 V P_4.1.39 Bridge Driver Gate High Side (GHx) VGHx, max -8.0 – 40 V – P_4.1.11 Bridge Driver Gate Low Side (GLx) VGLx, max -8.0 – 24 V – P_4.1.12 Voltage difference between GHx-SHx and between GLx- SLx Bridge Driver Source High (SHx) VSHx, max -8.0 – 40 V – P_4.1.14 Bridge Driver Source Low Side SL VSL, max -8.0 – 6.0 V – P_4.1.15 Current Sense Amplifier inputs (CSAP, CSAN) VCSx, max -8.0 – +8.0 V – P_4.1.16 Current Sense Amplifier Output CSO VCSx, max -0.3 – VCC1 + 0.3 V– P_4.1.17 Differential input voltage range CSAPx - CSANx VCSA,Diff -8.0 – 8.0 V – P_4.1.18 Wake Input WKx VWKx, max -0.3 – 40 V – P_4.1.19 PWM1/CRC, PWM2, PWM3, PWM4, PWM 5, PWM6 Input Pins VPWM1-2-3-4-5- 6, max Logic Input Pins (SDI, CLK, ) VI, max -0.3 – VCC1 + 0.3 V– P_4.1.28

Datasheet 12 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver General Product Characteristics Notes 1. Stresses above the ones listed here may cause perm anent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

4.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. CSN VCSN -0.3 – 40 V – P_4.1.29 Logic Output Pins (SDO, RSTN, INTN, ) VO, max -0.3 – VCC1 + 0.3 V– P_4.1.30 Temperatures Junction Temperature Tj -40 – 150 °C – P_4.1.32 Storage Temperature Tstg -55 – 150 °C – P_4.1.33 ESD Susceptibility ESD Resistivity VESD,11 -2 – 2 kV HBM 2) P_4.1.34 ESD Resistivity to GND VESD,12 -8 – 8 kV HBM 2)3) P_4.1.35 ESD Resistivity to GND VESD,21 -500 – 500 V CDM 4) P_4.1.36 ESD Resistivity Pin 1, 12,13,24,25,36,37,48 (corner pins) to GND VESD,22 -750 – 750 V CDM 4) P_4.1.37 1) Not subject to production test, specified by design. 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF). 3) For ESD “GUN” Resistivity (according to IEC61000-4-2 “gun test” (150 pF, 330Ω)), is shown in Application Information and test report will be provided from IBEE. 4) ESD susceptibility, Charged Device Mode l “CDM” EIA/JESD22-C101 or ESDA STM5.3.1. Table 2 Functional Range 1) 1) Not subject to production test, specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Voltage VSINT,func VPOR,f –2 8 V 2) 2) Including Power-On Reset, Over - and Undervoltage Protection. P_4.2.1 Bridge Supply Voltage VS,func 6.0 – 28 V – P_4.2.2 Junction Temperature Tj -40 – 150 °C – P_4.2.6 Table 1 Absolute Maximum Ratings 1) (cont’d) Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 13 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver General Product Characteristics Device Behavior Outside of Specified Functional Range

• 2 8 V < VSINT,func < 40 V: Device will still be functional including the state machine; the specified electrical characteristics might not be ensured anymore. The VCC1 is working properly, however, a thermal shutdown might occur due to high power dissipation. The specified SPI communication speed is ensured; the absolute maximum ratings are not violated, however the device is not intended for continuous operation of VSINT > 28 V and a thermal shutdown might occur due to high power dissipation. The device operation at high junction temperatures for long periods might reduce the operating life time.
• VPOR,f < VSINT < 5.5 V (given the fact that the device was powered up correctly before with VSINT > 5.5 V): Device will still be functional; the specified electrical characteristics might not be ensured anymore: – A reset could be triggered de pending on the Vrthx settings. – The specified SPI commun ication speed is ensured. Note: VS,UV < VS < 6.0 V: the charge pump might be deactivated due to a charge pump undervoltage detection, resulting in a turn-off of the external MOSFETs.

4.3 Thermal Resistance

4.4 Current Consumption

Table 3 Thermal Resistance 1) 1) Not subject to production test, specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to Soldering Point Rth(JSP) – 7.2 – K/W Exposed Pad P_4.3.1 Junction to Ambient Rth(JA) –2 7 –K / W 2) 2) Specified Rth(JA) value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for a power dissipation of 1.5 W; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm C); where applicable a thermal via array under the exposed pad contacted the first inner copper layer and 300 mm2 cooling areas on the top layer and bottom layers (70 µm). P_4.3.2 Table 4 Current Consumption Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Normal Mode Normal Mode current consumption INormal –4 . 5 5 . 5 m A 1) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; CP=off P_4.4.1 Stop Mode current consumption (low active peak threshold) IStop_1,25 –5 0 6 5 µ A 1)2) CSA=off; WKx=CP=off: Cyclic Wak.=off Watchdog = off; no load on V CC1; I_PEAK_TH = 0B P_4.4.2

Datasheet 14 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver General Product Characteristics Stop Mode current consumption (low active peak threshold) I Stop_1,85 –5 5 8 0 µ A 1)2)3) Tj = 85°C; CSA=off; WKx=CP=off: Cyclic Wak.=off Watchdog = off; no load on V CC1; I_PEAK_TH = 0B P_4.4.3 Stop Mode current consumption (high active peak threshold) IStop_2,25 –7 0 9 5 µ A 1)2) CSA=off; WKx=CP=off: Cyclic Wak.=off Watchdog = off; no load on V CC1; I_PEAK_TH = 1B P_4.4.4 Stop Mode current consumption (high active peak threshold) I Stop_2,85 – 75 105 µA 1)2)3) Tj = 85°C; CSA=off; Cyclic Wak.=off; Watchdog = off; no load on V CC1; I_PEAK_TH = 1B P_4.4.5 Sleep Mode Sleep Mode current consumption ISleep,25 –1 8 3 0 µ A 1) CSA=off; WKx=HSx=CP=off: Cyclic Wak.= off P_4.4.6 Sleep Mode current consumption I Sleep,85 –2 8 4 0 µ A 1)3) Tj = 85°C; CSA=off; WKx=HSx=CP=off: Cyclic Wak.=off P_4.4.7 Feature Incremental Current Consumption Current consumption for each WK input IWK,wake,25 –0 . 2 2µ A 1)4)5)6) Sleep Mode; WK wake capable; no activity on WK pin; P_4.4.22 Current consumption for each WK input I WK,wake,85 –0 . 5 3µ A 1)3)4)5)6) Sleep Mode; Tj = 85°C; WK wake capable; no activity on WK pin; P_4.4.23 Current consumption for watchdog active in Stop Mode I Stop,WD25 –1 8 2 3 µ A 3)7) Stop Mode; Watchdog running; P_4.4.28 Current consumption for watchdog active in Stop Mode IStop,WD85 –1 9 2 5 µ A 3)7) Stop Mode; Tj = 85°C; Watchdog running; P_4.4.29 Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 15 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver General Product Characteristics Notes 1. There is no additional current cons umption contribution in Normal Mode due to PWM generators or Timers. 2. The quiescent current consumption in Stop Mode and Sleep Mode will increase for VSINT < 9 V. Current Sense Amplifier ICSA1 ––4m A 7) CSA_OFF = 0B; VCSP = VCSAP = VCSAN = 0 V; CSO_CAP = 0 CCSO = 330 pF P_4.4.31 Current Sense Amplifier ICSA2 ––1 0 m A 7) CSA_OFF = 0B; VCSP = VCSAP = VCSAN = 0 V; CSO_CAP = 1B; CCSO = 2.2 nF P_4.4.36 Current consumption in parking braking mode (LSx ON) Iparking –1 0 1 4 µ A 3)7) Stop Mode or Sleep Mode; Tj < 85°C; PARK_BRK_EN = 1B P_4.4.32 Current consumption Over voltage braking mode (LSx OFF) IOV,LS_OFF –71 0 µ A 3)7) Stop Mode or Sleep Mode; Tj < 85°C; OV_BRK_EN = 1B P_4.4.34 Current consumption in VS for Charge Pump and Bridge Driver I CP,BD –3 0 4 0 m A N o r m a l M o d e ; Tj = -40°C to +150°C; CPEN = 1; All HB OFF P_4.4.35 1) Measured at VSINT. 2) If the load current on VCC1 will exceed the configured VCC1 active peak threshold, the current consumption will increase by typ. 2.9 mA to ensure optimum dynamic load behavior. See also Chapter 6. 3) Not subject to production test, specified by design. 4) Current consumption adders of features defined for Stop Mode also apply for Sleep Mode and vice versa. Wake input signals are stable (i.e. not toggling), cyclic wake & watchdog are OFF (unless otherwise specified). 5) No pull-up or pull-dow n configuration selected. 6) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are activated. 7) Additional current will be drawn from VSINT. Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 16 Rev. 1.0 2021-01-21

5 System Features

This chapter describes the system features and behavior of the TLE9185QX:

• State machine
• Device configuration
• State machine modes and mode transitions
• Wake-up features such as cyclic wake

5.1 Short State Machine Description

The BLDC Driver offers six operating modes:

• Init Mode: Power-up of the device and after a soft reset.
• Normal Mode: The main operating mode of the device.
• Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled.
• Sleep Mode: The second-level power saving mode with VCC1 disabled.
• Restart Mode: An intermediate mode after a wake event from Sleep Mode or Fail-Safe Mode or after a failure (e.g. WD failure, VCC1 under voltage reset).
• Fail-Safe Mode: A safe-state mode after critical fail ures (e.g. Temperature shutdown) to bring the system into a safe state and to ensure a proper restart of the system. A special mode, called Software Development Mode, is available during software development or debugging of the system. All above mentioned operating modes can be accessed in this mode. However, the watchdog is still running. Watchdog failures are indicated over INTN pin instead. However, the watchdog reset signaling can be reactivated ag ain in Software Development Mode. The Watchdog will start always with the Long Open Windows (t_low). The BLDC Driver is controlled vi a a 32-bit SPI interface (refer to Chapter 11 for detailed information). The configuration as well as the diagnosis is handled via the SPI. The device offers various supervision features to support functional safety requirements. Refer to Chapter 10 for more information.

Datasheet 17 Rev. 1.0 2021-01-21

5.2 Device Configuration

Two features on the BLDC Driver can be configured by hardware:

• The selection of the normal device operation or the Software Development Mode.
• Enabling/disabling the CRC on the SPI interface. The configurations are done monitoring the follow pins:
• I N T N / T E S T
• P W M 1 / C R C The hardware configuration can be done typically at device power-up, where the device is in Init Mode or (only in case of CRC setting) in Restart Mode. Software development Mode configuration detail After the RSTN is released, the INTN/TEST pin is internally pulled HIGH with a weak pull-up resistor. Therefore the default configuration is the device in normal operation. In order to configure the Software Development Mode, the following conditions have to be fulfilled:
• Init Mode from power-up
• VCC1>Vrtx
• POR=1
• R S T N = H I G H The Software Development Mode is configured using the following scheme:
• Only one external pull-down on INTN/TEST pin follow ed by an arbitrary SPI command, the device latches the Software Development Mode.
• External pull-up or no pull-do wn on INTN/TEST pin enable the device in normal operation.
• To enter Software Development Mode, a pull-down resistor to GND might be used. Figure 3 Software Development Mode Selection Timing Intn_filt is a filtered signal from INTN/TEST, with the filter time t SMD_F (P_11.2.7). Intn_filt starts (at the rising edge if RSNT) wit the value 1. The INTN/TEST is externally pulled-down Soft. Dev. Mode OFF for tSDM_F to avoid supply glitches Soft. Dev. Mode ON LATCHED (first SPI frame) Init Mode Normal Mode Successful latched Software Development Mode Time/us tSDM_FIntn_filt Mode RSTN INTN/TEST Intn_filt: internal filtered INTN/TEST signal Entry in Software Development Mode (not latched )

Datasheet 18 Rev. 1.0 2021-01-21 Note: If during monitoring the INTN /TEST pin for Software Development Mode entry, the device changes the mode without SPI command, the device will not enter/stay in Software Development Mode. CRC configuration detail The CRC is configured using the following scheme:

• Pull-down on PWM1/CRC enable the CRC.
• No external components on PWM1/CRC disables the CRC. In order to configure the CRC, the follow conditions have to be full filled:
• Init Mode (from power-up) or Restart Mode
• VCC1>Vrtx
• POR=1
• RSTN = LOW The configuration selection is done during the reset delay time t RD1 with a continuous filter time of tCFG_F and the configuration (depending on the voltage level at PWM1/CRC) is latched at the rising edge of RSTN. Figure 4 CRC configuration Selection Timi ng Diagram at the device power-up. In case of mismatch between CRC setting between the device and µC (CRC_STAT), the device can accept two recovery SPI commands (static patterns). The pattern 67AA AA0EH (addr + rw_bit = 67 ; data = AAAA ; CRC = 0E ) enables the CRC. The pattern E7AA AAC3H (addr + rw_bit = E7 ; data = AAAA ; CRC = C3) disables the CRC. The patterns shall be send only in Normal Mode. For additional details about the CRC setting and configuration, refer also to Chapter 11.3.1. t VCC1 t RSTN t VS_INT VPOR,r tRD1 VRT1,r tCFG_F Configuration selection monitoring period Continuous Filtering with

Datasheet 19 Rev. 1.0 2021-01-21

5.3 Block Description of State Machine

The state machine describes the different states of op eration, the device may ge t into. The following figure shows the state machine flow diagram. Figure 5 State Diagram show ing the operating modes Description:

• ON /OFF:= Indicate if the module is enabled or disabled either via SPI or from the device itself
• config:= Settings can be changed in this mode
• fixed:= Settings stay as defined in Normal Mode or Init Mode
• active/inactive:= Indicate if the device activates/deactivates one specific feature SPI cmd SPI cmd SPI cmd Any SPI command WD trigger First battery connection Automatic VCC1 Short to GND Soft Reset /g131/;#23#23#23Reset is released /g131/;#23#23#23WD starts with long open window (1) After Fail-Safe Mode entry, the device will stay for at least typ. 1s in this mode (with RSTN low) after a TSD2 event and min. typ. 100ms after other Fail-Safe Events. Only then the device can leave the mode via a wake-up event. Wake events are stored during this time. (2) HB Passive off due to gate-source resistors. TSD2 event * The Software Development Mode is a super set of state machine where the WD reset is not signaled. WK wake-up event OR Release of overtemperature TSD2 after a time depending on TSD2_DEL Init Mode * (Long open window) VCC1 ON CP(2) OFF WD fixed BD(2) OFF Cyc. Wake OFF Normal Mode VCC1 ON CP config. WD config. BD config. Cyc. Wake config. Stop Mode VCC1 ON CP(2) OFF WD fixed BD(2) OFF Cyc. Wake fixed Sleep Mode VCC1 OFF CP(2) OFF WD OFF BD(2) OFF Cyc. Wake fixed Fail-Safe Mode (1) VCC1 OFF CP(2) OFF WD OFF BD(2) OFF Cyc. Wake OFF Restart Mode (RO pin is asserted) VCC1 ON/ ramping CP(2) OFF WD OFF BD(3) OFF Cyc. Wake OFF Config.: settings can be changed in this device mode; Fixed: settings stay as defined in Normal Mode After 4x consecutive Watchdog failure VCC1 over voltage (depend from VCC1_OV_MOD setting) VCC1 over voltage (depend from VCC1_OV_MOD setting) VCC1 Under voltage Watchdog Failure Sleep Mode entry without any wake source enabled After 4x consecutive VCC1 under voltage events (if VS_INT > VS_INT_UV) Wake up event LS short circuit during VS_OV event CSA OFF CSA config. CSA OFF CSA OFF CSA OFF CSA OFF

Datasheet 20 Rev. 1.0 2021-01-21

5.4 State Machine Modes Description

5.4.1 Init Mode

The device starts up in Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 10.3) and the watchdog will start with a long open window (tLW) after RSTN is released (High level). In Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. Figure 6 Init Mode

5.4.2 Normal Mode

The Normal Mode is the standard operating mode for the device. The VCC1 is ac tive and all features are configurable. Supervision and monitoring features are enabled. Figure 7 Normal Mode Table 5 Init Mode Settings Part/Function Value Description VCC1 ON • The VCC1 is ON WD fixed • Watchdog is fixed and set with a long open window ( tLW) BD OFF • Bridge Drivers is OFF CP OFF •C h a r g e P u m p i s O F F CSA OFF • Current Sense Amplifier is OFF Cyc Wake OFF •C y c l e W a k e i s O F F Init Mode (Long open window) VCC1 ON CP OFF WD fixed BD OFF Cyc. Wake OFF CSA OFF Normal Mode VCC1 ON CP config. WD config. BD config. Cyc. Wake config. CSA config.

Datasheet 21 Rev. 1.0 2021-01-21

5.4.3 Stop Mode

The Stop Mode is the first level technique to reduce the overall current consumption VCC1 into a low-power mode. Note: All settings have to be done before entering Stop Mode. In Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to Normal Mode, triggering a device Soft Reset, refreshing the watchdog as well as for reading and clearing the SPI status registers. Note: A wake-up event on , WKx, Low-Side short circui t detection in parking braking mode or overvoltage brake detection, could generate an interrupt on pin INTN (based on INTN masking configuration; refer to Chapter 8) however, no change of the device mode will occur. Figure 8 Stop Mode Table 6 Normal Mode Settings Part/Function Value Description VCC1 ON •V C C 1 i s a c t i v e WD config • Watchdog may be configured by SPI BD/CP config • The Bridge Drivers and Charge Pump may be configured and switched ON or OFF by SPI CSA config • Current Sense Amplifier may be config urable and switched ON or OFF by SPI Cyc. Wake config • Cyclic wake can be configured with the Timer1 or Timer 2 Table 7 Stop Mode Settings Part/Function Value Description VCC1 ON •V C C 1 i s O N WD fixed • Watchdog is fixed as co nfigured in Normal Mode BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF Cyc. Wake fixed • Cyclic wake is fixed as configured in Normal Mode Stop Mode VCC1 ON CP OFF WD fixed BD OFF Cyc. Wake fixed CSA OFF

Datasheet 22 Rev. 1.0 2021-01-21 Note: In Stop Mode, it is possible to activate the Low-Si de of Bridge Drivers (e.g. in case of parking braking mode or overvoltage brake detection). Refer to Chapter 10.9 for additional details.

5.4.4 Sleep Mode

The Sleep Mode is the second level technique to re duce the overall current consumption to a minimum needed to react on wake-up events or for the device to perform autonomous actions . Note: All settings have to be done before entering Sleep Mode. Figure 9 Sleep Mode Note: In Sleep Mode, it is possible to activate the Low- Side’s of Bridge Drivers (e.g. in case of parking braking mode or overvoltage braking). Refer to Chapter 10.9 for additional details.

5.4.5 Restart Mode

The Restart Mode is a transition state where the RSNT pin is asserted. Figure 10 Restart Mode Table 8 Sleep Mode Settings Part/Function Value Description VCC1 OFF •V C C 1 i s O F F WD OFF • Watchdog is OFF BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF Cyc. Wake fixed • Cyclic wake is fixed Sleep Mode VCC1 OFF CP OFF WD OFF BD OFF Cyc. Wake fixed CSA OFF Restart Mode (RO pin is asserted) VCC1 ON/ ramping CP OFF WD OFF BD OFF Cyc. Wake OFF CSA OFF

Datasheet 23 Rev. 1.0 2021-01-21

5.4.6 Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning OFF VCC1 . After a wake event the system is then able to restart again. Figure 11 Fail-Safe Mode Note

• In Fail-Safe Mode, the default wake sources WKx (if co nfigured as wake inputs) are activated automatically and all wake event bits will be cleared.
• The Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake events during this time will be stored and will automatically lead to entering Restart Mode after the filter time. In case of an VCC1 overtemperature shutdown (TSD2) the Restart Mode will be reached automatically after a filter time of typ. 1s (tTSD2) without the need of a wake event once the device temperature has fallen below the TSD2 threshold.
• The parking braking mode is automa tically disabled in Fail-Safe Mode. Table 9 Restart Mode Settings Part/Function Value Description VCC1 ON/ ramping
• VCC1 is ON or ramping up WD OFF • WD will be disabled if it was activated before BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF Cyc. Wake OFF • Cyclic wake will be disabled if it was activated before Table 10 Fail-Safe Mode Settings Part/Function Value Description VCC1 OFF • VCC1 is switched OFF WD OFF •W D i s s w i t c h e d O F F BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF Cyc. Wake OFF • Cyclic wake is switched OFF Fail-Safe Mode VCC1 OFF CP OFF WD OFF BD OFF Cyc. Wake OFF CSA OFF

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5.4.7 Software Development Mode

The Software Development Mode is a dedicated devi ce configuration especially useful for software development. Compared to the default device user mode operation, this mode is a super set of the state machine. The device will start also in Init Mode and it is possible to use all the modes and functions with following differences:

• Restart Mode or Fail-Safe Mode (depending on the configuration) is not reached due to watchdog failure but the other reasons to enter these modes are still valid. Software Development Mode entry For timing and configuration details, refer to Chapter 5.2. Note
• After Init Mode, the pull-up is released as the INTN/T EST pin acts as output then to drive the INTN signal.
• If the device enters Fail-Safe Mode due to VCC1 shor t circuit to GND during the Init Mode, the Software Development Mode will not be entered and can only be reached at the next power-up of the device after the VCC1 short circuit is removed.
• The absolute maximum ratings of the pin INTN must be observed. To increase the robustness of this pin during debugging or programming a series resistor between INTN and the connector can be added. Watchdog in Software Development Mode The Watchdog is enabled in Software Development Mode as default state. One INTN event is generated due to wrong watchdog trigger. It is possible to deactivate the integrated Watchdog module using the WD_SDM_DISABLE bit. After disabling the Watchdog, no INTN events are generated and the WD_FAIL bit will also not be set anymore in case of a trigger failure. It is also possible only to mask / un mask the INTN event of the WD in Software Development Mode by using the bit WD_SDM. In case of unmasking, a WD trigger fail will only lead to WD_FAIL bit set.

5.5 Transition Between States

This chapter describes the transiti on between the modes triggered by power-up, SPI commands or wake-up events.

5.5.1 Transition into Init Mode

The device goes into Init Mode in case of a power-up or after sending a soft-reset in Normal or Stop Mode. Prerequisites:

• P o w e r O F F Table 11 Normal Mode Settings (Sof tware Development Mode active) Part/Function Default State

VCC1 ON •V C C 1 i s a c t i v e WD ON • WD is on, but will not trigger transi tion to Fail-Safe Mode or Restart Mode BD/CP OFF • The Bridge Drivers and Charge Pump may be configured and switched ON or OFF by SPI Cyc. Wake OFF •C a n b e c o n f i g u r e d

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• Device in Normal Mode or Stop Mode with follow conditions: –V S I N T > V P O R , r –R S T N H i g h Triggering Events:
• A Soft Reset command ( MODE = ‘11’). All SPI registers will be changed to their respective Soft Reset values. Note
• In case of Soft Reset command, a hardware RSTN ev ent can be generated depending on the configuration. An external Reset will be generated in case of SOFT_RESET_RO = 0 B . In case of SOFT_RESET_RO = 1B, no RSTN hardware event is generated in case of Soft Reset.
• At power-up, the SPI bit VCC1_UV will not be set as long as VCC1 is below the VRT,x threshold and if VSINT is below the VSINT,UV threshold. The RSTN pin will be kept LOW as long as VCC1 is below the selected VRT1,r threshold. The reset delay counter will start after VRT1,r threshold is reached. After the first threshold crossing of VCC1 > VRT1,R and RSTN transition from low to high, all subsequent undervoltage events will lead to Restart Mode.
• Wake events are ignored during Init Mode and will be lost.
• T h e b i t VSINT_UV will only be updated in Init Mode once RSTN resumes a high level.

5.5.2 Init Mode -> Normal Mode

This transition moves the device in the mode where all configurations are accessable via SPI command. Prerequisites:

• V S I N T > V P O R , r
• I n i t M o d e
• R S T N H i g h Triggering Events:
• Any valid SPI command (from SPI protocol point of vi ew) will bring the device to Normal Mode (i.e. any register can be written, cleared and read) during the long open window where the watchdog has to be triggered (refer also Chapter 11.2). The CRC is not taken into account for this transition.
• For example: – A SPI Sleep Mode command will still bring the device into Normal Mode. However, as this is an invalid state transition, the SPI bit SPI_FAIL is set. – Any invalid SPI command (from content point of view ) will still bring the device into Normal Mode. The SPI bit SPI_FAIL is set. Note
• It is recommended to use the first SPI command to trigger and to configure the watchdog.

5.5.3 Normal Mode -> Stop Mode

This transition is intended as first measure to reduce the current consumption. All the device features needed in Stop Mode shall be configured in Normal Mode. Prerequisites:

• VCC1>Vrtx
• Device in Normal Mode Triggering Events:

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• State transition is only init iated by specific SPI command. Note
• An interrupt is triggered on the pin INTN when Stop Mode is entered and not all wake source signalization flags were cleared.
• If high-side switches are kept enabled during St op Mode, then the device current consumption will increase.
• It is not possible to switch di rectly from Stop Mode to Sleep Mode. Doing so will also set the SPI_FAIL flag and will bring the device into Restart Mode.

5.5.4 Normal Mode -> Sleep Mode

This transition is intended to reduce as much as possible the current consumption keeping active only wake- up sources. All wake-up sources configurations shall be done in Normal Mode. Prerequisites:

• VCC1>Vrtx
• Device in Normal Mode
• All wake source signalization flags were cleared (including the LSxDSOV_BRK bit)
• At least one wake-u p source activated Triggering Events:
• State transition is only init iated by specific SPI command. Note
• I f VCC1_UV or VCC1_OV (with Config to go to Restart Mode) occurs at the border of the Sleep Mode entry: The device will go immeditaley into Restart Mode.
• I f TSD2 or VCC1_OV (with Config to go to Fail-Safe Mode) occurs at the border of the Sleep Mode entry: The device will enter immediately Fail-Safe Mode.
• As soon as the Sleep Mode command is sent, the Reset will go low.
• It is not possible to switch all wake sources off in Sleep Mode. Doing so will set the SPI_FAIL flag and will bring the device into Restart Mode.

5.5.5 Stop Mode -> Normal Mode

This transition is intented to set the device in Norm al Mode where all the device integrated features are availbale and configurable. Prerequisites:

• VCC1>Vrtx
• Device in Stop Mode Triggering Events:
• State transition is only initiated by SPI command. Note
• N o n e

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5.5.6 Sleep Mode -> Restart Mode

This transition is the consequence of a detection of wake-up event by the device. This transition is used to ramp up VCC1 after a wake in a defined way. Prerequisites:

• Device in Sleep Mode
• At least one wake-up source active Triggering Events:
• A wake-up event on WKx, Cyclic Wake.
• Bridge driver low-side short circuit detected duri ng overvoltage braking or in parking braking mode. Note
• It is not possible to switch off all wake sources in Sleep Mode. Doing so will set the SPI_FAIL flag and will bring the device into Restart Mode.
• RSTN is pulled low during Restart Mode.
• The Restart Mode entry is signalled in the SPI register DEV_STAT.
• The wake-up events are flaged in WK_STAT register or DSOV register.

5.5.7 Restart Mode -> Normal Mode

From Restart Mode, the device goes automatically to Normal Mode. Prerequisites:

• Device in Sleep Mode or Fail-Safe Mode Triggering Events:
• A u t o m a t i c
• Reset is released Note
• The watchdog timer will start with a long open window starting from the moment of the rising edge of RSTN and the watchdog period setting in the register WD_CTRL will be changed to the respective default value.

5.5.8 Fail-Safe Mode -> Restart Mode

This transition is similar to device from Sleep Mode to Restart Mode and consequence of a detection of wake- up event by the device. This transition is used to ramp up VCC1 after a wake in a defined way. Prerequisites:

• Device in Fail-Safe Mode Triggering Events:
• A wake-up event on WKx, TSD2 (rel eased over temperature TDS2 after t TSD2).
• Bridge Driver Low Side short circui t detected during VS/VSINT overvoltage braking mode or in parking braking mode. Note: After leaving Fail-Safe Mode, the FAILURE bit in DEV_STAT register is set.

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5.6 Reaction on Detected Faults

The device can react at some critical events either signalling the specific failure or changing the device mode. The chapter describes actions taken from the device in case of critical events in particular related the device mode change.

5.6.1 Stay in Current State

The following failures will not trigger any device mode changes, but will indicate the failures by an INTN event (depending from the Interrupt Masking) and in dedicated status registers:

• Failures in Bridge Driver and/or Charge Pump

5.6.2 Transition into Restart Mode

The Restart Mode can be entered in case of failure as shown in following figure. Figure 12 Move into Restart Mode Prerequisites

• In case of wake-up event from Sleep Mode or Fail Safe Mode
• I n c a s e o f N o r m a l M o d e
• In case of Stop Mode Trigger Events
• VCC1 Undervoltage in case of Normal Mode or Stop Mode.
• Watchdog trigger failure in case of Normal Mode or Stop Mode.
• VCC1 Overvoltage (based on VCC1_OV_MOD) in case of Normal Mode or Stop Mode.
• Sleep Mode entry without an y wake-up sources enabled in Normal Mode or Stop Mode. Note
• N o n e Restart Mode (RO pin is asserted) VCC1 ON/ ramping CP OFF WD OFF BD OFF Cyc. Wake OFF CSA OFF VCC1 over voltage (depend from VCC1_OV_MOD setting) VCC1 Under voltage Watchdog Failure Sleep Mode entry without any wake source enabled

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5.6.3 Transition into Fail-Safe Mode

The Fail-Safe Mode can be entered in case of critical event as shown in the following figure. Figure 13 Move into Fail-Safe Mode Prerequisites:

• Critical events on VCC1
• Watchdog trigger failures Trigger Events:
• Device thermal shutdown (TSD2) (see also Chapter 10.8.3).
• VCC1 is shorted to GND (see also Chapter 10.7).
• VCC1 over voltage (based on VCC1_OV_MOD).
• 4 consecutive Watchdog trigger failure.
• 4 consecutive VCC1 under voltage events.

5.7 Wake Features

Following wake sources are implemented in the device:

• Static Sense: WKx inputs are perm anently active as wake sources.
• Cyclic Wake: wake controlled by internal time rs, wake inputs are not used for cyclic wake.

5.7.1 Cyclic Wake

For the cyclic wake feature one timer is configured as internal wake-up source and will periodically trigger an interrupt on INTN in Normal Mode and Stop Mode. Du ring Sleep Mode, the timer triggers and wakes up the device again. The device enters via Restart Mode the Normal Mode. The correct sequence to configure the cyclic wake is shown in Figure 14. The sequence is as follows: VCC1 Short to GND TSD2 event Fail-Safe Mode VCC1 OFF CP OFF WD OFF BD OFF Cyc. Wake OFF CSA OFF After 4x consecutive Watchdog failure VCC1 over voltage (depend from VCC1_OV_MOD setting) After 4x consecutive VCC1 under voltage events (if VS_INT > VS_INT_UV)

Datasheet 30 Rev. 1.0 2021-01-21 Figure 14 Cyclic Wake: Configuration and Sequence Note: The on-time is only used to enable the cyclic wake function regardless of the value of the on time, i.e. the on time value has no meaning to the cyclic wake function as long as it is not ‘000’ or ‘110’ or ‘111’. The cyclic wake function will start as soon as the on-time is configured. An interrupt is generated for every start of the on-time except for the very first time when the timer is started.

5.7.2 Internal Timers

Two integrated timers can be used to control the below features:

• Cyclic Wake, i.e. to wake up the microcontroller peri odically in Normal Mode, Stop Mode and Sleep Mode. Cyclic Wake Configuration Cyclic Wake starts / ends by setting / clearing On-time INTN is pulled low at every rising edge of On-time except first one Select Timer Period and any On-Time in TIMER_CTRL Periods: 10, 20, 50, 100, 200ms, 1s, 2s On-times: any (OFF/LOW & OFF/HIGH are not allowed) Disable Timer1 and Timer2 as a wake source in TIMER_CTRL To avoid unintentional interrupts Select Timer1 or Timer2 as a wake source in TIMER_CTRL No interrupt will be generated, if the timer is not enabled as a wake source

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5.8 VS Supply Multiplexing

Figure 15 VS Supply Multiplexing The internal supply voltage is multiplexed from VSINT and VS, choosing continuously the larger of both. In case of transient low VBAT, the buffered supply voltage takes over the internal supply, avoiding loss of power. Note: Only the internal digital logic of the device is supplied by the VMAX SWITCH. In case of a power loss of either VS or VSINT, the internal register values will not be lost. MUX VSINT VS INTERNAL SUPPLY VMAX SWITCH

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6 Voltage Regulator 1

VCC1 is a voltage reference for the current sense amplifier, for the SPI interface and for the PWM inputs. VCC1 has its own internal voltage regulator and may not be connected to the output of another voltage regulator.

6.1 Block Description

Figure 16 Module Block Diagram Functional Features

• 5 V low-drop voltage regulator.
• Undervoltage monitoring with adjustable reset le vel and VCC1 undervoltage prewarning (refer to Chapter 10.6 and Chapter 10.7 for more information).
• Short circuit detection and switch off with undervoltage fail threshold, device enters Fail-Safe Mode.
• Effective capacitance must be ≥1 µF at nominal voltage output for stability. A 2.2 µF ceramic capacitor (MLCC) is recommended for best transient response.
• Output current capability up to IVCC1,lim. GND Overtemperature Shutdown Bandgap Reference VSINT State Machine VCC1 INH Vref

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6.2 Functional Description

The Voltage Regulator 1 (=VCC1) is “ON” in Normal Mode and Stop Mode and is disabled in Sleep Mode and in Fail-Safe Mode. The regulator can provide an output current up to IVCC1,lim. For low-quiescent current reasons, the output voltage tolerance is decreased in Stop Mode because only the less accurate low-power mode regulator will be active for small loads. If the load current on VCC1 exceeds the selected threshold (I VCC1,Ipeak1,r or I VCC1,Ipeak2,r) then the high-power mode regu lator will be also activated to support an optimum dynamic load behavior. The curr ent consumption will then increase (approx. 2.8 mA additional quiescent current). The device mode stays unchanged. If the load current on VCC1 falls below the selected threshold (I VCC1,Ipeak1,f or IVCC1,Ipeak2,f), then the low-quiescent current mode is resumed again by disabling the high-power mode regulator. Both regulators (low-power mode and high-power mode) are active in Normal Mode. Two different active peak thresholds can be selected via SPI:

• I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current consumption in Stop Mode.
• I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current consumption in Stop Mode.

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6.3 Electrical Characteristics

Table 12 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output Voltage including Line and Load Regulation VCC1,out1 4.9 5.0 5.1 V 1)Normal Mode; 10 µA < IVCC1 < 150 mA; P_6.3.1 Output Voltage including Line and Load Regulation (Full Load Current Range) VCC1,out2 4.9 5.0 5.1 V 1)Normal Mode; 6V < VSINT < 28 V; 10 µA < IVCC1 < 250 mA P_6.3.2 Output Voltage including Line and Load Regulation (Higher Accuracy Rage) VCC1,out3 4.95 – 5.05 V 2)Normal Mode; 20 mA < IVCC1 < 80 mA; 8V < VSINT < 18 V; 25°C < Tj < 150°C P_6.3.3 Output Voltage including Line and Load Regulation (low-power mode) VCC1,out4 4.9 5.05 5.2 V Stop Mode; 10 µA < IVCC1 < IVCC1,Ipeak P_6.3.4 Output Drop Voltage VCC1,d1 – 200 400 mV IVCC1 = 50 mA, VSINT = 5 V P_6.3.9 Output Drop Voltage VCC1,d2 – 300 500 mV IVCC1 = 150 mA, VSINT = 5 V P_6.3.10 VCC1 Active Peak Threshold 1 (Transition threshold between low-power and high- power mode regulator) I VCC1,Ipeak1,r –3 . 2 5 5 . 0 m A 2) ICC1 rising; VSINT = 13.5 V; I_PEAK_TH = ‘0’ P_6.3.17 VCC1 Active Peak Threshold 1 (Transition threshold between high-power and low- power mode regulator) IVCC1,Ipeak1,f 1.2 1.7 – mA 2) ICC1 falling; VSINT = 13.5V; I_PEAK_TH = ‘0’ P_6.3.18 VCC1 Active Peak Threshold 2 (Transition threshold between low-power and high- power mode regulator) IVCC1,Ipeak2,r 6– 2 0 m A 2) ICC1 rising; VSINT = 13.5 V; I_PEAK_TH = ‘1’ P_6.3.19 VCC1 Active Peak Threshold 2 (Transition threshold between high-power and low- power mode regulator) I VCC1,Ipeak2,f 5– 1 5 m A 2) ICC1 falling; VSINT = 13.5V; I_PEAK_TH = ‘1’ P_6.3.20 Overcurrent Limitation IVCC1,lim 260 360 500 mA current following out of pin, VCC1= 0V 2) P_6.3.21

Datasheet 35 Rev. 1.0 2021-01-21 Minimum Output Capacitance for stability CVCC1,min 13) –– µ F 2) P_6.3.22 Maximum Output Capacitance CVCC1,max –– 4 7 µ F 2) P_6.3.23 1) In Stop Mode, the specified output voltage tolerance applies when I VCC1 has exceeded the selected active peak threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) but with increased current consumption. 2) Not subject to production test, specified by design. 3) Value is meant to be an effective value at rated output voltage level. Table 12 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

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7 High-Voltage Wake Input

The WK4 pin is used to wake up the device.

7.1 Block Description

Figure 17 Wake Input Block Diagram

• High-Voltage inputs with a 3 V (typ.) threshold voltage.
• Wake-up capability for power saving modes.
• Edge sensitive wake feature low to high and high to low.
• Pull-up and Pull-down current sources, configurable via SPI.
• In Normal Mode and Stop Mode the level of the WKx pin can be read via SPI. tWK WKx Internal Supply Logic IPD_WK IPU_WK VRef

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7.2 High-Voltage Wake Function

7.2.1 Functional Description

The wake inputs pin are edge-sensitive inputs with a switching threshold of typically 3 V. Both transitions, high to low and low to high, result in a signalization by the device. The signalization occurs either in triggering the interrupt in Normal Mode and Stop Mode or by a wake up of the device in Sleep Mode and Fail-Safe Mode. A filter time tFWKx is implemented to avoid an uninte ntional wake-up due to transients or EMC disturbances in static sense configuration. The filter time (tFWKx) is triggered by a level change crossing the switching threshold and a wake signal is recognized if the input level will not cross again the threshold during the selected filter time. Figure 18 shows a typical wake-up timing and filtering of transient pulses. Figure 18 Wake-up Filter Timing for Static Sense The wake-up capability for the WKx pin can be enabled or disabled via SPI command. A wake event via the WKx pin can always be read in the register WK_STAT. The actual voltage level of the WKx pin (low or high) can always be read in Normal Mode, Stop Mode and Init Mode in the register WK_LVL_STAT.

7.2.2 Wake Input Configuration

To ensure a defined and stable voltage levels at the in ternal comparator input it is possible to configure integrated current sources via the SPI register WK_CTRL. Table 13 Pull-Up / Pull-Down Resistor WKx_PUPD_ WKx_PUPD_ Current Sources Note 00n o c u r r e n t source WK input is floating if left open (default setting) 0 1 pull-down WK input internally pulled to GND VWKTh,f t VWKx tFWK No Wake Event Wake Event VWKth,f tFWK t VINTN tINTN

Datasheet 38 Rev. 1.0 2021-01-21 Note: If a WK input is not used, the respective WK inpu t must be tied to GND on board to avoid unintended floating state of the pin. One additional configuration is related the filter time of each Wake-up module. The bits WK_FILT permit to set the filter time in static sensing. Note: When the device mode is changed to normal (from INIT ), in case of static sense, if the WK pin is set, the WK_STAT register is set in this time (also the interrupt pin). 1 0 pull-up WK input internally pulled to internal 5V supply 1 1 Automatic switching If a high level is detected at the WK input the pull-up source is activated, if low level is detected the pull down is activated. Table 13 Pull-Up / Pull-Down Resistor (cont’d) WKx_PUPD_ WKx_PUPD_ Current Sources Note

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7.3 Electrical Characteristics

Table 14 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. WK4 Input Pin Characteristics Wake-up/monitoring threshold voltage falling VWKx_th,f 2.5 3 3.5 V without external serial resistor RS P_10.3.1 Wake-up/monitoring threshold voltage rising VWKx_th,r 3 3.5 4 V without external serial resistor RS P_10.3.2 Threshold hysteresis VWKx_th,hys 0.4 0.6 0.85 V without external serial resistor RS P_10.3.3 WK pin Pull-up Current IPU_WKx -20 -10 -3 µA VWKx = 4 V P_10.3.4 WK pin Pull-down Current IPD_WKx 31 0 2 0 µ A VWKx = 2.5 V P_10.3.5 Input leakage current ILK,lx -2 2 µA 0 V < VWKx < 40 V; Pull-up / Pull-down disabled P_10.3.6 Timing Wake-up filter time 1 tFWK1 12 16 22 µs 1) 1) Not subject to production test, tolerance defined by internal oscillator tolerance. P_10.3.16 Wake-up filter time 2 tFWK2 50 64 80 µs 1) P_10.3.17

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8 Interrupt Function

8.1 Block and Functional Description

Figure 19 Interrupt Block Diagram The interrupt is used to signalize sp ecial events in real time to the mi crocontroller. The interrupt block is designed as a push/pull output stage as shown in Figure 19. An interrupt is triggered and the INTN pin is pulled low (active low) for t INTN in Normal Mode and Stop Mode and it is released again once t INTN is expired. The minimum high-time of INTN between two consecutive interrupts is tINTND. An interrupt does not cause a device mode change. Two different interrupt generation methods are implemented:

• Interrupt Mask: One dedicated register (INT_MASK) is intended to enable or disable set of interrupt sources. The interrupt sources follow the SPI Status Information Field. In details: – SUPPLY_STAT: “OR” of all bits on SUP_STAT register except POR, VCC1_UV, VCC1_SC, VCC1_OV – TEMP_STAT: “OR” of all bits on THERM_STAT register except TSD2 – BD_STAT: “OR” of all bits on DSOV register – SPI_CRC_FAIL: or between SPI_FAIL and CRC_FAIL bits on DEV_STAT register.
• Wake-up events: all wake-up events stored in the wake status SPI register WK_STAT only in case the corresponding input was configured as wake-up source. The wake-up sources are: –v i a W K p i n – via TIMERx (cyclic wake) – via LSx_DSOV_BRK if any of the brake-feature is enabled The methods are both available at the same time. Note: The errors which will cause Restart or Fail-S afe Mode (VCC1_UV, VCC1_SC, VCC1_OV, TSD2) are the exceptions of an INTN generation. Also the bit POR will not generate interrupts. If the above mentioned bits are not cleared after the device is back in Normal Mode or Stop Mode, the INTN is periodically generated (Register based cyclic interrupt generation). Note: Periodical interrupts are only generated by CRC fail and SPI fail from DEV_STAT register. INTERRUPT BLOCK.VSD Interrupt logic INTNTime out Vcc1

Datasheet 41 Rev. 1.0 2021-01-21 Note: During Restart Mode the SPI is blocked and the micr ocontroller is in reset. Therefore the INTN will not be in Restart Mode, which is the same behavior in Fail-Safe Mode or Sleep Mode. In addition to this behavior, INTN will be triggered when Stop Mode is entered and not all wake source bits were cleared in the WK_STAT register and also the LSx_DSOV_BRK bits in the DSOV register.. The SPI status registers are updated at every falling edge of the INTN pulse. All inte rrupt events are stored in the respective register until the register is cleared via SPI command. A second SPI read after reading out the respective status register is optional but recommended to verify that the interrupt event is not present anymore. The interrupt behavior is shown in Figure 20. The INTN pin is also used during Init Mode to select the Software Development Mode entry. See Chapter 5.2 for further information. In case of pending INTN event (SPI Status registers are not cleared after INTN event), additional periodical INTN events are generated as shown in Figure 21. The periodical INTN events generation can be disabled via SPI command using INTN_CYC_EN bit. Figure 20 Interrupt Si gnalization Behavior Note: For two or more interrupt events at the same time, when INTN pin is low the same time, it will not start multiple toggling. INTN WKx tINTN tINTD Update of WK_STAT register SPI Read & Clear Update of WK_STAT register WK_STAT

contents

Scenario 1 WKx no WK no WK optional SPI Read & Clear WK_STAT No SPI Read & Clear Command sent

Datasheet 42 Rev. 1.0 2021-01-21 Figure 21 Interrupt Signal ization Behavior in case of pending INTN events INTN WKx tINTN tINTN_PULSE Update of WK_STAT register SPI Read & Clear WK_STAT No SPI Read & Clear Command sent WKx tINTN tINTN_PULSE No SPI Read & Clear Command sent WKx

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8.2 Electrical Characteristics

Table 15 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Interrupt Output; Pin INTN INTN High Output Voltage VINTN,H 0.8 × VCC1 –– V 1)IINTN = -2 mA; INTN = off 1) Output Voltage Value also determines device configuration during Init Mode. P_11.2.1 INTN Low Output Voltage VINTN,L – – 0.2 × VCC1 V 1)IINTN = 2mA; INTN = on P_11.2.2 INTN Pulse Width tINTN 80 100 120 µs 2) 2) Not subject to production test, tolerance defined by internal oscillator tolerance. P_11.2.3 INTN Pulse Minimum Delay Time tINTND 80 100 120 µs 2) between consecutive pulses P_11.2.4 Pulse in case of pending INTN tINTN_PUL SE 45 6m s 2) between consecutive pulses P_11.2.5 SDM Select; Pin INTN Config Pull-up Resistance RSDM 30 60 100 k Ω VINTN = 5 V P_11.2.6 Config Select Filter Time tSDM_F 50 64 80 µs 2) P_11.2.7

Datasheet 44 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9 Gate Drivers

The TLE9185QX integrates six floating gate drivers capable of controlling a wide range of N-channel MOSFETs. They are configured as three high-sides and three low-sides, building three half-bridges. Figure 22 Half-bridge gate driver - Block diagram This section describes the MOSFET control in static activation and during PWM operation. Note: PWMx mentioned in this chapter refer to the PWMx pins and signal used by the bridge driver to control the external MOSFETs.

9.1 MOSFET control

Depending on the configuration bits HBxMODE[1:0] (refer to HBMODE), CPEN, each high-side and low-side MOSFETs can be:

• Kept off with the passive discharge.
• K e p t o f f a c t i v e l y . Current-Steering DACs SL GLx GHx VS VCP VDSMONTH VCP High-Speed Comparators Lowside Gate-Driver Highside Gate-Driver Current-Steering DACs Logic IPDDIAG VDSMONTH IPUDIAG ISINK_BRAKE SHx

Datasheet 45 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

• Activated (statically, no PWM, HBx_PWM_EN = 0).
• Activated in PWM mode (HBx_PWM_EN = 1). Refer to Table 16 for details.

9.2 Static activation

In this section, we consider the st atic activation of the high-side and low-side MOSFET of the half-bridge x: HBx_PWM_EN= 0 (in ST_ICHG) and CPEN = 1. T h e l o w - s i d e o r h i g h - s i d e M O S F E T o f H B x i s s t a t i c a l l y a c t i v a t e d ( n o P W M ) b y s e t t i n g H B x M O D E [ 1 : 0 ] t o respectively (0,1) or (1,0). The configured active cross-current protection and the Drain-Source overvoltage blank times for the Half- Bridge x are noted tHBxCCP ACTIVE and tHBxBLANK ACTIVE. The charge and discharge currents applied to the static controlled Half-Bridge x are noted ICHGSTx (ST_ICHG). IHARDOFF is the maximum current that the gate drivers can sink (150 mA typ.). This current is used to keep a MOSFET off, when the opposite MOSFET of the same half-bridge is being turned on. This feature reduces the risk of parasitic cross-current conduction. ICHGSTx is the current sourced, respec tively sunk, by the gate driver to turn-on the high-side x or low-side x. ICHGSTx is configured in the control register ST_ICHG. Table 16 Half-bridge mode selection CPEN HBxMODE[1:0] 1) 1) x = 1 … 3 Configuration of HSx/LSx1) CPEN = 0 Don’t care All MOSFETs are ke pt off by the passive discharge CPEN = 1 00 B HBx MOSFETs are kept off by the passive discharge CPEN = 1 01 B LSx MOSFET is ON, HSx MOSFET is actively kept OFF CPEN = 1 10 B HSx MOSFET is ON, LSx MOSFET is actively kept OFF CPEN = 1 11 B LSx and HSx MOSFETs are actively kept OFF with IHOLD Table 17 Static charge currents ICHGSTx[3:0] Nom. charge current [mA] Nom. discharge current [mA] Max. deviation to typ. values 0000B 0.5 (ICHG0)0 . 5 ( IDCHG0) +/- 60% 0001B 1.8 (ICHG4)1 . 8 ( IDCHG4) +/- 60 % 0010B 4.7 (ICHG8)4 . 7 ( IDCHG8) +/- 60 % 0011B 9.4 (ICHG12)9 . 4 ( IDCHG12) +/- 60 % 0100B 15.3 (ICHG16) 15.1 ( IDCHG16) +/- 40 % 0101B 23 (ICHG20) 22.5 ( IDCHG20) +/- 40 % 0110B 31.6 (ICHG24) 30.9 ( IDCHG24) +/- 40 % 0111B 41.6 (ICHG28) 40.8 ( IDCHG28) +/- 40%

Datasheet 46 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers IHOLD is the hold current used to keep the gate of the external MOSFETs in the desired state. This parameter is configurable with the IHOLD control bit in GENCTRL. If the control bit IHOLD = 0:

• A MOSFET is kept ON with the current ICHG15.
• A MOSFET is kept OFF with the current IDCHG15. If the control bit IHOLD = 1:
• A MOSFET is kept ON with the current ICHG20.
• A MOSFET is kept OFF with the current IDCHG20.

9.2.1 Static activation of a high-side MOSFET

Turn-on with cross-current protection If LSx is ON (HBxMODE[1:0] = 01 B), before the activation of HSx (HBxMODE[1:0] = 10 B) then the high-side MOSFET is turned on after a cross-current protection time (refer to Figure 23):

• After the CSN rising edge and for the duration tHBxCCP ACTIVE : – The high-side MOSFET is kept OFF with the current -ICHGSTx. – The gate of the low-side MOSFET is discharged with the current -ICHGSTx.
• At the end of tHBxCCP ACTIVE and for the duration tHBxBLANK ACTIVE + tFVDS: – The gate of the high-side MOSFET is charged with the current ICHGSTx. – Low-side MOSFET is kept OFF with th e current -IHARDOFF (hard off phase).
• At the end of tFVDS: – The drive current of the high-s ide MOSFET is reduced to IHOLD. – The drive current of the low-si de MOSFET is set to -IHOLD. 1000B 52.5 (ICHG32) 51.5 ( IDCHG32) +/- 30 % 1001B 63.6 (ICHG36) 62.4 ( IDCHG36) +/- 30 % 1010B 75.2 (ICHG40) 73.7 ( IDCHG40) +/- 30 % 1011B 87.1 (ICHG44) 85.5 ( IDCHG44) +/- 30 % 1100B 99.5 (ICHG48) 97.7 ( IDCHG48) +/- 30 % 1101B 112.2 (ICHG52) 110.8 ( IDCHG52) +/- 30 % 1110B 125.3 (ICHG56) 124.5 ( IDCHG56) +/- 30 % 1111B 139 (ICHG60) 138.7 ( IDCHG60) +/- 30 % Table 17 Static charge currents (cont’d) ICHGSTx[3:0] Nom. charge current [mA] Nom. discharge current [mA] Max. deviation to typ. values

Datasheet 47 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 23 Turn-on of a high-side MOSFET with cross-current protection Note: The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are executed with a delay of up to 3 µs after the CSN rising edge. VS SHx HSx LSx Previous State  N e w S t a t e HSx OFF  HSx ON LSx ON  LSx OFF GHx GLx IGHx IGLx SL CSN t t IGLx -ICHGSTx t IGHx tHBxCCP Active ICHGSTx tHBxBLANK Active t HSx internal drive signal ICHGSTx tFVDS -IHOLD IHOLD t-IHOLD IHOLD -ICHGSTx -IHARDOFF Hard off LSx internal drive signal -ICHGSTx SPI Frame accepted Turn on HSx

Datasheet 48 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Turn-on without cross-current protection If LSx is OFF (HBxMODE[1:0] = 11 B), before the activation of HSx (HBxMODE[1:0] = 10 B), then the high-side MOSFET is turned on without cross-current protection (refer to Figure 24):

• right after the CSN rising edge and for a duration tHBxBLANK ACTIVE + tFVDS: – The gate of the high-side MOSFET is charged with the current ICHGSTx. – The low-side MOSFET is kept OFF with the current -IHARDOFF.
• At the end of tFVDS: – The drive current of the high-s ide MOSFET is reduced to IHOLD. – The drive current of the low-si de MOSFET is set to -IHOLD. Figure 24 Turn-on of a high-side MO SFET without cross-current protection Note: The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are executed with a delay of up to 3 µs after the CSN rising edge. Previous State  N e w S t a t e HSx OFF  HSx ON LSx OFF  LSx OFF VS SHx HSx LSx GHx GLx IGHx IGLx SL CSN t t IGLx t IGHx ICHGSTx tHBxBLANK Active t ICHGSTx tFVDS -IHOLD IHOLD t-IHOLD IHOLD -IHARDOFF Hard off HSx internal drive signal LSx internal drive signal SPI Frame accepted Turn on HSx

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9.2.2 Static activation of a low-side MOSFET

The description of the static activation of a low-side x differs from the description of Chapter 9.2.1 only by exchanging high-side x and low-side x.

9.2.3 Turn-off of the high-side and low-side MOSFETs of a half-bridge

When the TLE9185QX receives a SPI command to turn-off both the high-side and low-side MOSFETs of the half- bridge x (HBxMODE[1:0] = (0,0) or (1,1)):

• The gate of HSx and LSx are discharged wi th the current -ICHGSTx for the duration tHBxCCP ACTIVE (Figure 25).
• At the end of tHBxCCP ACTIVE, the drive current of HSx and LSx are reduced to -IHOLD. Figure 25 Turn-off of the high-side and low-side MOSFETs of a half-bridge Note: The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are executed with a delay of up to 3 µs after the CSN rising edge. VS SHx HSx LSx GHx GLx IGHx IGLx SL CSN t t IGLx t IGHx -ICHGSTx t HSx internal drive signal -IHOLD IHOLD t-IHOLD -ICHGSTx LSx internal drive signal -ICHGSTx SPI Frame accepted Turn off HSx and LSx tHBxCCP Active

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9.3 PWM operation

The half-bridge can be controlled in PWM using either three or six PWM inputs. The TLE9185QX offers the possibility to detect the active and the freewhe eling (FW) MOSFET in each half- bridge.

9.3.1 Determination of the active and freewheeling MOSFET

If EN_GEN_CHECK = 1, right before each MOSFET acti vation, the device detects which MOSFET of the half- bridge is the active MOSFET and which MOSFET is the free-wheeling (FW) MOSFET:

• If VSHx > VS - VSHH: The high-side MOSFET is the FW MOSFET and the low-side MOSFET is the active MOSFET.
• If VSHx < VSHL: Then the low-side MOSFET is the FW MOSFET and the high-side MOSFET is the active MOSFET.
• If VSHL < VSHx < VSHH: No clear distinction between the active FW MOSFET and the active MOSFET. The next MOSFET to be turned on is turned on as if it was the active MOSFET. If EN_GEN_CHECK = 0, the detection of the active and FW MOSFET is disabled. The PWM MOSFET is considered as the active MOSFET. Figure 26 shows the detection of the active and of the FW MOSFET. Figure 26 Detection of the ac tive and FW MOSFET - Principle

9.3.2 Configurations in PWM mode

The following sections describe the different control schemes in PWM mode. SL GLx SHx GHx VS VCP VCP High-Speed Comparators Lowside Gate-Driver Highside Gate-Driver VSHH VSHL HS and LS off Freewheeling through high-side MOSFET body diode VSHx > VSHH HS = FW MOSFET LS = Active MOSFET HS and LS are off Freewheeling through low-side MOSFET body diode VSHx < VSHL LS = FW MOSFET HS = Active MOSFET SL GLx SHx GHx VS VCP VCP High-Speed Comparators Lowside Gate-Driver Highside Gate-Driver VSHH VSHL

Datasheet 51 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Active gate control (AGC) The active gate control is configured by the control bi ts AGC[1:0]. The control scheme during the pre-charge and pre-discharge phases of:

• T h e a c t i v e M O S F E T (EN_GEN_CHECK=1).
• The PWM MOSFET ( EN_GEN_CHECK=0). can be selected. The following settings are possible:
• Adaptive gate control (AGC[1:0] = (1,0) or (1,1), see GENCTRL): In this mode a pre-charge current and a pre- discharge current are applied to the gate of the controlled MOSFET. These currents are used to regulate effective the turn-on and turn-off delays to the respective target values.
• No adaptive gate control (AGC[1;0] = (0,0)): in th is mode, the pre-charge and pre-discharge phases are deactivated.
• No adaptive gate control (AGC[1;0] = (0,1)). In this mode: – During the pre-charge phase, the MOSFET is disc harged with the configured current IPCHGINIT (HB_PCHG_INIT). – During the pre-discharge phase, th e MOSFET is discharged with the configured current IPDCHGINIT (HB_PCHG_INIT). Note: It is recommended to configure tPCHGx < tHBxBL ANK Active and tPDCHGx < tHBxCCP Active (Refer to TPRECHG and CCP_BLK) independently from the AGC settings. Active free-wheeling (AFW) The active free-wheeling is activated for HBx if these conditions are fulfilled:
• AFWx = 1 ( HBMODE)
• HBx_PWM_EN = 1 ( HBMODE)
• PWM_NB = 0 If AFWx = 1, a cross-current protection time is applied to HBx (set by CCP_BLK) during the PWM operation. If AFWx = 0, no cross current protection is applied to HBx during the PWM operation. The active free-wheeling reduces the power dissipation of the free-wheeling MOSFET. If an active MOSFET is OFF, the opposite MOSFET of the same half-bridge is actively turned on. Refer to Figure 30 and Figure 31.

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9.3.3 PWM operation with 3 PWM inputs

Each half bridge are controlled by one input if PWM_NB = 0 (see CSA) and HBx_PWM_EN (see HBMODE):

• PWM1/CRC controls HB1
• P W M 3 c o n t r o l s H B 2
• P W M 5 c o n t r o l s H B 3 tHBxBLANK FW Freewheeling drain-sour ce overvoltage blank time of HBx. See control register and CCP_BLK. PWMz External PWM signal applied to the input pin PWMz. ICHGMAXx Maximum drive current of the half-bridg e x during the pre-charge and pre-discharge phases. See control register HB_ICHG_MAX. IPRECHGx and IPREDCHGx are limited to ICHGMAXx. IPRECHGx Pre-charge current sourced by the gate dr iver to the active MOSFET of the half-bridge x during tPCHGx (TPRECHG). Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL). IPRECHGx is clamped between ICHG0 (0.5 mA typ.) and ICHGMAXx. IPCHGINITx Initial value of IPRECHGx. Refer to HB_PCHG_INIT. IPREDCHGx Pre-discharge-current sunk by the gate driver mapped to the half-bridge x during tPDCHGx. Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL). IPREDCHGx is clamped between I DCHG0 (0.5 mA typ.) and ICHGMAXx. IPDCHGINITx Initial value of IPREDCHGx. Refer to HB_PCHG_INIT. ICHGx Current sourced by the gate driver to the active MOSFET of the half-bridge x during the charge phase. See control register HB_ICHG. IDCHGx Current sunk by the gate driver to turn-off the active MOSFET of the half-bridge x during the discharge phase. See control register HB_ICHG. ICHGFWx Current sourced or sunk by the gate dr iver to turn on / turn off the freewheeling MOSFET of the half-bridge x . See control register HB_ICHG. tPCHGx Duration of the pre-charge phase of half-bridge x. tPCHGx is configurable by SPI. See control register TPRECHG. tPDCHGx Duration of the pre-disc harge phase of half-bridge x. tPDCHGx is configurable by SPI. See control register TPRECHG. tDONx Turn-on delay of th e active MOSFET of HBx. tDOFFx Turn-off delay of the active MOSFET of HBx. IHOLD Hold current sourced or sunk by the gate driver to keep the MOSFET in the desired state. See IHOLD control bit in GENCTRL. IHARDOFF IHARDOFF is the maximum current that th e gate drivers can sink. It corresponds to the discharge current when IDCHGx[5:0] = 63D (150 mA typ.). TFVDS Drain-Source overvoltage filter time. See LS_VDS. Table 18 Abbreviations for adaptive turn-on and turn-off phases in PWM configuration (cont’d) Abbreviation Definition

Datasheet 54 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 29 Half-bridge PWM control with three PWM inputs, PWM_NB = 0

9.3.3.1 Control signals with active free-wheeling (AFWx = 1)

This section describes the MOSFET control signals with active freewheeling and HS PWM:

9.3.3.1.1 The PWM MOSFET is the active MOSFET

This section shows the control signals of the MOSFET when the PWM is the active MOSFET. Table 19 Half-bridge PWM settings with 3 PWM inputs PWM_NB HBxPWM_ EN1) 1) x = 1 to 3 HBxMODE1) AFW Half-bridge x settings 1) 0D o n ’ t c a r e 0 0 B Don’t care LSx and HSx MOSFETs are kept OFF by the passive discharge 01 0 1 B 0 PWM signal applied to LSx PWM signal = 1: LSx, ON, HSx OFF PWM signal = 0: LSx OFF, HS x OFF 01 1 0 B 1 PWM signal applied to HSx PWM signal= 1: HSx, ON, LSx OFF PWM signal = 0: HSx OFF, LS x ON 0D o n ’ t c a r e 1 1 B Don’t care LSx and HSx MOSFET s are actively kept OFF SL VSCP CP SL VSCP CP SL VSCP CP Control PWM1 PWM2 µC_PWM3 µC_PWM5 µC_PWM1 PWM3 PWM4 PWM6 PWM5 HS1 LS1 HS2 LS2 HS3 LS3

Datasheet 55 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 30 Turn-on of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10B (HS PWM), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) VSHx VSHL VSHH IGS_HSx IPRECHGx ICHGMAXx ICHGx VGS_HSx tDONx tRISEx Postcharge Phase VSHL Synchronized intern. PWM signal t t t t IDS_HSDx IPHASE tHBxBLANK Active VSHH VS IPRECHGx HSx internal drive signal t - IHOLD IHOLD ICHGMAXx ICHGx IHOLD LSx internal drive signal - IHARDOFF IHOLD t Hard off - IHOLD Charge phase tFVDS ICHGx t HS MOSFET (Active MOSFET)LS MOSFET (FW MOSFET) - ICHGFWx - IHOLD tHBxCCP FW tPCHGx tHBxCCP FW VSHx < VSHL right before activation of HSx HSx detected as active MOSFET t tPWM_SYNCHExternal PWM signal

Datasheet 56 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 31 Turn-off of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10B (HS PWM), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) tFALLx t t t t t tDOFFx VSHL VSHH - IDCHGx - IHOLD Discharge phase Hard off t tPWM_SYNCH tPDCHGx t IHOLD tFVDS tHBxCCP Active tHBx_BLANK FW VGS_HSx VSHx VSHL VSHH IDS_HSDx IPHASE VS HSx internal drive signal - IHOLD IHOLD - IPREDCHGx - IDCHGx - IHARDOFF HS MOSFET (Active) LS MOSFET (FW) LSx internal drive signal - IHOLD IHOLD ICHGFWx Synchronized intern. PWM signal External PWM signal VSHx < VSHL right before activation of LSx LSx detected as FW MOSFET

Datasheet 57 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.3.3.1.2 The PWM MOSFET is the free-wheeling MOSFET

This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET. Figure 32 PWM rising edge - PWM mode with active gate control, HS PWM (HBxMODE = 10B) , LS as active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) t VGS_LSx tFALLx tPDCHGx t t t t tDOFFx VSHH tHBxBLANK FW tHBxCCP Active for cross current protection VSHx VSHL VSHH IGS_LSx IGS_HSx - IPREDCHGx - IDCHGx IDS_LSDx IPHASE VS HSx internal drive signal t - IHOLD IHOLD LSx internal drive signal t - IHARDOFF - IHOLD IHOLD - IPREDCHGx - IDCHGx - IDCHGx - IHOLD IHOLD Discharge phase tFVDS tFVDS Hard off VSHL t Synchronized intern. PWMz t External PWMz tPWM_SYNCH Low-side = Active MOSFET High-side = FW MOSFET and PWM MOSFET \\G D i \\fi \\BLDC ICHGFWx ICHGFWx Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET

Datasheet 58 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 33 PWM falling edge - PWM mode with active gate control, HS PWM (HBxMODE = 10B) , LS as active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) VSHx VSHL VSHH IGS_LSx IGS_HSx IPRECHGx ICHGMAXx ICHGx VGS_LSx tDONx tRISEx Postcharge Phase VSHL 0 t t t t tPCHGx t IDS_LSDx tHBxCCP FW tHBxBLANK Active VS IPRECHGx LSx internal drive signal t - IHOLD IHOLD ICHGMAXx ICHGx IHOLD HSx internal drive signal - IHARDOFF - IHOLD IHOLD t Hard off - IHOLD Charge phase tFVDS tFVDS ICHGx VSHH Synchronized intern. PWMz External PWMz tPWM_SYNCH t t IPHASE - ICHGFWx - ICHGFWx Low-side = Active MOSFET High-side = FW MOSFET and PWM MOSFET Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET

Datasheet 59 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.3.3.2 Control signals with passive free-wheeling (AFWx = 0)

This section describes the MOSFET control signals with active freewheeling and HS PWM:

9.3.3.2.1 The PWM MOSFET is the active MOSFET

This section shows the control signals of the MOSFET when the PWM is the active MOSFET.

Datasheet 60 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 34 Adaptive turn-on with high-side PWM, AG C[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the PWM MOSFET is the active MOSFET. PWM_NB=0. VSHx VSHL VSHH IGS_HSx IGS_LSx IPRECHGx ICHGMAXx ICHGx VGS_HSx tDONx tRISEx Postcharge Phase VSHL Synchronized intern. PWMz t t t t tPCHGx t IDS_HSDx IPHASE tHBxBLANK VSHH VS IPRECHGx HSx internal drive signal t - IHOLD IHOLD ICHGMAXx ICHGx IHOLD LSx internal drive signal - IHARDOFF - IHOLD t Hard off - IHOLD Charge phase tFVDS tFVDS ICHGx External PWMz t ttPWM_SYNCH PWM MOSFET = Active MOSFET FW MOSFET PFW

Datasheet 61 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 35 Adaptive turn-off with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the PWM MOSFET is the active MOSFET.PWM_NB=0.

9.3.3.2.2 The PWM MOSFET is the free-wheeling MOSFET

This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET. VGS_HSx tFALLx t t t t t t tDOFFx VSHL VSHH tHBxCCP Active VSHx VSHL VSHH IGS_HSx IGS_LSx - IPREDCHGx - IDCHGx IDS_HSDx IPHASE VS LSx internal drive signal t - IHOLD HSx internal drive signal t - IHOLD IHOLD - IPREDCHGx - IDCHGx - IDCHGx - IHOLD Discharge phase Synchronized intern. PWMz t External PWMz tPWM_SYNCH tPDCHGx FW MOSFET PFW PWM MOSFET = Active MOSFET

Datasheet 62 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 36 PWM rising edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0. t VGS_LSx tFALLx tPDCHGx t t t t tDOFFx VSHH tHBxCCP Active for cross current protection VSHx VSHL VSHH IGS_LSx IGS_HSx - IPREDCHGx - IDCHGx IDS_LSDx IPHASE VS HSx internal drive signal t - IHOLD LSx internal drive signal t - IHOLD IHOLD - IPREDCHGx - IDCHGx - IDCHGx - IHOLD Discharge phase VSHL t Synchronized intern. PWMz t External PWMz tPWM_SYNCH Low-side = Active MOSFETHigh-side = FW MOSFET (and PWM MOSFET) \\G t D i \\fi \\BLDC\\ Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET

Datasheet 63 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 37 PWM falling edge with adaptive contro l, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0.

9.3.3.3 Time modulation of pre- charge and pre-discharge times

If DEEP_ADAP =0: VSHx VSHL VSHH IGS_LSx IGS_HSx IPRECHGx ICHGMAXx ICHGx VGS_LSx tDONx tRISEx Postcharge Phase VSHL 0 t t t t tPCHGx t IDS_LSDx tHBxBLANK Active VS IPRECHGx LSx internal drive signal t - IHOLD IHOLD ICHGMAXx ICHGx IHOLD HSx internal drive signal - IHARDOFF - IHOLD t Hard off - IHOLD Charge phase tFVDS tFVDS ICHGx VSHH Synchronized intern. PWMz External PWMz tPWM_SYNCH t t Low-side = Active MOSFETHigh-side FW MOSFET (and PWM MOSFET) IPHASE Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET

Datasheet 64 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

• one single precharge current is applied during tPCHGx to regulate TDON
• one single precharge current is applied during tPDCHGx to regulate TDOFF If DEEP_ADAP = 1 (“deep adaptation” or “time modulation”) it is possible to:
• to divide the precharge phase in two parts, during which two different precharge currents can be applied
• to divide the predischarge phase in two parts, du ring which two different precharge currents can be applied Figure 38 describes the principle of the time modulation applied to the precharge phase. The same principle is also applied for the regulation of the pre-discharge phase.

Datasheet 65 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 38 Principle of the time modulation of the precharge phase, DEEP_ADAP = 1, AGC = 10B or 11B TDON a da ptati on with two current steps (IPCHGADT = 3 consecutive sign changes of (TDON EFF- TDON TARGET) or No error for 3 cons ecutive PWM cycles TDON a da ptati on with o ne curren t step 3 consecutive sign changes of (TDON EFF- TDON TARGET) Precharge phase splitted in 2 sub-phases TDON EFF = TDON TARGET Precha rg e splitted: 75%-25% if TDON EFF > TDON TARGET 25%-75% if TDON EFF < TDON TARGET tPCHG i+1 50% 50% i or Exit from time modulation 2) tPCHG i+2Current tPCHG Current i tPCHG i+1 tPCHG i tPCHG i+1 i 75% 25% tPCHG i+1 25% 75% i Etc... 1) Yes No Yes Yes No TDON EFF = TDON TARGET Precha rg e splitted: E.g 87.5%-12.5% Yes No 2) Exit time modulation: - tPCHG cannot be further divided due to the limitation of the resolution - and the regulation of TDON is still not possible  One single current is applied during tPCHG TDON EFF = TDON TARGET No 1) Precharge further split either: - until TDON EFF = TDON TARGET - Or until no further split of tPCHG is possible. Refer to 2). No 2)

Datasheet 66 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.3.3.4 Operation at high and low duty cycles

In the particular cases where the on -time is shorter than tHBxCCP FW or the off-time of the PWM signal is shorter than tHBxCCP Active:

• No distinction between active MOSFET and FW MOSFET is possible. Therefore PWM MOSFET (selected by HBxMODE[1:0]) is controlled as active MOSFET.
• The MOSFET opposite to the PW M MOSFET stays off (passive FW)

9.3.3.5 Measurements of the switching times

The effective switching times in PWM operation:

• of the PWM MOSFET if EN_GEN_CHECK = 0
• of the active MOSFET if EN_GEN_CHECK = 1 are reported in the registers: EFF_TDON_OFF1,EFF_TDON_OFF2,EFF_TDON_OFF3. If the end of the rise time for a gi ven MOSFET is not detected before tHBxBLANK Active elapses, then the corresponding status register reports an effective rise time equal to zero. If the end of the fall time for a gi ven MOSFET is not detected before tHBxCCP Active active elapses, then the corresponding status register reports an effective fall time equal to zero. The device cannot measure the switching times tDON, tDOFF, tRISE and tFALL at very high and very low duty cycles: tON < tHBxCCP FW and tOFF < tHBxCCP active. In this case, the corresponding registers report effective tDON, tDOFF, tRISE and tFALL equal to zero.

Datasheet 67 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.3.4 PWM operation with 6 PWM inputs

Each high-side MOSFET and each low-side MOSFET is controlled by one PWM input. if PWM_NB is set to 1 (see CSA) and HBx_PWM_EN are set to 1 (see HBMODE). Refer to Table 20. Figure 39 Half-bridge PWM control with six PWM inputs, PWM_NB = 1 Table 20 Half-bridge PWM settings with 6 PW M inputs (PWM_NB = 1)FW and Active MOSFET PWM_NB HBx_PWM _EN1) 1) x = 1 to 3 HBxMODE1) Half-bridge x settings1) 1D o n ’ t c a r e 0 0 B LSx and HSx MOSFETs are kept OFF by the passive discharge (default) 110 1 B HBx is controlled by its PWM inputs

• I f EN_GEN_CHECK = 0: LSx is always considered as the active MOSFET
• I f EN_GEN_CHECK = 1: The active and the FW MOSFETs are detected according to Chapter 9.3.1, independently from HBxMODE 111 0 B HBx is controlled by its PWM inputs
• I f EN_GEN_CHECK = 0: HSx is always considered as the active MOSFET
• I f EN_GEN_CHECK = 1: The active and the FW MOSFETs are detected according to Chapter 9.3.1 independently from HBxMODE 1D o n ’ t c a r e 1 1 B LSx and HSx MOSFETs are actively kept OFF SL VSCP CP SL VSCP CP SL VSCP CP Control µC_PWM1 µC_PWM2 µC_PWM3 µC_PWM4 µC_PWM5 µC_PWM6 PWM1 PWM2 PWM3 PWM4 PWM6 PWM5 HS1 LS1 HS2 LS2 HS3 LS3

Datasheet 68 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 40 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the FW MOSFET (low-side MOSFET in this case) followed by the activation of the active MOSFET (high-side MOSFET in this case) 1) with PWM_NB = 1, AGC[1:0]=01B or 10B, POCHGDIS = 0 (post-charge enabled). This control scheme is applicable for the following cases: Table 21 PWM Control of HS1 and LS1, PWM_NB = 1, HB1_PWM_EN = 1 HB1MODE[1:0] PWM1/CRC PWM2 HS1 LS1

01 Low Low OFF OFF

01 Low High ON OFF

01 High Low OFF ON

01 High High OFF OFF

10 Low Low OFF OFF

10 Low High OFF ON

10 High Low ON OFF

10 High High OFF OFF

Table 22 PWM Control of HS2 and LS2, PWM_NB = 1, HB2_PWM_EN = 1 HB2MODE[1:0] PWM3 PWM4 HS2 LS2 Table 23 PWM Control of HS3 and LS3, PWM_NB = 1, HB3_PWM_EN = 1 HB3MODE[1:0] PWM5 PWM6 HS3 LS3 1) If the synchronized HS PWM rising edge occurs after tHBxCCP FW and before the end of tOFF timeout FW, then the LS MOSFET is discharged with IHARDOFF and the HS is turned on, when the HS PWM rising edge is detected

Datasheet 69 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers 1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is considered as active MOSFET by default). 2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET; HBxMODE[1:0] = 01B or10B. Note: If the synchronized HS PWM rising edge occurs before the end of tHBxCCP active, then the device prevents an activation of the HS MOSFET until tHBxCCP FW elapses. In other words, the HS PWM rising edge is ignored until the end of tHBxCCP FW.

Datasheet 70 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 40 Turn-on of an active MOSFET in PWM mode with active gate control, HS as active MOSFET, LS as FW MOSFET. Two PWM inputs per half-bridge, active gate control enabled. PWM_EN =1 VSHx VSHL VSHH IGS_HSx IPRECHGx ICHGMAXx ICHGx VGS_HSx tDONx tRISEx Postcharge Phase VSHL Synchronized HSx PWM signal t t t tPCHGx t IDS_HSDx IPHASE tHBxBLANK Active VSHH VS IPRECHGx HSx internal drive signal t - IHOLD IHOLD ICHGMAXx ICHGx IHOLD LSx internal drive signal - IHARDOFF IHOLD t Hard off - IHOLD Charge phase tFVDS tFVDS ICHGx t HS MOSFET (Active MOSFET)LS MOSFET (FW MOSFET) - ICHGFWx - IHOLD tOFF Timeout FW t tHBxCCP FWSynchronized LSx PWM signal VSHx < VSHL right before the activation of HSx HSx detected as active MOSFET External HSx PWM signal tPWM_SYNCH

Datasheet 71 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 41 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the active MOSFET (high-side MOSFET in this case) followed by the activation of the FW MOSFET low-side MOSFET in this case) with PWM_NB = 1, AGC[1:0] = 01B or 10B, POCHGDIS = 0 (post-charge enabled). This control scheme is applicable for the following cases: 1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is considered as active MOSFET by default). 2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET; HBxMODE[1:0] = 01B or 10B. Note: If the synchronized LS PWM rising edge occurs before the end of tHBxCCP active, then the device prevents an activation of the LS MOSFET until tHBxCCP active elapses. In other words, the LS PWM rising edge is ignored until the end of tHBxCCP active.

Datasheet 72 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 41 Turn-off of an active MOSFET in PWM mode with active gate control, HS as active MOSFET, LS as FW MOSFET. two PWM inputs per half-bridge, active gate control enabled. PWM_NB=1.

9.3.5 Status bits for regulation of turn-on and turn-off delay times

The control bits TDREGx (TDREG) indicate if tDONx and tDOFFx of the half-bridge x, using the adaptive control scheme (AGC = 10B or 11B), are in regulation. tFALLx t t t t t tDOFFx VSHL VSHH - IDCHGx - IHOLD Discharge phase Hard off t tPWM_SYNCH tPDCHGx t IHOLD tFVDStHBxBLANK FW t VGS_HSx VSHx VSHL VSHH IDS_HSDx IPHASE VS HSx internal drive signal - IHOLD IHOLD - IPREDCHGx - IDCHGx - IHARDOFF HS MOSFET (Active MOSFET) LS MOSFET (FW MOSFET) LSx internal drive signal - IHOLD IHOLD ICHGFWx - IHOLD tOFF timeout Active tHBxCCP Active Synchronized HSx PWM signal Synchronized LSx PWM signal External HSx PWM signal VSHx < VSHL right before the activation of HSx HSx detected as active MOSFET

Datasheet 73 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers The half-bridge x is considered in regulation if one of the following conditions is met:

• Condition 1: The effective turn-on an d turn-off delays are equal to the configured delays for at least eight cumulative PWM cycle (HBx tDON counter ≥ 8 and HBx tDOFF counter ≥ 8). For each PWM cycle –i f t D O N x E F F1) = TDONx2), x = 1.. 3, HBx tDON counter is incremented –i f t D O N x E F F1) ≠ TDONx2), x = 1.. 3, HBx tDON counter is decremented – if tDOFFxEFF 1) = TDOFFx3), x = 1.. 3, HBx tDOFF counter is incremented – if tDOFFxEFF 1) ≠ TDOFFx3), x = 1.. 3, HBx tDOFF counter is decremented
• Condition 2: The error between the effective de lays ((tDONxEFF-TDONx) and(tDOFFxEFF-TDOFFx )) changes its sign three times consecutively 1) Refer to EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3 2) Refer to TDON_HB_CTRL 3) Refer to TDOFF_HB_CTRL

Datasheet 74 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.3.6 Gate driver current

Each gate driver is able to source and sink currents from 0.5 mA to 150 mA, with 64 steps. Figure 42 Configurable discharge currents in PWM operation 100 110 120 130 140 150 0 5 10 15 20 25 30 35 40 45 50 55 60 Nominal PWM charge/ intial precharge current [mA] ICHG[5:0]dec

Datasheet 75 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Table 24 Charge currents and initial precharge currents ICHGx[5:0], PCHGINITx[5:0] Parameter name Nom. current [mA] Max. deviation to nominal values [%] 000000B ICHG0 0.5 +/- 60% 000001B ICHG1 0.7 +/- 60 % 000010B ICHG2 1.0 +/- 60 % 000011B ICHG3 1.4 +/- 60 % 000100B ICHG4 1.8 +/- 60 % 000101B ICHG5 2.4 +/- 60 % 000110B ICHG6 3.0 +/- 60 % 000111B ICHG7 3.8 +/- 60 % 001000B ICHG8 4.7 +/- 55% 001001B ICHG9 5.8 +/- 55% 001010B ICHG10 6.9 +/- 55% 001011B ICHG11 8.1 +/- 55% 001100B ICHG12 9.4 +/- 55% 001101B ICHG13 10.8 +/- 55% 001110B ICHG14 12.2 +/- 40% 001111B ICHG15 13.7 +/- 40% 010000B ICHG16 15.3 +/- 40 % 010001B ICHG17 17.1 +/- 40 % 010010B ICHG18 19 +/- 40% 010011B ICHG19 21 +/- 40 % 010100B ICHG20 23 +/- 40% 010101B ICHG21 25 +/- 40 % 010110B ICHG22 27.1 +/- 40 % 010111B ICHG23 29.3 +/- 40 % 011000B ICHG24 31.6 +/- 40 % 011001B ICHG25 34 +/- 40 % 011010B ICHG26 36.5 +/- 40 % 011011B ICHG27 39 +/- 40 % 011100B ICHG28 41.6 +/- 40 % 011101B ICHG29 44.2 +/- 30 % 011110B ICHG30 46.9 +/- 30 % 011111B ICHG31 49.7 +/- 30 % 100000B ICHG32 52.5 +/- 30 % 100001B ICHG33 55.3 +/- 30 % 100010B ICHG34 58.1 +/- 30 % 100011B ICHG35 60.8 +/- 30 %

Datasheet 76 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers 100100B ICHG36 63.6 +/- 30 % 100101B ICHG37 66.5 +/- 30 % 100110B ICHG38 69.4 +/- 30 % 100111B ICHG39 72.3 +/- 30 % 101000B ICHG40 75.2 +/- 30 % 101001B ICHG41 78.1 +/- 30 % 101010B ICHG42 81.1 +/- 30 % 101011B ICHG43 84.1 +/- 30 % 101100B ICHG44 87.1 +/- 30 % 101101B ICHG45 90.2 +/- 30 % 101110B ICHG46 93.3 +/- 30 % 101111B ICHG47 96.4 +/- 30 % 110000B ICHG48 99.5 +/- 30 % 110001B ICHG49 102.7 +/- 30 % 110010B ICHG50 105.8 +/- 30 % 110011B ICHG51 109 +/- 30 % 110100B ICHG52 112.2 +/- 30 % 110101B ICHG53 115.4 +/- 30 % 110110B ICHG54 118.7 +/- 30 % 110111B ICHG55 122 +/- 30 % 111000B ICHG56 125.3 +/- 30 % 111001B ICHG57 128.7 +/- 30 % 111010B ICHG58 132.1 +/- 30 % 111011B ICHG59 135.5 +/- 30 % 111100B ICHG60 139 +/- 30 % 111101B ICHG61 142.5 +/- 30 % 111110B ICHG62 146 +/- 30 % 111111B ICHG63 150 +/- 30 % Table 24 Charge currents and initial precharge currents (cont’d) ICHGx[5:0], PCHGINITx[5:0] Parameter name Nom. current [mA] Max. deviation to nominal values [%]

Datasheet 77 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Figure 43 Configurable discharge currents in PWM operation 100 110 120 130 140 150 0 5 10 15 20 25 30 35 40 45 50 55 60 Nominal PWM Discharge/Initial precharge current [mA] IDCHG[5:0]dec

Datasheet 78 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Table 25 Discharge currents and initial predischarge currents IDCHG[5:0], PDCHGINITx[5:0] Parameter name Nom. current [mA] Max. deviation to nominal values [%] 000000B IDCHG0 0.5 +/- 60% 000001B IDCHG1 0.7 +/- 60 % 000010B IDCHG2 1.0 +/- 60 % 000011B IDCHG3 1.4 +/- 60 % 000100B IDCHG4 1.8 +/- 60 % 000101B IDCHG5 2.4 +/- 60 % 000110B IDCHG6 3.0 +/- 60 % 000111B IDCHG7 3.8 +/- 60 % 001000B IDCHG8 4.7 +/- 60 % 001001B IDCHG9 5.8 +/- 60 % 001010B IDCHG10 6.9 +/- 60 % 001011B IDCHG11 8.1 +/- 60 % 001100B IDCHG12 9.4 +/- 60 % 001101B IDCHG13 10.7 +/- 60 % 001110B IDCHG14 12.1 +/- 40% 001111B IDCHG15 13.5 +/- 40% 010000B IDCHG16 15.1 +/- 40 % 010001B IDCHG17 16.8 +/- 40 % 010010B IDCHG18 18.6 +/- 40% 010011B IDCHG19 20.5 +/- 40 % 010100B IDCHG20 22.5 +/- 40% 010101B IDCHG21 24.5 +/- 40 % 010110B IDCHG22 26.5 +/- 40 % 010111B IDCHG23 28.7 +/- 40 % 011000B IDCHG24 30.9 +/- 40 % 011001B IDCHG25 33.2 +/- 40 % 011010B IDCHG26 35.7 +/- 40 % 011011B IDCHG27 38.2 +/- 40 % 011100B IDCHG28 40.8 +/- 40 % 011101B IDCHG29 43.4 +/- 30 % 011110B IDCHG30 46.1 +/- 30 % 011111B IDCHG31 48.8 +/- 30 % 100000B IDCHG32 51.5 +/- 30 % 100001B IDCHG33 54.2 +/- 30 % 100010B IDCHG34 56.9 +/- 30 % 100011B IDCHG35 59.6 +/- 30 %

Datasheet 79 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.4 Passive discharge

Resistors ( RGGND) between the gate of GHx and GND, and betw een GLx and GND, ensure that the external MOSFETs are turned off in the following conditions:

• VCC1 undervoltage
• HBxMODE = 00 B in Normal Mode
• CPEN = 0 in Normal Mode
• CSA Overcurrent detection with OCEN = 1 in normal mode 100100B IDCHG36 62.4 +/- 30 % 100101B IDCHG37 65.2 +/- 30 % 100110B IDCHG38 68 +/- 30 % 100111B IDCHG39 70.8 +/- 30 % 101000B IDCHG40 73.7 +/- 30 % 101001B IDCHG41 76.6 +/- 30 % 101010B IDCHG42 79.5 +/- 30 % 101011B IDCHG43 82.5 +/- 30 % 101100B IDCHG44 85.5 +/- 30 % 101101B IDCHG45 88.5 +/- 30 % 101110B IDCHG46 91.5 +/- 30 % 101111B IDCHG47 94.6 +/- 30 % 110000B IDCHG48 97.7 +/- 30 % 110001B IDCHG49 100.9 +/- 30 % 110010B IDCHG50 104.2 +/- 30 % 110011B IDCHG51 107.5 +/- 30 % 110100B IDCHG52 110.8 +/- 30 % 110101B IDCHG53 114.2 +/- 30 % 110110B IDCHG54 117.6 +/- 30 % 110111B IDCHG55 121 +/- 30 % 111000B IDCHG56 124.5 +/- 30 % 111001B IDCHG57 128 +/- 30 % 111010B IDCHG58 131.5 +/- 30 % 111011B IDCHG59 135.1 +/- 30 % 111100B IDCHG60 138.7 +/- 30 % 111101B IDCHG61 142.3 +/- 30 % 111110B IDCHG62 145.8 +/- 30 % 111111B IDCHG63 150 +/- 30 % Table 25 Discharge currents and initial predischarge currents (cont’d) IDCHG[5:0], PDCHGINITx[5:0] Parameter name Nom. current [mA] Max. deviation to nominal values [%]

Datasheet 80 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

• VS overvoltage or VSINT overvoltage
• Charge pump undervoltage and charge pump blank time ( tCPUVBLANK)
• Charge pump overtemperature ( CP_OT)
• VDS overvoltage after active discharge in Normal Mode
• In Init Mode, Stop Mode, Fail Safe Mode, Restart Mode and Sleep Mode (exceptions for low-sides in parking braking and VS / VSINT overvoltage braking , refer to Chapter 9.6 and Chapter 10.9.3)

9.5 Slam mode

The slam mode is applicable in Normal Mode. If the SLAM bit is set in BRAKE register: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then charge pump is deactivated independently from CPEN 3. Then PWM1/CRC input pin is ma pped to LS1, LS2, LS3, independently from PWM_NB, HBxMODE and HBx_PWM_EN a) If PWM1/CRC is High, then the low- side MOSFETs are turned on within tON_BRAKE. b) If PWM1/CRC is Low, then the low- side MOSFETs are turned off within tOFF_BRAKE. There is also the possibility to disable selectively the LSx in SLAM mode.

9.6 Parking braking mode

If PARK_BRK_EN bit is set, while the device goes in Sleep Mode or in Stop Mode: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then charge pump is deactivated independently from CPEN bit. 3. Then the passive discharge ( RGGND) of the low-sides is deactivated, the passive discharge of the high-sides are activated 4. If PWM1/CRC is High, then the low- side MOSFETs are turned on within tON_BRAKE. Refer to Chapter 10.9.2 for the protection of the of low-side MOSFETs against short circuits when the parking braking mode is activated.

Datasheet 81 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.7 Charge pump

A dual-stage charge pump supplies the gate drivers for the high-side and low-side MOSFETs. It requires three external capacitors connected between CPC1N and CPC1P, CPC2N and CPC2P, VS and CP. The buffer capacitor between VS and CP must have a capacitance equal or higher than 470 nF. Figure 44 Charge pump - Block diagram Logic or normal level MOSFETs The regulation of the charge pump outputs voltage can be configured depending on the type of MOSFET. FET_LVL = 0: Logic level MOSFETs are selected:

• V C P - V S = VCP3 (11 V typ. at VS > 8 V).
• The high-side gate-source voltage GHx - SHx is VGH4 (VS > 8 V).
• The low-side gate-source voltage GLx - SL is VGH3 (VS > 8 V). FET_LVL = 1: Normal level MOSFETs are selected:
• V C P - V S = VCP1(15 V typ. at VS > 8 V).
• The high-side and low-side gate-source voltage GHx - SHx or GLx - SL is VGH1 (VS > 8 V). CPSTGA = 0 (default, see GENCTRL), the device operates with the dual-stage charge pump. If CPSTGA = 1, the device switches to single-stage or dual-stage charge pump automatically:
• I f VS > VCPSO DS: the TLE9185QX switches from a dual-stage to a single-stage charge pump.
• I f VS < VCPSO SD: the TLE9185QX switches from single-stage to dual-stage charge pump. The operation with the single-stage charge pump reduces the current consumption from the VS pin. Single/dual stage charge pump Pr ec har ge VS CPC1N CPC1P CPC2N CPC2PCP CCP ≥ 470 nF CCP1 CCP2 Logic

Datasheet 82 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.8 Frequency modulation

A modulation of the charge pump frequency can be activated to reduce the peak emission. The modulation frequency is set by the control bit FMODE in GENCTRL:

• FMODE = 0: No modulation.
• FMODE = 1: Modulation fr equency = 15.6 kHz (default).

Datasheet 83 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers

9.9 Electrical characteristics gate driver

The electrical characteristics related to the gate driver are valid for VCP > VS + 8.5 V Table 26 Electrical characteristics: gate drivers VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Comparators SHx High Threshold VSHH VS - 2.6 – VS - 1.9 V P_12.11.1 SHx Low Threshold VSHL 1.9 – 2.6 V Referred to GND P_12.11.2 SHx comparator delay tSHx –1 2 3 0 n s 1) P_12.11.3 MOSFET Driver Output High Level Output Voltage GHx vs. SHx and GLx vs. SL VGH1 10 11.5 12.5 V 2) VS ≥ 8 V , CLoad = 10 nF, ICP = -12 mA, FET_LVL = 1 P_12.11.4 High Level Output Voltage GHx vs. SHx and GLx vs. SL VGH2 7 – 12.5 V VS = 6 V, CLoad = 10 nF, ICP = -6 mA, FET_LVL = 1 P_12.11.5 High Level Output Voltage GLx vs. SL VGH3 10 – 12.5 V 3) VS ≥ 6 V , CLoad = 10 nF, FET_LVL = 0 P_12.11.6 High Level Output Voltage GHx vs. SHx VGH4 8.5 10 12.5 V 2) VS ≥ 8 V , CLoad = 10 nF, ICP = -12 mA, FET_LVL = 0 P_12.11.7 High Level Output Voltage GHx vs. SHx VGH5 7 – 12.5 V VS = 6 V, CLOAD= 10 nF, ICP = -6 mA, FET_LVL =0 P_12.11.8 Charge current ICHG0 -60% 0.5 +60% mA ICHG = 0 D 1) CLoad = 2.2 nF VS ≥8V, VGS≤VGS(ON) P_12.11.70 Charge current ICHG8 -55% 4.7 +55% mA ICHG =8 D 1) CLoad = 2.2 nF VS ≥8V, VGS≤VGS(ON) P_12.11.71 Charge current ICHG16 -40% 15.3 +40% mA ICHG =16 D 1) CLoad = 2.2 nF VS ≥8V, VGS≤VGS(ON) P_12.11.72 Charge current ICHG32 -30% 52.5 +30% mA ICHG =32 D 1) CLoad = 10 nF VS ≥8V, VGS≤VGS(ON) P_12.11.73

Datasheet 84 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Charge current ICHG48 -30% 99.5 +30% mA ICHG =48 D 1) CLoad = 10 nF VS ≥8V, VGS≤VGS(ON) P_12.11.74 Charge current ICHG63 -30% 150 +30% mA ICHG =63 D 1) CLoad = 22 nF VS ≥8V, VGS≤VGS(ON) P_12.11.75 Discharge current IDCH0 -60% -0.5 +60% mA IDCHG =0 D 1) CLoad = 2.2 nF VS ≥8V,VGS≥VGS(OFF1) P_12.11.76 Discharge current IDCH8 -55% -4.7 55% mA IDCHG =8 D 1) CLoad = 2.2 nF VS ≥8V,VGS≥VGS(OFF1) P_12.11.77 Discharge current IDCHG16 -40% -15.1 +40% mA IDCHG =16 D 1) CLoad = 2.2 nF VS ≥8V,VGS≥VGS(OFF1) P_12.11.78 Discharge current IDCHG32 -30% -51.5 +30% mA IDCHG =32 D 1) CLoad = 10 nF VS ≥8V,VGS≥VGS(OFF2) P_12.11.79 Discharge current IDCHG48 -30% -97.7 +30% mA IDCHG = 48 D 1) CLoad = 10 nF VS ≥8V,VGS≥VGS(OFF2) P_12.11.80 Discharge current IDCHG63 -30% -150 +30% mA IDCHG = 63 D 1) CLoad = 22 nF VS ≥8V,VGS≥VGS(OFF2) P_12.11.81 Charge current temperature drift ICHG0,TDrift -37% -12% 15% ICHG = 0 D 1)5) P_12.11.119 Charge current temperature drift ICHG8,TDrift -17% 1% 20% ICHG = 8 D 1)5) P_12.11.120 Charge current temperature drift ICHG16,TDrift -12% 3% 18% ICHG = 16 D 1)5) P_12.11.121 Charge current temperature drift ICHG32,TDrift -11% -1% 9% ICHG = 32 D 1)5) P_12.11.122 Charge current temperature drift ICHG48,TDrift -7.5% 0.5% 8% ICHG = 48 D 1)5) P_12.11.123 Charge current temperature drift Discharge current temperature drift IDCHG0,TDrift -29% -4.5% 20% IDCHG = 0 D 1)5) P_12.11.125 Table 26 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 85 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Discharge current temperature drift IDCHG8,TDrift -8% 8.5% 26% IDCHG = 8 D 1)5) P_12.11.126 Discharge current temperature drift IDCHG16,TDrift -4% 9.5% 23% IDCHG = 16 D 1)5) P_12.11.127 Discharge current temperature drift IDCHG32,TDrift -4% 4.5% 13% IDCHG = 32 D 1)5) P_12.11.128 Discharge current temperature drift IDCHG48,TDrift -4% 3.5% 10% IDCHG = 48 D 1)5) P_12.11.129 Discharge current temperature drift Charge current VS drift ICHG0,VsDrift 3% 4.5% 6% ICHG = 0 D 1)6) P_12.11.131 Charge current VS drift ICHG8,VsDrift 4.5% 6% 7.5% ICHG = 8 D 1)6) P_12.11.132 Charge current VS drift ICHG16,VsDrift 4% 5.8% 7.5% ICHG = 16 D 1)6) P_12.11.133 Charge current VS drift ICHG32,VsDrift 2% 3.8% 5.8% ICHG = 32 D 1)6) P_12.11.134 Charge current VS drift ICHG48,VsDrift -0.5% 2% 4.5% ICHG = 48 D 1)6) P_12.11.135 Discharge current VS drift IDCHG0,VsDrift -3% -1.5% 0% IDCHG = 0 D 1)6) P_12.11.137 Discharge current VS drift IDCHG8,VsDrift -3% -0.5% 2% IDCHG = 8 D 1)6) P_12.11.138 Discharge current VS drift IDCHG32,VsDrift -2% 0% 2% IDCHG = 32 D 1)6) P_12.11.140 Discharge current VS drift IDCHG48,VsDrift -1.5% 0% 1.5% IDCHG = 48 D 1)6) P_12.11.141 Passive discharge resistance between GHx/GLx and GND RGGND 10 20 30 k Ω 1) P_12.11.22 Resistor between SHx and GND RSHGND 10 20 30 k Ω 1)7) P_12.11.23 Low RDSON mode RONCCP –2 2 3 5 Ω 1) VS = 13.5 V VCP = VS + 14 V ICHG = IDCHG = 63D P_12.11.24 Gate Drivers Dynamic Parameters Table 26 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 86 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Gate Driver turn-on delay Time tDGDRV_ON1 – – 400 ns 8) From PWM9) rising edge to 20% of ICHGx , x = 0 to 63, C Load = 10 nF, BDFREQ = 0 P_12.11.25 Gate Driver turn-on delay Time tDGDRV_ON2 – – 300 ns 8) From PWM9) rising edge to 20% of ICHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 1 P_12.11.93 Gate Driver current turn-on rise time tGDRV_RISE(ON) –3 0 5 0 n s 8) From 20% of ICHGx to ICHGx , x = 0 to 63, CLoad = 10 nF P_12.11.26 Gate Driver turn-off delay Time tDGDRV_OFF1 – – 400 ns 8) From PWM9) rising edge to 20% of IDCHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 0 P_12.11.27 Gate Driver turn-off delay Time tDGDRV_OFF2 – – 300 ns 8) From PWM9) rising edge to 20% of I DCHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 1 P_12.11.94 Gate Driver current turn-off rise time tGDRV_RISE(OFF –3 0 5 0 n s 8) From 20% of IDCHGx to IDCHGx , x = 0 to 63, C Load = 10 nF P_12.11.28 External MOSFET gate-to- source voltage - ON VGS(ON)1 7––V 1) VS ≥ 8 V, FET_LVL=1 P_12.11.29 External MOSFET gate-to- source voltage - ON VGS(ON)1 7––V 1) VS ≥ 8 V, FET_LVL=1 P_12.11.102 External MOSFET gate-to- source voltage - ON VGS(ON)2 5.5 – – V 1) VS ≥ 8 V, FET_LVL=0 P_12.11.103 External MOSFET gate-to- source voltage - OFF VGS(OFF)1 ––1 . 5 V 1) IDCHGx ≤ 24D(≤ 41 mA typ.) P_12.11.30 Table 26 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 87 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers External MOSFET gate-to- source voltage - OFF VGS(OFF)2 ––5V 1)IDCHGx > 28D(> 41 mA typ.) P_12.11.101 PWM synchronization delay tPWM_SYNCH0 80 – 200 ns 1) BDFREQ = 0 P_12.11.33 PWM synchronization delay tPWM_SYNCH1 40 – 100 ns 1) BDFREQ= 1 P_12.11.82 Pre-charge time tPCHG000 80 107 140 ns 1) TPCHG = 000, BDFREQ= 0 or 1 P_12.11.34 Pre-charge time tPCHG001 130 160 190 ns 1) TPCHG = 001, BDFREQ= 0 or 1 P_12.11.35 Pre-charge time tPCHG010 170 214 260 ns 1) TPCHG = 010, BDFREQ= 0 or 1 P_12.11.36 Pre-charge time tPCHG011 210 267 330 ns 1) TPCHG = 011, BDFREQ= 0 or 1 P_12.11.37 Pre-charge time tPCHG100 250 320 390 ns 1) TPCHG = 100, BDFREQ= 0 or 1 P_12.11.85 Pre-charge time tPCHG101 420 533 630 ns 1) TPCHG = 101, BDFREQ= 0 or 1 P_12.11.86 Pre-charge time tPCHG110 600 747 900 ns 1) TPCHG = 110, BDFREQ= 0 or 1 P_12.11.87 Pre-charge time tPCHG111 840 1067 1260 ns 1) TPCHG = 111, BDFREQ= 0 or 1 P_12.11.88 Pre-discharge time tPDCHG000 80 107 140 ns 1) TPDCHG = 000, BDFREQ= 0 or 1 P_12.11.38 Pre-discharge time tPDCHG001 130 160 190 ns 1) TPDCHG = 001, BDFREQ= 0 or 1 P_12.11.39 Pre-discharge time tPDCHG010 170 214 260 ns 1) TPDCHG = 010, BDFREQ= 0 or 1 P_12.11.40 Pre-discharge time tPDCHG011 210 267 330 ns 1) TPDCHG = 011, BDFREQ= 0 or 1 P_12.11.41 Pre-discharge time tPDCHG100 250 320 390 ns 1) TPDCHG = 100, BDFREQ= 0 or 1 P_12.11.89 Pre-discharge time tPDCHG101 420 533 630 ns 1) TPDCHG = 101, BDFREQ= 0 or 1 P_12.11.90 Pre-discharge time tPDCHG110 600 747 900 ns 1) TPDCHG = 110, BDFREQ= 0 or 1 P_12.11.91 Table 26 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 88 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Pre-discharge time tPDCHG111 840 1067 1260 ns 1) TPDCHG = 111, BDFREQ= 0 or 1 P_12.11.92 Discharge timeout tOFF_TIMEOUT 3.2 4 4.8 µs 1) PWM_NB=1B P_12.11.9 Low-side gate driver, CP off - Slam mode, parking braking and VS overvoltage braking LS turn-on time, CP off tON_BRAKE –4 . 5 9µ s C LOAD = 10 nF VGLx-VSL = 5 V, VS > 8 V or VSINT > 8 V P_12.11.42 LS turn-off time, CP off tOFF_BRAKE –0 . 7 2µ s C LOAD = 10 nF VGLx-VSL = 1.5 V, V S > 8 V or VSINT > 8 V P_12.11.43 High output voltage GLx - SL VGLx_BRAKE 5–1 0 V V S > 8 V or VSINT > 8 V P_12.11.48 Charge pump Charge Pump Frequency fCP – 250 – kHz 1) P_12.11.49 Output Voltage VCP vs. VS VCPmin1 8 . 5 – –V VS = 6 V, ICP = - 6 mA, FET_LVL =1 P_12.11.50 Output Voltage VCP vs. VS VCPmin2 7 . 5 – –V VS = 6 V, ICP = - 6 mA, FET_LVL =0 P_12.11.51 Regulated CP output voltage, VCP vs. VS VCP1 12 15 17 V 8 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 0, FET_LVL =1 P_12.11.52 Regulated CP output voltage, VCP vs. VS V CP2 12 15 17 V 18 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 1, FET_LVL =1 P_12.11.53 Regulated CP output voltage, VCP vs. VS VCP3 7.5 11 13 V 8 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 0, FET_LVL =0 P_12.11.54 Regulated CP output voltage, VCP vs. VS VCP4 7.5 11 13 V 13 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 0, FET_LVL =0 P_12.11.55 Turn-on time tON_VCP1 5 – 6 0 µ s 1)10)11)18 V<VS< 23 V (25%), ICP = 0 , CPSTGA = 1, FET_LVL =1 P_12.11.56 Table 26 Electrical characteristics: gate drivers (cont’d) V SINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 89 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Rise time tRISE_VCP1 5 30 60 µs 1)10)11)18 V < VS < 23 V (25%-75%) ICP = 0 , CPSTGA = 1, FET_LVL =1 P_12.11.57 Turn-on time tON_VCP2 20 60 120 µs 1)10)11) 13 V < VS <23 V (25%), ICP = 0, CPSTGA = 1, FET_LVL =0 P_12.11.58 Rise time tRISE_VCP2 5 30 60 µs 1)10)11)13 V < VS < 23 V (25%-75%) ICP = 0 , CPSTGA = 1, FET_LVL =0 P_12.11.59 Automatic switch over dual to single stage charge pump VCPSO DS 16 17 18 V CPSTGA = 1, FET_LVL =1, VS rising P_12.11.60 Automatic switch over dual to single stage charge pump VCPSO DS 11.5 12.25 13 V CPSTGA = 1, FET_LVL = 0, VS rising P_12.11.61 Automatic switch over single to dual stage charge pump V CPSO SD 15.5 16.5 17.5 V CPSTGA = 1, FET_LVL =1, VS falling P_12.11.62 Automatic switch over single to dual stage charge pump V CPSO SD 11 11.75 12.5 V CPSTGA = 1, FET_LVL = 0, VS falling P_12.11.64 Charge pump switch over hysteresis VCPSO HY – 0 . 5 – V 1) CPSTGA = 1 VCPSO DS - VCPSO SD P_12.11.65 Charge pump minimum output current ICPOC1 ––- 1 2 m A 11) 8 V < VS < 28 V CPSTGA = 0 FET_LVL =1 P_12.11.68 Charge pump minimum output current ICPOC2 ––- 1 2 m A 11) 8 V < VS < 28 V CPSTGA = 0 FET_LVL =0 P_12.11.69 Table 26 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 90 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Gate Drivers Digital PWMx Inputs High Level Input Voltage Threshold VPWMH ––0 . 7 × Vcc1 V– P_12.11.95 Low Level Input Voltage Threshold VPWML 0.3 × Vcc1 ––V – P_12.11.96 PWMx Input Hysteresis VPWM,hys – 0.12 × Vcc1 –V 1) P_12.11.97 PWMx Pull-down Resistance RPD_PWM 20 40 80 k Ω – P_12.11.98 CRC Select; Pin PWM1/CRC Config Pull-up Resistance RCFG 100 k Ω 12) P_12.11.99 Config Select Filter Time tCFG_F 51 0 1 4 µ s 1) P_12.11.105 1) Not subject to production test, specified by design. 2) Independent from CPSTGA. 3) ICP = -12 mA for VS ≥ 8V , I C P = 6m A f o r V S = 6V . 4) VGS(ON) = VGS(ON)1 if FET_LVL = 1, VGS(ON) = VGS(ON)2 if FET_LVL = 0. 5) Tj reference = 25°C 6) Valid for V S = 8 to 19 V, VS reference = 13.5 V 7) This resistance is the resistance between GHx and GND connected through a diode to SHx. As a consequence, the voltage at SHx can rise up to 0.6 V typ. before it is discharged through the resistor. 8) Not subject to production test, specified by design. 9) External PWM signal. 10) Parameter dependent on the capacitance C CP. 11) CCPC1 = CCPC2 = 220 nF, CCP = 470 nF. Other CCP values higher than 470 nF can be used. Note that this capacitor influences the charge pump rise and turn-on times, and the charge , VCP ripple voltage when charging the gate of a MOSFET. 12) Config Pull-up will be only active during startup-phase for checking external pull-down. After checking, the typ. 40 kΩ Pull-down resistance will be present. Table 26 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 91 Rev. 1.0 2021-01-21

10 Supervision Functions

10.1 Reset Function

Figure 45 Reset Block Diagram

10.1.1 Reset Output Description

The reset output pin RSTN provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold VRTx. In case of a reset event, the reset output RSTN is pulled to low after the filter time tRF and stays low as long as the reset event is present plus a reset delay time tRD1 or tRD2 depending on the value in RSTN_DEL. When connecting the device to battery voltage, the reset signal remains low initially. When the output voltage VCC1 has reached the reset default threshold VRT1,r, the reset output RSTN is released to high after the reset delay time tRD1. A reset can also occur due to a watchdog trigger failure. The reset threshold can be adjusted via SPI, the default reset threshold is VRT1,f. The RSTN pin has an integrated pull-up resistor. In ca se reset is triggered, it will be pulled low for VCC1 ≥ 1V and for VSINT ≥ VPOR,f (see also Chapter 10.3). The timings for the RSTN triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 46. Reset logic Incl. filter & delay RSTN VCC1

Datasheet 92 Rev. 1.0 2021-01-21 Figure 46 Reset Timing Diagram

10.1.2 Soft Reset Description

In Normal Mode and Stop Mode, it is also possible to trigger a device internal reset via a SPI command in order to bring the device into a de fined state in case of failures. In this case the microcontroller must send a SPI command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as th is command becomes valid, the device is set back to Init Mode and all SPI registers are set to their default values (see SPI Chapter 11.5.1 and Chapter 11.6.1). Two different soft reset configurations are possible via the SPI bit SOFT_RESET_RO:

• SOFT_RESET_RO = ‘0’: The reset output (RSTN) is triggered when the soft reset is executed (default setting) The configured reset delay time tRD1 or tRD2 is applied depending on the value in RSTN_DEL).
• SOFT_RESET_RO = ‘1’: The reset output (RSTN) is not triggered when the soft reset is executed. Note: The device must be in Normal Mode or Stop Mode when sending this command. Otherwise, the command will be ignored. Note: Allow CRC configuration after software-reset - or better check once again via SPI after software reset. The reset threshold can be configured via SPI in Normal Mode, default is VRT1 tRD1 tLW Init RSTN SPI t VCC1 VRT1 undervoltage tRDx (config) Normal t t tLW t < tRF tRF tCW Restart Normal SPI Init Reset_timing.vsd tCW tOW WD Trigger tCW tOW WD Trigger SPI Init tLW= long open window tCW= closed window tOW= open window

Datasheet 93 Rev. 1.0 2021-01-21

10.2 Watchdog Function

The watchdog is used to monitor the communication with the microcontroller and to trigger a reset or move the device to Fail Safe Mode, if the microcontroller stops serving the watchdog. Two different types of watchdog functions are implemented and can be selected via the bit WD_CFG:

• Time-Out Watchdog (default value)
• W i n d o w W a t c h d o g The respective watchdog functions can be selected and programmed in Normal Mode. The configuration stays unchanged in Stop Mode. Please refer to Table 27 to match the device modes with the respective watchdog modes. The watchdog timing is programmed via SPI command in the register WD_CTRL. As soon as the watchdog is programmed, the timer starts with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid SPI-write command to the watchdog configuration register. The watchdog trigger command is executed when the SPI command is interpreted. When coming from Init Mode, Restart Mode or in certain cases from Stop Mode, the watchdog timer is always started with a long open window. The long open window ( t LW) allows the microcontroller to run its initialization sequences and then to trigger the watchdog via SPI. The watchdog timer period can be selected via SPI ( WD_TIMER).The timer setting is valid for both watchdog types. The following watchdog timer periods are available:
• WD Setting 1: 10 ms
• WD Setting 2: 20 ms
• WD Setting 3: 50 ms
• WD Setting 4: 100 ms
• WD Setting 5: 200 ms
• WD Setting 6: 500 ms
• WD Setting 7: 1 s
• WD Setting 8: 10 s In case of a reset, Restart Mode or Fail-Safe Mode is entered according to the co nfiguration and the SPI bits WD_FAIL are set. Once the RSTN goes high again the watc hdog immediately starts with a long open window the device enters automatically Normal Mode. The Watchdog behaviour in Software Development Mode is described in Chapter 5.4.7. Table 27 Watchdog Functionality by modes Mode Watchdog Mode Remarks Init Mode Starts with Long Open Window Watchdog starts with Long Open Window after RSTN is released. Normal Mode WD Programmable Window Watchdog, Time-Out watchdog or switched off for Stop Mode. Stop Mode Watchdog is fixed or off Sleep Mode Off Device will start with Long Open Window when entering Normal Mode. Restart Mode Off Device will start with Long Open Window when entering Normal Mode.

Datasheet 94 Rev. 1.0 2021-01-21 In case a watchdog-trigger was missed in Software Development Mode, the watchdog will start with the long- open-window once again. The WD_FAIL bits will be set after a watchdog trigger failure. The WD_FAIL bits are cleared automatically when following conditions apply:

• After a successful watchdog trigger.
• When the watchdog is off: in Stop Mo de after successfully disabling it, in Sleep Mode, or in Fail-Safe Mode (except for a watchdog failure).

10.2.1 Time-Out Watchdog

The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog trigger can be done at any time within the configured watchdog timer period. A correct watchdog service immediately results in starting a new watchdog timer period. Taking the tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 47. If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RSTN low and the device switches to Restart Mode or Fail-Safe Mode. Figure 47 Time-out Wa tchdog Definitions open window t / [tWD_TIMER ] safe trigger area Watchdog Timer Period (WD_TIMER) uncertainty Typical timout watchdog trigger period tWD x 1.80tWD x 1.20 tWD x 1.50

Datasheet 95 Rev. 1.0 2021-01-21

10.2.2 Window Watchdog

Compared to the time-out watchdog the characteristic of the window wa tchdog is that the watchdog timer period is divided between a closed and an open wind ow. The watchdog must be triggered within the open window. A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an open window. The watchdog timer period is at the same time the ty pical trigger time and defi nes the middle of the open window. Taking the oscillator tolerances into account leads to a safe trigger area of: tWD × 0.72 < safe trigger area < tWD × 1.20. The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking the tolerances of the internal oscillator into account leads to the timings as defined in Figure 48. A correct watchdog service immediately results in starting the next closed window. If the trigger signal meet the closed window or if the watchdog timer period elapses, then a watchdog reset is triggered (RSTN low) and the device switches to Restart Mode or Fail-Safe Mode. Figure 48 Window Watchdog Definitions

10.2.3 Watchdog Setting Check Sum

A check sum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting. The sum of the 16 data bits in the register WD_CTRL needs to have even parity (see Equation (10.1)). This is realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set. The written value of the reserved bits of the WD_CTRL register is considered (eve n if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is written on the reserved bit position, then a 1 will be used in the checksum calculation. (10.1) closed window open window t / [tWD_TIMER ] safe trigger area tWD x 0.72 t WD x 1.20 uncertainty uncertainty tWD x 0.48 t WD x 1.80 Watchdog Timer Period (WD_TIMER) Typ. closed window Typ. open window tWD x 0.6 tWD x 1.0 tWD x 0.9 Bit CHECKSUM() Bit22 … Bit8⊕⊕=

Datasheet 96 Rev. 1.0 2021-01-21

10.2.4 Watchdog during Stop Mode

The watchdog can be disabled for Stop Mode in Normal Mode. For safety reasons, there is a special sequence to be followed in order to disa ble the watchdog as described in Figure 49. Two different SPI bits (WD_STM_EN_0, WD_STM_EN_1) in the registers HW_CTRL and WD_CTRL need to be set. Figure 49 Watchdog disablin g sequence in Stop Mode If a sequence error occurs, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started again. The watchdog can be enabled by triggering the watchdog in Stop Mode or by switching back to Normal Mode via SPI command. In both cases the watchdog will start with a long open window and the bits WD_STM_EN_1 and WD_STM_EN_0 are cleared. After the long open window the watchdog has to be served as configured in the WD_CTRL register. Note: The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was 1 before. WD_STM_EN_0 can also not be set if WD_STM_EN_1 isn't yet set. Correct WD disabling sequence Set bit WD_STM_EN_1 = 1 Set bit WD_STM_EN_0 = 1 with next WD Trigger WD is switched off Sequence Errors /;#23#23#23Missing to set bit WD_STM_EN_0 with the next watchdog trigger after having set WD_STM_EN_1 /;#23#23#23Staying in Normal Mode instead of going to Stop Mode with the next trigger Change to Stop Mode Before subsequent WD Trigger Will enable the WD: /;#23#23#23Switching back to Normal Mode /;#23#23#23Triggering the watchdog

Datasheet 97 Rev. 1.0 2021-01-21

10.3 VSINT Power On Reset

At power up of the device, the Power on Reset is detected when VSINT > VPOR,r and the SPI bit POR is set to indicate that all SPI registers are set to POR default setti ngs. VCC1 is starting up and the reset output will be kept low and will only be released once VCC1 has crossed VRT1,r and after tRD1 has elapsed. In case VSINT < VPOR,f, an device internal reset will be generated and the device is switched off and will restart in Init Mode at the next VSINT rising. This is shown in Figure 50. Figure 50 Ramp up / down example of Supply Voltage t VCC1 t VPOR,f RSTN t VSINT VPOR,r tRD1 VRT1,r VRTx,f t Mode OFF OFFINIT MODE Any MODE SPI Command The reset threshold can be configured via SPI in Normal Mode, default is VRT1 Re- start Restart Mode is entered whenever the Reset is triggered

Datasheet 98 Rev. 1.0 2021-01-21

10.4 VSINT Under- and Overvoltage

10.4.1 VSINT Undervoltage

The VSINT under-voltage monitoring is always active in Init Mode, Restart Mode, Normal Mode. If the supply voltage VSINT drops below VSINT,UV for more than tVSUV_FILT, then the device does the following measures:

• The VCC1 short circuit diagnosis becomes inactive (see Chapter 10.7). However, the thermal protection of the device remains active. If the undervoltage threshold is exceeded (VSINT rising) then the function will be automatically enabled again.
• The status bit VSINT_UV is set and latched until a clear command of SUP_STAT is received. Note: VSINT under-voltage monitoring is not availabl e in Stop Mode due to current consumption saving requirements except if the VCC1 load current is above the active peak threshold (I_PEAK_TH) or if VCC1 is below the VCC1 prewarning threshold.

10.4.2 VSINT Overvoltage

The VSINT over-voltage monitoring is always active in Init Mode, Restart Mode and Normal Mode. If VSINT rises above VS,OVD1, VS,OVD2 for more than tVSOV_FILT then the device does the following measures: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then the charge pump is turned off and the passive discharge is activated. 3. The status bits VSINT_OV is set and latched until a clear command of SUP_STAT is received. If VS or VSINT fall below VS,OVD1 or VS,OVD2:

• I f CPEN = 0 : the charge pumps stays and the bridge driver stay off.
• I f CPEN = 1 : –I f BDOV_REC = 0 : Then the charge pump is reactivated but the bridge driver stays off until VS_OV and VSINT_OV are cleared. The current sense amplifier is reactivated (provided that CSA_OFF = 0) –I f BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge driver is enabled if VCP > VCPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is according to the control registers.

Datasheet 99 Rev. 1.0 2021-01-21

10.5 VS Under- and Overvoltage

10.5.1 VS Undervoltage

The VS under-voltage monitoring is always active in In it-, Restart Mode and Normal Mode. If VS drops below VS,UV for more than tVSUV_FILT, then the device does the following measures: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then the charge pump is turned of f and the passive discharge is activated and the current sense amplifier is turned off. 3. The status bits VS_UV is set and latched until a clear command of SUP_STAT is received. If VS rises above VS,UV, then the charge pump is reactivated (provided that CPEN is set) and the current sense amplifier is reactivated (provided CSA_OFF = 0) but the bridge driver stays off until VS_UV is cleared. The bridge driver will be reactivated once the VS_UV bit is cleared.

10.5.2 VS Overvoltage

The VS over-voltage monitoring is always active in Init-, Restart Mode and Normal Mode or when the charge pump is enabled. If VS rises above VS,OVD1 or VS,OVD2 for more than tVSOV_FILT, then the device does the following measures: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then the charge pump is turned off and the passive discharge is activated and current sense amplifier is turned off . 3. The status bits VS_OV is set and latched until a clear command of SUP_STAT is received. If VS and VSINT fall below VS,OVD1 or VS,OVD2:

• I f CPEN = 0 : the charge pumps and the bridge driver stay off.
• I f CPEN = 1 : –I f BDOV_REC = 0 : Then the charge pump is reactivated (provided that CPEN = 1 and CP_UV = 0) but the bridge driver stays off until VS_OV and VSINT_OV are cleared. The current sense amplifier is reactivated provided that CSA_OFF = 0 –I f BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge driver is enabled if VCP > VCPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is according to the control registers.

Datasheet 100 Rev. 1.0 2021-01-21

10.6 VCC1 Over-/ Undervoltage and Undervoltage Prewarning

10.6.1 VCC1 Undervoltage and Undervoltage Prewarning

This function is always active when the VCC1 voltage regulator is enabled. A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The prewarning event is signaled with the bit VCC1_WARN. No other actions are taken. As described in Chapter 10.1 and Figure 51, a reset will be triggered (RSTN pulled low) when the VCC1 output voltage falls below the selected undervoltage threshold (VRTx). The device will enter Restart Mode and the bit VCC1_UV is set when RSTN is released again. The hysteresis of the VCC1 undervoltage threshold can be increased by setting the bit RSTN_HYS. In this case always the highest rising threshold ( VRT1,R) is used for the release of the un dervoltage reset. The falling reset threshold remains as configured. An additional safety mechanism is implemented to av oid repetitive VCC1 undervoltage resets due to high dynamic loads on VCC1:

• A counter is increased for every consecutive VCC1 un dervoltage event (regardless on the selected reset threshold).
• The counter is active in Init Mode, Normal Mode and Stop Mode.
• F o r V S < VSINT,UV the counter will be stopped in Normal Mode (i.e. the VS UV comparator is always enabled in Normal Mode).
• A 4th consecutive VCC1 undervoltage event will lead to Fail-Safe Mode entry and to setting the bit VCC1_UV_FS.
• This counter is cleared: – When Fail-Safe Mode is entered. – When the bit VCC1_UV is cleared. – When a Soft-Reset is triggered. Note: After 4 consecutive VCC1_UV events, th e device will enter Fail-Safe Mode and the VCC1_UV_FS bit is set. Note: The VCC1_WARN or VCC1_UV bits are not set in Sleep Mode as V CC1 = 0 V in this case. Figure 51 VCC1 Undervol tage Timing Diagram RSTN t VCC1 VRTx tRDx (config) Normal Mode t tRF Restart Mode Normal Mode

Datasheet 101 Rev. 1.0 2021-01-21 Note: It is recommended to clear the VCC1_WARN and VCC1_UV bit once it is detected by the microcontroller software to verify if the undervoltage still exists or not.

10.6.2 VCC1 Overvoltage

For fail-safe reasons a configurable VCC1 over voltage detection feature is implemented. It is active when the VCC1 voltage regulator is enabled. In case the VCC1,OV,r threshold is crossed, the device trigge rs following measures depending on the configuration:

• T h e b i t VCC1_OV is always set.
• Based on the configuration of VCC1_OV_MOD, different kind of event are generated from device.
• I f t h e VCC1_OV_MOD=11B, in case of the device enters in Fail Safe Mode. Figure 52 VCC1 Over Voltage Timing Diagram

10.7 VCC1 Short Circuit Diagnostics

The short circuit protection feature for VCC1 is implemented as follows:

• The short circuit detection is only enabled if VS > VSINT,UV.
• If VCC1 is not above the V RTx within tVCC1,SC after device power up or after waking from Sleep Mode or Fail- Safe Mode (i.e. after VCC1 is enabled) then the SPI bit VCC1_SC bit is set, VCC1 is turned off, the FO pin is enabled, FAILURE is set and Fail-Safe Mode is entered. The device can be activated again via a wake-up sources.
• The same behavior applies, if VCC1 falls below VRTx for longer than tVCC1,SC. RSTN t VCC1 tRDx (config) Normal Mode t tOV_filt Restart Mode Normal Mode VCC1,OV

Datasheet 102 Rev. 1.0 2021-01-21

10.8 Thermal Protection

Three independent and different thermal protection features are implemented in the device according to the system impact:

• Individual thermal shutdo wn of specific blocks
• Temperature prewarning of VCC1 voltage regulator
• Device thermal shutdown due to VCC1 overtemperature

10.8.1 Individual Thermal Shutdown

As a first-level protection measure, the charge pump is independently sw itched off if the respective block reaches the temperature threshold TjTSD1. Then the TSD1 bit is set. This bit can only be cleared via SPI once the overtemperature is not present anymore. Inde pendent of the device mo de the thermal shutdown protection is only active if the respective block is ON. The respective modules behave as follows:

• Charge pump: If the charge pump reaches T jTSD1, then CP_OT is set, CPEN is cleared and the activated MOSFETs are actively discharged with their respective static currents during their respective active cross current protection times (tHBxCCP active). When all tHBxCCP active elapsed, then the charge pump and the MOSFETs active discharge are disabled and the current sense amplifier is deactivated. Once the over temperature condition is not present anymore, then CPEN has to be configured again by SPI. Note: The diagnosis bits are not cleared automatically and have to be cleared via SPI once the overtemperature condition is not present anymore.

10.8.2 Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only be cleared via SPI once the overtemperature is not present anymore.

10.8.3 Thermal Shutdown

As a highest level of thermal protec tion a temperature shutdown of the device is implemented if the main supply VCC1 reaches the thermal shutdown temperature threshold TjTSD2. Once a TSD2 event is detected Fail- Safe Mode is entered. Only when device temperature falls below the TSD2 threshold then the device remains in Fail-Safe Mode for tTSD2 to allow the device to c ool down. After this time has expired, the device will automatically change via Restart Mode to Normal Mode (see also Chapter 5.4.6). When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in Normal Mode once the overtemperature is not present anymore. For increased robustness requirements it is possible to extend th e TSD2 waiting time by 64x of tTSD2 after 16 consecutive TSD2 events by setting the SPI bit TSD2_DEL. The counter is incremented with each TSD2 event even if the bit TSD2 is not cleared. Once the counter has reached the value 16, then the bit TSD2_SAFE is set and the extended TSD2 waiting ti me is active. The extended waiting time will be kept until TSD2_SAFE is cleared. The TSD counter is cleared when TSD2 or TSD2_DEL is cleared. Note: In case a TSD2 overtemperature occurs while en tering Sleep Mode then Fail-Safe Mode is still entered. Note: In case of a TSD2 event, the FAILURE bit is set to ‘1’ and the DEV_STAT field is set to ‘01’ inside the DEV_STAT register.

Datasheet 103 Rev. 1.0 2021-01-21

10.9 Bridge driver

This section describes the supervision functions related to the bridge driver.

10.9.1 Bridge driver supervision with activated charge pump

This section describes the supervision functions when the charge pump is activated.

10.9.1.1 Drain-source voltage monitoring

Voltage comparators monitor the activated MOSFETs to protect high-side MOSFETs and low-side MOSFETs against a short circuit respectively to ground and to the battery during ON-state. A drain-source overvoltage is detect ed on a low-side MOSFET if the voltage difference between VSHx and SL exceeds the threshold vo ltage configured by LS_VDS (see Table 28). Consequently, the corresponding half- bridge is latched off with the static discharge current. A drain-source overvoltage is detected on a high-side MOSFET if the voltage difference between VS and VSHx exceeds the threshold vo ltage configured by HS_VDS (see Table 29). Consequently, the corresponding half- bridge is latched off with the static discharge current. Attention: 2 V threshold is dedicated for the diagnostic in off-state. It is highly recommended to select another drain-source overvoltage threshold once the routine of the diagnostic in off-state has been performed to avoid additional current consumption from VS and from the charge pump. The device reports a Drain-Source overvoltage error if both conditions are met: Table 28 Low-side drain-source overvoltage threshold LSxVDSTH[2:0] Drain-Source overvolt age threshold for LSx (typical) 000B 160 mV 001B 200 mV (default) 010B 300 mV 011B 400 mV 100B 500 mV 101B 600 mV 110B 800 mV 111B 2 V Table 29 High-side drain-sour ce overvoltage threshold HSxVDSTH[2:0] Drain-Sou rce overvoltage threshold for HSx (typical) 000B 160 mV 001B 200 mV (default) 010B 300 mV 011B 400 mV 100B 500 mV 101B 600 mV 110B 800 mV 111B 2 V

Datasheet 104 Rev. 1.0 2021-01-21

• After expiration of the blank time .
• If the Drain-Source voltage monitoring exceeds the co nfigured threshold for a duration longer than the configured filter time (refer to Table 30 and LS_VDS TFVDS bits). If a short circuit is detected by the Drain-Source voltage monitoring:
• The impacted half-bridge is latched off with the stat ic discharge current for the configured cross-current protection time.
• The corresponding bit in the status register DSOV is set.
• The DSOV bit in Global Status Register GEN_STAT is set. If a Drain-Source overvoltage is detected for one of the MOSFETs, then the status register DSOV must be cleared in order to re-enable the faulty half-bridge.

10.9.1.2 Cross-current protection and drain-source overvoltage blank time

All gate drivers feature a cross-current protection time and a Drain-Source overvoltage blank time. The cross-current protection avoids the simultaneous activation of the high-side and the low-side MOSFETs of the same half-bridge. During the blank time, the drain-source overvoltage de tection is disabled, to avoid a wrong fault detection during the activation phase of a MOSFET. Note: The setting of the cross-current protection and of the blank times may be changed by the microcontroller only if all HBx_PWM_EN bits are reset. Note: Changing the Drain-Source overvoltage of a half -bridge x (HBx) in on-state (HBxMODE[1:0]=(0,1) or (1,0)) may result in a wrong VDS overvoltage detection on HBx. Therefore it is highly recommended to change this threshold when HBxMODE[1:0]=(0,0) or (1,1)

10.9.1.2.1 Cross-current protection

The active and freewheeling cross-current protection times of each half-bridge is configured individually with the control register CCP_BLK. The typical cross-current protection time applied to th e freewheeling MOSFET of the half-bridge x is 587 ns + 266 ns x TCCP[3:0]D, where TCCP[3:0]D is the decimal value of the control bits TCCP.

10.9.1.2.2 Drain-source overvoltage blank time

A configurable blank time for the Drain-Source monitori ng is applied at the turn -on of the MOSFETs. During the blank time, a Drain-Source overvoltage error is masked. Table 30 Drain-Source overvoltage filter time TFVDS[2:0] Drain-Source overvoltage filter time (typical) 00B 0.5 µs (default) 01B 1 µs 10B 2 µs 11B 6 µs

Datasheet 105 Rev. 1.0 2021-01-21 For Half-Bridges in PWM mode with AFWx = 1:

• the blank time of the PWM MOSFET starts at the expira tion of the cross-current protection time of the PWM MOSFET. Refer to Figure 53.
• the blank time of the free-wheeling MOSFET starts after expiration of the cross-current protection time at turn-off of the PWM MOSFET. Refer to Figure 53. Figure 53 Blank time for half-bridg es in PWM operation with AFW = 1 For statically activated half-bridges, the blank time starts:
• Case1: at expiration of the cross-current protection ( Figure 23), if the opposite MOSFET was previously activated.
• Case 2: right after the decoding of the SPI command to turn on a MOSFET, if the half-bridge was in high impedance (Figure 24). The blank times of the active and FW MOSFETs can be configured with the control register CCP_BLK. The typical blank is 587 ns + 266 ns x TBLK[3:0]D). Note: The blank time is implemented at every new acti vation of a MOSFET, including a recovery from VS undervoltage, VS overvoltage, VSINT overvoltage, CP UV, CP OT.

10.9.1.3 OFF-state diagnostic

In order to support the off-st ate diagnostic (HBxMODE= 11 and CPEN = 1), the gate driver of each MOSFET provides pull-up (IPUDiag) and a pull-down currents (IPDDiag) at the SHx pins. This function requires an activated charge pump. The pull-up current source of a given half-bridge is on when the half-bridge is active: HBxMODE= 01, 10 or 11 and CPEN = 1. The pull-down current of each low-side gate dr iver is activated by the control bits HBx ( HB_ICHG_MAX register). During the off-state diagnostic routine performed by the microcontroller, the drain-source overvoltage threshold of the relevant half-bridges m u s t b e s e t t o 2 V n o m i n a l . R e f e r t o Table 28. Once the routine is finished, it is highly recommended to decrease the drain-source overvoltage th reshold to a lower value, avoiding additional current consumption from the VS input. IGS_PWM MOSFET IGS Freewheeling MOSFET ICHGMAXz - ICHGMAXz IPRECHGz - IPREDCHGz ICHGMAXz - IDCHGz ICHGz Post-charge PWM tPDCHGz t t t tHBxCPP tBLANK for PWM MOSFET tBLANK for freewheeling MOSFET tHBxCPP for symmetrisation tHBxCPP tPCHGz

Datasheet 106 Rev. 1.0 2021-01-21 The following failures can be detected:

• MOSFET short circuit to GND
• MOSFET short circuit the battery
• Open load (disconnected motor) The status of the output voltages VOUTx, can be read back with status bit HBxVOUT (register GEN_STAT) when the corresponding half-bridge is in off-state (HBxMODE[1:0] = 11). Note: HBxVOUT = 0 if the half-bridge x is not active ly off (HBxMODE[1:0] = (0,0), (0,1) or (1,0) and CPEN=1) or when the charge pump is deactivated (CPEN=0).

10.9.1.4 Charge pump undervoltage

The voltage of the charge pump output (VCP) is monitored in order to ensure a correct control of the external MOSFETs. The charge pump undervoltage threshold is configurable by the control bits FET_LVL and CPUVTH. If VCP falls below the configured charge pump undervoltage threshold while CPEN = 1:

• If one of the MOSFET is on, then al l MOSFETs are actively turned off with their configured static discharge current during their respective tHBxCCP active.
• Then the gate drivers are turned off and CSA is turned off .
• CP_UV is set and latched. The CP_UV is reset and the normal operation is resumed once SUP_STAT is cleared and VCP > VCPUV. The charge pump undervoltage detection is blanked ( tCPUVBLANK) during each new activation of the charge pump1).

10.9.1.5 Switching parameters of MOSFETs in PWM mode

The effective switching paramete rs of the active MOSFETs ( EN_GEN_CHECK=1), respectively PWM MOSFET (EN_GEN_CHECK=0)can be read out with dedicated status registers:

• The turn-on and turn off delays, noted tDON an d tDOFF are reported by the status register EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3.
• The rise and fall times, noted tRISE and tF ALL, are reported by the status register TRISE_FALL1, TRISE_FALL2, TRISE_FALL3.

10.9.2 Low-side drain-source volt age monitoring during braking

The low-side MOSFETs are turned-on while the charge pump is deactivated in the following conditions:

• The slam mode is activated and PWM1/CRC is High. Table 31 Charge pump un dervoltage thresholds FET_LVL = 0 FET_LVL = 1 CPUVTH = 0 VCPUV1 (6 V typ. referred to VS) VCPUV3 (7.5 V typ. referred to VS) CPUVTH = 1 VCPUV2 (6.5 V typ. referred to VS) VCPUV4 (8 V typ. referred to VS) 1) Including CPEN set to 1, recovery from VS under/overvoltage, VSINT overvoltage and CP_ OT

Datasheet 107 Rev. 1.0 2021-01-21

• The parking braking mode is activated and th e device is in Sleep Mode or Stop Mode.
• VS overvoltage brake is activated an d (VS > VS Overvoltage braking or VSINT > VSINT Overvoltage braking) in all device modes if OV_BRK_EN is set. Under these conditions, the drain-source voltage of the low-sides are monitored and the applied drain-source overvoltage thresholds are according to VDSTH_BRK. The applied blank time, which starts at the beginning of the brake activation, is:
• tBLK_BRAKE1 if TBLK_BRK = 0
• tBLK_BRAKE2 if TBLK_BRK = 1 During the blank time, a drain-source overvoltage of the low-sides is masked. The applied filter time is tFVDS_BRAKE. If a drain-source overvoltage is dete cted during braking , then all low-si de MOSFETs are turned off (latched) within tOFF_BRAKE. SLAM_LSx_DIS ( BRAKE, SLAM, PARK_BRK_EN, OV_BRK_EN are unchanged. The corresponding status bit LSxDSOV_BRK is set in DSOV. The low-sides can be reactivated only if all LSxDSOV_BRK bits (DSOV) are cleared (even in slam mode with the respective LSx disabled by the SLAM_LSx_DIS bit). If any of the status bits LSxDSOV_BRK is set, then th e charge pump stays off ( CPEN=1 command is accepted but the charge pump stays disabled until all LSxDSOV_BRK are cleared).

10.9.3 VS or VSINT Overvoltage braking

The VS and VSINT overvoltage braking is activated if the OV_BRK_EN bit in BRAKE register is set regardless of the device mode. If VS, respectively VSINT, exceeds VOVBR,cfgx,r (x = 0 to 7), then all low-sides MOSFETs are turned-on within tON_BRAKE. The status bits VSOVBRAKE_ST, respectively VSINTOVBRAKE_ST, is set and latched (see DSOV register). If VS and VSINT decrease below VOVBR,cfgx,r - VHYS,cfgx (x = 0 to 7), then all low-sides MOSFETs are turned-off within tOFF_BRAKE after the filter time tOV_BR_FILT. If (VSHx - VSL) exceeds the config ured threshold, then all low-side s MOSFETs are turned-off within tOFF_BRAKE after the filter time tFVDS_BRAKE. The threshold is:

• VVDSMONTH0_BRAKE if VDSTH_BRK = 0
• VVDSMONTH1_BRAKE if VDSTH_BRK = 1

10.10 Current sense amplifier

The current sense amplifier (CSA) allows current meas urements with external shunt resistor in low-side configuration. The CSA is supplied by the charge pump (CP). Therefore, if the CP i s o f f , t h e n t h e C S A i s deactivated.

10.10.1 Unidirectional and bidirectional operation

The current sense amplifier (CSA) can work either as unid irectional or bi-directional operation. Refer to CSA register. Unidirectional operation CSD = 0

Datasheet 108 Rev. 1.0 2021-01-21 In unidirectional operation, the CS A is optimized to measure the curren t flowing through the external shunt resistor when VCSAP ≥ VCSAN. VCSO = VREF Unidir + (VCSAP - VCSAN + VOS) × GDIFF provided that VCSO is in the linear range1) 2). Bidirectional operation CSD = 1 In bidirectional operation, the CSA measures the current flow ing through the external shunt resistor in both directions: VCSAP ≥ VCSAN or VCSAP ≤ VCSAN. The output CSO works at half-scale range: VCSO = VREF Bidir+ (VCSAP - VCSAN + VOS) × GDIFF, provided that VCSO is in the linear range 2).

10.10.2 Gain configuration

The gain of the current sense amplifier is configurable by the configuration bits CSAG bits. Refer to Table 32.

10.10.3 Overcurrent Detection

A comparator at CSO detects overcurrent conditions. The overcurrent threshold is configurable with the OCTH bits. Refer to Table 33 for unidirectional operation and Table 34 for bidirectional operation. 1) Valid if 0.5 V ≤ VCSO ≤ VCC1 - 0.5 V. 2) VCSO is clamped between VCC1 and GND. Table 32 Configuration of the current sense amplifier gain CSAG[1:0] Current sense amplifier gain GDIFF 00B GDIFF10 01B GDIFF20 10B GDIFF40 11B GDIFF60 Table 33 Overcurrent detection thresholds in unidirectional operation (CSD = 0) OCTH[1:0] Typical Overcurrent Detection Threshold 00B VCSO > VCC1/2 01B VCSO > VCC1 /2+ VCC1/10 10B VCSO > VCC1 /2+ 2 × VCC1/10 11B VCSO > VCC1/2 /2+ 3 × VCC1/10

Datasheet 109 Rev. 1.0 2021-01-21 Figure 54 Overcurrent detection thresholds in unidirectional operation (CSD = 0) VCC1 / 2 VCSO VCC1 CSO unidirectional overcurrent detection threshold OCTH[1:0] (1,1) (1,0) (0,1) VREF Unidir Typ. VCC1/5 VOCTH1 Unidir (0,0) VOCTH2 Unidir VOCTH3 Unidir VOCTH4 Unidir VCC1 / 2 + VCC1 / 10 VCC1 / 2 + 2 x VCC1 / 10 VCC1 / 2 + 3 x VCC1 / 10

Datasheet 110 Rev. 1.0 2021-01-21 Figure 55 Overcurrent detection thresholds in bidirectional operation (CSD = 1) It is possible to program the device behavior when an overcurrent condition is detected:

• OCEN bit = 0 (see CSA): the device only reports the over current event ( bit is set), without any change of the gate driver states.
• OCEN bit = 1 (see CSA): the device reports the overcurr ent event ( bit is set) and actively turns off all MOSFETs with static discharge curent: – The MOSFETs can be reactivated by clearing OC_CSA or by resetting the OCEN bit. The overcurrent filter time is configurable (refer to tFOC) by the OCFILT control bits. tFOC refers to the output of the current sense amplifier. The CSO settling time (2 µs max, tSET) and the analog propagation delay (< 1 µs) are not taken into account by the overcurrent filter time.

10.10.4 CSO output capacitor

The capacitor connected to CSO (CCSO) must be between 10 pF and 2.2 nF. The control bit CSO_CAP optimizes the current consumption for CCSO < 400 pF or 400 pF < CCSO < 2.2 nF1). Table 34 Overcurrent detection thresholds in bidirectional operation (CSD = 1) OCTHx[1:0] Typical Overcurrent Detection Threshold 00B VCSO > VCC1/2 + 2 × VCC1/20 or VCSO< VCC1/2 -2 × VCC1/20 01B VCSO > VCC1/2 + 4 × VCC1/20 or VCSO< VCC1/2 - 4 × VCC1/20 10B VCSO > VCC1/2+ 5 × VCC1/20 or VCSO< VCC1/2 - 5 × VCC1/20 11B VCSO > VCC1/2+ 6 × VCC1/20 or VCSO< VCC1/2 - 6 × VCC1/20 VREF Bidir Typ. VCC1 /2 VCSO VCC1 OCTH[1:0] (1,1) (1,0) (0,1) (0,0) (1,1) (1,0) (0,1) (0,0) VOCTH1 BidirH VOCTH2 BidirH VOCTH3 BidirH VOCTH4 BidirH VOCTH1 BidirL VOCTH2 BidirL VOCTH3 BidirL VOCTH4 BidirLVCC1 / 2 - 6 x VCC1 / 20 VCC1 / 2 - 5 x VCC1 / 20 VCC1 / 2 - 4 x VCC1 / 20 VCC1 / 2 - 2 x VCC1 / 20 VCC1 / 2 + 2 x VCC1 / 20 VCC1 / 2 + 4 x VCC1 / 20 VCC1 / 2 + 6 x VCC1 / 20 VCC1 / 2 + 5 x VCC1 / 20 CSO bidirectional overcurrent detection threshold

Datasheet 111 Rev. 1.0 2021-01-21

10.11 Electrical Characteristics

1) for 400 pF < CCSO < 2.2 nF, a seial resistor of min. 45 Ohm between the CSO pin and the CCSO capacitor is required, Table 35 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. VCC1 Monitoring; VCC1 = 5.0V Version Undervoltage Prewarning Threshold Voltage PW,f VPW,f 4.53 4.70 4.84 V VCC1 falling, SPI bit is set P_13.12.1 Undervoltage Prewarning Threshold Voltage PW,r Undervoltage Prewarning Threshold Voltage hysteresis VPW,hys 30 50 90 mV 6) P_13.12.3 VCC1 UV Prewarning Detection Filter Time tVCC1,PW_F 51 0 1 4 u s 2) rising and falling P_13.12.4 Reset Threshold Voltage RT1,f VRT1,f 4.45 4.6 4.75 V default setting; VCC1 falling P_13.12.5 Reset Threshold Voltage RT1,r VRT1,r 4.58 4.74 4.90 V default setting; VCC1 rising P_13.12.6 Reset Threshold Voltage RT2,f Reset Threshold Voltage RT2,r Reset Threshold Voltage RT3,f VRT3,f 3.24 3.40 3.55 V VS ≥ 4V ; VCC1 falling P_13.12.9 Reset Threshold Voltage RT3,r VRT3,r 3.39 3.54 3.70 V VS ≥ 4V ; VCC1 rising P_13.12.10 Reset Threshold Voltage RT4,f VRT4,f 2.49 2.65 2.8 V VS ≥ 4V ; VCC1 falling P_13.12.11 Reset Threshold Voltage RT4,r VRT4,r 2.65 2.76 2.95 V VS ≥ 4V ; VCC1 rising P_13.12.12 Reset Threshold Hysteresis VRT,hys 70 140 220 mV 6) P_13.12.13 VCC1 Over Voltage Detection Threshold Voltage VCC1 Over Voltage Detection Threshold Voltage V VCC1 OV Detection Filter Time tVCC1,OV_F 51 64 80 us 2) P_13.12.31

Datasheet 112 Rev. 1.0 2021-01-21 VCC1 Short to GND Filter Time tVCC1,SC 3.2 4 4.8 ms 2) blanking time during power-up, short circuit detection for VS ≥VS,UV P_13.12.32 Reset Generator; Pin RSTN Reset Low Output Voltage V RSTN,L –0 . 2 0 . 4 V IRSTN = 1 mA for VCC1 ≥ 1 V & VS ≥VPOR,f P_13.12.33 Reset High Output Voltage VRSTN,H 0.8 x VCC1 – VCC1 + 0.3 V V IRSTN = -20 µA P_13.12.34 Reset Pull-up Resistor RRSTN 10 20 40 k Ω VRSTN = 0 V P_13.12.35 Reset Filter Time tRF 41 0 2 6 µ s 2) VCC1 < VRT1x to RSTN = L see also Chapter 10.3 P_13.12.36 Reset Delay Time 1 tRD1 81 0 1 2 m s 2) RSTN_DEL = 0 P_13.12.37 Reset Delay Time 2 tRD2 1.6 2 2.4 ms 2) RSTN_DEL = 1 P_13.12.64 Watchdog Generator / Internal Oscillator Long Open Window tLW 160 200 240 ms 2) P_13.12.42 Internal Clock Generator Frequency Minimum Waiting time during Fail-Safe Mode Min. waiting time Fail-Safe tFS,min 80 100 120 ms 2)3) P_13.12.45 Power-on Reset, Over / Undervoltage Protection VSINT Power on reset rising VPOR,r ––4 . 5 V V S I N T i n c r e a s i n g P_13.12.46 VSINT Power on reset falling VPOR,f ––3V V S I N T d e c r e a s i n g P_13.12.47 VSINT Undervoltage Detection Threshold VSINT,UV 5.3 – 6.0 V Supply UV threshold for VCC1 SC detection; hysteresis included; includes rising and falling threshold P_13.12.48 Charge Pump Undervoltage Table 35 Electrical Characteristics (cont’d) V SINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 113 Rev. 1.0 2021-01-21 Charge Pump Undervoltage Referred to VS V CPUV1 5.4 5.9 6.4 V FET_LVL = 0 CPUVTH = 0 falling threshold, VS ≥6 V P_13.12.59 Charge Pump Undervoltage Referred to VS VCPUV2 5.85 6.35 6.85 V FET_LVL = 0 CPUVTH = 1 falling threshold, VS ≥ 6 V P_13.12.60 Charge Pump Undervoltage Referred to VS V CPUV3 6.85 7.35 7.85 V FET_LVL = 1 CPUVTH = 0 falling threshold, VS ≥ 6 V P_13.12.61 Charge Pump Undervoltage Referred to VS V CPUV4 7.5 8 8.5 V FET_LVL = 1 CPUVTH = 1 falling threshold, VS ≥ 6 V P_13.12.62 Charge Pump Undervoltage Filter Time tCPUV 51 64 80 µs 6)VS ≥ 6 V P_13.12.63 Charge Pump Undervoltage Blank Time tCPUVBLANK 400 500 600 µs 6)VS ≥ 6 V P_13.12.175 VS monitoring VS undervoltage threshold VS,UV 4.7 – 5.4 V hysteresis included P_13.12.66 VS overvoltage threshold detection 1 VS,OVD1 19 – 22.5 V hysteresis included, VS_OV_SEL = 0 P_13.12.68 VS overvoltage threshold detection 2 VS,OVD2 27.75 – 31.25 V hysteresis included, VS_OV_SEL = 1 P_13.12.65 VS undervoltage filter time tVSUV_FILT 51 0 1 4 µ s 2) rising and falling P_13.12.71 VS overvoltage filter time tVSOV_FILT 51 0 1 4 µ s 2) rising and falling P_13.12.72 Off-state open load diagnosis Pull-up diagnosis current IPUDiag -600 -400 -270 µA VS ≥ 6 V P_13.12.73 Pull-down diagnosis current IPDDiag 1600 2200 2800 µA VS ≥ 6 V P_13.12.74 Diagnosis current ratio IDiag_ratio 4.25 5.25 6.25 Ratio IPDDiag / IPUDiag P_13.12.302 Drain-source monitoring CP activated Table 35 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 114 Rev. 1.0 2021-01-21 Blank time t BLANK typ- 20% 587 +266 xTBLK typ+20 ns 6) TBLK: decimal value of TBLK[3:0], VS ≥ 6 V P_13.12.75 Cross-current protection time t CCP typ- 20% 587 +266 xTCCP typ+20 ns 6) TCCP: decimal value of TCCPx[3:0], VS ≥ 6 V P_13.12.76 HS/LS Drain-source overvoltage 0 VVDSMONTH0_ CPON 0.115 0.16 0.195 V VDSTH[2:0] = 000 B, VS≥6 V, TFVDS=00B P_13.12.77 HS/LS Drain-source overvoltage 1 VVDSMONTH1_ CPON 0.16 0.2 0.25 V VDSTH[2:0] = 001 B, VS≥6 V, TFVDS=00B P_13.12.78 HS/LS Drain-source overvoltage 2 VVDSMONTH2_ CPON 0.24 0.3 0.36 V VDSTH[2:0] = 010 B, VS≥6 V, TFVDS=00B P_13.12.79 HS/LS Drain-source overvoltage 3 VVDSMONTH3_ CPON 0.32 0.4 0.48 V VDSTH[2:0] = 011 B, VS≥6 V, TFVDS=00B P_13.12.80 HS/LS Drain-source overvoltage 4 VVDSMONTH4_ CPON 0.4 0.5 0.6 V VDSTH[2:0] = 100 B, VS≥6 V, TFVDS=00B P_13.12.81 HS/LS Drain-source overvoltage 5 VVDSMONTH5_ CPON 0.48 0.6 0.72 V VDSTH[2:0] = 101 B, VS≥6 V, TFVDS=00B P_13.12.82 HS/LS Drain-source overvoltage 6 VVDSMONTH6_ CPON 0.64 0.8 0.96 V VDSTH[2:0] = 110 B, VS≥6 V, TFVDS=00B P_13.12.83 HS/LS Drain-source overvoltage 7 VVDSMONTH7_ CPON 1.75 2.0 2.25 V VDSTH[2:0] = 111 B, VS≥6 V, TFVDS=00B P_13.12.84 Drain-Source monitoring - Slam mode, parking braking and VS overvoltage braking, VS or VSINT ≥ 8V Blank time tBLK_BRAKE1 4.5 7 9.5 µs TBLK_BRK = 0, VS or VSINT ≥ 8V P_13.12.85 Blank time tBLK_BRAKE2 91 1 1 3 µ s TBLK_BRK = 1, VS or VSINT ≥ 8V P_13.12.86 VDS Filter time tFVDS_BRAKE 0.5 1 2.5 µs VS or VSINT ≥ 8V P_13.12.87 LS Drain-source monitoring thresholds VVDSMONTH0_ BRAKE 0.56 0.8 1.05 V VS or VSINT ≥ 8V VDSTH_BRK = 0 P_13.12.89 LS Drain-source monitoring thresholds VVDSMONTH1_ BRAKE 0.15 0.22 0.29 V VS or VSINT ≥ 8V VDSTH_BRK = 1 P_13.12.90 VS Overvoltage Braking Mode VS Overvoltage braking config 0 rising VOVBR,cfg0,r 25.65 27 28.35 V OV_BRK_TH=000B P_13.12.97 VS Overvoltage braking config 1 rising VOVBR,cfg1,r 26.60 28 29.40 V OV_BRK_TH=001B P_13.12.98 Table 35 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 115 Rev. 1.0 2021-01-21 VS Overvoltage braking config 2 rising VOVBR,cfg2,r 27.55 29 30.45 V OV_BRK_TH=010B P_13.12.99 VS Overvoltage braking config 3 rising VOVBR,cfg3,r 28.50 30 31.50 V OV_BRK_TH=011B P_13.12.100 VS Overvoltage braking config 4 rising VOVBR,cfg4,r 29.45 31 32.55 V OV_BRK_TH=100B P_13.12.101 VS Overvoltage braking config 5 rising VOVBR,cfg5,r 30.40 32 33.60 V OV_BRK_TH=101B P_13.12.102 VS Overvoltage braking config 6 rising VOVBR,cfg6,r 31.35 33 34.65 V OV_BRK_TH=110B P_13.12.103 VS Overvoltage braking config 7 rising VOVBR,cfg7,r 32.30 34 35.70 V OV_BRK_TH=111B P_13.12.104 VS Overvoltage braking config 0 VS Overvoltage braking config 1 VS Overvoltage braking config 2 VS Overvoltage braking config 3 VS Overvoltage braking config 4 VS Overvoltage braking config 5 VS Overvoltage braking config 6 VS Overvoltage braking config 7 VS and VSINT overvoltage braking filter time tOV_BR_FILT 10 15 20 µs 6) P_13.12.200 Current sense amplifier4) Operating common mode input voltage range referred to GND (CSAP - GND) or (CSAN- GND) V Table 35 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 116 Rev. 1.0 2021-01-21 Common Mode Rejection Ratio CMRR 63 dB 6) CSAG = (0,0) CSAG = (0,1) CSAG = (1,0) CSAG = (1,1) DC to 50 kHz V CM = -2 … 2 V VCSAP = VCSAN P_13.12.139 Settling time to 98% tSET – 1500 2000 ns 6) P_13.12.140 Settling time to 98% after gain change tSET_GAIN – – 5000 ns 6) After gain change from CSN rising edge P_13.12.141 Input Offset voltage VOS -1 0 1 mV P_13.12.142 Current Sense Amplifier DC Gain (uncalibrated) Current Sense Amplifier DC Gain (uncalibrated) Current Sense Amplifier DC Gain (uncalibrated) Current Sense Amplifier DC Gain (uncalibrated) Gain drift GDRIFT -0.5 – 0.5 % 6) Gain drift after calibration P_13.12.151 CSO single ended output voltage range (linear range) VCSO 0.5 – VCC1 - 0.5 V 6) P_13.12.152 Reference voltage for unidirectional CSAx VREF Unidir -1.25% VCC1/5 +1.25% V CSD = 0 VCSAP = VCSAN P_13.12.153 Reference voltage for bidirectional CSAx VREF Bidir -1% VCC1/2 +1% V CSD = 1 VCSAP = VCSAN P_13.12.154 Overcurrent detection Overcurrent filter time tFOC 4 100 120 µs 5)6) OCFILT = 00 B OCFILT = 01B OCFILT = 10B OCFILT = 11B P_13.12.155 OC threshold, unidirectional VOCTH1 Unidir -4% VCC1/2 +4% V CSD = 0, OCTH[1:0]= 00B P_13.12.156 OC threshold, unidirectional VOCTH2 Unidir -4% VCC1/2 VCC1/10 +4% V CSD = 0, OCTH[1:0]= 01B P_13.12.157 Table 35 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 117 Rev. 1.0 2021-01-21 OC threshold, unidirectional VOCTH3 Unidir -4% VCC1/2 + 2x VCC1/1 +4% V CSD = 0, OCTH[1:0]= 10 B P_13.12.158 OC threshold, unidirectional VOCTH4 Unidir -4% VCC1/2 + 3x VCC1/10 +4% V CSD = 0, OCTH[1:0]= 11B P_13.12.159 High OC threshold, bidirectional VOCTH1 BidirH -4% VCC1/2 + 2x V CC1/20 +4% V CSD = 1, OCTH[1:0]= 00B P_13.12.160 High OC threshold, bidirectional VOCTH2 BidirH -4% VCC1/2 + 4x VCC1/20 +4% V CSD = 1, OCTH[1:0]= 01B P_13.12.161 High OC threshold, bidirectional VOCTH3 BidirH -4% VCC1/2 + 5x VCC1/20 +4% V CSD = 1, OCTH[1:0]= 10B P_13.12.162 High OC threshold, bidirectional VOCTH4 BidirH -4% VCC1/2 + 6x V CC1/20 +4% V CSD = 1, OCTH[1:0]= 11B P_13.12.163 Low OC threshold, bidirectional VOCTH1 BidirL -4% VCC1/2 - VCC1/20 +4% V CSD = 1, OCTH[1:0]= 00B P_13.12.164 Low OC threshold, bidirectional VOCTH2 BidirL -4% VCC1/2 - VCC1/20 +4% V CSD = 1, OCTH[1:0]= 01B P_13.12.165 Low OC threshold, bidirectional VOCTH3 BidirL -4% VCC1/2 - V CC1/20 +4% V CSD = 1, OCTH[1:0]= 10B P_13.12.166 Low OC threshold, bidirectional VOCTH4 BidirL -4% VCC1/2 - VCC1/20 +4% V CSD = 1, OCTH[1:0]= 11B P_13.12.167 Current Sense Amplifier Dynamic Parameters Power Supply Rejection Ratio PSRR 60 – – dB 6) VCP modulated with sinewave (100 kHz, 1 Vpp P_13.12.168 Overtemperature Shutdown6) Thermal Prewarning Temperature TjPW 125 145 165 °C Tj rising P_13.12.169 Thermal Shutdown TSD1 TjTSD1 170 185 200 °C Tj rising P_13.12.170 Thermal Shutdown TSD2 TjTSD2 170 185 200 °C Tj rising P_13.12.171 Table 35 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 118 Rev. 1.0 2021-01-21 Thermal Shutdown hysteresis TjTSD,hys –2 5 –° C 6) P_13.12.172 TSD/TPW Filter Time tTSD_TPW_F 5 10 15 us rising and falling, applies to all thermal sensors (TPW, TSD1, TSD2) P_13.12.173 Deactivation time after thermal shutdown TSD2 t TSD2 0.8 1 1.2 s 2) P_13.12.174 1) It is ensured that the threshold VCC1,OV,r is always higher than the highest regulated VCC1 output voltage VCC1,out4. 2) Not subject to production test, tolerance defined by internal oscillator tolerance. 3) This time applies for all failure en tries except a device thermal shutdown (TSD2 has a typ. 1 s waiting time tTSD2). 4) 6 V ≤ VS ≤ 23 V 5) tFOC refers to the output of the current sense amplifier. The CSO settling time (2 µs max, tSET) and the analog propagation delay (< 1 µs)are not taken into account by the overcurrent filter time. 6) Not subject to production test, specified by design. Table 35 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 119 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11 Serial Peripheral Interface

The Serial Peripheral Interface is the communication link between the device and the microcontroller. The TLE9185QX is supporting multi-slave operation in full-duplex mode with 32-bit data access. The SPI behavior for the different device modes is as follows:

• The SPI is enabled in Init Mode, Normal Mode and Stop Mode.
• The SPI is OFF in Sleep Mode, Restart Mode and Fail-Safe Mode.

11.1 SPI Block Description

The Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 56 with a 32-bit data access example). The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content. The SDO output switches to tristate status (high impeda nce) at this point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input regist er with every falling edge on CLK. The state of SDO is shifted out of the output register after every rising ed g e o n C L K . T h e S P I o f t h e d e v i c e i s n o t d a i s y c h a i n capable. Figure 56 SPI Data Transfer Timing (note the reve rsed order of LSB and MSB shown in this figure compared to the register description) 0 0 +1 2 3 4 5 6 31 1 0 1 2 3 4 5 6 27 28 29 30 31 CSN high to low: SDO is enabled. Status information transferred to output shift register CSN low to high: data from shift register is transferred to output functions SDI: will accept data on the falling edge of CLK signal SDO: will change state on the rising edge of CLK signal Actual status 27 28 29 30 Actual data New data New status SDO SDI CSN CLK time time time time ERRERR - 0 LSB LSB MSB MSB

Datasheet 120 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.2 Failure Signalization in the SPI Data Output

When the microcontroller sends a wrong SPI command to the device, the device ignores the information. Wrong SPI commands are either invalid device mode commands or commands whic h are prohibited by the state machine to avoid undesired device or system states (see below). In this case the diagnosis bit SPI_FAIL is set and the SPI Write command is ig nored (no partial interpretation). This bit can be only reset by actively clearing it via a SPI command. Invalid SPI Commands leading to SPI_FAIL are listed below (in this case the SPI command is ignored):

• Illegal state transitions: - Going from Stop Mode to Sleep Mode. In this case the device enters Restart Mode. - Trying to go to Stop Mode or Sleep Mode from Init Mode1). In this case Normal Mode is entered.
• Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored and/or the new watchdog settings are ignored respectively.
• In Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration is ignored; only WD trigger, returning to Normal Mode, triggering a device soft reset, and read & clear status registers commands are valid SPI commands in Stop Mode; Note: No failure handling is done for the attempt to go to Stop Mode when all bits in the register WK_CTRL is cleared because the microcontroller can leave this mode via SPI.
• When entering Stop Mode and WK_STAT is not cleared; SPI_FAIL will not be set but the INTN pin will be triggered.
• Changing from Stop Mode to Normal Mo de and changing the other bits of the M_S_CTRL register. The other modifications will be ignored.
• Sleep Mode: attempt to go to Sleep Mode without any wake source set, i.e. when all bits in the WK_CTRL register is cleared. In this case the SPI_FAIL bit is set and the device enters Restart Mode. Even though the Sleep Mode command is not entered in this case, the rest of the command is executed but restart values apply during Restart Mode; Note: At least one wake source must be activated in order to avoid a deadlock situation in Sleep Mode. If the only wake source is a timer and the timer is OFF, then the device will wake immediately from Sleep Mode and enter Restart Mode.
• Setting a longer or equal on-time than the timer period of the respective timer.
• SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’. Note: There is no SPI fail in formation for unused addresses. Note: In case that the register or banking are access ed but they are not valid as address or banks, the SPI_FAIL is not triggered and the cmd is ignored. Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 56): The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set for following conditions:
• in case the number of receiv ed SPI clocks is not 0 or 32.
• in case RSTN is LOW and SPI frames are being sent at the same time. 1) If the device is externally configured to use SPI with CRC (by PWM1/CRC pin), the attempt to go to Stop or Sleep from Init , will generate SPI_FAIL even if it is a SPI command with correct CRC. Still, the first SPI command will put the device from Init to Normal Mode even if CRC is not correct (CRC_FAIL status bit will be set).

Datasheet 121 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not valid if the CLK is high on a falling edge of CSN. The number of received SPI clocks is not 0 or 32: The number of received input clocks is supervised to be 0 or 32 clock cycles and the input word is discarded in case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high during CSN edges. Both errors ( 0 or 32 bit CLK mismatch or CLK high during CSN edges ) are flagged in the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock is received. The complete SPI command is ignored in this case. RSTN is LOW and SPI frames are being sent at the same time: The ERR flag will be set when the RSTN pin is triggered (during device restart) and SPI frames are being sent to the device at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below conditions:

• If the command begins when RSTN is HIGH and it ends when RSTN is LOW.
• If a SPI command will be sent while RSTN is LOW.
• If a SPI command begins when RSTN is LOW and it ends when RSTN is HIGH. And the SDO output will behave as follows:
• Always when RSTN is LOW then SDO will be HIGH.
• When a SPI command begins when RS TN is LOW and ends when RSTN is HIGH, then the SDO should be ignored because wrong data will be sent. Note: It is possible to quickly check fo r the ERR flag without sending any data bits. i.e. only the CSN is pulled low and SDO is observed - no SPI Clocks are sent in this case. Note: The ERR flag could also be set after the de vice has entered Fail-Safe Mode because the SPI communication is stopped immediately.

Datasheet 122 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.3 SPI Programming

For the TLE9185QX, 7 bits are used fo r the address selection (BIT 6...0). Bi t 7 is used to decide between Read Only and Read & Clear for the status bits, and betwee n Write and Read Only for configuration bits. For the actual configuration and status information, 16 data bits (BIT 23...8) are used. Writing, clearing and reading is done word wise. The SPI status bits are not cleared automatically and must be cleared by the microcontroller. Some o f t h e c o n f i g u r a t i o n b i t s w i l l a u t o m a t i c a l l y b e c l e a r e d b y t h e d e v i c e (refer to the respective register descriptions for detailed information). In Restart Mode, the device ignores all SPI communication, i.e. it does not interpret it. There are two types of SPI registers:

• Control registers: These registers are used to configure the device, e.g. mode, watchdog trigger, etc.
• Status registers: These registers indicate the status of the device, e.g. wake events, warnings, failures, etc. For the status registers, the requested information is given in the same SPI comma nd in the data out (SDO). For the control registers, the status o f e a c h b y t e i s s h o w n i n t h e s a m e S P I c o m m a n d a s w e l l . H o w e v e r , configuration changes of the same register are only shown in the next SPI command (configuration changes inside the device become valid only after CSN changes from low to high). See Figure 57. Writing of control registers is possible in Init and Normal Mode. During Stop Mode only the change to Normal Mode and triggering the watchdog is allowed as well as reading and clearing the status registers. No status information can be lost, even if a bit change s right after the first 7 SPI clock cycles before the SPI frame ends. In this case the status information field will be updated with the next SPI command. However, the flag is already set in the relevant status register.The device status information from the SPI status registers is transmitted in a compressed format with each SPI response on SDO in the so-called Status Information Field register (see also Table 36). The purpose of this register is to qu ickly signal changes in dedicated SPI status registers to the microcontroller. Table 36 Status Information Field Bit in Status Information Field Corresponding Address Bit Status Register Description

0 SUPPLY_STAT = OR of all bits on SUP_STAT register

1 TEMP_STAT = OR of all bi ts on THERM_STAT register

3 WAKE_UP = OR of all bits on WK_STAT register

5 DEV_STAT = OR of all bits on DEV_STAT except

CRC_STAT and SW_DEV

6 BD_STAT = OR of all bits on DSOV register

7 SPI_CRC_FAIL = (SPI_FAIL) OR (CRC_FAIL)

Datasheet 123 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Figure 57 SPI Operation Mode

11.3.1 CRC

The SPI interface includes also 8 Bits (bits 24 to 31) used for Cyclic Re dundancy Check (CRC) to ensure data integrity on sent or received SPI command. The implemented CRC is based on Auto sar specification of CRC Routines re vision 4.3.0 and in particular the function CRC8-2FH. The specification are based on the follow table: Some examples of CRC calculation are shown in the follow table: Table 37 CRC8x2FH definition CRC result width: 8 bits Polynomial 2F H Initial Value FF H Input data reflected No Result data reflected No XOR value FF H Check DF H Magic check 42 H Table 38 CRC8x2FH calculation example Data Bytes (hexadecimal) CRC 00 00 00 00 12 F2 01 83 C2 0F AA 00 55 C6

00 FF 55 11 77

33 22 55 AA BB CC DD EE FF 11 92 6B 55 33 FF FF FF FF 6C 0 1 2 3 4 5 76 8 9 10 11 12 13 1514 Data Bits DI Address Bits x x x x x x xx R/W 0 1 2 3 4 5 76 8 9 10 11 12 13 1514 Data Bits DO Status Information Field x x x x x x xx Register content of selected address LSB MSB time LSB is sent first in SPI message x x x x x x xx x x x x x x xx 16 17 18 19 20 21 2322 16 17 18 19 20 21 2322 CRC or Static Pattern CRC or Static Pattern 24 25 26 27 28 29 3130 24 25 26 27 28 29 3130 x x x x x x xx x x x x x x xx

Datasheet 124 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Polynominal The polynomial is: x8 + x5 + x3 + x2 + x1 + x0 (11.1) Calculation in SDI and SDO The calculation of the CRC is done considering the first 24 bits (BIT 0..23) either of SDI or SDO. The content of SDO Payload (BIT 8..23) is referring the previous data written at the addressed register via SDI. Figure 58 CRC calculation CRC Activation and status information For CRC activation, refer to Chapter 5.2. The CRC status (CRC_STAT)and failure (CRC_FAIL) are readable on DEV_STAT. Read out of the regist er which contains the CRC_STAT and CRC_FAIL is done ignoring the CRC field and no failure flag are set. The DEV_STAT register shall be cleared considering the CRC setting (ON or OFF). The CRC_STAT bit is read only. The CRC_FAIL is set in the follow conditions:

• If the CRC is enabled and the µC sends wrong CRC field.
• If the CRC is disabled and the µC sends wrong static pattern (no A5H). CRC field in case of CRC disabled In case that the CRC is not activated, the bits needed for CRC field have to be filled with static pattern. In case of SDI, the CRC field has to be filled with A5H (bits 24:31). In case of SDO, the device will always answer with 5AH (bits 24:31). The status of the CRC is updated accordingly in CRC_STAT bit. Add. r w Payload - Configuration CRC SDI ∑ PASS/FAIL Status Info. Field From previous SPI cmd CRC SDO

Datasheet 125 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.4 SPI Bit Mapping

The following figures show the mapping of the registers and the SPI bits of the respective registers. The Control Registers are Read/Write Register with the following structure:

• Device Control Registers from 000 0001 B to 000 1011B.
• Bridge Driver Control Registers from 001 0000 B to 001 1101B. Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after a write can be seen with a new read / write command. The Status Registers are Read/Clear with the following structure:
• Device Status Registers from 100 0000 B to 100 0110B.
• Bridge Driver Status Registers from 101 0000 B to 101 1011B.
• Product Family is 111 0000 B. The registers can be read or can be cleared (if clearing is possible) depending on bit 7. To clear the payload of one of the Status Registers bit 7 must be set to 1. The registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at the respective WKx pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared. It is recommended for proper diagnosis to clear respective status bits for wake events or failure. When changing to a different device mode, certain co n f i g u r a t i o n s b i t s w i l l b e cleared automatically or modified:
• The device mode bits are updated to the actual status, e.g. when returning to Normal Mode.
• When changing to a low-power mode (Stop Mode or Sleep Mode), the diagnosis bits of the integrated module are not cleared.
• When changing to Stop Mode, the control bits will not be modified.
• When changing to Sleep Mode, the control bits will be modified if they were not OFF or wake capable before. Note: The detailed behavior of the respective SPI bits and control functions is described in Chapter 11.5, Chapter 11.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the device will modify respective control bits.

Datasheet 126 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Figure 59 SPI Register Mapping Structure The detailed register mappings for control registers and status registers are shown in Table 39 and Table 61 respectively.

11.4.1 Register Banking

In order to minimize the number of configuration registers, seven registers follow a bank structure. The banked registers are:

• WK_CTRL
• CCP_BLK
• TPRECHG
• HB_ICHG
• HB_PCHG_INIT
• TDON_HB_CTRL
• TDOFF_HB_CTRL In these register, the first 3 bits of the payload (bit 8 to 10) select the bank that has to be configured. The rest of the payload is used to configure the selected bank (for more details refer to the specific banked register). In case that CRC is used, the CRC calculation is done considering the first 24 bits (from bit 0 to 23). The banked registers can be read like the other configuration registers but in the SDO one ‘0’ is automatically added after the status information field. Figure 60 shows the structure of SDO in banked register. 7 Address Bits [bits 6...0] for Register Selection 16 Data Bits [bits 23...8] for Configuration & Status Information Reg. Type Device Control Registers Addresses: 0 0 0 0 0 0 1 0 0 0 1 0 1 1 Status Registers Status Information Field Bit Addresses: 1 0 0 0 0 0 0 1 1 1 0 0 0 0 The most important status registers are represented in the Status Information Field Bridge Driver Control Registers Addresses: 0 0 1 0 0 0 0 0 0 1 1 1 0 1

Datasheet 127 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Figure 60 Register read Out of banked register (3 bit banking) Add. r w Configuration of selected Bank CRC Status Info. Filed Selected Bank Content CRC SDO B K B K SDI B K B K R e s B K B K

Datasheet 128 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.5 SPI control registers

READ/WRITE Operation (see also Chapter 11.3):

• The ‘POR / Soft Reset Value’ defines the re gister content after POR or device reset.
• The ‘Restart Value’ defines the register content after device restart, where ‘x’ means the bit is unchanged.
• There are different bit types: – ‘r’ = READ: read only bits (or reserved bits). – ‘rw’ = READ/WRITE: readable and writable bits. – ‘rwh’ = READ/WRITE/Hardware: readable/writable bits , which can also be modified by the device hardware.
• Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be programmed as “0”.
• Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only).
• SPI control bits are in general not cleared or ch anged automatically. This must be done by the microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register description and the respective bit type is marked with a ‘h’ meaning that the device is able to change the register content. The registers are addressed wordwise. Table 39 Register Overview Register Short Name Register Long Name Offset Address Page Number SPI control registers, Device Control Registers M_S_CTRL Mode and Supply Control 0000001 B 130 HW_CTRL Hardware Control 0000010 B 132 WD_CTRL Watchdog Control 0000011 B 134 WK_CTRL Wake-up Control 0000101 B 135 TIMER_CTRL Timer 1 and Timer 2 Control and Selection 0000110 B 137 INT_MASK Interrupt Mask Control 0001001 B 139 SYS_STAT_CTRL System Status Control 0001011 B 141 SPI control registers, Control registers bridge driver GENCTRL General Bridge Control 0010000 B 142 CSA Current sense amplifier 0010001 B 144 LS_VDS Drain-Source monitoring threshold 0010010 B 146 HS_VDS Drain-Source monitoring threshold 0010011 B 148 CCP_BLK CCP and times selection 0010100 B 150 HBMODE Half-Bridge MODE 0010101 B 151 TPRECHG PWM pre-charge and pre-discharge time 0010110 B 153 ST_ICHG Static charge/discharge current 0010111 B 154 HB_ICHG PWM charge/discharge current 0011000 B 155 HB_ICHG_MAX PWM max. pre-charge/pre-discharge current and diagnostic pull-down 0011001B 156 HB_PCHG_INIT PWM pre-charge/pre-discharge initialization 0011010 B 158

Datasheet 129 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface TDON_HB_CTRL PWM inputs TON configuration 0011011 B 159 TDOFF_HB_CTRL PWM inputs TOFF configuration 0011100 B 160 BRAKE Brake control 0011101 B 161 Table 39 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Page Number

Datasheet 130 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.5.1 Device Control Registers

M_S_CTRL Mode and Supply Control (000 0001 B) Reset Value: see Table 40 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 MODE RES VCC1_OV_MO D RES RSTN_ HYS RES I_PEA K_TH RES VCC1_RT rwh r rwh r rw r rw r rw Field Bits Type Description MODE 15:14 rwh Device Mode Control 00B NORMAL, Normal Mode 01B SLEEP, Sleep Mode 10B STOP, Stop Mode 11B RESET, Device reset: Soft reset is executed (configuration of RSTN triggering in bit SOFT_RESET_RO) RES 13:11 r Reserved, always reads as 0 VCC1_OV_MOD 10:9 rwh Reaction in case of VCC1 Over Voltage B NO, no reaction 01B INTN, INTN event is generated 10B RSTN, RSTN event is generated 11B FAILSAFE, Fail-Safe Mode is entered RES 8r Reserved, always reads as 0 RSTN_HYS 7r w VCC1 Undervoltage Reset Hysteresis Selection (see also Chapter 10.6.1 for more information) 0B DEFAULT, default hysteresis applies as specified in the electrical characteristics table 1B HIGHEST, the highest rising threshold (VRT1,R) is always used for the release of the undervoltage reset RES 6r Reserved, always reads as 0 I_PEAK_TH 5r w VCC1 Active Peak Threshold Selection 0B LOW, low VCC1 active peak threshold selected 1B HIGH, high VCC1 active peak threshold selected RES 4:2 r Reserved, always reads as 0 VCC1_RT 1:0 rw VCC1 Reset Threshold Control 00B VRT1, Vrt1 selected (highest threshold) 01B VRT2, Vrt2 selected 10B VRT3, Vrt3 selected 11B VRT4, Vrt4 selected

Datasheet 131 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Notes 1. It is not possible to change from Stop Mode to Sl eep Mode via SPI Command. See also the State Machine Chapter. 2. After entering Restart Mode, the MODE bits will be automatically set to Normal Mode. 3. The SPI output will always show the previously written state with a Write Command (what has been programmed before) . Table 40 Reset of M_S_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 0000 x0x0 00xx B

Datasheet 132 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Hardware Control HW_CTRL Hardware Control (000 0010 B) Reset Value: see Table 41 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TSD2_ DEL VS_OV _SEL SH_DI SABLE RSTN_ DEL RES SOFT_ RESET _RO RES RES WD_S TM_E N_1 RES rr w r w r w r w r r w r r r w h r Field Bits Type Description RES 15:13 r Reserved, always reads as 0 TSD2_DEL 12 rw TSD2 minimum Waiting Time Selection 0B 1s, Minimum waiting time until TSD2 is released again is always 1 s 1B 64s, Minimum waiting time until TSD2 is released again is 1 s, after >16 TSD2 consecutive events, it will extended x 64 VS_OV_SEL 11 rw VS OV comparator threshold change 0B 20V, Default threshold setting (VS,OVD1) 1B 30V, increased threshold setting (VS,OVD2) SH_DISABLE 10 rw Sample and hold circuitry disable 0B ENABLED, Gate driver S&H circuitry enabled 1B DISABLED, Gate driver S&H circuitry disabled RSTN_DEL 9r w Reset delay time 0B 10ms, Reset delay time 10 ms (tRD1) 1B 2ms, Reset delay time to 2 ms (tRD2) RES 8:7 r Reserved, always reads as 0 SOFT_RESET_RO 6r w Soft Reset Configuration 0B RSTN, RSTN will be triggered (pulled low) during a Soft Reset 1B NO_RSTN, no RSTN trigger during a Soft Reset RES 5r Reserved, always reads as 0 RES 4:3 r Reserved, always reads as 0 WD_STM_EN_1 2r w h Watchdog Deactivation during Stop Mode, bit1 0B ACTIVE, Watchdog is active in Stop Mode 1B INACTIVE, Watchdog is deactivated in Stop Mode RES 1:0 r Reserved, always reads as 0 Table 41 Reset of HW_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR 0000 0000 0000 0000 B Soft reset 0000 00x0 0000 0000 B Restart 000x 00x0 0x00 0000 B

Datasheet 133 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Notes 1. WD_STM_EN_1 will also be cleared when ch anging from Stop Mode to Normal Mode .

Datasheet 134 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Watchdog Control Notes 1. See also Chapter 10.2.4 for more information on disabling the watchdog in Stop Mode. 2. See chapter Chapter 10.2.3 for calculation of checksum. WD_CTRL Watchdog Control (000 0011 B) Reset Value: see Table 42 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CHEC KSUM RES WD_S TM_E N_0 WD_C FG RES RES WD_TIMER rw r rwh rw rwh r rwh Field Bits Type Description CHECKSUM 15 rw Watchdog Setting Check Sum Bit 0B 0, Counts as 0 for checksum calculation 1B 1, Counts as 1 for checksum calculation RES 14:7 r Reserved, always reads as 0 WD_STM_EN_0 6r w h Watchdog Deactivation during Stop Mode, bit0 0B ACTIVE, Watchdog is active in Stop Mode 1B INACTIVE, Watchdog is deactivated in Stop Mode WD_CFG 5r w Watchdog Configuration 0B TIMEOUT, Watchdog works as a Time-Out watchdog 1B WINDOW, Watchdog works as a Window watchdog RES 4r w h Reserved, to be set to ‘0’ RES 3r Reserved, always reads as 0 WD_TIMER 2:0 rwh Watchdog Timer Period 000B 10ms, 10ms 001B 20ms, 20ms 010B 50ms, 50ms 011B 100ms, 100ms 100B 200ms, 200ms 101B 500ms, 500ms 110B 1s, 1s 111B 10s, 10s Table 42 Reset of WD_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0001 0100 B Restart 0000 0000 000x 0100 B

Datasheet 135 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Wake-up Control WK_CTRL Wake-up Control (000 0101 B) Reset Value: see Table 43 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES WK_FILT WK_PUPD RES WK_EN RES WK_BNK r r rw rw r rw r rw Field Bits Type Description RES 15 r Reserved, always reads as 0 RES 14 r Reserved, always reads as 0 WK_FILT 13:11 rw Wake-up Filter Time Configuration 000B 16us, Filter with 16 µs filter time (static sensing) 001B 64us, Filter with 64 µs filter time (static sensing) 010B TIMER1, Filtering at the end of the on-time; filter time of 16 µs (cyclic sensing) is selected, Timer1 011B TIMER2, Filtering at the end of the on-time; filter time of 16 µs (cyclic sensing) is selected, Timer2 100B , reserved 101B , reserved 110B , reserved 111B , reserved WK_PUPD 10:9 rw WKx Pull-Up/Pull-Down Configuration 00B NO, No pull-up/pull-down selected 01B PULL_DOWN, Pull-down resistor selected 10B PULL_UP, Pull-up resistor selected 11B AUTO, Automatic switching to pull-up or pull- down RES 8:7 r Reserved, always reads as 0 WK_EN 6:5 rw WKx Enable ,to be set to 01B1) 00B WK_OFF, WKx module OFF 01B WK_ON, WKx module ON 10B RES, reserved 11B OFF, OFF 1) Warning: if WK_EN is not set to 01 B, then the device cannot wake up upon an edge of WK4. RES 4:3 r Reserved, always reads as 0 WK_BNK 2:0 rw WKs input Banking, to be set to 011B 011B WK4, WK4 Module (Bank 4) 100B , reserved 101B , reserved 110B , reserved 111B , reserved

Datasheet 136 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Notes 1. At Fail-Safe Mode entry WK_EN will be automatically changed (by the device) in “01”. 2. During Fail-Safe Mode the WK_FILT bits are ignored and static-sense with 16 µs filter time is used by default. Table 43 Reset of WK_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0010 0000 B Restart 00xx xxx0 0xx0 0000 B

Datasheet 137 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Timer 1 and Timer2 Control and Selection TIMER_CTRL Timer 1 and Timer2 Control and Selection (000 0110 B) Reset Value: see Table 44 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 TIMER2_ON RES TIMER2_PER CYCWK TIMER1_ON RES TIMER1_PER rwh r rwh rwh rwh r rwh Field Bits Type Description TIMER2_ON 15:13 rwh Timer2 On-Time Configuration 000B OFF, OFF 001B 100us, 0.1ms on-time 010B 300us, 0.3ms on-time 011B 1ms, 1.0ms on-time 100B 10ms, 10ms on-time 101B 20ms, 20ms on-time 110B , reserved 111B , reserved RES 12 r Reserved, always reads as 0 TIMER2_PER 11:9 rwh Timer2 Period Configuration 000B 10ms, 10ms 001B 20ms, 20ms 010B 50ms, 50ms 011B 100ms, 100ms 100B 200ms, 200ms 101B 500ms, 500ms 110B 1s, 1s 111B 2s, 2s CYCWK 8:7 rwh Cyclic Wake Configuration 00B DISABLED, Timer1 and Timer2 disabled as wake- up sources 01B TIMER1, Timer1 is enabled as wake-up source (Cyclic Wake) 10B TIMER2, Timer2 is enabled as wake-up source (Cyclic Wake) 11B , reserved TIMER1_ON 6:4 rwh Timer1 On-Time Configuration 000B OFF, OFF 001B 100us, 0.1ms on-time 010B 300us, 0.3ms on-time 011B 1ms, 1.0ms on-time 100B 10ms, 10ms on-time 101B 20ms, 20ms on-time 110B , reserved 111B , reserved RES 3r Reserved, always reads as 0

Datasheet 138 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Notes 1. The timer must be first assigned and is then automati cally activated as soon as the on-time is configured. 2. Timer accuracy is linked to the osci llator accuracy (see Parameter P_13.12.43). TIMER1_PER 2:0 rwh Timer1 Period Configuration 000B 10ms, 10ms 001B 20ms, 20ms 010B 50ms, 50ms 011B 100ms, 100ms 100B 200ms, 200ms 101B 500ms, 500ms 110B 1s, 1s 111B 2s, 2s Table 44 Reset of TIMER_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 0000 0000 0000 B Field Bits Type Description

Datasheet 139 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Interrupt Mask Control1) 1) Every event will generate a signal on th e INTN pin (when masked accordingly). Even if the status-bit was already set in the corresponding status-register it can still trigger a signal on the INTN pin. INT_MASK Interrupt Mask Control (000 1001 B) Reset Value: see Table 45 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES INTN_ CYC_E N WD_S DM_DI SABLE WD_S DM SPI_C RC_FA IL BD_ST AT RES RES TEMP _STAT SUPP LY_ST AT r r wr wr wr wr wr wr wr wr w Field Bits Type Description RES 15:9 r Reserved, always reads as 0 INTN_CYC_EN 8r w Periodical INTN generation 0B DISABLED, no periodical INTN event generated in case of pending interrupts 1B ENABLED, periodical INTN event generated in case of pending interrupts WD_SDM_DISABLE 7r w Disable Watchdog in Software Development Mode 0B ENABLED, WD is enabled in Software Development Mode 1B DISABLED, WD is disabled in Software Development Mode WD_SDM 6r w Watchdog failure in Software Development Mode 0B DISABLED, no INTN event generated in case of WD trigger failure in Software Development Mode 1B ENABLED, one INTN event is generated in case of WD trigger failure in Software Development Mode SPI_CRC_FAIL 5r w SPI and CRC interrupt generation 0B DISABLED, no INTN event generated in case of SPI_FAIL or CRC_FAIL 1B ENABLED, one INTN event is generated n case of SPI_FAIL or CRC_FAIL BD_STAT 4r w Bridge Driver Interrupt generation 0B DISABLED, no INTN event generated in case BD_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case BD_STAT (on Status Information Field) is set RES 3r w Reserved, to be set to ‘0’ RES 2r w Reserved, to be set to ‘0’

Datasheet 140 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface TEMP_STAT 1r w Temperature Interrupt generation 0B DISABLED, no INTN event generated in case TEMP_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case TEMP_STAT (on Status Information Field) is set SUPPLY_STAT 0r w SUPPLY Status Interrupt generation 0B DISABLED, no INTN event generated in case SUPPLY_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case SUPPLY_STAT (on Status Information Field) is set Table 45 Reset of INT_MASK Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0001 0100 0000 B Restart 0000 000x xxxx xxxx B Field Bits Type Description

Datasheet 141 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface System Status Control Note: This register is intended for storing system configuration of the ECU by the microcontroller and is only accessible in Normal Mode. The register is not accessible by the TLE9185QX and is also not cleared after Fail-Safe or Restart Mode. It allows the microcontroller to quickly store system configuration without loosing data. SYS_STAT_CTRL System Status Control (000 1011 B) Reset Value: see Table 46 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 SYS_STAT rw Field Bits Type Description SYS_STAT 15:0 rw System Status Control (bit0=LSB; bit15=MSB) Dedicated bytes for system configuration, access only by microcontroller. Cleared after power up and soft reset. Table 46 Reset of SYS_STAT_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR / Soft reset 0000 0000 0000 0000 B Restart xxxx xxxx xxxx xxxx B

Datasheet 142 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.5.2 Control registers bridge driver

General Bridge Control (001 0000 B) Reset Value: see Table 47 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 BDFR EQ RES RES CPUV TH FET_L VL CPST GA BDOV _REC IPCHG ADT AGC CPEN POCH GDIS AGCFI LT EN_GE N_CH ECK IHOLD FMOD E rw r r rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description BDFREQ 15 rw Bridge driver synchronization frequency 0B 18MHz, typ. 18.75 MHz (default) 1B 37MHz, typ. 37.5 MHz RES 14 r Reserved, always reads as 0 RES 13 r Reserved, always reads as 0 CPUVTH 12 rw Charge pump under voltage (referred to VS) 0B TH1, (default) CPUV threshold 1 for FET_LVL = 0, CPUV threshold 1 for FET_LVL = 1 1B TH2, CPUV threshold 2 for FET_LVL = 0, CPUV threshold 2 for FET_LVL = 1 FET_LVL 11 rw External MOSFET normal / logic level selection 0B LOGIC, Logic level MOSFET selected 1B NORMAL, Normal level MOSFET selected(default) CPSTGA 10 rw Automatic switchover between dual and single charge pump stage 0B INACTIVE, Automatic switch over deactivated (default) 1B ACTIVE, Automatic switch over activated BDOV_REC 9r w Bridge driver recover from VS and VSINT Overvoltage 0B INACTIVE, Recover deactivated (default) 1B ACTIVE, Recover activated IPCHGADT 8r w Adaptation of the pre-charge and pre-discharge current 0B 1STEP, 1 current step (default) 1B 2STEPS, 2 current steps

Datasheet 143 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface AGC 7:6 rw Adaptive gate control 00B INACTIVE1, (default) Adaptive gate control disabled, pre-charge and pre-discharge disabled 01B INACTIVE2, Adaptive gate control disabled, precharge is enabled with IPRECHG = IPCHGINIT, predischarge is enabled with IPREDCHG = IPDCHGINIT 10B ACTIVE, Adaptive gate control enabled, IPRECHG and IPREDCHG are self adapted 11B , reserved. Adaptive gate control enabled, IPRECHG and IPREDCHG are self adapted CPEN 5r w CPEN 0B DISABLED, Charge pump disabled (default) 1B ENABLED, Charge pump enabled POCHGDIS 4r w Postcharge disable bit 0B ENABLED, The postcharge phase is enabled during PWM (default) 1B DISABLED, The postcharge phase is disabled during PWM AGCFILT 3r w Filter for adaptive gate control 0B NO_FILT, No filter applied (default) 1B FILT_APPL, Filter applied EN_GEN_CHECK 2r w Detection of active / FW MOSFET 0B DISABLED, Detection disabled (default) 1B ENABLED, Detection enabled IHOLD 1r w Gate driver hold current IHOLD 0B TH1, (default) Charge: ICHG15, discharge IDCHG15. 1B TH2, Charge: ICHG20, discharge: IDCHG20 FMODE 0r w Frequency modulation of the charge pump 0B NO, No modulation 1B 15KHz, Modulation frequency 15.6 kHz (default) Table 47 Reset of GENCTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 1000 0000 0001 B Restart x00x xxxx xxxx xxxx B Field Bits Type Description

Datasheet 144 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Current sense amplifier CSA Current sense amplifier (001 0001 B) Reset Value: see Table 48 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES PWM_ NB CSO_ CAP CSD OCFILT CSA_O FF OCTH CSAG OCEN r r w r w r wr wr wr w r wr w Field Bits Type Description RES 15:11 r Reserved, always reads as 0 PWM_NB 10 rw Selection of 3 or 6 PWM inputs 0B 3PWM, 3 PWM inputs (default) 1B 6PWM, 6 PWM inputs CSO_CAP 9r w Capacitance connected to the current sense amplifier output (CCSO), see also Chapter 10.10.4 0B 400pF, CCSO < 400 pF (default) 1B 2nF, 400 pF < CCSO < 2.2 nF CSD 8r w Direction of the current sense amplifier 0B UNI, Unidirectional 1B BI, Bidirectional (default) OCFILT 7:6 rw Overcurrent filter time of CSO 00B 6us, 6 µs (default) 01B 10us, 10 µs 10B 50us, 50 µs 11B 100us, 100 µs CSA_OFF 5r w CSA OFF 0B CSA_ON, CSA enabled 1B CSA_OFF, CSA disabled (default) OCTH 4:3 rw Overcurrent detection threshold of CSO 00B TH1, VCSO > VCC1/2+2 x VCC1/20 or VCSOx< VCC1/2- 2x VCC1/20 (default) 01B TH2, VCSO > VCC1/2+ 4x VCC1/20 or VCSOx< VCC1/2- 4x VCC1/20 10B TH3, VCSO > VCC1/2+ 5 x VCC1/20 or VCSOx< VCC1/2- 5 xVCC1/20 11B TH4, VCSO > VCC1/2+ 6x VCC1/20 or VCSOx< VCC1/2- 6x VCC1/20 CSAG 2:1 rw Gain of the current sense amplifier 00B 10VV, GDIFF10 (default) 01B 20VV, GDIFF20 10B 40VV, GDIFF40 11B 60VV, GDIFF60 OCEN 0r w Overcurrent shutdown Enable 0B DISABLED, Disabled 1B ENABLED, Enabled (default)

Datasheet 145 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Table 48 Reset of CSA Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0001 0010 0001 B Restart 0000 0xxx xxxx xxx1 B

Datasheet 146 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Drain-Source monitoring threshold LS1-3 LS_VDS VDS monitoring threshold LS1-3 (001 0010 B) Reset Value: see Table 49 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TFVDS RES LS3VDSTH LS2VDSTH LS1VDSTH r rw r rw rw rw Field Bits Type Description RES 15:14 r Reserved. Always read as 0 TFVDS 13:12 rw Filter time of drain-source voltage monitoring 00B 500ns, 0.5 µs (default) 01B 1us, 1 µs 10B 2us, 2 µs 11B 6us, 6 µs RES 11:9 r Reserved, always reads as 0 LS3VDSTH 8:6 rw LS3 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V LS2VDSTH 5:3 rw LS2 drain-source overvoltage threshold 000B 160mV, 0.16V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V LS1VDSTH 2:0 rw LS1 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V

Datasheet 147 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Table 49 Reset of LS_VDS Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0100 1001 B 0000 0000 0000 0000 Restart 0000 000x xxxx xxxx B

Datasheet 148 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Drain-Source monitoring Threshold HS1-3 HS_VDS VDS monitoring threshold HS1-3 (001 0011 B) Reset Value: see Table 50 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES DEEP_ ADAP RES HS3VDSTH HS2VDSTH HS1VDSTH r rw rw r rw rw rw Field Bits Type Description RES 15:14 r Reserved. Always read as 0 RES 13 rw Reserved. This bit must be programmed to ‘0‘ DEEP_ADAP 12 rw Deep adaptation enable 0B NO_DEEP_ADAP, Deep adaptation disabled (default) 1B DEEP_ADAP, Deep adaptation enabled RES 11:9 r Reserved, always reads as 0 HS3VDSTH 8:6 rw HS3 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V HS2VDSTH 5:3 rw HS2 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V HS1VDSTH 2:0 rw HS1 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V

Datasheet 149 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Table 50 Reset of HS_VDS Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0100 1001 B Restart 00xx 000x xxxx xxxx B

Datasheet 150 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface CCP and times selection CCP_BLK CCP and times selection (001 0100 B) Reset Value: see Table 51 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 TBLANK TCCP RES CCP_BNK rw rw r rw Field Bits Type Description TBLANK 15:12 rw Blank time nom. tHBxBLANK = 587 ns + 266 x T[3:0]D The CCP_BNK bits select the blank time for the FW or active MOSFET and the half-bridge HBx Reset of active and FW tHBxBLANK: 2450 ns typ. TCCP 11:8 rw Cross-current protection time nom. tHBxCCP = 587 ns + 266 x TCCP[3:0]D The CCP_BNK bits select the cross-current protection time for the FW or active MOSFET and the half-bridge HBx Reset of all active and FW tHBxCCP: 2450 ns typ. RES 7:3 r Reserved, always reads as 0 CCP_BNK 2:0 rw Cross-current and time banking 000B ACT_HB1, Active blank and cross-current prot. times for HB1 (default) 001B ACT_HB2, Active blank and cross-current prot. times for HB2 010B ACT_HB3, Active blank and cross-current prot. times for HB3 011B RES, reserved 100B FW_HB1, FW blank and cross-current prot. times for HB1 101B FW_HB2, FW blank and cross-current prot. times for HB2 110B FW_HB3, FW blank and cross-current prot. for times for HB3 111B RES, reserved Table 51 Reset of CCP_BLK Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0111 0111 0000 0000 B Restart xxxx xxxx 0000 0000 B

Datasheet 151 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Half-Bridge MODE HBMODE Half-Bridge MODE (001 0101 B) Reset Value: see Table 52 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES HB3MODE AFW3 HB3_ PWM_ EN HB2MODE AFW2 HB2_ PWM_ EN HB1MODE AFW1 HB1_ PWM_ EN r r wr w r wr wr w r wr wr w r w Field Bits Type Description RES 15:12 r Reserved, always reads as 0 HB3MODE 11:10 rw Half-bridge 3 MODE selection 00B PASSIVE_OFF, LS3 and HS3 are off by passive discharge (default) 01B LS3_ON, LS3 is ON 10B HS3_ON, HS3 is ON 11B ACTIVE_OFF, LS3 and HS3 kept off by the active discharge AFW3 9r w Active freewheeling for half-bridge 3 during PWM 0B DISABLED, active freewheeling disabled 1B ENABLED, active freewheeling enabled (default) HB3_PWM_EN 8r w PWM mode for half-bridge 3 0B INACTIVE, PWM deactivated for HB2(default) 1B ACTIVE, PWM activated for HB2 HB2MODE 7:6 rw Half-bridge 2 MODE selection 00B PASSIVE_OFF, LS2 and HS2 are off by passive discharge (default) 01B LS2_ON, LS2 is ON 10B HS2_ON, HS2 is ON 11B ACTIVE_OFF, LS2 and HS2 kept off by the active discharge AFW2 5r w Active freewheeling for half-bridge 2 during PWM 0B DISABLED, active freewheeling disabled 1B ENABLED, active freewheeling enabled (default) HB2_PWM_EN 4r w PWM mode for half-bridge 2 0B INACTIVE, PWM deactivated for HB2(default) 1B ACTIVE, PWM activated for HB2 HB1MODE 3:2 rw Half-bridge 1 MODE selection 00B PASSIVE_OFF, LS1 and HS1 are off by passive discharge (default) 01B LS1_ON, LS1 is ON 10B HS1_ON, HS1 is ON 11B ACTIVE_OFF, LS1 and HS1 kept off by the active discharge

Datasheet 152 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface AFW1 1r w Active freewheeling for half-bridge 1 during PWM 0B DISABLED, active freewheeling disabled 1B ENABLED, active freewheeling enabled (default) HB1_PWM_EN 0r w PWM mode for half-bridge 1 0B INACTIVE, PWM deactivated for HB1 (default) 1B ACTIVE, PWM activated for HB1 Table 52 Reset of HBMODE Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0010 0010 0010 B Restart 0000 0010 0010 0010 B Field Bits Type Description

Datasheet 153 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HB pre-charge and pre-discharge time TPRECHG HB pre-charge and pre-discharge time (001 0110 B) Reset Value: see Table 53 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TPCHG3 TPCHG2 TPCHG1 RES TPCHG_BNK rr w r w r w r r w Field Bits Type Description RES 15:13 r Reserved, always reads as 0 TPCHG3 12:10 rw If TPCHG_BNK=0: precharge time of HB 3, If TPCHG_BNK=1: predischarge time of HB 3 TPCHG2 9:7 rw If TPCHG_BNK=0: precharge time of HB 2, If TPCHG_BNK=1: predischarge time of HB 2 TPCHG1 6:4 rw If TPCHG_BNK=0: precharge time of HB 1, If TPCHG_BNK=1: predischarge time of HB 1 RES 3r Reserved, always read as 0 TPCHG_BNK 2:0 rw Precharge/predischarge time selection 000B PRECHARGE, Precharge time selected (default) 001B PREDISCHARGE, Predischarge time selected x1xB , wrong setting of TPCHG_BNK 1xxB , wrong setting of TPCHG_BNK Table 53 Reset of TPRECHG Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 000x xxxx xxxx 0000 B

Datasheet 154 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Static charge/discharge current ST_ICHG Static charge/discharge current (001 0111 B) Reset Value: see Table 54 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES ICHGST3 ICHGST2 ICHGST1 r r wr wr w Field Bits Type Description RES 15:12 r Reserved, always read as 0 ICHGST3 11:8 rw Static charge and discharge currents of HB3 Refer to Table 17 Default: 0100B - charge: ICHG16,15.3 mA typ., discharge: IDCHG16, 15.1 mA typ. ICHGST2 7:4 rw Static charge and discharge currents of HB2 Refer to Default: 0100 B - charge: ICHG16,15.3 mA typ., discharge: IDCHG16, 15.1 mA typ. ICHGST1 3:0 rw Static charge and discharge currents of HB1 Refer to Table 17 Default: 0100B - charge: ICHG16,15.3 mA typ., discharge: IDCHG16, 15.1 mA typ. Table 54 Reset of ST_ICHG Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0100 0100 0100 B Restart 0000 xxxx xxxx xxxx B

Datasheet 155 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HB charge/discharge currents for PWM operation HB_ICHG HB charge/discharge currents for PWM operation (001 1000B) Reset Value: see Table 55 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 IDCHG ICHG RES ICHG_BNK rw rw r rw Field Bits Type Description IDCHG 15:10 rw If ICHG_BNK =0xxB: Discharge current of HBx active MOSFET If ICHG_BNK=1xx B: Reserved. Always read as ‘0’ Default value for all active MOSFETs discharge currents: 001111B, IDCHG15 Refer to Table 25 for the configuration of the discharge current ICHG 9:4 rw If ICHG_BNK=0xxB: Charge current of HBx active MOSFET If ICHG_BNK=1xxB: Charge and discharge current of HBx FW MOSFETs Default value for all active MOSFETs charge currents and all FW MOSFETs charge/discharge currents: 001101B, ICHG13 Refer to Table 24 for the configuration of the charge current of the active and FW MOSFET Refer to Table 25 for the configuration of the discharge current of the FW MOSFET RES 3r Reserved, always read as 0 ICHG_BNK 2:0 rw Banking bits for charge and discharge currents of active MOSFETs 000 B ACT_HB1, Active MOSFET of HB1 is selected (default) 001B ACT_HB2, Active MOSFET of HB2 is selected 010B ACT_HB3, Active MOSFET of HB3 is selected 011B RES, reserved 100B FW_HB1, FW MOSFET of HB1 is selected 101B FW_HB2, FW MOSFET of HB2 is selected 110B FW_HB3, FW MOSFET of HB3 is selected 111B RES, reserved Table 55 Reset of HB_ICHG Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0011 1100 1101 0000 B POR value valid for ICHG_BNK = 0 Restart xxxx xxxx xxxx 0000 B

Datasheet 156 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down HB_ICHG_MAX HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down (001 1001B) Reset Value: see Table 56 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES HB3ID IAG HB2ID IAG HB1ID IAG RES RES ICHGMAX3 ICHGMAX2 ICHGMAX1 r rrw rw rw r r rw rw rw Field Bits Type Description RES 15 r Reserved, always read as 0 HB3IDIAG 14 rrw Control of HB3 off-state current source and current sink 0B INACTIVE, Pull-down deactivated (default) 1B ACTIVE, Pull-down activated HB2IDIAG 13 rw Control of HB2 pull-down for off-state diagnostic 0B INACTIVE, Pull-down deactivated (default) 1B ACTIVE, Pull-down activated HB1IDIAG 12 rw Control of HB1 pull-down for off-state diagnostic 0B INACTIVE, Pull-down deactivated (default) 1B ACTIVE, Pull-down activated RES 11:8 r Reserved, always read as 0 RES 7:6 r Reserved, always reads as 0 ICHGMAX3 5:4 rw Maximum drive current of HB3 during the pre- charge and pre-discharge phases1) 00B 31mA, charge ICHG24: typ. 31.6 mA, discharge IDCHG24: typ. 30.9 mA (default) 01B 52mA, charge ICHG32: typ. 52.5 mA, discharge IDCHG32: typ. 51.5 mA 10B 112mA, charge ICHG52: typ. 112.2mA, discharge IDCHG52: typ. 110.8 mA 11B 150mA, charge ICHG63: typ. 150 mA, discharge IDCHG63: typ. 150 mA ICHGMAX2 3:2 rw Maximum drive current of HB2 during the pre- charge phase and pre-discharge phases1) 00B 31mA, charge ICHG24: typ. 31.6 mA, discharge IDCHG24: typ. 30.9 mA (default) 01B 52mA, charge ICHG32: typ. 52.5 mA, discharge IDCHG32: typ. 51.5 mA 10B 112mA, charge ICHG52: typ. 112.2mA, discharge IDCHG52: typ. 110.8 mA 11B 150mA, charge ICHG63: typ. 150 mA, discharge IDCHG63: typ. 150 mA

Datasheet 157 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface ICHGMAX1 1:0 rw Maximum drive current of HB1 during the pre- charge and pre-discharge phases1) 00B 31mA, charge ICHG24: typ. 31.6 mA, discharge IDCHG24: typ. 30.9 mA (default) 01B 52mA, charge ICHG32: typ. 52.5 mA, discharge IDCHG32: typ. 51.5 mA 10B 112mA, charge ICHG52: typ. 112.2mA, discharge IDCHG52: typ. 110.8 mA 11B 150mA, charge ICHG63: typ. 150 mA, discharge IDCHG63: typ. 150 mA 1) ICHGMAX is also the current applied du ring the post-charge of the PWM MOSFET. Table 56 Reset of HB_ICHG_MAX Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0xxx 0000 00xx xxxx B Field Bits Type Description

Datasheet 158 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HBx pre-charge/pre-dischage initialization configuration in PWM operation HB_PCHG_INIT HBx pre-charge/pre-discharge initialization configuration in PWM operation (001 1010B) Reset Value: see Table 57 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 PDCHGINIT PCHGINIT RES INIT_BNK rw rw r rw Field Bits Type Description PDCHGINIT 15:10 rw Initial predischarge current of HBx, IPDCHGINITx The INIT_BNK bits select the addressed half-bridge Default: 001111 B Refer to Table 24 PCHGINIT 9:4 rw Initial precharge current of HBx, IPCHGINITx The INIT_BNK bits select the addressed half-bridge Default: 001101B Refer to Table 24 RES 3r Reserved, always reads as 0 INIT_BNK 2:0 rw Banking bits for Precharge an Predischarge Initial Current 000 B HB1, precharge/discharge init. for HB1 selected (default) 001B HB2, precharge/discharge init. for HB2 selected 010B HB3, precharge/discharge init. for HB3 selected 010B RES, reserved 011B RES, reserved 1xxB , wrong setting of INIT_BANK Table 57 Reset of HB_PCHG_INIT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0011 1100 1101 0000 B Restart xxxx xxxx xxxx 0000 B

Datasheet 159 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HBx inputs TDON configuration TDON_HB_CTRL HBx inputs TDON configuration (001 1011 B) Reset Value: see Table 58 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TDON RES HB_TDON_BNK rr w rr w Field Bits Type Description RES 15:14 r Reserved, always read as 0 TDON 13:8 rw Turn-on delay time of active MOSFET of HBx The HB_TDON_BNK bits selects the turn-on delay time of the active MOSFET of the half-bridge HBx Nominal tDON = 53.3 ns x TDON[5:0]D Default: 00 1100B : 640 ns typ. RES 7:3 r Reserved, always read as 0 HB_TDON_BNK 2:0 rw Banking bits for turn-on delay time 000B HB1, tDON of HB1 selected (default) 001B HB2, tDON of HB2 selected 010B HB3, tDON of HB3 selected 011B RES, reserved 1xxB , wrong setting of PWM_TDON_BNK Table 58 Reset of TDON_HB_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 1100 0000 0000 B Restart 00xx xxxx 0000 0000 B

Datasheet 160 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HBx TDOFF configuration TDOFF_HB_CTRL HBx TDOFF configuration (001 1100 B) Reset Value: see Table 59 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TDOFF RES HB_TDOFF_BNK rr w rr w Field Bits Type Description RES 15:14 r Reserved, always read as 0 TDOFF 13:8 rw Turn-off delay time of active MOSFET of HBx The HB_TDOFF_BNK bits selects the turn-off delay time of the active MOSFET of the half-bridge HBx Nominal tDOFF = 53.3 ns x TDOFF[5:0]D Default: 0000 1100B : 640 ns RES 7:3 r Reserved, always read as 0 HB_TDOFF_BNK 2:0 rw Banking bits for turn-off delay time 000B HB1, tDOFF of HB1 selected (default) 001B HB2, tDOFF of HB2 selected 010B HB3, tDOFF of HB3 selected 1xxB , wrong setting of PWM_TDOFF_BNK Table 59 Reset of TDOFF_HB_CTRL Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 1100 0000 0000 B Restart 00xx xxxx 0000 0000 B

Datasheet 161 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Brake control BRAKE Brake control (001 1101 B) Reset Value: see Table 60 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES SLAM _LS3_ DIS SLAM _LS2_ DIS SLAM _LS1_ DIS SLAM VDST H_BR K TBLK_ BRK PARK_ BRK_E N OV_B RK_E N RES OV_BRK_TH r r rw rw rw rw rw rw rw rw rw rw Field Bits Type Description RES 15:14 r Reserved, always read as 0 RES 13 r Reserved, always read as 0 SLAM_LS3_DIS 12 rw LS3 output disable during SLAM mode 0B ACTIVE, LS3 control active in Slam mode (default) 1B DISABLED, LS3 control disabled in Slam mode SLAM_LS2_DIS 11 rw LS2 output disable during SLAM mode 0B ACTIVE, LS2 control active in Slam mode (default) 1B DISABLED, LS2 control disabled in Slam mode SLAM_LS1_DIS 10 rw LS1 output disable during SLAM mode 0B ACTIVE, LS1 control active in Slam mode (default) 1B DISABLED, LS1 control disabled in Slam mode SLAM 9r w Slam mode 0B INACTIVE, Slam mode deactivated (default) 1B AVTIVE, Slam mode activated VDSTH_BRK 8r w VDS Overvoltage for LS1-3 during braking 0B 800mV, VVDSMONTH0_BRAKE, 0.8 V, typ. (default) 1B 220mV, VVDSMONTH1_BRAKE, 0.22 V typ. TBLK_BRK 7r w Blank time of VDS overvoltage during braking 0B 7uS, tBLK_BRAKE1,7 µs typ. 1B 11uS, tBLK_BRAKE2, 11 µs typ. (default) PARK_BRK_EN 6r w Parking brake enable 0B DISABLED, Parking brake disabled (default) 1B ENABLED, Parking brake enabled OV_BRK_EN 5r w Overvoltage brake enable 0B DISABLED, Overvoltage brake disabled 1B ENABLED, Overvoltage brake enabled (default) RES 4:3 rw Reserved, to be set to 0

Datasheet 162 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Note: For min and max values of OV_BRK_TH, refer to Chapter 10.11. OV_BRK_TH 2:0 rw Overvoltage brake threshold 000B 27V, typ. 27V (default) 001B 28V, typ. 28V 010B 29V, typ. 29V 011B 30V, typ. 30V 100B 31V, typ. 31V 101B 32V, typ. 32V 110B 33V, typ. 33V 111B 34V, typ. 34V Table 60 Reset of BRAKE Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 1010 0000 B Restart 000x xxxx xxx0 0xxx B Field Bits Type Description

Datasheet 163 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.6 SPI status information registers

READ/CLEAR Operation (see also Chapter 11.3):

• One 32-bit SPI command consist of four bytes: - The 7-bit address and one additional bit for the register access mode and - following the two data bytes and the CRC. The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the SPI bits 8...23 (see also figure).
• There are two different bit types: - ‘r’ = READ: read only bits (or reserved bits). - ‘rc’ = READ/CLEAR: readable and clearable bits.
• Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only).
• Clearing a register is done word wise by setting the SPI bit 7 to “1”. No single bits can be cleared. Therefore the content of a SPI message (bit 8..23) doesn’t matter.
• SPI status registers are in general not cleared or changed automatically (an exception are the x bits). This must be done by the microcontroller via SPI command. The registers are addressed wordwise. Table 61 Register Overview Register Short Name Register Long Name Offset Address Page Number SPI status information registers, Device Status Registers SUP_STAT Supply Voltage Fail Status 1000000 B 164 THERM_STAT Thermal Protection Status 1000001 B 166 DEV_STAT Device Information Status 1000010 B 167 WK_STAT Wake-up Source and Information Status 1000100 B 169 WK_LVL_STAT WK Input Level 1000101 B 170 SPI status information registers, Status registers bridge driver GEN_STAT GEN Status register 1010000 B 171 TDREG Turn-on/off delay regulation register 1010001 B 173 DSOV Drain-source overvoltage HBVOUT 1010010 B 175 EFF_TDON_OFF1 Effective MOSFET turn-on/off delay - PWM half- bridge 1 1010011B 177 EFF_TDON_OFF2 Effective MOSFET turn-on/off delay - PWM half- bridge 2 1010100B 178 EFF_TDON_OFF3 Effective MOSFET turn-on/off delay - PWM half- bridge 3 1010101B 179 TRISE_FALL1 MOSFET rise/fall time - PWM half-bridge 1 1010111 B 180 TRISE_FALL2 MOSFET rise/fall time - PWM half-bridge 2 1011000 B 181 TRISE_FALL3 MOSFET rise/fall time - PWM half-bridge 3 1011001 B 182 SPI status information registers, Family and product information register FAM_PROD_STAT Family and Product Identification Register 1110000 B 183

Datasheet 164 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.6.1 Device Status Registers

Supply Voltage Fail Status SUP_STAT Supply Voltage Fail Status (100 0000 B) Reset Value: see Table 62 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 POR RES CP_O T VCC1_ UV_FS RES VSINT _UV VSINT _OV VS_UV VS_OV CP_UV VCC1_ SC VCC1_ UV VCC1_ OV VCC1_ WARN r c r r cr c r c r cr cr cr cr cr cr cr cr c Field Bits Type Description POR 15 rc Power-On reset detection 0B NO_POR, No POR 1B POR, POR occurred RES 14:13 r Reserved, always reads as 0 CP_OT 12 rc Charge pump overtemperature 0B NO_CP_OT, No charge pump OT detected 1B CP_OT, Charge pump OT detected VCC1_UV_FS 11 rc 4th consecutive VCC1 UV-Detection 0B NO_FAILSAFE, No Fail-Safe Mode entry due to 4th consecutive VCC1_UV 1B FAILSAFE, Fail-Safe Mode entry due to 4th consecutive VCC1_UV RES 10:9 rc Reserved VSINT_UV 8r c VSINT UV-Detection 0B NO_UV, No Undervoltage 1B UV_EVENT, VSINT Undervoltage detected VSINT_OV 7r c VSINT OV-Detection 0B NO_OV, No Overvoltage 1B OV_EVENT, VSINT Overvoltage detected VS_UV 6r c VS Undervoltage Detection (VS,UV) 0B NO_VS, No VS undervoltage detected 1B VS_EVENT, VS undervoltage detected (detection is only active when VCC1 is enabled) VS_OV 5r c VS Overvoltage Detection (VS,OV) 0B NO_OV, No VS overvoltage detected 1B OV_EVENT, VS overvoltage detected (detection is only active when VCC1 is enabled) CP_UV 4r c CP_UV 0B NO_UV, No CP undervoltage detected 1B UV_EVENT, CP undervoltage detected VCC1_SC 3r c VCC1 SC 0B NO_SC, No VCC1 short to GND detected 1B SC_EVENT, VCC1 short to GND

Datasheet 165 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Notes 1. The VCC1 undervoltage prewarning threshold V PW,f / VPW,r is a fixed threshold and independent of the VCC1 undervoltage reset thresholds. 2. VSINT undervoltage monitoring is not available in Stop Mode due to current consumption saving requirements. Exception: VSINT undervoltage detection is also available in Stop Mode if the VCC1 load current is above the active peak threshold (I_PEAK_TH) or if VCC1 is below the VCC1 prewarning threshold (VCC1_WARN is set). 3. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on reset (POR value = 1000 0000). However it will be cleared after a device Soft Reset command (Soft Reset value = 0000 0000). 4. During Sleep Mode, the bits V CC1_SC, VCC1_OV and VCC1_UV will not be set when VCC1 is off. 5. The VCC1_UV bit is never updated in Re start Mode, in Init Mode it is only updated after RSTN was released, it is always updated in Normal Mode and Stop Mode, and it is always updated in any device modes in a VCC1_SC condition (after VCC1_UV = 1 for > 2 ms). VCC1_UV 2r c VCC1 UV-Detection (due to Vrtx reset) 0B NO_UV, No VCC1_UV detection 1B UV_EVENT, VCC1 undervoltage detected VCC1_OV 1r c VCC1 Overvoltage Detection 0B NO_OV, No VCC1 overvoltage warning 1B OV_EVENT, VCC1 overvoltage detected VCC1_WARN 0r c VCC1 Undervoltage Prewarning 0B NO_UV, No VCC1 undervoltage prewarning 1B UV_PREWARN, VCC1 undervoltage prewarning detected Table 62 Reset of SUP_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset y000 0000 0000 0000 B Restart x00x xxxx xxxx xxxx B Field Bits Type Description

Datasheet 166 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Thermal Protection Status Note: Temperature warning and shutdown bits are not reset automatically, even if the temperature pre warning or the TSD condition is not present anymore. THERM_STAT Thermal Protection Status (100 0001 B) Reset Value: see Table 63 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TSD2_ SAFE TSD2 TSD1 TPW r r cr cr cr c Field Bits Type Description RES 15:4 r Reserved, always reads as 0 TSD2_SAFE 3r c TSD2 Thermal Shut-Down Safe State Detection 0B NO_TSD2_SF, No TSD2 safe state detected 1B TSD2_SF, TSD2 safe state detected: >16 consecutive TSD2 events occurred, next TSD2 waiting time will be 64s TSD2 2r c TSD2 Thermal Shut-Down Detection B NO_TSD2, No TSD2 event 1B TSD2_EVENT, TSD2 OT detected - leading to Fail- Safe Mode TSD1 1r c TSD1 Thermal Shut-Down Detection 0B NO_TSD1, No TSD1 fail 1B TSD1_EVENT, TSD1 OT detected (affected module is disabled) TPW 0r c Thermal Pre Warning 0B NO_TPW, No Thermal Pre warning 1B TPW, Thermal Pre warning detected Table 63 Reset of THERM_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 0000 0000 xxxx B

Datasheet 167 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Device Information Status DEV_STAT Device Information Status (100 0010 B) Reset Value: see Table 64 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES CRC_S TAT CRC_F AIL DEV_STAT RES SW_D EV WD_FAIL SPI_F AIL FAILU RE r r rc rc r rh rh rc rc Field Bits Type Description RES 15:10 r Reserved, always read as 0 CRC_STAT 9r CRC STAT Information 0B DISABLED, CRC disabled 1B ENABLED, CRC enabled CRC_FAIL 8r c CRC Fail Information1) 0B NO_FAIL, No CRC Failure 1B FAIL, CRC Failure detected 1) The CRC_FAIL bit will not be set in case the stat ic CRC enabling / disabling sequence is sent (see Chapter 5.2). DEV_STAT 7:6 rc Device Status before Restart Mode 00B CLEARED, Cleared (Register must be actively cleared) 01B RESTART, Restart due to failure (WD fail, TSD2, VCC1_UV, trial to access Sleep Mode without any wake source activated); also after a wake from Fail-Safe Mode B SLEEP, Sleep Mode 11B , reserved RES 5r Reserved, always reads 0 SW_DEV 4r h Status of Operating Mode 0B NORMAL, Normal operation 1B SW_DEV, Software Development Mode is enabled WD_FAIL 3:2 rh Number of WD-Failure Events 00B NO_FAIL, No WD Fail 01B 1x, 1x WD Fail, 10B 2x, 2x WD Fail 11B 3x, more than 3xWD Fail SPI_FAIL 1r c SPI Fail Information 0B NO_FAIL, No SPI fail 1B INVALID, Invalid SPI command detected FAILURE 0r c Failure detection 0B NO_FAIL, No Failure 1B FAIL, Failure occured

Datasheet 168 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Notes 1. The bits DEV_STAT show the status of the device before exiting Restart Mode. Either the device came from regular Sleep Mode or a failure (Restart Mode or Fail-Safe Mode) occurred. Coming from Sleep Mode will also be shown if there was a trial to enter Sleep Mode without having cleared all wake flags before. 2. The WD_FAIL bits are implemented as a counter and are the only status bits, which are cleared automatically by the device. 3. The SPI_FAIL bit can only be cleared via SPI command. 4. The bit CRC_STAT and CRC_FAIL can be read regardless the CRC setting. The SPI read command on DEV_STAT ignores the CRC field. Table 64 Reset of DEV_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 00xx xx0x xxxx B

Datasheet 169 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Wake-up Source and Information Status Note: At Fail-Safe Mode entry, the WK_STAT register is automatically cleared by the device. WK_STAT Wake-up Source and Information Status (100 0100 B) Reset Value: see Table 65 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES RES TIMER 2_WU TIMER 1_WU RES RES WK4_ WU RES RES RES rr r r c r c r r r c r r r Field Bits Type Description RES 15:11 r Reserved, always reads as 0 RES 10 r Reserved, always reads as 0 RES 9r Reserved, always reads as 0 TIMER2_WU 8r c Wake up via Timer2 0B NO_WU, No Wake up 1B WU, Wake up detected TIMER1_WU 7r c Wake up via Timer1 0B NO_WU, No Wake up 1B WU, Wake up detected RES 6:5 r Reserved, always reads as 0 RES 4r Reserved, always reads as 0 WK4_WU 3r c Wake up via WK4 0B NO_WU, No Wake up 1B WU, Wake up detected RES 2r Reserved, always reads as 0 RES 1r Reserved, always reads as 0 RES 0r Reserved, always reads as 0 Table 65 Reset of WK_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 0xxx x000 00x0 B

Datasheet 170 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface WK Input Level Note: WK_LVL_STAT is updated in Normal Mode and Stop Mode and also in Init and Restart Mode. In cyclic wake mode, the registers contain the sampled level, i.e. the registers are updated after every sampling. WK_LVL_STAT WK Input Level (100 0101 B) Reset Value: see Table 66 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES WK4_ LVL RES RES RES r rrrrr Field Bits Type Description RES 15:5 r Reserved, always reads as 0 RES 4r Reserved, always reads as 0 WK4_LVL 3r Status of WK4 0B LOW, Low Level (=0) 1B HIGH, High Level (=1) RES 2r Reserved, always reads as 0 RES 1r Reserved, always reads as 0 RES 0r Reserved, always reads as 0 Table 66 Reset of WK_LVL_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 00x0 B Restart 0000 0000 0000 00x0 B

Datasheet 171 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.6.2 Status registers bridge driver

GEN_STAT General Status register (101 0000 B) Reset Value: see Table 67 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES HB3V OUT HB2V OUT HB1V OUT PWM6 STAT PWM5 STAT PWM4 STAT PWM3 STAT PWM2 STAT PWM1 STAT r rrrrrrrrrr Field Bits Type Description RES 15:10 r Reserved, always reads as 0 RES 9r Reserved, always reads as 0 HB3VOUT 8r Voltage level at VSH3 when HB3MODE[1:0] = 11 and CPEN=11) 0B LOW, VSH3 = Low : VS - VSH3 > VHS3VDSTHx 1B HIGH, VSH3 = High: VS - VSH3 ≤ VHS3VDSTHx HB2VOUT 7r Voltage level at VSH2 when HB2MODE[1:0] = 11 and CPEN=11) 0B LOW, VSH2 = Low : VS - VSH2 > VHS2VDSTHx 1B HIGH, VSH2 = High: VS - VSH2 ≤ VHS2VDSTHx HB1VOUT 6r Voltage level at VSH1 when HB1MODE[1:0] = 11 and CPEN=11) 0B LOW, VSH1 = Low : VS - VSH1 > VHS1VDSTHx 1B HIGH, VSH1 = High: VS - VSH1 ≤ VHS1VDSTHx 1) HBxVOUT = 0 if ( CPEN=1 and HBxMODE ≠ 11) or CPEN=0. PWM6STAT 5r PWM6 status 0B LOW, PWM6 is Low 1B HIGH, PWM6 is High PWM5STAT 4r PWM5 status 0B LOW, PWM5 is Low 1B HIGH, PWM5 is High PWM4STAT 3r PWM4 Status 0B LOW, PWM4 is Low 1B HIGH, PWM4 is High PWM3STAT 2r PWM3 status 0B LOW, PWM3 is Low 1B HIGH, PWM3 is High PWM2STAT 1r PWM2 Status 0B LOW, PWM2 is Low 1B HIGH, PWM2 is High PWM1STAT 0r PWM1/CRC status 0B LOW, PWM1/CRC is Low 1B HIGH, PWM1/CRC is High

Datasheet 172 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Table 67 Reset of GEN_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 0000 xx00 000x B

Datasheet 173 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Turn-on/off delay regulation register TDREG Turn-on/off delay regulation register (101 0001 B) Reset Value: see Table 68 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES RES IPDCH G3_ST IPDCH G2_ST IPDCH G1_ST RES IPCHG 3_ST IPCHG 2_ST IPCHG 1_ST RES TDRE TDRE TDRE r rrrrrrrrrrrr Field Bits Type Description RES 15:12 r Reserved, always reads as 0 RES 11 r Reserved, always reads as 0 IPDCHG3_ST 10 r HB3 predischarge status 0B CLAMP, the predischarge current is equal to 0.5 mA typ. or ICHGMAX3 if AGC[1:0] = 10B or 11B, and HB3_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < predischarge current < ICHGMAX31) IPDCHG2_ST 9r HB2 predischarge status 0B CLAMP, the predischarge current is equal to 0.5 mA typ. or ICHGMAX2 if AGC[1:0] = 10B or 11B, and HB2_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < predischarge current < ICHGMAX21) IPDCHG1_ST 8r HB1 predischarge status 0B CLAMP, the predischarge current is equal to the 0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10B or 11B, and HBx_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < predischarge current < ICHGMAX11) RES 7r Reserved, always reads as 0 IPCHG3_ST 6r HB3 precharge status 0B CLAMP, the precharge current is equal to 0.5 mA typ. or ICHGMAX3 if AGC[1:0] = 10B or 11B, and HB3_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < precharge current < ICHGMAX31) IPCHG2_ST 5r HB2 precharge status 0B CLAMP, the precharge current is equal to 0.5 mA typ. or ICHGMAX2 if AGC[1:0] = 10B or 11B, and HB2_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < precharge current < ICHGMAX21)

Datasheet 174 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface IPCHG1_ST 4r HB1 precharge status 0B CLAMP, the precharge current is equal to the 0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10B or 11B, and HB1_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < precharge current < ICHGMAX11) RES 3r Reserved, always reads as 0 TDREG3 2r HB3 Regulation of turn-on/off delay 0B NO_REG, tDON3 and tDOFF3 are not in regulation 1B REG, tDON3 and/or tDOFF3 are in regulation TDREG2 1r HB2 Regulation of turn-on/off delay 0B NO_REG, tDON2 and tDOFF2 are not in regulation 1B REG, tDON2 and/or tDOFF2 are in regulation TDREG1 0r HB1 Regulation of turn-on/off delay 0B NO_REG, tDON and tDOFF are not in regulation 1B REG, tDON and/or tDOFF are in regulation 1) IPCHGx_ST = 1 otherwise (PWM disabled, HB in high impedance or AGC[1:0] = 00B or 01B ). Table 68 Reset of TDREG Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0000 0000 xx00 000x B Field Bits Type Description

Datasheet 175 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Drain-source overvoltage status DSOV Drain-source overvoltage (101 0010 B) Reset Value: see Table 69 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES OC_C SA VSINT OVBR AKE_S T VSOV BRAK E_ST RES LS3DS OV_B RK LS2DS OV_B RK LS1DS OV_B RK RES RES LS3DS OV HS3D SOV LS2DS OV HS2D SOV LS1DS OV HS1D SOV r rc rc rc r rc rc rc r r rc rc rc rc rc rc Field Bits Type Description RES 15 r Reserved, always reads as 0 OC_CSA 14 rc CSA Overcurrent detection 0B NO_OC, No overcurrent detected 1B OC, Overcurrent detected VSINTOVBRAKE_ST 13 rc VSINT Brake status 0B NOT_DETECT, VSINT overvoltage brake condition is not detected 1B DETECT, VSINT overvoltage brake conditions is detected VSOVBRAKE_ST 12 rc VS Brake status 0B NOT_DETECT, VS overvoltage brake conditions is not detected 1B DETECT, VS overvoltage brake conditions is detected RES 11 r Reserved, always reads as 0 LS3DSOV_BRK 10 rc Drain-source overvoltage on low-side 3 during braking 0B NO_OV, No drain-source overvoltage on LS3 1B OV, Drain-source overvoltage on LS3 LS2DSOV_BRK 9r c Drain-source overvoltage on low-side 2 during braking B NO_OV, No drain-source overvoltage on LS2 1B OV, Drain-source overvoltage on LS2 LS1DSOV_BRK 8r c Drain-source overvoltage on low-side 1 during braking 0B NO_OV, No drain-source overvoltage on LS1 1B OV, Drain-source overvoltage on LS1 RES 7r Reserved, always reads as 0 RES 6r Reserved, always reads as 0 LS3DSOV 5r c Drain-source overvoltage on low-side 3 0B NO_OV, No drain-source overvoltage on LS3 1B OV, Drain-source overvoltage on LS3

Datasheet 176 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface HS3DSOV 4r c Drain-source overvoltage on high-side 3 0B NO_OV, No drain-source overvoltage on HS3 1B OV, Drain-source overvoltage on HS3 LS2DSOV 3r c Drain-source overvoltage on low-side 2 0B NO_OV, No drain-source overvoltage on LS2 1B OV, Drain-source overvoltage on LS2 HS2DSOV 2r c Drain-source overvoltage on high-side 2 0B NO_OV, No drain-source overvoltage on HS2 1B OV, Drain-source overvoltage on HS2 LS1DSOV 1r c Drain-source overvoltage on low-side 1 0B NO_OV, No drain-source overvoltage on LS1 1B OV, Drain-source overvoltage on LS1 HS1DSOV 0r c Drain-source overvoltage on high-side 1 0B NO_OV, No drain-source overvoltage on HS1 1B OV, Drain-source overvoltage on HS1 Table 69 Reset of DSOV Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 0xxx 0xxx 00xx xxxx B Field Bits Type Description

Datasheet 177 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Effective MOSFET turn.on/off delay - PWM half-bridge 1 EFF_TDON_OFF1 Effective MOSFET turn.on/off delay - HB1 (101 0011 B) Reset Value: see Table 70 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TDOFF1EFF RES TDON1EFF rrrr Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TDOFF1EFF 13:8 r Effective active MOSFET turn-off delay HB1 Nominal effective tDOFF1 = 53.3 ns x TDOFF1EFF[13:8]D RES 7:6 r Reserved, always reads as 0 TDON1EFF 5:0 r Effective active MOSFET turn-on delay HB1 Nominal effective tDON1 = 53.3 ns x TDON1EFF[5:0]D Table 70 Reset of EFF_TDON_OFF1 Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 00xx xxxx 00xx xxxx B

Datasheet 178 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Effective MOSFET turn.on/off delay - PWM half-bridge 2 EFF_TDON_OFF2 Effective MOSFET turn.on/off delay - HB 2 (101 0100 B) Reset Value: see Table 71 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TDOFF2EFF RES TDON2EFF rrrr Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TDOFF2EFF 13:8 r Effective active MOSFET turn-off delay HB2 Nominal effective tDOFF2 = 53.3 ns x TDOFF2EFF[13:8]D RES 7:6 r Reserved, always reads as 0 TDON2EFF 5:0 r Effective active MOSFET turn-on delay HB2 Nominal effective tDON2 = 53.3 ns x TDON2EFF[5:0]D Table 71 Reset of EFF_TDON_OFF2 Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 00xx xxxx 00xx xxxx B

Datasheet 179 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Effective MOSFET turn.on/off delay - PWM half-bridge 3 EFF_TDON_OFF3 Effective MOSFET turn.on/off delay - HB3 (101 0101 B) Reset Value: see Table 72 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TDOFF3EFF RES TDON3EFF rrrr Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TDOFF3EFF 13:8 r Effective active MOSFET turn-off delay HB3 Nominal effective tDOFF3 = 53.3 ns x TDO3EFF[13:8]D RES 7:6 r Reserved, always reads as 0 TDON3EFF 5:0 r Effective active MOSFET turn-on delay HB3 Nominal effective tDON3 = 53.3 ns x TDON3EFF[5:0]D Table 72 Reset of EFF_TDON_OFF3 Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 00xx xxxx 00xx xxxx B

Datasheet 180 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface MOSFET rise/fall time - PWM half-bridge 1 TRISE_FALL1 MOSFET rise/fall time - HB1 (101 0111 B) Reset Value: see Table 73 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TFALL1 RES TRISE1 rrrr Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TFALL1 13:8 r Active MOSFET fall time HB1 Nominal tFALL1 = 53.3 ns x TFALL1[5:0]D RES 7:6 r Reserved, always reads as 0 TRISE1 5:0 r Active MOSFET rise time HB1 Nominal tRISE1 = 53.3 ns x TRISE1[5:0]D Table 73 Reset of TRISE_FALL1 Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 00xx xxxx 00xx xxxx B

Datasheet 181 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface MOSFET rise/fall time - PWM half-bridge 2 TRISE_FALL2 MOSFET rise/fall time - HB2 (101 1000 B) Reset Value: see Table 74 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TFALL2 RES TRISE2 rrrr Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TFALL2 13:8 r Active MOSFET fall time HB2 Nominal tFALL2 = 53.3 ns x TFALL2[5:0]D RES 7:6 r Reserved, always reads as 0 TRISE2 5:0 r Active MOSFET rise time HB2 Nominal tRISE2 = 53.3 ns x TRISE2[5:0]D Table 74 Reset of TRISE_FALL2 Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 00xx xxxx 00xx xxxx B

Datasheet 182 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface MOSFET rise/fall time - PWM half-bridge 3 TRISE_FALL3 MOSFET rise/fall time - HB3 (101 1001 B) Reset Value: see Table 75 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES TFALL3 RES TRISE3 rrrr Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TFALL3 13:8 r Active MOSFET fall time HB3 Nominal tFALL3 = 53.3 ns x TFALL3[5:0]D RES 7:6 r Reserved, always reads as 0 TRISE3 5:0 r Active MOSFET rise time HB3 Nominal tRISE3 = 53.3 ns x TRISE3[5:0]D Table 75 Reset of TRISE_FALL3 Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0000 0000 0000 B Restart 00xx xxxx 00xx xxxx B

Datasheet 183 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.6.3 Family and product information register

Family and Product Identification Register FAM_PROD_STAT Family and Product Identification Register (111 0000 B) Reset Value: see Table 76 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RES FAM PROD rr r Field Bits Type Description RES 15:11 r Reserved, always reads as 0 FAM 10:7 r Device Family Identifier 1000B, BLDC Driver PROD 6:0 r Device Product Identifier 000 0000BTLE9562-3QX/QX, TLE9562-3QX/-3QXJ/QX 000 0001BTLE9561-3QX/QX, TLE9561-3QX/-3QXJ/QX 000 0010BTLE9563-3QX, TLE9563-3QX 000 0011BTLE9564QX, TLE9564QX,TLE9185QX 001 0000BTLE9562-3QX V33, TLE9562-3QX V33 001 0010BTLE9563-3QX V33, TLE9563-3QX V33 001 0011BTLE9564QX V33, TLE9564QX V33,TLE9185QX V33 001 1000BTLE9560QX, TLE9560-3QX/-3QXJ Table 76 Reset of FAM_PROD_STAT Register Reset Type Reset Values Reset Short Name Reset Mode Note POR/Soft reset 0000 0100 0000 0011 B Restart 0000 0100 0000 0011 B

Datasheet 184 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface

11.7 Electrical Characteristics

Table 77 Electrical Characteristics: Power Stage VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SPI frequency Maximum SPI frequency fSPI,max ––6 . 0 M H z 1) VCC1 > 3 V P_14.7.1 SPI Interface; Logic Inputs SDI, CLK and CSN H-input Voltage Threshold VIH – – 0.7 × VCC1 V– P_14.7.2 L-input Voltage Threshold VIL 0.3 × VCC1 ––V – P_14.7.3 Hysteresis of input Voltage VIHY – 0.12 × VCC1 –V 1) P_14.7.4 Pull-up Resistance at pin CSN RICSN 20 40 80 k Ω – P_14.7.5 Pull-down Resistance at pin SDI and CLK RICLK/SDI 20 40 80 k Ω VSDI/CLK = 0.2 × VCC1 P_14.7.6 Input Capacitance at pin CSN, SDI or CLK CI –1 0 –p F 1) VCSN, VSDI, VCLK = VCC1 P_14.7.7 Logic Output SDO H-output Voltage Level VSDOH 0.8 × VCC1 ––V IDOH = -2 mA P_14.7.8 L-output Voltage Level VSDOL – – 0.2 × VCC1 V IDOL = 2 mA P_14.7.9 ‘Tri-state Input Capacitance CSDO – 1 01 5p F 1)VCSN, VSDI, VCLK = VCC1 P_14.7.11 Tri-state Leakage Current ISDOLK –10 – 10 µA 1)VCSN= VCC1, 0V < VSDO< VCC1 P_14.7.38 Data Input Timing1) Clock Period tpCLK 160 – – ns – P_14.7.12 Clock HIGH Time tCLKH 7 0 ––n s – P_14.7.13 Clock LOW Time tCLKL 7 0 ––n s – P_14.7.14 Clock LOW before CSN LOW tbef 7 0 ––n s – P_14.7.15 CSN Setup Time tlead 160 – – ns – P_14.7.16 CLK Setup Time tlag 160 – – ns – P_14.7.17 Clock LOW after CSN HIGH tbeh 7 0 ––n s – P_14.7.18 SDI Setup Time tDISU 6 0 ––n s – P_14.7.19 SDI Hold Time tDIHO 4 0 ––n s – P_14.7.20

Datasheet 185 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Serial Peripheral Interface Figure 61 SPI Timing Diagram Note: Numbers in drawing correlate with the last 2 digits of the Number field in the Electrical Characteristics table. Input Signal Rise Time at pin SDI, CLK and CSN trIN ––2 0 n s – P_14.7.21 Input Signal Fall Time at pin SDI, CLK and CSN tfIN ––2 0 n s – P_14.7.22 Delay Time for Mode Changes2) tDel,Mode ––5µ s 3) P_14.7.23 CSN HIGH Time tCSN(high) 3––µ s – P_14.7.24 Data Output Timing1) SDO Rise Time trSDO – 3 04 0n s CL = 50 pF, 0.2 × VCC1 to 0.8 × VCC1 P_14.7.25 SDO Fall Time tfSDO – 3 04 0n s CL = 50 pF, 0.8 × VCC1 to 0.2 × VCC1 P_14.7.26 SDO Enable Time tENSDO – – 40 ns LOW impedance P_14.7.27 SDO Disable Time tDISSDO – – 40 ns HIGH impedance P_14.7.28 SDO Valid Time tVASDO ––4 0 n s CL = 50 pF P_14.7.29 1) Not subject to production test; specified by design. 2) Applies to all mo de changes triggered via SPI commands. 3) Guaranteed by design. Table 77 Electrical Characteristics: Power Stage (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. CSN CLK SDI SDO 1413 not defined LSB MSB Flag LSB MSB 27 29 15 18

Datasheet 186 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver

Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

12.1 Application Diagrams

Figure 62 Application Diagram Note: This is a very simplified example of an application circuit. The function must be always verified in the real application. Note: Before going to sleep mode, it is highly reco mmended keep the WK4 internal pull-up and pull-down deactivated, keep WK4 to Low and enable the static wake for WK4. The 5V microcontroller wakes up the device by pulling WK4 above VWKx_th,r. TLE9185QX RSTN SDI SDO CLK CSN VBAT VS GND CP Rrev2 Cin2b Cin4 VCC1 CVCC1 GHx GLx SHx Rrev1 Drev2 Trev1 CPC1N CPC1PCCP1 CPC2PCCP2 CPC2N CCP VSINT Cin2 Cin3 Drev3 Rrev3 Trev2 Bridge x3 INTN PWM2 PWM4 Drev1 SL PWM3 PWM5 PWM6 PWM1 to other bridges RSENSE CSAP CSAN RFILT1 RFILT2 CFILT1 CFILT2 CFILT3 CSO ADC IN RCSO CCSO Microcontroller Cin1 Cin5 CHB1x CHB2x WK4 RSeries RSeries RSeries RSeries RSeries RSeries RSeries RSeries RSeries RSeries RSeries RSeries RSeries

Datasheet 187 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Ref. Typical Value Purpose / Comment Capacitances Cin1 100 nF ±20% ceramic Input filter battery capacitor for optimum EMC behavior Cin2 100 µF ±20%, 50 V Electrolytic Buffering capacitor to cut off battery spikes, depending on the application Cin2b 470 µF ±20%, 50 V Electrolytic Buffering capacitor for bridges. Cut off battery spikes, depending on the application Cin3 100 nF ±20%, 50 V Ceramic Input capacitor Cin4 100 nF ±20%, 50 V Ceramic Input capacitor Cin5 470 µF ±20%, 50 V Electrolytic Buffering capacitor for bridges. Cut off battery spikes, depending on the application CCP 470 nF ±20%, 50 V Ceramic Charge-Pump buffering capacitor CCP1/ CCP2 220 nF ±20%, 50 V Ceramic Charge-Pump flying capacitor to be placed as closed as possible to the device pins, in order to minimize the length of the PCB tracks CFILT1 1.5 nF ±20%, 16 V Ceramic Current-sense filtering CFILT2 / CFILT3 22 nF ±20%, 16 V Ceramic Current-sense filtering CCSO 16 V Ceramic CSO buffering cap for a stable ADC voltage. Max 400 pF in case no resistor is used. With 50 Ω resistor up to 2.2 nF. (See CSA configuration register) CVCC1 2.2 uF ±20%, 16 V Blocking capacitor. Low ESR. Minimum 1 uF effective capacitance CHB1x 10 nF ±20%, 50 V Ceramic Half-Bridge EME (electromagnetic emission) and ESD suppression filter to be placed close to the connector. Other capacitance values might be needed depending on application CHB2x 560 pF ±20%, 50 V Ceramic Optional filter for EMI immunity to be placed close to the SHx pin (PCB footprints highly recommended). Other capacitance values might be needed depending on application CWK1 / CWK2 47 nF / OEM dependent Spike filtering, as requ ired by application, mandatory protection for off-board connections Inductances L1 4 uH ... 6 uH Input filter for power stage - consider high current rating (application dependent)

Datasheet 188 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver RREV1 100 kΩ ±5% Other values needed depending on application RREV2 10 kΩ ±5% Device protection against reverse battery RREV3 10 kΩ ±5% RSENSE 5m Ω ±1% Current-sense resistor RFILT1 / RFILT2 4.7 Ω ±5% Current-sense filtering RCSO 50 Ω ±5% Compensation for internal opamp.Depending on SPI configuration RLED 1 k Limit LED-current RWK1 / RWK2 / RWK3 / RWK4 10 kΩ ±5% RSERIES The value of the resistor depends on the voltage difference between VCC1 and the microcontroller GPIO voltage Active Components D REV1 RR268MM600 Reverse polarity protection DREV2 BZX84C16 Gate protection. Limit V GS DREV3 BAS21 TREV1 IPZ40N04S5L-2R8 Reverse ba ttery protection, N-MOS TREV2 BC846 Q1 / Q2 IPZ40N04S5-3R1 Main power switches Table 78 Bill of Material (cont’d) Ref. Typical Value Purpose / Comment

Datasheet 189 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver

12.2 ESD Tests

12.2.1 ESD according to IEC61000-4-2

Tests for ESD robustness according to IEC61000-4-2 “GUN test” (150 pF, 330 Ω) have been performed. The results and test condition are available in a test report. The values for the test are listed below. Table 79 ESD “GUN test” 1)2) 1) ESD susceptibility “ESD GUN” according to EMC 1.3 Test specification, Section 4.3 (IEC 61000-4-2). Tested by external test house (IBEE Zwickau, EMC Test report Nr. 20.12.20). 2) ESD Test “Gun Test” is specified with external components for pins VS, VSINT, VS, WKx. See the application diagram in Chapter 12.1 for more information. Performed Test Result Unit Remarks ESD at pin VS,VSINT,VS, WKx versus GND > 6 kV positive pulse ESD at pin VS,VSINT,VS, WKx versus GND < -6 kV negative pulse

Datasheet 190 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver

12.3 Thermal Behavior of Package

Board setup is defined according JESD 51-2, -5, -7. Board: 76.2 × 114.3 × 1.5 mm 3 w i t h 2i n n e r c o p p e r l a y e r s ( 3 5µ m t hick), with thermal via array under the exposed pad contacting the first inner copper layer and 300 mm2 cooling area on the bottom layer (70 µm).

12.4 Further Application Information

• The VS pin supplies the bridge driver and the charge pump, and is the sense pin for the high-side MOSFETs drain voltage. It is therefore highly recommended to connect a 100 nF / 50V ceramic by-pass capacitor as close as possible to the VS pin with a short PCB trace to GND.
• Please contact us for information regarding the FMEA pin
• For further information you may contact http://www.infineon.com/ Top view Bottom view cooling area Detail solder pads and vias

Datasheet 191 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver Package Outlines Figure 64 PG-VQFN-48 1) Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages 1) Dimensions in mm PG-VQFN-48-29, -31-PO V05 7±0.1 A6.8 7±0.1 B 11 x 0.5 = 5.5 0.5 0.5±0.07 0.1±0.05 0.13 ±0.05 0.26 0.15±0.05 (6) (5.2) 0.9 MAX. (0.65) +0.03 48x 0.08 (0.2) 0.05 MAX.C (5.2) (6) 0.1±0.03 ±0.050.23 M 48x

0.1 A B C

1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Index Marking SEATING PLANE Index Marking 6.8 12 1 25 36 (0.35) 0.4 x 45°

Datasheet 192 Rev. 1.0 2021-01-21 TLE9185QX BLDC Driver

Revision History

1.0 2021-01-21 First release

All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-01-21 Published by Infineon Technologies AG

81726 Munich, Germany

© 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.