TLE8209-2SA

TLE8209-2SA_12 INFINEON | Alldatasheet

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Data Sheet, Rev. 1.2, Dec. 2012 Automotive Power

Data Sheet 2 Rev. 1.2, 2012-12-20 TLE8209-2SA Table of Contents Table of Contents

Type Package Body Width Marking TLE8209-2SA PG-DSO-20-65 430 mil TLE8209-2SA PG-DSO-20-65 Data Sheet 3 Rev. 1.2, 2012-12-20 SPI Programmable H-Bridge TLE8209-2SA 1O v e r v i e w

Features

• Programmable current limitation from 1.5 to 8.6 A typ.
• Full path RDSon of 240 mΩ (typ. at Tj=25°C)
• Operating battery supply voltage 4.5 V to 28 V
• Operating logic supply voltage 4.4 to 5.25 V
• Low standby current (8 µA typ.)
• Logic inputs TTL /CMOS-compatible
• All I/O pins overvoltage tolerant up to 18 V
• Enable and disable input
• Short circuit and overtemperature protection S undervoltage shutdown
• V DD over- and undervoltage monitoring
• Open load detection in off condition
• Temperature dependent current reduction
• Extensive diagnosis capab ilities via SPI interface
• Status Flag for basic diagnosis without SPI
• Configurable as H-bridge or two independent half bridges
• Control of power stages by parallel inputs or via SPI
• Output switching frequency up to 11 kHz
• Slewrate programmable through SPI
• Excellent EMC performance
• AEC qualified
• Green product (RoHS compliant) Functional Description The TLE8209-2SA is a SPI programmable H-bridge, designe d for the control of DC motors in safety critical automotive applications. It features four selectable current ranges, two selectable slew rate settings and extensive diagnosis via SPI. The device monitors the digital supply voltage VDD and shuts down the output stages in case of VDD over- or undervoltage, thus providing a safe switch off path in case of malfunction of the digital control circuitry. In order to reduce power dissipation in extreme therma l conditions the current limitation threshold is reduced linearly for junction temperatures over 165°C. A thermal warning bit is set in the SPI. The two half bridges can also be used independently to drive two separate loads like solenoids or unidirectional DC motors.

Data Sheet 4 Rev. 1.2, 2012-12-20

2 Pin Configuration

2.1 Pin Assignment

Figure 1 Pinout TLE8209-2SA

2.2 Pin Definitions and Functions

Pin Symbol Function in SPI Mode Function in Status Flag Mode

1 GND Ground Ground

2 SO SPI Serial Data Out no function - connect to GND

VDDIO Supply Voltage for Logic Output Buffer Swi tches to SF-mode if connected to GND 4S S /SF Slave Select (low active) Status Flag (low active)

5 CP Pin for external Charge Pump Capacitor Pin for external Charge Pump Capacitor

6 VS Battery Supply Voltage, has to be connected to

Battery Supply Voltage, has to be connected to pin 15

7 IN1 Input 1 Input 1

8 OUT1 Output 1 Output 1

9 DIS Disable Disable

10 GND Ground Ground

11 GND Ground Ground

12 ABE

Bidirectional Enable Pin B idirectional Enable Pin

13 OUT2 Output 2 Output 2

14 IN2 Input 2 Input 2

VS Input battery supply voltage, has to be connected to pin 6 Input battery supply voltage, has to be connected to pin 6

16 SI SPI Serial Data Input no function - connect to GND

Data Sheet 5 Rev. 1.2, 2012-12-20 TLE8209-2SA Pin Configuration

2.3 Terms

Figure 2 Terms TLE8209-2SA

17 SCK SPI Clock no function - connect to GND

18 VDD VDD supply VDD supply

19 GNDABE Sense ground for VDD monitoring Sense ground for VDD monitoring

20 GND Ground Ground

21 GND Heatslug - connect to GND Heatslug - connect to GND

Pin Symbol Function in SPI Mode Function in Status Flag Mode VDD ABE GNDABE SO SI DIS SCK SS/SF VDDIO IN1 IN2 OUT1 GND VS OUT2 VDDI O ISS / SF ISC K ISI ISO IDI S IIN 2 IIN 1 IGNDA B E IABE IDD IDDI O VSS /SF VSC K VSI VSO VDI S VIN 2 VIN 1 VGNDA B E VABE VDD IOUT1 IOUT2 VOUT2 VOUT1 IS VS CP VCP ICP

Data Sheet 6 Rev. 1.2, 2012-12-20

3 Block Diagram

Figure 3 Block Diagram TLE8209-2SA VDD- Monitoring VDD ABE GNDABE SO SI DIS SCK SS/SF VDDIO IN1 IN2 OUT1 GND VS OUT2 Logic SPI /Flag Gate Control VS Undervoltage Diagnostics internal Supply CP

Data Sheet 7 Rev. 1.2, 2012-12-20 TLE8209-2SA General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Absolute Maximum Ratings 1) Tj = -40 ⋅C to 150 ⋅C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) Not subject to production test, specified by design. Pos. Parameter Symbol Limit Values Unit Test Conditions / Comment Min. Max.

4.1.1 Junction temperature Tj -40

°C– 100h cumulative

4.1.2 Storage temperature Ts -55 150 °C–

4.1.3 Ambient temperature Ta -40 125 °C–

4.1.4 Battery supply voltage VS -0.5 40 V Static destruction proof -2 40 V Dynamic destruction proof t < 0.5 s (single pulse, Tjstart < 85 °C) 4.1.5 Logic supply voltage VDD -0.5 18 V – 4.1.6 Supply for logic out VDDIO -0.5 18 V –

4.1.7 Voltage at logic pins

ABE, IN1, IN2, DIS, SCK, SS/SF, SI VIN -0.5 18 V – 4.1.8 Voltage at SO VSO -0.5 VDDIO +0.3 4.1.9 Voltage at CP VCP VS-0.3 VS+5.0 V 0V < VS < 40V 4.1.10 Voltage at GNDABE VGNDABE VGND-0.3 VGND+0.3 V ESD Susceptibility

4.1.11 ESD Resistivity to GND

VESD -2 2 kV HBM 2) 2) ESD susceptibility HBM accordi ng to EIA/JESD22-A114-B (1.5kΩ, 100pF) 4.1.12 -8 8 kV HBM 2), Pins OUT1 and OUT2 4.1.13 -500 500 V CDM 3) 3) ESD susceptibility, Charged Devi ce Model “CDM” EIA/JESD22-C101 4.1.14 -750 750 V CDM 3), Pins 1, 10, 11, 20

General Product Characteristics Data Sheet 8 Rev. 1.2, 2012-12-20

4.2 Operating Range

Note: Within the operating range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

4.3 Thermal Resistance

Pos. Parameter Symbol Lim it Values Unit Remark Min. Max. 4.2.1 VS supply voltage range VS 4.5 28 V – 4.2.2 VDD supply voltage VDD 4.4 5.25 V – 4.2.3 VDDIO supply voltage VDDIO 05 . 5 V –

4.2.4 PWM frequency f –1 1 k H z –

4.2.5 Junction temperature TJ -40 150 °C–

Pos. Parameter Symbol Limit Values Unit Remark Min. Typ. Max.

4.3.6 Junction to Case 1)

1) Not subject to production test, specified by design. RthJC –– 1 . 6 K / W –

4.3.7 Junction to Ambient 1) RthJA –1 7 – K / W 2)

2) Simulation according to Jedec JESD51-2,-5,-7; natural conv ection; FR4 2s2p board 76.2 x 114.3 x 1.5 mm (2 x 70µm Cu, 2 x 35µm Cu)

Data Sheet 9 Rev. 1.2, 2012-12-20 TLE8209-2SA Power Supply

5 Power Supply

5.1 Basic Supply Characteristics

The TLE8209-2SA has three different supply pins: VDD, VS and VDDIO. VDD is used to supply the internal logic circuitry. VS connects to battery voltage and supplies the output stages. The voltage at pin VDDIO defines the high level output voltage at the pin SO of the SPI interface. VDDIO is also used as a mode select pin. If VDDIO is connected to ground, the device is set to status flag mode (SPI inactive). On power up the device will enter a functional state when VDD rises above the functional reset threshold VDD_RES. In this state all output stages are inactive and internal registers are cleared. When VDD rises further above the power on reset threshold VDD_POR the device starts operation with a delay time of tPOR.

5.2 VDD Monitoring

The logic supply voltage level at the pin VDD is monitored. If the voltage at pin VDD is out of the permissible range of VDD_L … VDD_H the power stages of TLE8209-2SA are switched off and pin ABE is pulled to ground. To suppress glitches in the VDD monitoring, a glitch filter is implemented.VDD is measured with reference to pin GNDABE. The state of VDD monitoring is stored in STATCON_REG and can be read out via SPI. The output stages can also be turned off by pulling the ABE pin to ground externally. In case of VDD failure, the output stages are switched off, even if the pin ABE should be connected to a high level signal because of external short circuit to VDD or battery voltage (up to 18V). OUT1 and OUT2 cannot be switched on in over- or undervoltage condition, switching off is always possible. A power on reset (VDD < VDD_POR) switches off all stages without delay. Control of VDD-monitoring is possible in SPI mode only. Detailed information (differentiation of over and under- voltage detection) is only possible by SPI interface. Behavior of VDD monitoring in SF mode: - monitoring is present with the specified values for over- and undervoltage - any test of over- and undervoltage threshold is not possible - the latch for overvoltage is disabled VDD Undervoltage If the VDD voltage is lower than the supply voltage supervisory lower threshold (V DD_THL), output stages are shut off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. At the transition from undervoltage to normal voltage the signal at pin ABE goes high and the output stages will return to normal operation after a filtering time (tFIL_ON) has expired. For output control via SPI the bits MU X and SINx in the config register have to be re- programmed. New failures are not stored to diagnostic registers during undervoltage, register content remains valid, writing new information to configuration registers is possible as far as they are not reset by ABE. If VDD falls below the power-on-reset supply voltage (VDD_POR) all stages are shut off and ABE is switched active low. When VDD is rising above the power-on-reset supply voltage threshold (VDD_POR) a power-on-reset is generated (tPOR), setting all registers to its default state. VDD Overvoltage If the VDD voltage is higher than the s upply voltage supervisory upper threshold (VDD_THH), all output stages are shut off after a filtering time ( tFIL_OFF) and the bi-directional pin ABE is pulled low. The behavior of the ABE level and output stages on the return of VDD from overvolt age to the correct range is configured in STATCON_REG, bit CONFIG0) CONFIG0=’1’: ABE is latched and outputs remain off after overvoltage. Return to normal operation is only possible with power-on reset or by changing this bit via SPI.

Data Sheet 10 Rev. 1.2, 2012-12-20 CONFIG0=’0’: ABE is inactive after VDD returned to normal operating voltage and filtering time has expired. At the transition from overvoltage to normal condition, the output stages will return to normal operation. For output control via SPI the bits MUX and SINx in the config register have to be re-programmed. New failures are not stored to diagnostic registers during overvoltage, register cont ent remains valid, writing ne w information to configure registers is possible as far as they are not reset by ABE. VDD Monitoring Test Mode Testing of VDD monitoring is possible in SPI mode only. The latch function for over voltage at VDD has to be switched of (CONFIG0=0 in STATCON_REG) Testing upper threshold: By writing 00xxxxxxb into STATCON_REG, the over voltage threshold is reduced to VDD_TEST_H. STATCON_REG bit 2 and 0 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 0 in STATCON_REG must be HIGH again Testing lower threshold: By writing 01xxxxxxb into STATCON_REG, the unde rvoltage threshold is in creased to VDD_TEST_L. STATCON_REG bit 2 and 1 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 1 in STATCON_REG must be HIGH again.

5.3 VDDIO - Digital Output Supply and Diagnostic Mode Selection

The voltage at VDDIO is used to supply the output buffer at the SO pin (serial output of SPI-interface). The VDDIO pin is also used to select SPI- or in stat us flag (SF) diagnostic mode. As soon as VDDIO is lower than VDDIO_L, the device is put into status flag mode. Figure 4 VDDIO and SO-Pin to internal logic (SF-mode / SPI -mode ) from internal logic SO - SF/SPI - mode threshold VDDI O_L VDDIO

Data Sheet 11 Rev. 1.2, 2012-12-20 TLE8209-2SA Power Supply

5.4 Electrical Characteris tics Power Supply and VDD-Monitoring

Electrical Characteristics: Power Supply and VDD-Monitoring VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. Supply

5.4.1 Supply Current IVS –82 0 µ A IOUT = 0 A, VDD = 0V,

VS < 18 V, Tj < 125°C –2 . 1 4m A bridge disabled, IOUT = 0 A,

5 V < VS < 18 V

–2 . 5 5m A f = 2 kHz, IOUT = 0 A, –49m A f = 10 kHz, IOUT = 0 A, –4 . 8 1 3 m A f = 10 kHz, IOUT = 0 A,

5 V < VS < 28 V

5.4.2 Functional Reset Threshold VDD_RES –1 . 4 2 . 5 V –

5.4.4 Power On Reset Delay

tPOR –0 . 2 2 0 . 5 m s VDD = on --> output stage active, no load 5.4.5 VDD Input current IDD –79m A 4 . 5 V < V DD < 5.5V

5.4.6 VDDIO Input current IDDIO – 30 100 µA SPI-mode

5.4.7 SF-mode Threshold VDDIO_L ––1 . 0 V – 5.4.8 SPI-mode Threshold VDDIO_H 2.0 – – V – VDD-Monitoring

5.4.12 Test mode reduced

VDD_TEST_H 4.2 4.3 4.4 V

5.4.13 Test mode increased

VDD_TEST_L 5.25 5.4 5.5 V

5.4.14 Filter time for glitch

tFIL 60 100 135 μs–

5.4.15 Maximum Slew Rate on

VDD1) 1) Not subject to production test; specified by design VDD_slew ––0 . 5 V / µ s –

Data Sheet 12 Rev. 1.2, 2012-12-20

6 Logic Inputs and Outputs

The threshold specifications for the logic inputs are compatible to both 5 and 3.3 V standard CMOS micro- controller ports. All inputs (except ABE ) feature internal pull-up current source s. The logic output SO is supplied by VDDIO. VDDIO can be supplied with either 5 or 3.3 V, so the output thresholds of SO can be configured to the required I/O voltage. Electrical Characteristics: Control Inputs VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. IN1, IN2 6.0.1 Low level VINx_L -0.3 – 1.0 V – 6.0.2 High level VINx_H 2.0 – VDD+0.3 V – 6.0.3 Hysteresis VINx_HYS 0.2 – 1.0 V –

6.0.4 Input Current (Pull Up)

IINx -30 -20 -10 µA 0 V < VINx < 2.1 V 6.0.5 0 2 5 µA VINx > 3.0 V

6.0.6 Input Capacity 1) CINx –– 2 0 p F 2)

6.0.7 Low level VDIS_L -0.3 – 1.0 V – 6.0.8 High level VDIS_H 2.0 – VDD+0.3 V – 6.0.9 Hysteresis VDIS_HYS 0.2 – 1.0 V – 6.0.10 Input Current (Pull Up) IDIS -200 -125 -50 µA 0 V < VDIS< 2.1 V 6.0.11 0 2 5 µA VDIS > 3.0 V

6.0.12 Input Capacity 1) CDIS –– 2 0 p F 2)

6.0.14 Output low-level voltage VABE_OUTL –– 1 . 2 V VDD_THH < VDD < 18 V IABE < 5 mA 6.0.15 – – 1.0 V 2.5 V < VDD < VDD_THL IABE < 1 mA 6.0.16 Input threshold high VABE_INH 0.7*VDD –– V – 6.0.17 Input threshold low VABE_INL – – 0.3* VDD V– 6.0.18 Hysteresis VABE_INHY 0.2 – 1.0 V –

6.0.20 ABE Input current (Pull

Down) -IABE_L 20 40 120 μA 1.5 V < VABE < 18 V 6.0.21 0 – 60 μA0 V < VABE < 1.5 V SI

6.0.22 Low level

VSI_L -0.3 – 1.0 V – 6.0.23 High level VSI_H 2.0 – VDD+0.3 V – 6.0.24 Hysteresis VSI_HYS 0.2 – 1.0 V – 6.0.25 Input Current (Pull Up) ISI -30 -20 -10 µA 0 V < VSI < 2.1 V

6.0.26 Input Capacity 1) CSI 14 pF 2)

Data Sheet 13 Rev. 1.2, 2012-12-20 TLE8209-2SA Logic Inputs and Outputs SCK 6.0.27 Low level VSCK_L -0.3 – 1.0 V – 6.0.28 High level VSCK_H 2.0 – VDD+0.3 V – 6.0.29 Hysteresis VSCK_HYS 0.2 – 1.0 V – 6.0.30 Input Current (Pull Up) ISCK -30 -20 -10 µA 0 V < VSCK < 2.1 V

6.0.31 Input Capacity 1) CSCK –– 1 4 p F 2)

6.0.32 Low level VSS_L -0.3 – 1.0 V – 6.0.33 High level VSS_H 2.0 – VDD+0.3 V – 6.0.34 Hysteresis VSS_HYS 0.2 – 1.0 V –

6.0.35 Input Current in SPI

mode (Pull Up) ISS -30 -20 -10 µA 0 V < VSS < 2.1 V 6.0.36 -30 – 5 µA 2.1 V < VSS < 3.0 V 6.0.37 0 2 5 µA VSS > 3.0 V

6.0.38 Input Current in SF

mode (Open Drain) ISF 02 5 µ A VSF = 5.0 V, SF inactive 6.0.39 300 – – µA VSF = 1.0 V, SF active

6.0.40 Input Capacity 1) CSS –– 1 5 p F 2)

6.0.41 Low level VSO_L 0.0 – 0.4 V ISO = 2 mA 6.0.42 High level VSO_H VDDIO-0.75 – VDDIO V ISO = -2 mA 2.9 V < VDDIO < 5.5 V

6.0.43 Output capacitance 1) CSO – – 19 pF In tristate 2)

6.0.44 Leakage current ISO -2 – 2 μA In tristate

0 < VSO < VDDIO 1) Not subject to production test; specified by design 2) Vbias = 2 V; Vtest = 20 mVpp; f = 1 MHz Electrical Characteristics: Control Inputs (cont’d) VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max.

Data Sheet 14 Rev. 1.2, 2012-12-20

7 Power Stages

The TLE8209-2SA contains four n-channel power-DMOS transi stors that can be used in an H-bridge or in dual half bridge configuration. Integrated circuits protect the outputs against overcurrent and over-temperature, in case of short-circuit to ground, to the supply voltage or across the load. Positive and negative voltage spikes, wh ich occur when switching inductive loads, are limited by integrated freewheeling diodes (body diodes of power-DMOS).

7.1 Parallel or SPI Control

By default the setting of the power sw itches is controlled by the Inputs IN1, IN2 (parallel control). The outputs OUT1 and OUT2 are set to High (high-side switch ON, lo w-side switch OFF) or Low (high-side switch OFF, low- side switch ON) by the parallel inputs IN1 and IN2, respectively. In SPI mode there is also the option to control the outputs via the SPI bits SIN1 and SIN2 of the SPI configuration register. To switch to SPI control the bit MUX has to be set to ’0’. In addition, the outputs can be disabled (set to tristate, high- and low-side switch OFF) by the disable input DIS and the bidirectional reset pin ABE. Disabling sets the device to parallel control Table 1 shows the different options for the output control.

7.2 H-Bridge or Si ngle Switch Usage

The IC can be set to H-bridge mode or single-switch mode by SPI. This setting changes the behavior of the device in the following features:

• current limiting
• overcurrent shut-down
• open load diagnosis Table 1 Functional Truth Table Pos. DIS ABE IN1 IN2 SPI MUX SPI SIN1 SPI SIN2 OUT1 OUT2 Forward, parallel ctrl. L H H L 1 X X H L Reverse, parallel ctrl. L H L H 1 X X L H Free-wheeling low, parallel ctrl. L H L L 1 X X L L Free-wheeling high, parallel ctrl. L H H H 1 X X H H Forward, SPI ctrl. L H X X 0 1 0 H L Reverse, SPI ctrl. L H X X 0 0 1 L H Free-wheeling low, SPI ctrl. L H X X 0 0 0 L L Free-wheeling high, SPI ctrl. L H X X 0 1 1 H H Disabled by DIS H X X X X X X Z Z Disabled by ABE XLXXXXXZZ Table 2 OUT States OUT High-Side DMOS Low-Side DMOS HO N O F F LO F F O N ZO F F O F F

Data Sheet 15 Rev. 1.2, 2012-12-20 TLE8209-2SA Power Stages

7.3 Electrical Charact eristics Power Stages

Electrical Characteristics: Power Stage VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. Power Outputs OUT1, OUT2

7.3.1 Switch on resistance low

– 125 – m Ω IOUTx =3A ; Tj = 25°C – 215 250 IOUTx =3A ; Tj = 150°C

7.3.2 Switch on resistance high

– 115 – m Ω IOUTx =3A ; Tj = 25°C – 200 240 IOUTx =3A ; Tj = 150°C

7.3.3 Leakage current IOUT1(off)

IOUT2(off) -200 – 200 μA Output stage switched off VS =1 3V

7.3.4 Free-wheel diode forward

UD –0 . 9 1 . 1 V ID = 3 A

7.3.5 Free-wheel diode reverse

recovery time1) trr ––1 0 0 n s – Output Switching Times - Fast Slew Rate 7.3.6 Rise time HS tr (HS) 3.5 6.0 10 μs SPI bit SL=’0’ Output Switching Times - Slow Slew Rate

7.3.10 Rise time HS

tr (HS) 15 30 48 μs SPI bit SL=’1’ VS =8 . . 1 8V ; IOUT = 3 A7.3.11 Fall time HS tf (HS) 15 30 48

7.3.12 Rise time LS tr (LS) 18 30 48

7.3.13 Fall time LS tf (LS) 18 30 48

Output Delay - Parallel Control, Fast Slew Rate 7.3.14 Output on-delay tdon ––1 2 μs VS =8 . . 1 8V ; IOUT = 3 A

7.3.15 Output off-delay tdoff ––7 μs

Output Delay - SPI Control, Fast Slew Rate 7.3.16 Output on-delay tdon ––1 3 μs VS =8 . . 1 8V ; IOUT = 3 A

7.3.17 Output off-delay tdoff ––1 2

Output Delay - Parallel Control, Slow Slew Rate 7.3.18 Output on-delay tdon ––4 1 μs VS =8 . . 1 8V ; IOUT = 3 A

7.3.19 Output off-delay tdoff ––2 5

Output Delay - SPI Control, Slow Slew Rate 7.3.20 Output on-delay tdon ––4 2 μs VS =8 . . 1 8V ; IOUT = 3 A

7.3.21 Output off-delay tdoff ––2 6

Data Sheet 16 Rev. 1.2, 2012-12-20 Figure 5 Output Switching Time Figure 6 Output Delay Time – Low-Side FETs Enable and Disable Delay Times

7.3.22 Disable delay time, fast

tddis –82 0 μs VS =8 . . 1 8V ; IOUT = 3 A

7.3.23 Disable delay time, slow

tddis –3 8 7 5

7.3.24 Enable delay time, fast

tdel –82 0

7.3.25 Enable delay time, slow

tdel –3 8 7 5 7.3.26 Power on delay time tdel –0 . 1 0 . 4 m s VS = on --> output stage active, no load 1) Not subject to production test - specified by design Electrical Characteristics: Power Stage VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. 90% 10% tRISE tFALL OUTx 10% 90% 90% 10% tdon 30% 30% tdoff OUTx INx V

Data Sheet 18 Rev. 1.2, 2012-12-20

8 Protection and Monitoring

Both output stages of the TLE8209-2SA are equipped with fault diagnostic functions:

• Short to battery voltage (SCB). Can be detected when low side-switches are turned on
• Short to ground (SCG). Can be detect ed when high side-switches are turned on
• Open load (OL). Can be detected in inactive mode
• Over-temperature (OT). Can be detected in active and inactive mode
• VDD over- and under voltage ( Chapter 5.2)
• Battery under voltage detection. Can be detected in active and inactive mode Individual detection for each output in single swit ch operation mode (SCB, SCG, OL) is possible. The corresponding diagnostics bits for each failure will be set in the SPI according to Table 8 “Failure Encoding” on Page 29.

8.1 Diagnosis in Status Flag Mode

Instead of using the SPI interface for control and diagnos is of the TLE8209-2SA, the device can also be set into status flag mode by connecting pin VDDIO to GND as described in Chapter 5.3. In status flag mode the pin SF will be pulled low in the following cases:

• undervoltage at VS
• bridge disabled by ABE or DIS
• bridge disabled by VDD monitoring
• bridge disabled by short circuit detection
• overtemperature shut down SF will not be pulled low if VDD is below the power on reset threshold (VDD_POR).

8.2 Current Limitation

To limit the output current at low power loss, a chopper current limitation is integrated. Current measurement for current limitation is done in the high side path. This requ ires high side freewheeling in case of active current limitation. Figure 9 Chopper Current Limitation Figure 9 shows the behavior of the current limitation for over current detection in HS1. It applies accordingly also for HS2: When the current in high-side switch of OUT1 (HS1) exceeds the limit IL longer than the blanking time tb, OUT2 is switched to high (e.g. LS2->OFF, HS2->ON), independent of the input signal at IN2. This leads to a slow-decay current decrease in the load and in HS1. As soon as the current falls below IL-Ihys, OUT2 is switched back to normal IOUT time IL ttrans LS2 HS2 tb Ihys HS1 LS1

Data Sheet 19 Rev. 1.2, 2012-12-20 TLE8209-2SA Protection and Monitoring operation, i.e. the outputs follow the inputs according to the truth table. The current limit IL can be programmed to four different values by setting the SPI bits CL1 and CL2 in the SPI configuration register. To avoid high chopper frequencies the time between two transients ttrans is limited. Current limitation is available in H-bridge operation mode, not in single switch operation mode. This means, that the current limit, current limit hysteresis and blanking time has no effect in single switch operation mode.

8.3 Temperature Dependent Current Reduction

For TILR < Tj < TSD the current limit decreases from IL as set by the SPI to IL_TSD = 2.5 A typ. as shown in Figure 10. Figure 10 Temperature Dependent Current Reduction

8.4 Short Circuit to Ground

Figure 11 Short to Ground Detection A Tj [°C]TILR (typ. 165°C) tolerance of temperature dependent current reduction range of over - temperature shut -down TSD (min. 175°C) IL IL_TSD (typ. 2.5A) IOUT IL time tb IOUK IN1 tDF_H t<tb OUT1 current short circuit detected current tracking output off Ihys current limitation active tDF_OFF Short IN2 tristate OUT2 tristate

Data Sheet 20 Rev. 1.2, 2012-12-20 The short circuit to ground detection is activated when the current through one of the high side switches rises over the threshold IOUK and remains higher than IOUK for at least the filter time tDF_H within the blanking time tb. The output stage in which the short circuit was detected will be switched off within tDF_OFF. In H-bridge mode also the other output will be switched off after a short delay of tDF_del . In single switch mode only the affected output will be switched off.

8.5 Short Circuit to Battery

A short circuit to battery is detected in the same way as a short circuit to ground, only in the low side switch instead of the high side switch.

8.6 Short Circuit across the Load

Short circuit over load is indicated by two failures - short circuit to ground on one output and short circuit to battery on the other output. Both failure bits will be set in the SPI diagnostics register. Both output stages will be turned off.

8.7 Overtemperature

In case of high DC-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above the thermal shut-down temperature TSD (see Figure 10). In that case, all output transistors are turned off.

8.8 Undervoltage Shut-Down

If the supply voltage at the VS pins falls below the undervoltage detection threshold VUV_OFF, the outputs switches are turned off. As soon as VS rises above VUV_ON again, the device is returning to normal operation.

8.9 Open Load Diagnosis

Open load diagnosis is only possible if outputs are switched off by DIS or ABE. The diagnostic current sources are deactivated in status flag mode. Diagnostic current s ources are disconnected if outputs are active. That means that the diagnostic current sources are also disconnected if the outputs are deactivated due to short circuit. The open load detection in H-bridge mode is different from the open load detection in single switch mode. Open Load Detection in H-Bridge mode Figure 12 Open Load Detection in H-Bridge Mode VDD Vref _L OUT1 OUT1_L + Vref_L OUT2 OUT2_L

Data Sheet 21 Rev. 1.2, 2012-12-20 TLE8209-2SA Protection and Monitoring Open Load Detection in Single Switch Mode Figure 13 Open Load Detection in Single Switch Mode Table 3 Open Load Detection in H-Bridge Mode VOUT1 OUT1_L VOUT2 OUT2_L Diagnostic Comment < Vref_L H< V ref_L H Load o.k. pull down current is stronger < Vref_L H> V ref_L L Load o.k. transient area > Vref_L L< V ref_L H Open Load > Vref_L L> V ref_L L Load o.k. transient area Table 4 Open Load Detection in Single Switch Mode VOUTx (OFF State) OUTx_H OUTx_L Diagnostic Comment VOUTx < Vref_L L H o.k. Load to ground Vref_L <VOUTx < Vref_H L L Open Load Output open VOUTx > Vref_H H L o.k. Load to VS VDD Vref _H Vref _M Vref _L VDDVref _M -Vref _ H Vref _L OUTx OUTx_H OUTx_L

Data Sheet 22 Rev. 1.2, 2012-12-20

8.10 Electrical Characteristics

Electrical Characteristics: Protection and Monitoring VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. Chopper Current Limitation Dependent on SPI setting; Default = IL3 8.10.5 Current Limit Hysteresis Ihys 00 . 2 5 0 . 4 0 A - 4 0 °C < Tj < TILR

8.10.6 Blanking time tb 81 1 1 5 μs–

8.10.7 Time between transients ttrans 90 – 130 μs–

Temperature Dependent Current Limitation1)

8.10.9 Start of current limit

TILR 150 165 – °C–

8.10.10 Thermal shut-down TSD 175 – – °C–

8.10.11 Range of temperature

TSD - TILR 20 25 30 °C– Short Circuit Detection to GND

8.10.12 Short circuit detection

current (HS) |IOUKH1| 2.5 5.0 6.5 A -40 °C < Tj < TILR Dependent on SPI- setting for |IL|; Default = IOUKH3 8.10.13 | IOUKH2|5 . 0 7 . 3 1 0 Short Circuit Detection to VS

8.10.20 Short circuit detection

current (LS) |IOUKL1| 2.5 4.6 6.5 A -40 °C < Tj < TILR Dependent on SPI- setting for |IL|; Default = IOUKL3 8.10.21 | IOUKL2|5 . 0 7 . 9 1 0 8.10.23 | IOUKL4| 9.5 14 17.4

Data Sheet 23 Rev. 1.2, 2012-12-20 TLE8209-2SA Protection and Monitoring Short Circuit Detection Timing

8.10.28 Delay time for fault

tDF_H, tDF_L 12 5 µ s –

8.10.29 Time from detected fault to

high impedance of output1) tDF_OFF –– 4 µ s –

8.10.30 Delay time between

switching off of the output stages in short circuit tDF_del 51 7 4 0 µ s – Open Load

8.10.31 Open Load Diagnostic

Filter Time1) tOL_DIAG 60 – 135 µs – 8.10.32 Low Diagnosis Threshold Vref_L 0.4 * VDD - 0.2 0.4 * VDD 0.4 * VDD + 0.2 8.10.33 High Diagnosis Threshold Vref_H 0.8 * VDD - 0.2 0.8 * VDD 0.8 * VDD + 0.2 8.10.34 Diagnosis Bias Voltage Vref_M 0.6 * VDD - 0.2 0.6 * VDD 0.6 * VDD + 0.2

8.10.35 Positive Diagnostic Current

(pull down current source) IDIA_P 300 620 980 µA VOUTx = 14 V 8.10.36 270 610 980 µA VOUTx = Vref_H

8.10.37 Negative Diagnostic

IDIA_N -350 -240 -100 µA VOUTx = 0 V 8.10.38 -350 -210 -80 µA VOUTx = Vref_L

8.10.39 Ratio of current sources

(Pos/Neg) RatioI_DIA 22 . 9 4 – – Undervoltage VUV ON 3.3 3.9 4.6 V Switch on threshold VUV HY 100 200 400 mV Hysteresis

8.10.41 VS Undervoltage Detection

Filter Time1) tUV –– 1 . 5µ s 1) Not subject to production test; specified by design. Electrical Characteristics: Protection and Monitoring VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max.

Data Sheet 24 Rev. 1.2, 2012-12-20

9 SPI Interface

The serial SPI interface establishes a communica tion link between TLE8209-2SA and the systems microcontroller. The TLE8209-2SA always operates in slave mode whereas the cont roller provides the master function. The maximum baud rate is 2 MBaud. By applying an active slave select signal at SS the TLE8209-2SA is selected by the SPI-master. SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock In put) the SPI-clock is provided by the master. In case of inactive slave select signal (High) the data output SO goes into tristate. The first two bits of an instruction may be used to es tablish an extended device-addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit (see Figure 16). Figure 14 SPI Block Diagram

9.1 General SPI Characteristics

1. During active reset conditions the SPI is driven into its default state. T he output SO is set to high impedance (tristate). When reset becomes inactive, the state machine enters into a wait state for the next instruction. 2. If the slave select signal at SS is inactive (high), the state machine is forced to wait for the following instruction. 3. During active (low) state of the sele ct signal SS the falling edge of the serial clock signal SCK will be used to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the data according to the in struction (i.e. modification of internal registers) will be tr iggered by the rising edge of the SS signal. 4. In order to establish the option of extended addressing the upper two bits of the inst ruction byte (i.e. the first two SI bits of a frame) are reserved to send a chip address. To avoid a bus conflict the output SO will remain tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip SS SCK SI SO shift-register SPI-Control: -> state machine -> clock counter -> instruction recognition DIA_REG Diagnostics OR ABE DIS Reset

Data Sheet 25 Rev. 1.2, 2012-12-20 TLE8209-2SA SPI Interface address). If the chip address does not match, the according frame will be ignored and SO remains tristate for the complete frame. 5. Verification byte: Simultaneously to the receipt of an SPI instruction the TLE8209-2SA transmits a verification byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bit pattern and a flag indicating an invalid instruction of the previous access. 6. On a read access the data bits at the SPI input SI are rejected. During a valid write access the SPI will transmit the data byte "00hex" at the output SO after having sent the verification byte. 7. An instruction is invalid if one of the following conditions is fulfilled: - an unused instruction code is detected (see tables with SPI instructions). - the previous transmission is not completed in terms of internal data processing. - the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses. If an unused instruction code occurres, the data byte “FFhex” (no error) will be transmitted after having sent the verification byte. This transmission takes place within the same SPI-frame that contained the unused instruction byte. If an invalid instruction is detected, bit TRANS_F in the following verification byte (next SPI-transmission) is set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the microcontroller.

9.2 SPI Communication

The 16 input bits consist of the SPI instruction byte and an input data byte. The 16 output bits consist of the verification byte and the output data byte (see also Figure 15). The definition of these bytes is given in the subsequent sections. The access mode of the registers is described in the column “Type” (r = read, w = write). Figure 15 SPI Communication

9.2.1 Instruction Byte

The upper 2 bit of the instruction byte contain the chip address. The chip address of the TLE8209-2SA is ’00’. During read access, the output data according to the regi ster requested in the instruction byte are applied to SO within the same SPI frame. That means, the output data corresponding to an instruction byte sent during one SPI frame are transmitted to SO during the same SPI-frame 076543210 7654321 SI SCK SS SO SPI Instruction input data-byte MSB LSB Verification byte output data-byte M S BL S B M S BL S B

Data Sheet 26 Rev. 1.2, 2012-12-20 Figure 16 Bus Arbitration by Chip Address Table 5 SPI Instruction Format 76543210 CPAD1 CPAD0 INSTR5 INSTR4 INSTR3 INSTR2 INSTR1 INSTR0 Field Bits Type Description CPAD1:0 7:6 w Chip Address (00B) INSTR5:0 5:0 w SPI Instruction (encoding) Z 076543210 7654321 7 12345670123456 0SI SCK SS 1234567012345SO 0 Address sent by master is "00B" SO remains tristated after SS active Correct addres is recognized, data transmitted to SO Z 0765432107654321 7 12345670123456 0SI SCK SS SO Address sent by master is different from "00B" SO remains tristated after SS active Correct addres is not recognized, SO remains tristated and SI data are ignored

Data Sheet 27 Rev. 1.2, 2012-12-20 TLE8209-2SA SPI Interface

9.2.2 Verification Byte

9.2.3 Device Identi fier and Revision

The IC’s identifier (device ID) and revision number are used for production test purposes and features plug & play functionality depending on the systems software release. The two numbers are read-only accessible via the SPI- instructions RD_ID and RD_REV as described in Section 9.2.1. The device ID is defined to allow identification of different IC-types by software and is fixed for the TLE8209-2SA. The revision number may be utilized to distinguish different states of hardware and is updated with each redesign of the TLE8209-2SA. It is divided into an upper 4 bit field reserved to define revi sions (SWR) corresponding to specific software releases and a lower 4 bit field utilized to identify the actual mask set revision (MSR). Table 6 SPI Instruction Set Command SPI Instruction Byte Description RD_ID 0000 0000 Read identifier RD_REV 0000 0011 Read version RD_DIA 0000 1001 Read diagnostics register RD_CONFIG 0011 0000 Read power stage configuration RD_STATCON 0011 1100 Read VDD monitoring status WR_CONFIG 0010 1000 Write power stage configuration WR_STATCON 0001 1000 Write VDD monitoring status all other instructions 00xx xxxx Unused - TRANS_F is set to high, ff_hex is sent as data bit. all other chip addr. xxxx xxxx Inva lid address - SO remains tristate during entire SPI-frame. Table 7 Verification Byte Format 76543210 VER6 VER5 VER4 VER3 VER2 VER1 VER0 TRANS_F Field Bits Type Description VER6 7 r Fixed to tristate (Z) VER5 6 r Fixed to tristate (Z) VER4 5 r Fixed to high (1) VER3 4 r Fixed to low (0) VER2 3 r Fixed to high (1) VER1 2 r Fixed to low (0) VER0 1 r Fixed to high (1) TRANS_F 0 r Transfer failure: B Error detected during previous transfer 0B Previous transfer was recognized as valid

Data Sheet 28 Rev. 1.2, 2012-12-20

9.2.4 Diagnostics Register

ID_REG Device Identifier 76543210 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Field Bits Type Description ID7:0 7:0 r Device-ID TLE8209-2SA: DE hex REV_REG Device Revision 76543210 SWR3 SWR2 SWR1 SWR0 MSR3 MSR2 MSR1 MSR0 Field Bits Type Description SWR3:0 7:4 r Revision corresponding to software release MSR3:0 3:0 r Revision corresponding to mask set DIA_REG Diagnostics Register Reset Value: x111 1111 B 76543210 ABE/DIS OT CurrRed CurrLim DIA21 DIA20 DIA11 DIA10 Field Bits Type Description ABE/DIS 7 r Is set to “0” in case of ABE = L or DIS = H OT 6 r Is set to “0” in case of over temperature CurrRed 5 r Is set to “0” in case of temperature dependent current limitation CurrLim 4 r Is set to “0” in case of current limitation DIA21 3 r Diagnosis-Bit2 of OUT2 DIA20 2 r Diagnosis-Bit1 of OUT2 DIA11 1 r Diagnosis-Bit2 of OUT1 DIA10 0 r Diagnosis-Bit1 of OUT1

Data Sheet 29 Rev. 1.2, 2012-12-20 TLE8209-2SA SPI Interface Note: The bit ABE/DIS shows directly the status of inputs ABE and DIS. It is set to ‘0’ if the power stages are disabled by ABE or DIS. The bits OT, CurrRed and CurrLim are latched. They will be reset with each read access. If the failure condition is still present the according bits are set again. Undervoltage at VS is reported and the outputs are switched off as long as the undervoltage condition is present. The previous setting of the DIAx bits is masked but not reset. Once the supply voltage is back in the operating range the diagnostic bits DIAxx will return to their setting before VS undervoltage. The outputs will return to normal operation. Detection of short circuit will switch of the output stages. In single half bridge operation only the affected output is switched off. In H-Bridge mode both outputs are shut do wn. The outputs remain off until the failure condition is removed and the diagnosis register is reset. A short across the load may also be reported as SCG at one output and SCB at the other. The diagnostic information DIAxx in the SPI interface is reset in the following cases:

• Read out of DIA_REG: only bit 4, 5 and 6 will be reset
• Enabling or disabling of the bridge via ABE or DIS
• Undervoltage at VDD
• Reset command via SPI Table 8 Failure Encoding ABE/DIS DIA21 DIA20 DIA11 DIA10 Description Comment X 1 1 1 1 no failure

1 X X 0 1 short circuit to battery at OUT1 (SCB1) latched

1 X X 1 0 short circuit to ground at OUT1 (SCG1) latched

1 X X 1 1 no error detected at OUT1

1 0 1 X X short circuit to battery at OUT2 (SCB2) latched 1 1 0 X X short circuit to ground at OUT2 (SCG2) latched 1 1 1 X X no error detected at OUT2 1 0 1 1 0 short circuit accross load (HS1+LS2 active) latched 1 1 0 0 1 short circuit accross load (HS2+LS1 active) latched X 0 0 0 0 Undervoltage at pin VS not latched 0 1 1 0 0 open load (H-Bridge) latched 0 1 1 X 0 open load at OUT1 (single switch operation) latched 0 1 1 0 X open load at OUT2 (single switch operation) latched

Data Sheet 30 Rev. 1.2, 2012-12-20

9.2.5 Configuration Register

9.2.6 STATCON Register

CONFIG_REG Configuration Register Reset Value: 1111 1010 B 76543210 MODE MUX SIN1 SIN2 CL1 CL2 RESET SL Field Bits Type Description MODE 7 wr ’1’: H-bridge mode ’0’: single output stages (for current levels 1 to 3 only) MUX 6 wr ’1’: control by parallel inputs IN1 and IN2 ’0’: control by SPI bits SIN1 and SIN2 SIN1 5 wr control of OUT1 if MUX=’0’ SIN2 4 wr control of OUT2 if MUX=’0’ CL1 3 wr current limitation level (see table below) CL2 2 wr current limitation level (see table below) RESET 1 wr ’0’: reset of digital logic SL 0 wr slew rate setting ’1’: slow ’0’: fast Table 9 Current Limitation Levels CL1 CL2 Current Level Typical Current 00 1 1 . 5 A 01 2 4 . 0 A 1 0 3 (default) 6.6A 11 4 8 . 6 A STATCON_REG STATCON Register Reset Value: 1101 1xxx B 76543210 CONFIG2 CONFIG1 CONFIG0 DIACLR2 DI ACLR1 STATUS2 STATUS1 STATUS0 Field Bits Type Description CONFIG2 7 wr VDD threshold test mode ’1’: VDD monitoring in normal operation ’0’: VDD thresholds are changed according to CONFIG1

Data Sheet 31 Rev. 1.2, 2012-12-20 TLE8209-2SA SPI Interface CONFIG1 6 wr changes thresholds in VDD threshold test mode (CONFIG2=’0’) ’1’: increase lower threshold of VDD monitoring to test switch off path ’0’: decrease upper threshold of VDD monitoring to test switch off path CONFIG0 5 wr latch function for overvoltage at VDD ’1’: overvoltage at VDD latched ’0’: overvoltage at VDD not latched DIACLR2 4 wr ’0’: clears diagnosis of OUT2 always returns ’1’ at read access DIACLR1 3 wr ’0’: clears diagnosis of OUT1 always returns ’1’ at read access STATUS2 2 r returns level at ABE STATUS1 1 r ’0’: under voltage at VDD ’1’: VDD voltage above lower limit STATUS0 0 r 0’: over voltage at VDD ’1’: VDD voltage below upper limit Field Bits Type Description

Data Sheet 32 Rev. 1.2, 2012-12-20

9.2.7 Contents of the SPI regi sters after a reset condition

Note: The registers for device identifier and revision (ID_REG and REV_REG) are not affected by reset. POR: Reset due to VDD power up SPIR: Reset via SPI by writing 0 into the RESET of CONFIG_REG ABE/DISR: Reset due to enabling or disabling the power stages via DIS or ABE (edge triggered) DISR: Reset due to a disabled power stage by DIS or ABE (level triggered) RDR: Reset due to a read access to DIA_REG DIACLR1: Reset via SPI by writing 0 into the DIACLR1 of STATCON_REG DIACLR2: Reset via SPI by writing 0 into the DIACLR2 of STATCON_REG SFMODE: Reset by setting the TLE8209-2SA in to the Status Flag Mode (VDDIO = 0V) x: No change Note: If a reset condition is not listed for a particular register it has no effect on the contents of this register. DIA_REG 76543210 ABE/DIS OT CurrRed CurLim DIA21 DIA20 DIA11 DIA10 P O R x1111111 S P I R x1111111 ABE/ D I S R x1111111 R D R x111xxxx D I A C L R 1 xxxxxx11 D I A C L R 2 xxxx11xx CONFIG_REG 76543210 MODE MUX SIN1 SIN2 CL1 CL2 RESET SL P O R 11111010 S P I R 11111010 D I S R x111xx1x S F M O D E 11111010 STATCON_REG 76543210 CONFIG2 CONFIG1 CONFIG0 DIACLR2 DIACLR1 STATUS2 STATUS1 STATUS0 P O R 11011xxx S P I R 11011xxx S F M O D E 11011xxx

Data Sheet 33 Rev. 1.2, 2012-12-20 TLE8209-2SA SPI Interface

9.3 Electrical Characteristics SPI

Electrical Characteristics: SPI Interface VS = 5 V to 28 V; VDD = 5.0 V; VDDIO = 2.9 V to 5.5 V, Tj = -40 ⋅C to 150 ⋅C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. SPI-Timing (see Figure 17)1) 1) All timing parameters specified by design - not subject to production test

9.3.1 Cycle-time (1) tcyc 490 – – ns referred to master

9.3.2 Enable Lead Time (2) tlead 50 – – ns referred to master

9.3.3 Enable Lag Time (3) tlag 150 – – ns referred to master

9.3.4 Data Valid (4)

H->L: VSCK=2V -> VSO=0.2 VDDIO L->H: VSCK=2V -> VSO=0.8 VDDIO if VDDIO < 4.5V: L->H: VSCK=2V -> VSO=0.7 VDDIO tv – 150 230 ns CL = 200 pF CL = 350 pF referred to TLE8209-2

9.3.5 Data Setup Time (5) tsu 40 – – ns referred to master

9.3.6 Data Hold Time (6) th 40 – – ns referred to master

9.3.7 Disable Time (7) tdis – – 100 ns referred to TLE8209-2

9.3.8 Transfer Delay (8) tdt 250 – – ns referred to master

9.3.9 Disable Lead Time (9) tdld 250 – – ns referred to master

9.3.10 Disable Lag Time (10) tdlg 250 – – ns referred to master

9.3.11 Access time (11) tacc 8.35 – – μs referred to master SS SO SI SCK 1 2 5 6 tristate Bit (n-3) Bit (n-4)…1 Bit 0; LSB MSB IN Bit (n-2) Bit (n-3) Bit (n-4)…1 LSB IN n=16

Application Information

Data Sheet 34 Rev. 1.2, 2012-12-20 Note: The following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. The function of the described circuits must be verified in the real application Figure 18 Application Example H-Bridge with SPI-Interface VDD ABE GNDABE SO SI DIS SCK SS/ SF VDDIO IN1 IN2 OUT1 GND VS OUT2 M CP 10 nFVbat 5V ECU supply Enable input (s) open -drain output (s) 3.3 or 5V port supply <33 nF<33 nF µC 100nF100 uFVs < 40V 8.2k VDD voltage regulator GND pin TLE8209-2SA

Data Sheet 36 Rev. 1.2, 2012-12-20 Figure 21 PG-DSO-20-65 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Heatslug1101 10 Index Marking Does not include plastic or metal protrusion of 0.15 max. per side 1 x 45˚ (Mold) 15.9 1)±0.15 A -0.2 (Metal) 13.7 0+0.1 +0.130.4 20 11

0.25 M A

1.27 1.1±0.1 (Heatslug) 15.74 ±0.1 (Metal) 0.25 Heatslug(Mold) 20x 3.2 14.2 ±0.3 ±0.1 0.95 3.25 3.5 MAX. 0.1 1.3 ±0.1 -0.0 +0. 6.3 0.25 ±0.15 2.8 11 1) B (Metal) 5.9 B ±0.1 ±0.15 5˚±3˚ Bottom View 1.27 1.83 9 x 1.27 = 11.43 13.48 0.68 GPS05791 Footprint: hlg09550 You can find all of our packages, sorts of packing and others in our Infineon Internet Page: http://www.infineon.com/packages Dimensions in mm

Data Sheet 37 Rev. 1.2, 2012-12-20 TLE8209-2SA

Revision History

Revision Date Comments / Changes 0.1 2008-08-21 Initial Product Proposal 0.2 2008-12-05 - General: Package PG-DSO-20-37 (TLE8209-2SA) added - Page 13, Chapter 6: Description of digital inputs modified - Page 16: Switching times adjusted to TLE8209-1 values - Page 36ff: Application diagrams updated (Figures 19 & 20) - Page 38: Package drawing added - Page 39: Package drawing updated 0.3 2009-07-31 Target Data Sheet - General: Package names changed - Page 24, Pos. 8.10.5, current limit hysteresis min. changed 0.4 2009-12-11 Preliminary Data Sheet - Limits revised throughout the whole document - Cover: Subtitle changed to “SPI Programmable H-Bridge” - Page 3: Feature List and Functional Description revised - Page 17ff: Rearranged figures 6 to 9 - Page 20: Figures 11 & 12 revised - Page 21: Short circuit description revised - Page 36: Application Diagram with Status Flag (Figure 20) updated - Page 38: Package Drawing updated 1.0 2010-02-16 Data Sheet - General: Single package version: PG-DSO-20-65 (PowerSO20) only. - Page 3, Overview: added “low standby current” in feature list - Page 11, Pos. 5.4.1: Parameter name changed to “Supply Current”; - Page 11, Pos. 5.4.1: added limits for I VS at VDD= 0V. - Page 19, Figure 11 updated. 1.2 2012-12-20 - Page3: Feature list revised - Page 27, Chapter 9.2.3: Description of device identifier and revision modified

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