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Technical content

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TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com

Features

/C0068Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings /C0068Internal Filter Eliminates Signal Fluctuation Due to AC Lighting Flicker — No External Capacitor Required /C0068In-Package Trim Provides an Easy and Accurate Means to Achieve System-to-System Repeatability /C006816-Bit Digital Output with I2C at 400 kHz /C0068Programmable Analog Gain and Integration Time Supporting 1,000,000-to-1 Dynamic Range /C0068SYNC Input Synchronizes Integration Cycle to Modulated Light Sources (e.g. PWM) /C0068Operating Temperature Range −40/C0053C to 85/C0053C (CS Package) −30/C0053C to 70/C0053C (FN Package) /C0068Operating voltage of 2.7 V to 3.6 V /C0068Available in Both an FN and a CS Package. The CS Package is the Industry’s Smallest Digital RGB Color Sensor

Applications

/C0068Provides Method to Derive Chromaticity Coordinates to Manage Display Backlighting (i.e. RGB LED, CCFL, etc.) /C0068Provides Means to Derive Color Temperature to White-Color Balance Displays Under Various Lighting Conditions End Products and Market Segments /C0068HDTVs /C0068Tablets, Laptops, Monitors /C0068Medical Instrumentation /C0068Consumer Toys /C0068Industrial/Commercial Lighting /C0068Industrial Process Control

Description

The TCS3404 and TCS3414 digital color light sensors are designed to accurately derive the color chromaticity and illuminance (intensity) of ambient light and provide a digital output with 16-bits of resolution. The devices include an 8 × 2 array of filtered photodiodes, analog-to-digital converters, and control functions on a single monolithic CMOS integrated circuit. Of the 16 photodiodes, 4 have red filters, 4 have green filters, 4 have blue filters, and 4 have no filter (clear). With the advanced patent pending in-package trim capability, device-to-device and system-to-system tolerance can be minimized allowing very precise repeatability to be attained. /C0114 /C0114 Texas Advanced Optoelectronic Solutions Inc.

1001 Klein Road /C0083 Suite 300 /C0083 Plano, TX 75074 /C0083 (972) 673-0759

(TOP VIEW) SCL SYNC GND SDA VDD INT PACKAGE FN DUAL FLAT NO-LEAD (TOP VIEW)

6 GND

5 VDD

4 INT

Package Drawings are Not to Scale ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. The LUMENOLOGY /C0114 Company www.taosinc.com A synchronization input (SYNC) provides precise external control of sensor integration allowing the internal conversion cycles to be synchronized to a pulsed light source. Furthermore, the synchronization feature supports the following advanced modes of operation to maximize flexibility across a broad range of hardware systems: (1) sync for one internal-time cycle, and (2) accumulate for specified number of pulses. The device also supports free-running and serial-bus-controlled integration modes if precise coupling between the sensor and light source is not required. Four parallel analog-to-digital converters (ADC) transform the photodiode currents to an SMBus (TCS3404) or I 2C (TCS3414) digital output that, in turn, can be input to a microprocessor. The RGB values can be read in a single read cycle to minimize the number of read command protocols defined in the communication interface. The slave address for this device is 39h (0111001b). A single SMB-Alert style interrupt (TCS3404) as well as a single traditional level-style interrupt (TCS3414) can be dynamically configured for any one of the four channels including a corresponding high/low threshold setting. The interrupt will remain asserted until the firmware clears the interrupt. The TCS3404/14 devices can help (1) automatically adjust the display brightness of a backlight to extend battery, increase lamp life, and provide optimum viewing in diverse lighting conditions, (2) white-color balance display panel and/or captured images in diverse lighting conditions, and (3) manage RGB LED backlighting to maintain color consistency over a long period of time. These devices are also ideal in controlling keyboard illumination in low ambient light conditions. Chromaticity coordinates (x,y) can be used to derive color temperature for the purpose of white-color balancing of displays and/or captured images. Illuminance, in lux, can be used to approximate the human eye response of ambient light and to manage exposure control in digital cameras. The TCS3404/14 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel televisions, cell phones, and digital cameras. Additional applications include street light control, security lighting, sunlight harvesting, and automotive instrumentation clusters. Functional Block Diagram Two-Wire Serial Interface Interrupt SDA VDD Blue Channel Clear Channel Command Register 4-Parallel ADC Registers INT SCL Green Channel Red Channel Integrating A/D Converter Integrating A/D Converter Integrating A/D Converter Integrating A/D Converter SynchronizationSYNC IR-Blocking Filter (CS Package Only) ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com Terminal Functions TERMINAL NAME CS PKG NO. FN PKG NO. TYPE DESCRIPTION GND A3 6 Power supply ground. All voltages are referenced to GND. INT B3 4 O Level interrupt — open drain. SCL A1 1 I Serial clock input terminal — clock signal for I 2C serial data. SDA B1 3 I/O Serial data I/O terminal — serial data I/O for I 2C. SYNC A2 2 I Synchronous input. VDD B2 5 Supply voltage. Available Options DEVICE INTERFACE I2C ADDRESS PACKAGE − LEADS PACKAGE DESIGNATOR ORDERING NUMBER TCS3404 SMBus − Chipscale−6 CS TCS3404CS TCS3404 SMBus − Dual Flat No-Lead−6 FN TCS3404FN TCS3413 I2C 0x29 Chipscale−6 CS TCS3413CS TCS3413 I2C 0x29 Dual Flat No-Lead−6 FN TCS3413FN TCS3414† I2C 0x39 Chipscale−6 CS TCS3414CS TCS3414† I2C 0x39 Dual Flat No-Lead−6 FN TCS3414FN TCS3415 I2C 0x49 Chipscale−6 CS TCS3415CS TCS3415 I2C 0x49 Dual Flat No-Lead−6 FN TCS3415FN TCS3416 I2C 0x59 Chipscale−6 CS TCS3416CS TCS3416 I2C 0x59 Dual Flat No-Lead−6 FN TCS3416FN † Recommended device for single-device systems.. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage, VDD 2.7 3 3.6 V Operating free-air temperature, TA (CS PAckage) −40 85 °C Operating free-air temperature, TA (FN PAckage) −30 70 °C SCL, SDA input low voltage, VIL −0.5 0.8 V SCL, SDA input high voltage, VIH 2.1 3.6 V ams AG Technical content still valid

† Specified by design and characterization; not production tested. Figure 1. Timing Diagram for Sync

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com Optical Characteristics, VDD = 3 V, TA = 25/C0053C, GAIN = 64/C0121, Tint = 12ms (unless otherwise noted) (see Notes 1 and 2) PARAMETER TEST Red Channel Green Channel Blue Channel Clear Channel UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Irradiance λp = 470 nm, See Note 3 0% 15% 15% 50% 65% 90% 59.0 65.6 72.5 Re responsivity (CS package) λp = 524 nm, See Note 4 0% 15% 60% 90% 0% 35% 71.2 76.9 82.7 (counts/ μW/ cm2)package) λp = 640 nm, See Note 5 80% 110% 0% 15% 0% 15% 80.6 90.1 99.5 cm2) Irradiance λp = 470 nm, See Note 3 0% 15% 10% 50% 65% 90% 56.3 62.5 69.1 Re responsivity (FN package) λp = 524 nm, See Note 4 0% 15% 60% 90% 0% 35% 72.5 78.4 84.3 (counts/ μW/ cm2)package) λp = 640 nm, See Note 5 80% 110% 0% 15% 0% 15% 94.2 105.3 116.3 cm2) NOTES: 1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel valu e. 2. Optical measurements are made using small-angle incident radiation from a light-emitting diode (LED) optical source. 3. The 470 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: peak wavelength λp = 470 nm, spectral halfwidth Δλ½ = 35 nm, and luminous efficacy = 75 lm/W. 4. The 524 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: peak wavelength λp = 524 nm, spectral halfwidth Δλ½ = 47 nm, and luminous efficacy = 520 lm/W. 5. The 640 nm input irradiance is supplied by a AlI nGaP light-emitting diode with the following characteristics: peak wavelength λp = 640 nm, spectral halfwidth Δλ½ = 17 nm, and luminous efficacy = 155 lm/W. 6. Illuminance responsivity R v is calculated from the irradiance responsivity Re by using the LED luminous efficacy values stated in notes 3, 4, and 5 and using 1 lx = 1 lm/m 2. Operating Characteristics, VDD = 3 V, TA = 25/C0053C, (unless otherwise noted) (see Notes 2, 3, and 4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4× 3.8 4 4.2 Gain scaling, relative to 1× gain setting 16× 15.2 16 16.8Gain scaling, relative to 1× gain setting 64× 60.8 64 67.2 Dark ADC count value Ee = 0, 64× gain setting, Tint = 400 ms 0 3 15 counts Maximum digital count value Prescale = 1, Tint = 400 ms (Note 1) 65535 counts fosc Oscillator frequency 4.2 4.4 4.6 MHz Internal integration time tolerance −5 5 % Temperature coefficient of responsivity (SYNC mode) λ /C0020 700 nm, −40 °C /C0020 TA /C0020 85°C ± 200 ppm/°C NOTES: 1. At shorter integration times and/or higher Prescale settings, the device will reach saturation of the analog section before the digital count reaches the maximum 16-bit value. The worst-case (lowest) analog saturation value can be obtained using the formula: Analog saturation = (fosc(min) ×Tint) ÷Prescale, where Fosc(min) is the minimum oscillator frequency in Hz, and tint is the actual integration time (internal, manually-timed, or sync-generated) in seconds. 2. Gain is controlled by the gain register (07h) described in the Register section. 3. Measurements taken when the Photodiode field value in the Photodiode Register (06h) is 00b and when the Prescaler field value in the Gain Register (07h) is 000b. 4. The full scale ADC count value is slew-rate limited for short integration times and is limited by the 16-bit counter for long integration times. The nominal transition between the two regions is t int = 65535/5000 = 13.1 ms. ams AG Technical content still valid

Copyright /C0069 2011, TAOS Inc. the transfer, the device automatically begins the next integration cycle. (i.e. ADC_EN in Control Register) using the serial interface, or by 1 or more pulses input to the SYNC pin. Management Bus (SMBus) versions 1.1 and 2.0, and I2C bus Fast-Mode. Table 1. Slave Address be appended to the slave address by the master device to communicate properly with the device. information on configuring the interrupt functions.

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. The LUMENOLOGY /C0114 Company www.taosinc.com SMBus and I2C Protocols Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the TCS3404/14 with the most significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND byte form the register select address (see Table 1), which is used to select the destination for the subsequent byte(s) received. The TCS3404/14 responds to any Receive Byte requests with the contents of the register specified by the stored register select address. The TCS3404/14 implements the following protocols of the SMB 2.0 specification: /C0068Send Byte Protocol /C0068Receive Byte Protocol /C0068Write Byte Protocol /C0068Write Word Protocol /C0068Read Word Protocol /C0068Block Write Protocol /C0068Block Read Protocol The TCS3404/14 implements the following protocols of the I2C specification: /C0068I2C Write Protocol /C0068I2C Read (Combined Format) Protocol When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains the byte count (i.e. the number of bytes to be transferred). The TCS3404 (SMBus) device ignores this field and extracts this information by counting the actual number of bytes transferred before the Stop condition is detected. When an I 2C Write or I2C Read (Combined Format) is initiated, the byte count is also ignored but follows the SMBus protocol specification. Data bytes continue to be transferred from the TCS3414 (I2C) device to Master until a NACK is sent by the Master. The data formats supported by the TCS3404 and TCS3414 devices are: /C0068Master transmitter transmits to slave receiver (SMBus and I2C): − The transfer direction in this case is not changed. /C0068Master reads slave immediately after the first byte (SMBus only): − At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. /C0068Combined format (SMBus and I2C): − During a change of direction within a transfer, the master repeats both a START condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition. For a complete description of SMBus protocols, please review the SMBus Specification at http://www.smbus.org/specs. For a complete description of the I 2C protocol, please review the NXP I2C design specification at http://www.i2c−bus.org/references/. ams AG Technical content still valid

Copyright /C0069 2011, TAOS Inc. of the ADC conversions. The register set is summarized in Table 2. Table 2. Register Set specific control/status register for following read/write operations.

The command register specifies the address of the target register for subsequent read and write operations. This register contains eight bits as described in Table 3 and defaults to 00h at power on. Table 3. Command Register CMD 7 Select command register. Must write as 1. Transaction. Selects type of transaction to follow in subsequent data transfer.

00 Byte protocol SMB read/write byte protocol

10 Block protocol SMB read/write block protocol

11 Interrupt clear Clear any pending interrupt and is a write-

be read simultaneously in a single SMBus transaction. This is the only 64-bit data block supported by the TCS3404 SMBus protocol. Byte Count (Byte Count = 8) as illustrated in Figure 18. A write condition should not be used in conjunction with the 0Fh register.

  1. Only the Send Byte Protocol should be used when clearing interrupts.

Copyright /C0069 2011, TAOS Inc. Table 4. Control Register Resv 7:6 Reserved. Write as 0. Resv 5 Reserved. Write as 0. ADC_VALID 4 ADC valid. This read-only field indicates that the ADC channel has completed an integration cycle. Resv 3:2 Reserved. Write as 0. channels, and writing a 0 disables the ADCs. POWER 0 Power on. Writing a 1 powers on the device, and writing a 0 turns it off. NOTES: 1. Both ADC_EN and POWER must be asserted before the ADC channels will operate correctly.

  1. INTEG_MODE and TIME/COUNTER fields in the Timing Register (01h) should be written before ADC_EN is asserted.
  2. If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be used to verify that the device is
  3. During writes and reads, the POWER bit is overridden and the oscillator is enabled, independent of the state of POWER.

Register settings apply to all four ADC channels. The Timing Register defaults to 00h at power on. Table 5. Timing Register Resv 7 Reserved. Write as 0. stop an integration cycle when INTEG_MODE is 11. (see Integration Time table below). IN must be low at least 3.6 μs. number of SYNC IN pulses to count when the INTEG_MODE accumulate mode (11) is selected. NOTE: INTEG_MODE and TIME/COUNTER fields should be written before ADC_EN is asserted.

Copyright /C0069 2011, TAOS Inc. period of time as outlined in the table below. writing an 11 in the TRANSACTION field in the COMMAND register. arbitration, the interrupt will not be cleared. The Alert Response Address is 0Ch. behaves in an SMB-Alert mode, and the software set interrupt may be cleared by an SMB-Alert cycle. Table 6. Interrupt Control Register Resv 7 Reserved. Write as 0. Stop ADC integration on interrupt. When high, ADC integration will stop once an interrupt is asserted. a particular condition when the sensor is continuously integrating. 00 Interrupt output disabled. 11 Sets an interrupt and functions as mode 10. service routine software. See Application Software section for further information. Resv 3 Reserved. Write as 0.

000 Every Every ADC cycle generates interrupt

PERSIST 2:0 001 Single Any value outside of threshold range.

four ADC channels can be selected. Table 7. Interrupt Source Register Resv 7:2 Reserved. Write as 0.

00 Green channel

10 Blue channel

11 Clear channel

The ID register provides the value for both the part number and silicon revision number for that part number. It is a read-only register, whose value never changes. Table 8. ID Register

Copyright /C0069 2011, TAOS Inc. occurring, the use of PRESCALER can be useful. count value to the right). The PRESCALER adjustment range is divide by 1 to 64 in multiples of 2. lowered (see Timing Register section). Table 9. Gain Register Resv 7:6 Reserved. Write as 0. Resv 3 Reserved. Write as 0.

Register (03h) converges above the high threshold specified, an interrupt is asserted on the interrupt pin. HIGH_THRESH_HIGH_BYTE provide the low and high bytes, respectively, of the upper interrupt threshold. The interrupt threshold registers default to 00h on power up. Table 10. Interrupt Threshold Register LOW_THRESH_LOW_BYTE 08h 7:0 ADC interrupt source lower byte of the low threshold. LOW_THRESH_HIGH_BYTE 09h 7:0 ADC interrupt source upper byte of the low threshold. HIGH_THRESH_LOW_BYTE 0Ah 7:0 ADC interrupt source lower byte of the high threshold. HIGH_THRESH_HIGH_BYTE 0Bh 7:0 ADC interrupt source upper byte of the high threshold. setting. Both registers should be configured appropriately when setting up an interrupt service routine.

  1. Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the SMBus Send Byte

HIGH_THRESH_HIGH_BYTE registers) can be written together to set the 16-bit ADC value in a single transaction. Table 11. ADC Channel Data Registers ADC integration cycles complete between the reading of the lower and upper registers. well as the other three individual register pairs) may be read together to obtain the 16-bit ADC value in a single transaction.

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com APPLICATION INFORMATION: SOFTWARE Basic Operation After applying VDD, the device will initially be in the power−down state. To operate the device, issue a command to access the control register followed by the data value 03h to the control register to set ADC_EN and POWER to power up the device. At this point, all four ADC channels will begin a conversion at the default integration time of 12 ms. After 12 ms, the conversion results will be available in ADC Channel Data Registers (10h through 17h). The following pseudo code illustrates a procedure for reading the TCS3404/14 device using Word and Byte transactions: // Read ADC Channels Using Read Word Protocol − RECOMMENDED Address = 0x39 Command = 0x80 PowerUp = 0x03 //Power Up and Enable ADC //Wait for integration conversion //Address the Ch1 lower data register and configure for Read Word Command = 0xB0 //Set Command bit and Word transaction //Reads two bytes from sequential registers 10h and 11h //Results are returned in DataLow and DataHigh variables ReadWord (Address, Command, DataLow, DataHigh) Channel1 = 256 * DataHigh + DataLow //Address the Ch2 lower data register and configure for Read Word Command = 0xB2 //Set Command bit and Word transaction //Reads two bytes from sequential registers 12h and 13h //Results are returned in DataLow and DataHigh variables ReadWord (Address, Command, DataLow, DataHigh) Channel2 = 256 * DataHigh + DataLow //Shift DataHigh to upper byte //Address the Ch3 lower data register and configure for Read Word Command = 0xB4 //Set Command bit and Word transaction //Reads two bytes from sequential registers 14h and 15h //Results are returned in DataLow and DataHigh variables ReadWord (Address, Command, DataLow, DataHigh) Channel3 = 256 * DataHigh + DataLow //Address the Ch4 lower data register and configure for Read Word Command = 0xB8 //Set Command bit and Word transaction //Reads two bytes from sequential registers 16h and 17h //Results are returned in DataLow and DataHigh variables ReadWord (Address, Command, DataLow, DataHigh) Channel4 = 256 * DataHigh + DataLow //Shift DataHigh to upper byte ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. The LUMENOLOGY /C0114 Company www.taosinc.com // Read ADC Channels Using Read Byte Protocol Address = 0x39 //Slave addr − also 0x29 or 0x49 Command = 0x90 //Address the Ch1 lower data register ReadByte (Address, Command, DataLow) //Result returned in DataLow Command = 0x91 //Address the Ch1 upper data register ReadByte (Address, Command, DataHigh) //Result returned in DataHigh Channel1 = 256 * DataHigh + DataLow //Shift DataHigh to upper byte Command = 0x92 //Address the Ch2 lower data register ReadByte (Address, Command, DataLow) //Result returned in DataLow Command = 0x93 //Address the Ch2 upper data register ReadByte (Address, Command, DataHigh) //Result returned in DataHigh Channel2 = 256 * DataHigh + DataLow //Shift DataHigh to upper byte Command = 0x94 //Address the Ch3 lower data register ReadByte (Address, Command, DataLow) //Result returned in DataLow Command = 0x95 //Address the Ch3 upper data register ReadByte (Address, Command, DataHigh) //Result returned in DataHigh Channel3 = 256 * DataHigh + DataLow //Shift DataHigh to upper byte Command = 0x96 //Address the Ch4 lower data register ReadByte (Address, Command, DataLow) //Result returned in DataLow Command = 0x97 //Address the Ch4 upper data register ReadByte (Address, Command, DataHigh) //Result returned in DataHigh Channel4 = 256 * DataHigh + DataLow //Shift DataHigh to upper byte ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com APPLICATION INFORMATION: SOFTWARE Configuring the Timing Register The command, timing, and control registers are initialized to default values on power up. Setting these registers to the desired values would be part of a normal initialization or setup procedure. In addition, to maximize the performance of the device under various conditions, the integration time and gain may be changed often during operation. The following pseudo code illustrates a procedure for setting up the timing register for various options. // Set up Timing Register //Low Gain (1x), integration time of 12ms (default value) Address = 0x39 Command = 0x81 //Timing Register Data = 0x02 WriteByte(Address, Command, Data) //Low Gain (1x), integration time of 101ms Command = 0x81 //Timing Register Data = 0x01 WriteByte(Address, Command, Data) //Low Gain (1x), integration time of 12ms Data = 0x00 WriteByte(Address, Command, Data) //High Gain (16x), integration time of 101ms Command = 0x81 //Timing Register Data = 0x01 WriteByte(Address, Command, Data) Command = 0x87 //Gain Control Register Data = 0x20 WriteByte(Address, Command, Data) //Read data registers (see Basic Operation example) //Perform Manual Integration of 50 us //Set up for manual integration Command = 0x80 Data = 0x01 //Disable ADC_EN WriteByte(Address, Command, Data) Command = 0x81 Data = 0x10 //Set manual integration WriteByte(Address, Command, Data) Command = 0x80 Data = 0x03 //Enable ADC_EN and begin integration WriteByte(Address, Command, Data) //Integrate for 50ms Sleep (50) //Wait for 50ms //Stop integrating Command 0x80 Data = 0x01 //Disable ADC_EN and stop integration WriteByte(Address, Command, Data) //Read data registers (see Basic Operation example) ams AG Technical content still valid

information regarding how the scale values were obtained. Figure 22. Manual Integration (INTEG_MODE 01b)

  1. Disable ADC_EN (= 0) before initiating a manual integration cycle
  2. Clear and enable INTR before each cycle
  3. Write 01b to INTEG_MODE field
  4. Set ADC_EN (= 1) to start integration
  5. Clear ADC_EN ( = 0) to stop integration

Copyright /C0069 2011, TAOS Inc. in the PARAM field, is completed. Figure 23. One-Shot Integration (INTEG_MODE 10b) Falling Edge

  1. Set PARAM for desired integration cycle (12ms, 100ms, or 400ms)
  2. Disable SYNC and clear INTR

until the rising or falling edge of a subsequent pulse as specified by the SYNC_EDGE and PARAM field values. the device with an external light source (e.g. LED).

  1. ADC_EN must be toggled (i.e. from high to low and back to high again) before next integration cycle

Figure 24. Integrate Over One Pulse (SYNC_EDGE 1b, INTEG_MODE 11b, PARAM 0b) Rising Edge

  1. Set PARAM for SYNC PULSE COUNT of 1
  2. Input two external SYNC pulses
  3. Disable SYNC and read channels

Copyright /C0069 2011, TAOS Inc. Figure 25. Integrate Over One Pulse (SYNC_EDGE 0b, INTEG_MODE 11b, PARAM 0b) Falling Edge

  1. Set PARAM for SYNC PULSE COUNT of 1
  2. Input external SYNC pulse
  3. Disable SYNC and read channels

1 N N+1

  1. ADC_EN must be toggled (i.e. from high to low and back to high again) before next integration cycle

Figure 26. Integrate Over Two Pulses (SYNC_EDGE 1b, INTEG_MODE 11b, PARAM Xb) Rising Edge

  1. Set PARAM for desired SYNC PULSE COUNT
  2. Input N+1 external SYNC pulses
  3. Disable SYNC and read channels

Figure 27. Integrate Over Two Pulses (SYNC_EDGE 0b, INTEG_MODE 11b, PARAM Xb) Falling Edge

  1. Set PARAM for desired SYNC PULSE COUNT
  2. Input N external SYNC pulse(s)
  3. Disable SYNC and read channels

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com APPLICATION INFORMATION: SOFTWARE A synchronization input (SYNC IN) is supported to precisely start/stop sensor integration and synchronize with the light source. The TIMING Register (01h) provides two synchronization modes of operation. The first mode of operation synchronizes the SYNC IN pin for one integration cycle as specified in the Timing Register (01h). When the rising edge of the signal is detected, the TCS3404/14 begins integration. The second mode accumulates a specified number of SYNC IN pulses (see Timing Register) in which the minimum pulse width is 50 μs. A pulse counter is used to count the rising and falling edges of the pulse(s) and precisely integrate the light level when the SYNC IN pulse is high. The following pseudo code illustrates a procedure for reading the TCS3404/14 device using the synchronization feature: // Synchronize one integration cycle // See ”Basic Operation” to power−on and start device // See ”Configuring the Timing Register” to setup environment Address = 0x39 //Slave addr − also 0x29 or 0x49 Command = 0x81 //Set Command bit and address Timing Register Data = 0x21 //Sync one 100ms integration period //External SYNC IN pulse initiates 100ms integration Sleep (100) // See ”Basic Operation” to read Data Registers using Byte or Word Protocol // Synchronize N number of SYNC IN pulses // See ”Basic Operation” to power−on and start device // See ”Configuring the Timing Register” to setup environment Address = 0x39 //Slave addr − also 0x29 or 0x49 Command = 0x81 //Set Command bit and address Timing Register Data = 0x30 //Integrate one SYNC IN pulse //External SYNC IN pulse synchronizes integration // See ”Basic Operation” to read Data Registers using Byte or Word Protocol ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. The LUMENOLOGY /C0114 Company www.taosinc.com APPLICATION INFORMATION: SOFTWARE Interrupts The interrupt feature of the TCS3404/14 device simplifies and improves system efficiency by eliminating the need to poll the sensor for a light intensity value. Interrupt mode is determined by the INTR field in the Interrupt Control Register. The interrupt feature may be disabled by writing a field value of 00h to the Interrupt Control Register (02h) so that polling can be performed. The versatility of the interrupt feature provides many options for interrupt configuration and usage. The primary purpose of the interrupt function is to signal a meaningful change in light intensity. However, it also be used as an end-of-conversion signal. The concept of a meaningful change can be defined by the user both in terms of light intensity and time, or persistence, of that change in intensity. The TCS3404/14 device implements two 16-bit-wide interrupt threshold registers that allow the user to define thresholds above and below a desired light level. An interrupt will then be generated when the value of a conversion exceeds either of these limits. For simplicity of programming, the threshold comparison uses the Interrupt Source Register (03h) to select which ADC channel (1 through 4) to generate the interrupt. This simplifies calculation of thresholds that are based on a percent of the current light level. For example, it is adequate to use only one channel (e.g. green channel) when calculating light intensity differences since, for a given light source, channel values are linearly proportional to each other and thus each value scales linearly with light intensity. To further control when an interrupt occurs, the TCS3404/14 device provides an interrupt persistence feature. This feature allows the user to specify the length in time of the number of consecutive ADC channel values for which a light intensity exceeding either interrupt threshold must persist before actually generating an interrupt. This can be used to prevent transient changes in light intensity from generating an unwanted interrupt. See Table 6 regarding the number of timer values provided. Two different interrupt styles are available: Level and SMBus Alert. The difference between these two interrupt styles is how they are cleared. Both result in the interrupt line going active low and remaining low until the interrupt is cleared. A level style interrupt is cleared by setting the Interrupt Clear field in the the COMMAND register to 11b. The SMBus Alert style interrupt is cleared by an Alert Response as described in the Interrupt Control Register section and SMBus specification. To configure the interrupt as an end−of−conversion signal so that every ADC integration cycle generates an interrupt, the interrupt PERSIST field in the Interrupt Control Register (02h) is set to 000b. Either Level or SMBus Alert style can be used. An interrupt will be generated upon completion of each conversion. The interrupt threshold registers are ignored. The following example illustrates the configuration of a level interrupt: // Set up end−of−conversion interrupt, Level style Address = 0x39 //Slave address − alternatively 0x29 or 0x49 Command = 0x83 //Interrupt Source Register Data = 0x01 //Select Channel 2 WriteByte(Address, Command, Data) Command = 0x82 //Address Interrupt Register Data = 0x10 //Level style, every ADC cycle WriteByte(Address, Command, Data) ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com APPLICATION INFORMATION: SOFTWARE The following example pseudo code illustrates the configuration of an SMB-Alert style interrupt when the light intensity changes 20% from the current value, and persists for 2.5 seconds: //Assume Interrupt Source as Channel 1 //Read current light level Address = 0x39 //Slave address − alternatively 0x29 or 0x49 Command = 0xB0 //Set Command bit and SMBus Word read ReadWord (Address, Command, DataLow, DataHigh) Channel1 = (256 * DataHigh) + DataLow //Calculate upper and lower thresholds T_Upper = Channel1 + (0.2 * Channel1) T_Lower = Channel1 − (0.2 * Channel1) //Write the lower threshold register Command = 0xA8 //Address lower threshold register, set Word Bit WriteWord (Address, Command, T_Lower.LoByte, T_Lower.HiByte) //Write the upper threshold register Command = 0xAA //Address upper threshold register, set Word bit WriteWord (Address, Command, T_Upper.LoByte, T_Upper.HiByte) //Enable interrupt Command = 0x82 //Address interrupt register Data = 0x24 //SMBAlert style, Persist 2.5 seconds WriteByte(Address, Command, Data) In order to generate an interrupt on demand during system test or debug, a test mode (INTR = 11) can be used. The following example illustrates how to generate an interrupt on demand: // Generate an interrupt Address = 0x39 //Slave address alternately 0x29 or 0x49 Command = 0x82 //Address Interrupt Control Register Data = 0x30 //Test interrupt WriteByte(Address, Command, Data) //Interrupt line should now be low ams AG Technical content still valid

at high frequencies to handle transient currents caused by internal logic switching. Figure 28. Bus Pull-Up Resistors and minimum Rp values, please review the NXP I2C design specification at http://www.i2c−bus.org/references/.

610 Nominal438 /C0043 30

128 Nominal

NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is ± 25 μm unless otherwise noted. B. Solder bumps are formed of Sn (96.5%), Ag (3%), and Cu (0.5%). C. The layer above the photodiode is glass and epoxy with an index of refraction of 1.53. D. This drawing is subject to change without notice. Figure 31. Package CS — Six-Lead Chipscale Packaging Configuration

Copyright /C0069 2011, TAOS Inc. NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is ± 20 μm unless otherwise noted. B. The die is centered within the package within a tolerance of ± 3 mils. C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55 . D. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish. E. This package contains no lead (Pb). F. This drawing is subject to change without notice. Figure 32. Package FN — Dual Flat No-Lead Packaging Configuration

NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted. B. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. C. Symbols on drawing A o, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. D. Each reel is 178 millimeters in diameter and contains 3500 parts. E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B. G. This drawing is subject to change without notice. Figure 33. Package CS Carrier Tape

Copyright /C0069 2011, TAOS Inc. NOTES: H. All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted. I. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. J. Symbols on drawing A o, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. K. Each reel is 178 millimeters in diameter and contains 3500 parts. L. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B. N. This drawing is subject to change without notice. Figure 34. Package FN Carrier Tape

be limited to a maximum of three passes through this solder reflow profile. Table 12. Solder Reflow Profile Figure 35. Solder Reflow Profile Graph

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 The LUMENOLOGY /C0114 Company /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. www.taosinc.com MANUFACTURING INFORMATION Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package molding compound. To ensure the package molding compound contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. The CS package has been assigned a moisture sensitivity level of MSL 2 and the devices should be stored under the following conditions: Temperature Range 5 °C to 50°C Relative Humidity 60% maximum Floor Life 1 year out of bag at ambient < 30° C / 60% RH Rebaking will be required if the aluminized envelope has been open for more than 1 year. If rebaking is required, it should be done at 50°C for 12 hours. The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under the following conditions: Temperature Range 5 °C to 50°C Relative Humidity 60% maximum Total Time 12 months from the date code on the aluminized envelope — if unopened Opened Time 168 hours or fewer Rebaking will be required if the devices have been stored unopened for more than 12 months or if the aluminized envelope has been open for more than 168 hours. If rebaking is required, it should be done at 50°C for 12 hours. ams AG Technical content still valid

TCS3404, TCS3414 DIGITAL COLOR SENSORS TAOS137A − APRIL 2011 /C0114 /C0114 Copyright /C0069 2011, TAOS Inc. The LUMENOLOGY /C0114 Company www.taosinc.com PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. LEAD-FREE (Pb-FREE) and GREEN STATEMENT Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TAOS has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced Optoelectronic Solutions Incorporated. ams AG Technical content still valid