SST89C59-33-I-NJ

SST89C59 SST | Alldatasheet

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——___ $ST89054 / SSTB9C5S8 / SST89C59_ Advance Information FEATURES: + Multi-Purpose 8-bit 8051 Family Compatible + High Current Drive on Port 1 (5, 6, 7) pins Microcontroller Unit (MCU) with Embedded + Three 1 Timer/Cou SuperFlash Memory for Flexibility ree 16-bit Timer , pon UART + Programmable Serial Po: + Fully Software and Development Toolset Compatible as well as Pin-For-Pin Package + Six Interrupt Sources at 2 Priority Levels Compatible with Standard &xC5x . lectab! fatchdog (woT) Microcontrollers Sel lew Timer . 12 Register RAM + Four 6-bit I/O Ports (32 I/O Pins) + 20/36/68 KByte Embedded High Performance * TTL and patible Logic Flexible SuperFlash EEPROM + Extended Power-Saving Modes — One 16/32/64 KByte block (128-Byte — Idle Mode sector size) — Power Down Mode with External Interrupt — One 4 KByte block (64-Byte sector size) Wake-up — Individual Block Security Lock — Standby (Stop Clock) Mode - 87C5x Programmer i er ‘i + Oto 33 MHz Operation at 5 Volts Supply - INCUI in ication om, Pe + Low Voltage (3V) Operation (0 to 12 MHz) — Memory Re-Mapping + PDIP-40, PLCC-44 and TQFP-44 Packages + Support External Address Range up to T are Ranges:

64 KByte of Program and Data Memory * Temperature manges:

ne — Commercial (0°C to +70°C) — Industrial (-40°C to +85°C) PRODUCT DESCRIPTION counter and used as an independent E*like data memory. The flash memory blocks can be programmed SST89C54, SST89C58 and SST89C59 are members of via a standard 87C5x OTP EPROM programmer or a the FlashFlex51 family of 8-bit microcontrollers. The standard flash EEPROM memory programmer fitted FlashFlex51 family is a family of embedded with aspecial adapter and firmware for SST89C54/58/59 microcontroller products designed and manufactured on devices. During the power-on reset, the SST89C54/58/ the state-of-the-art SuperFlash CMOS semiconductor 59 can be configured as a master for source code process technology. storage or as aslaveto anexternal host for In-Application As a member of the FlashFlex51 controller family, the Programming™ (IAP) operation. SST89C54/S8/59 is SST89C54/58/59 uses the same powerful amweion designed to be programmed “in-place” and “in-opera- set, has the same architecture, and s pin-for-pincompat- tion” on the printed circuit board assembly for maximum ible with standard 8xC5x microcontroller devices flexibility. ' The highly reliable, patented SuperFlash technology and SST89C54/58/59 comes with 20/36/68 KByte of : integrated on-chip flash EEPROM program memory _‘ Memory cell have anumber of important advantages for using the patented and propnetary Silicon Storage designing and manufacturing flash EEPROMs, when Technology, inc. (SST) CMOS SuperFlash EEPROM ©°Mpared with other approaches. These advantages technology with the SST field enhancing tunneling translate into significant cost and reliability benefits for injector split-gate memory cells. The SuperFlash UF customers. memory is partitoned into 2 independent program In addition to 20/36/68 KByte of SuperFlash EEPROM memory blocks. The primary SuperFlashblock occupies = program memory on-chip, the SST89C54/58/59 can 16/32/64 KByte of internal program memory space and —_ address up to 64 KByte of program memory extemal to the secondary SuperFlash block occupies 4 KByte of the chip, The SST89C54/58 have 256 x 8 bits of on-chip SST89C54/58/59's Internal program memory space. RAM, and the SST89C59 has 512 x 8 bits of on-chip The 4 KByte secondary SuperFlash block can be RAM. Up to 64 KByte of external data memory (RAM) Mapped to the highest or lowest location of the 64 KByte can be addressed. address space, it can also be hidden from the program

tty, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information TABLE OF CONTENTS MCU Core on. .cccssesesssestessesseessssnesesnsssssnsansasscnssnsseneesscusessesessscnuesuseusenseaneneesnssussussuesnesssassesnsesecnsanesssssvsereaneesecsse © Dat MEMOTy «0.0... ccsseesseeecessseseseesseenneessesssseeneessnessseessessnecesacsncereessecsssesneesseesisecstsssieenteceiseesisssneestessseecseesse 15) TIM@P/COUNKELS SERS w..seesecsecssessseensensenneevecneeneensenecnsssseneeenecnsenssneenssansssaneensearensseresnssnsssersenneeereaeeereeesees 16, INtOrACE SERS... cece eeeeecneceeeeseeeesnesneencenceneenecseeresneesecssenessessresnessseenssstsneseenssacsnesnessissessicesseerecssees 16 POI eeccesssssssssesessssnssssssssssosenessssssssesunssessseesusnessseeesisessesenensussssseesnussesseeesuntessunsassseeeenees 25 Interrupt Priority LEVEIS oo... ccecssseessssesssesescsesescscsescessescscseecevsvssevaneceseesesstacatesesanssecevscecersnsacavsesestevscaeeesavees OO {© 1999 Silicon Storage Technology, ne 2 325-22 1198

SST89C54 / SST89C58 / SST89C59 ae Advance Information Operation RANGE 0... cc ceceeceeseceesnesneesecseeseesseescesesneesseseessssessesnesnesnesestssnssisesecstasesseesasncietsecseereeseeseeseests OO) Sieee Sion Siowge Teme

tly, or FlashFlex51 MCU i SST89C54 / SST89C58 / SST89C59 Advance Information FUNCTIONAL BLOCKS Functionat Biock Diacram Program/Erase | SuperFlash SuperFlash EEPROM 8 & IAP EEPROM rT ersDIedK x 8 Pio Control 4K x8 RST Power Mode one vo Vss Management a6 a roy! Vpb cPU il ALE/PROG# 8 PSEN# Bus Controller oa Port 2 Pio loscilat g oe | Mode Interrupt RAM 8-bit Port 3 Pp vo Tri Control | Control 256/256/512 x 8 UART iming XTAL1 XTAL2 $25 ILL BI.10 {© 10999 Silicon Storage Technology, Inc a 325-22 1198

tlt, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 a Advance Information MCU Core PA[0:7) Fier nit XTAL1 XTAL2 MEERA AEEEIEL y | Port 3 Port 1 Drivers Drivers Latch Latch > PSEN# 2 &| Timing = ALE DPTR @ | 0 Ll eae & 3'| Control ag Lt ast [Program Pointer Counter| Register PC Incrementer Interrupt, Serial Port and Timer Blocks Program Addr. Register| SFR Addr. Port 2 Port 0 a2 Register Latch Latch gz ee Port 2 Port 0 Drivers Drivers Flash EEPROM SFR Address&@ Flash & SFR . RAM RAM Address & Control! Control Signals Data Bus P2(0:7] Pol0.7] Data Bus Address & Control

325 LL E25

tty, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information PIN ASSIGNMENTS gags priE 2 39 [7] P00 (Ado) Ecceco See ee Prat |s 38[_] Po.t (aD1) OUI prsL]4 37[-] Po.2 (AD2) 6 44 43 42 41 40 99 98 37 96 35 Bt Pi4[|5 36] ] Po.3 (AD3) pisL]i 337] Po.4 (AD4) Pis[ |e 35[/] Po.4 (AD4) pr6Lj2 32|_] Po.5 (ADs) P1.6[ 17 go.pin ppip 3+] P05 (ADS) pi.7L]3 31 |] P06 (ade) P177]8 ‘Topview 33{_] P0.6 (ADs) rst(]4 30 |] Po.7 (ab7) rst[_]o 32[/] Po.7 (AD7) (Axo) p3.0L]5 . 2a[] caw (Axo) P3.0 [_] 10 3i{-] eae no(]o 44-Pin TOFP 28[7] no (Txo) P34 [| 14 30[] ALE/PROG# crxo) p31 E47 Top View 27 7] aveproce (INTo#) P3.2[_] 12 L_] een (into) P3.218 26|_] PSEN# (71) P35 L] 15 26[ | P25 (A13) ry past za] pasaaia) wa Feet tte in resin 12.19 14 15 16 17 18 19 20 21 22 (ROW P3.7 |) 17 QWUOUUUOUOUUUUO xTAL2 [_] 18 23[] P2.2(A10) 5958985985 xTaut [_] 19 22[ | P2.1 (A9) £Eeggr Tee eae = eegeca vss [_] 20 2i[] P20 (a8) ge¢ S2ZzE = SOS ILL FICS masuLries Figure 1: Pin Assicnents For 40-Pin PLastic DIP Ficure 2: Pin Assignments For 44-Pin TQFP efag 8aag gece taane enaa ~~ rr er tr Oo BSsSo 85 zrirrteraezSe &22 CULV AT CAE AE AVE 6 5 4 3 21% 44 43 42 41 40 pisL]7 ° 39 |_] Po.4 (AD4) Pi6[]s 38 |_] Po.5 (AD5) pi7Li9 37 [_] Po.6 (Ade) rst L] 10 36 [_] Po.7(AD7) (Rxp) P3.0 J 11 44-Pin PLCC 35 [_] Eat ne [J 12 Top View 34 (_] ne (Txp) P3.1 (_] 13 33 [_] ALE/PROG# (INTO#) P3.2 [_] 14 32 [_] PSEN#t 18 19 20 21 22 23 24 25 26 27 28 UUUUUUUOUUOUU espsaseeguges 2ReEErT RRR AE ee xX egeoca ge aa 325 LL F20.3 Ficure 3: Pin AssicnmeNts For 44-Pin PLCC Note: NC pins must be left unconnected {© 10999 Silicon Storage Technology, Inc 6 325-22 1198

tlt, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information TasLe 1: Pin Descriptions PO[7:0] vot Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pull-ups when transitioning to 1’s. Port 0 also receives the code bytes during FLASH MEMORY programming, and outputs the code bytes during program verification. External pull-ups are required during program verification. P1[7:0] /O with internal | Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 pull-ups output buffers can drive LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (lit, on the data sheet) because of the internal pull-ups. P1(5, 6, 7) have high Current drive of 16 mA. Port 1 also receives the low-order address bytes during FLASH MEMORY programming and program verification. P2[7:0] 1/O with internal | Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins pull-ups that have 1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (li, on the data sheet) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application it uses strong internal pull-ups when outputting 1’s. During accesses to external Data Memory that use 8-bit addresses (MOVX@Ri), Port 2 sends the contents of the P2 Special Function Register. Port 2 also receives some control signals and a partial of high-order address bits during FLASH MEMORY programming and program verification. P3[7:0] /O with internal | Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 pull-ups output buffers could drive LS TTL inputs. Port 3 pins that have 1’s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (li_, on the data sheet) because of the pull-ups. Port 3 also serves the functions of various special features of the FlashFlex51 Family. Port 3 also receives some control signals and a partial of high-order address bits during FLASH MEMORY programming and program verification. [P31 |__| TXD:Serial output line [ps2 | INTO#: External Interrupt 0 [P33] INT1#: External Interrupt 1 [P34 TO: Timer 0 external input [P35 ft 71: Timer 1 external input [P36 | =O ‘| _ WR#: External Data Memory Write strobe [P37__| 0 _| D#: External Data Memory Read strobe PSEN# O/ Program Store Enable: PSEN# is the Read strobe to External Program Memory. When the SST89C 54/58/59 are executing from Internal Program Memory, PSEN¢# is inactive (high). When the device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, except that two PSEN# activations are skipped during each access to External Data Memory. While the RST input is continually held high (for more than ten machine cycles), a forced high-to-low input transition on the PSEN# pin will bring the device into the “External Host” mode for the internal flash memory programming operation. ‘01900 Slicon Storage Technology Ins——SSCSCSCSSSSSSSSSS TIO 7 32522 1198

tty, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information Pin DescRIPTIONS (CONTINUED) RST Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum Vixi voltage is applied whether the oscillator is running or not. An internal pulldown resistor permits a power-on reset with only a capacitor connected to Vpp. After a successful reset is completed, if the PSEN# pin is driven by an input force with a high-to-low transition while the RST input pin is continually held high, the device will enter the “External Host” mode for the internal flash memory programming operation, otherwise the device will enter the “Normal” operation mode. EA# External Access Enable: EA# must be strapped to Vss in order to enable the SST89C54/58/59 to fetch code from External Program Memory locations starting at 0000h up to FFFFh. Note, however, that if the Security Lock is activated on either block, the logic level at EA# is internally latched during reset. EA# must be strapped to Vpp for internal program execution. The EA# pin can tolerate a high voltage? of 12V (see Electrical Specification). ALE/PROG# vO Address Latch Enable: ALE is the output signal for latching the low byte of the address during accesses to external memory. This pin is also the programming pulse input (PROG#). XTAL1 Oscillator: \\nput and output to the inverting oscillator amplifier. XTAL1 is input to XTAL2 internal clock generation circuits from an external clock source. Vop Power Supply: Supply voltage during normal, Idle, Power Down, and Standby Mode operations. ee ee Ground: Circuit ground. (OV reference) Note: 1) | = Input $25 FOMTI.10 O = Output 2) Its not necessary to receive a 12V programming supply voltage during flash programming. {© 10999 Silicon Storage Technology, Inc 3 88522198

getty, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ae Advance Information MEMORY ORGANIZATION The 4 K by 8 secondary SuperFlash block is organized as 128 rows (64 of 64-Byte sectors/pages, 7 X-address The SST89C54/58/59 has separate address spaces for lines) and 128 columns (32 Bytes per row, 5 Y-address program and data memory. lines). When internal code operation is enabled (EA# = 1), the Program Memory secondary 4 KByte flash memory block is only visible There are two internal flash memory blocks in the during In-Application Programming operation, otherwise SST89C54/58/59. The primary flash memory block it is hidden from the program counter. The secondary (Block 0) has 16/32/64 KByte and occupies the address block is accessible through the SuperFlash mailbox space 0000h to 3FFFh/7FFFh/FFFFh. The secondary registers: SFCM, SFCF, SFAL, SFAH and SFDT. When flash memory block (Block 1) has 4 KByte and occupies bit 7 of the SuperFlash Configuration/Status mailbox the address space F000h to FFFFh accessible through register (SFCF:7), SFR address location B6h, is set, the In-Application Programming. secondary 4 KByte block will be available for code The 16 K by 8 primary SuperFlash block is organized as fetching. 256 rows (128 of 128-Byte sections/pages, 8 X-address The primary 16/32/64 KByte flash memory block is lines) and 512 columns (64 Bytes per row, 6 Y-address always visible to the program counter for code fetching. lines). After the hardware resets, if the external enable is not The 32 K by 8 primary SuperFlash block is organized as asserted, EA# = 1, the MCU starts program execution from the lowest address space of the primary block, 512 rows (256 of 128-Byte sectors/pages, 9 X-address lines) and 512 columns (64 Bytes per row, 6 Y-address unless the secondary block is re-mapped to the lowest lines) , address space. Figure 4, 5 and6 showprogram memory : organizations for the SST89C54/58/59. The 64 K by 8 primary SuperFlash block is organized as 1024 rows (512 of 128-Byte sectors/pages, 10 X-ad- dress lines) and 512 columns (64 Bytes per row, 6 Y- address lines). EA# = 1 & SFCF:7 =1 EA# = 1 & SFCF:7 =0 EA#=0 FFFFH (ae FFFFh FFFFh INTERNAL F000h (Block 1) EFFFh

48 KByte

44 KByte EXTERNAL

16 KByte 16 KByte

(Block 0) (Block 0) o000h 0000h 0000h SOS ILLFa12 Fiaure 4: SST89C54 Procram Memory OrGaNizaTION ‘1900 Slicon Storage Technology ins——SSCSCSCSCSSSSSS TT 9 32522 198

tly, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information EA# = 1 & SFCF:7=1 EA# = 1 & SFCF:7 =0 EA# =0 FFFFh aie FFFFh FFFFh INTERNAL FOOOh (Block 1) EFFFh 32 KByte EXTERNAL

28 KByte

64 KByte

32 KByte 32 KByte

(Block 0) (Block 0) 0000h 0000h 0000h S25 ILL FIt2 Figure 5: SST89C58 Procram Memory OrcanizaTion EA# = 1 & SFCF:7 =1 EA# = 1 & SFCF:7 =0 EA#=0 FFFFh Byte FFFFh FFFFh INTERNAL Foooh L__@eck 1) EFFFh

60 KByte 64 KByte" 64 KByte

(Block 0) (Block 0) EXTERNAL 0000h 0000h 0000h * An additional 4 KByte is accessible through the SFAs during In-Appication Programming, Sasi F223 Ficure 6: SST89C59 Procram Memory OrcanizaTION {© 1999 Silicon Storage Technology, ne to 325-22 1798

git, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information Memory Re-mapping The SST89C54/58/59 memory re-mapping feature will reassigned, any flash accesses within the address allow users to reorganize the internal Flash memory range of 0000h — OFFFh will have the uppermost 4 sectors so that interrupts may be supported/serviced address bits interpreted as ones, redirecting the access when an In-Application Programming operation is in to FO00h—FFFFh range on the address map. Therefore, progress. When re-mapping is enabled, up to 4 KBytes the reassigned physical flash memory will have dual of flash memory from the Block 0 will be reassigned to (virtual) addresses. Figure 7, 8 and 9 shows re-mapped overlay the address space of Block 1. If 4 KBytes are program memory organizations for SST89C 54/58/59. EA# = 1 & SFCF:7=1 EA# = 1 & SFCF:7 =0 Addr:FFFFh=8Xh Addr:FFFFh=8Xh FFFFA eye FFFFh INTERNAL F000h |_(Block 1) EFFFh

44 KByte

(Block 0) (Block 0) 1/2/4 KByte 1/2/4 KByte INTERNAL INTERNAL oooon| (Beck) oooon | (Beck?)

325 ILL F361

Figure 7: SST89C54 Re-Maprep Procram Memory OncanizATION Sess SHconsiraa TERME gE

tly, or FlashFlex51 MCU i SST89C54 / SST89C58 / SST89C59 Advance Information EA#=1&SFCF:7=1 EA#=1&SFCF:7=0 Addr:FFFFh=8Xh Addr:FFFFh=8Xh FFFFh TT Byte FFFFh INTERNAL F000h L_(Block 1) EFFFh

32 KByte

EXTERNAL| 8000h 8000h 7FFFh 7FFFh 31/30/28 31/30/28 KByte KByte INTERNAL INTERNAL (Block 0) (Block 0) 1/2/4 KByte 1/2/4 KByte INTERNAL INTERNAL oooon | ‘Bleck 1) oooon| ‘Beck 1) Figure 8: SST89C58 Re-Mappep Procram Memory OrcanizaTION {© 10999 Silicon Storage Technology, Inc 2 325-22 1198

tlt, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information EA# = 1 & SFCF:7 =1 EA# = 1 & SFCF:7=0 Addr:FFFFh=8Xh Addr:FFFFh=8Xh FFFFR Byte FFFFh INTERNAL F000h L_(Block 1) EFFFh 59/58/56 KBye. KByte INTERNAL NL (Block 0) 1/2/4 KByte 1/2/4 KByte INTERNAL INTERNAL oovon| Bleck 1) ooooh| (Bleck 1) 325 ILL FS7.1 Figure 9: SST89C59 Re-Maprep Procram Memory OncaNizaTION Activation and Deactivation of Memory Re-mapping only take effect at the next MCU reset. The configuration The Re-Map Enable Control (RMEC) bit located in bit [7] of the re-mapped memory may be altered at any time of Flash memory location FFFFh activates the Re- after a Power-On Reset by programming the MAP_EN mapping feature. A “O” programmed to the RMEC loca- byte located in the SFCF [1:0] register with value listed in tion turns on re-mapping. A “1” disables all re-mapping Table 2. and pam fash memo “he oeaap tr Ol bie. ‘n fash To deactivate memory re-mapping, a CHIP ERASE 9 gt i ap [1 — operation will reprogram the REMC bit with a “1”, and memory location FFDFh determines the size of the : disabling the re-mapping feature. Programming 00h to memory sector to be remapped. Figure 10 shows the the SFCF [1:0 ister thi hIn-Application Pi location of REMC and Re-Map bits. Re-mapping will be e [1:0] register through In-Application rogram- were " - ming Mode may also deactivate memory Re-mapping, initialized according to the contents in REMC and Re- Map [1.0] bits after a successful reset. See Table 2 note that upon the next reset, the contents on REMC and Once the device completes the reset initialization pro- for [1:0] will again determine the contents of SFCF cess, altering the contents of REMC and Re-Map bits will ” B1RRe Silom SioageToemMOIG ME

tty, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information FFFFh p= ees. MSB LSB rooon | BLOCK 1 ect Sea EFFFH Soe een 325 ILL F34.1 Figure 10: Location of REMC anp Re-map sits TasLe 2: RE-MAPPING TABLE Re-mapping is turned off. Program memory is in normal oi configuration 10 01 1 KByte of flash memory location is re-mapped. Address location 0000h-03FFh is re-mapped to FO00h — F3FFh. 01 10 2 KBytes of flash memory location are re-mapped. Address location 0000h-07FFh is re-mapped to FO0Oh — F7FFh. 11 4 KBytes of flash memory location is re-mapped. Address location 0000h-OFFFh is re-mapped to FO00h — FFFFh. Re-Map Enable Control (REMC) is bit [7] of flash memory address location FFFFh 2 Re-Map [1:0] are the lowest bits in flash memory address FFDFh. 3 MAP_EN bits are located in the SFR SuperFlash Configuration/Status register, SFCF [1:0]. + Re-mapping will be enabled according to the contents of REMC and Re-Map during the reset process. 5 Re-mapping configuration may be altered through the SFCF [1:0] register during In-Application Programming after power up. {© 10999 Silicon Storage Technology, Inc 14 88S

git, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ae Advance Information Data Memory SST89C54/58/59 have 256/256/512 x 8 bits on chip RAM and can address up to 64 KByte of off-chip data memory. Special Function Registers (SFR) Mostof the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the FlashFlex51 SFR Memory Map shown below. Individual descriptions of each SFR are provided and Reset values indicated in Tables 3a to 3c.

8 BYTES

i Fol pe fy 9 0 Eofaccs [fe ed I Cd a cal taco] [Rcapat[rcapan[ Tle [tHe [ [| CF cof[worc[ fT cz sete [tT BF Bo[ _ps* | [srcm|sra. [sraq [sot | sece[ | 87 Cd a a ss{scon|ssur[ ff TF sof pr [of ft yf 97 ss{tcon'{Twop[ tio [ui [rHo [tHi [| ar sof por [ sp [ore [opH [| [worp [Poon | 87 FlashFlex51 SFR Memory Map * = BIT ADDRESSABLE All addresses are hexadecimal 326 ILL F23.2 SST89C54/58/59 Special Function Registers Tasie 3a: CPU RELATED SFRs [Syme Description Bit Address, Symbol, or Alternative Port Function RESET Address|_MSB LSB Value [e [BRegister | Fon | 87 | 86 | 85 | 64 | 83 | 82 | 81 | BO | On PSW* | Program Status DOh CY AC FO RS1 RSO ov FA P 00h Word [s? [Stack Pointer | _ath_| FH oh DPL Data Pointer 82h DPL[7:0] 00h Low 0 Data Pointer 83h DPH[7:0] 00h High 0 [ie [intereupt Enabie | Aan | EA] - | €72 | ESO | eT) | ExT] ETO | EXO | Ooh [1p [intenrupt Priorty | Ban |_- | - | Pr2 | ps | Pt | xt] PTo | PXO | mov00008 25 POM TOA.1

11900 Slicon Storage Technology, Ine gg 8 32522 198

efit, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information Tase 38: FLasH Memory Procramminc SFRs Symbol | Description Direct Bit Address, Symbol, or Alternative Port Function RESET Address|_ MSB LSB Value Pe eed eT TT Configuration/Status| Command Address Low Address High 325 PGM 98.4 Taste 3c: Cup OperationaL SFRs [PCON | Power Controt | a7 [ SWOD] - | - | -] GFi] GFO] PD | TOL | oon00oe8| ad a Da id ll Control Data/Reload 325 PGM T8C.2 Taste 3p: Timer/Counters SFRs TMOD J Timer/Counter 9h elcome | OY eee eee Control Control 825 PGM T9D.0 Taste 3e: InterFace SFRs | SCON’ | Serial Port Control | ean | smo | smi | sm2 | ReN | Tes] Res] Ti | Ri | oon | [ro [rono _—+| aon | por | po | pos| po | po3| po2| poi | poo | FFn | [Po [Pon2 | Aon | Pav | p26 | Pas | Poa | pea] p22 | P21 | P20 | Fh | [Pa [Pons | Bon | _RD# | wRe| Ti | To | wre] inTor| TxD0| AXDO | FH | * SFRs are bit addressable 325 PGM T9E.0 SraReSiiconStoage Tec RH

; stn, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information FLASH MEMORY PROGRAMMING Port 1 pins are assigned to be the non-muxed low order , address bus signals for the internal flash memory (A0- The aiden nme internal fash memory cart be A7). The first six bits of Port2 pins (P2[0:5]) are assigned Programmed or erased using tne following two methods: —_ ta he the non-muxed upper order address bus signals for + — External Host Mode (parallel only) the internal flash memory (A8-A13) along with two of the + — In-Application Programming (IAP) Mode Port 3 pins (P3.4 as A14 and P3.5 as A15). Two upper (parallel or serial) order Port 2 pins (P2.6 and P2.7) and two upper order Port 3 pins (P3.6 and P3.7) along with RST, PSEN#, EXTERNAL HOST PROGRAMMING MODE PROG#/ALE, EA# pins are assigned as the control , F . signal pins. The Port 3 pin (P3.3) is assigned to be the icdbsiaaiaren Se praviie thewee: wivadinectiiaeh ready/busy status signal, which can be used for hand- thetlasn access vthout e ‘ath CPU thediroctrlash shaking with the external host during a flash memory le asmemory wit nt ed e th : Ext inal Host programming operation. The flash memory program- Mode. While the 's et rere t asp ine nual held ming operation (Erase, Program, Verify, etc.) is internally ode. Ne the reset input ( } is con tnually ne self-timed and can be controlled by an external host active (high), if the PSEN# pin is forced by an input with asynchronously or synchronously a transition from high-to-low state, the device enters the . External Host Mode arming state at this time. The CPU The insertion of an “arming” command prior to entering core is stopped from running and all the chip I/O pins are the External Host Mode by utilizing the “READ ID” reassigned and become flash memory access and con- operation provides additional protection for inadvertent trol pins. At this time, the external host should initiate a writes to the internal flash memory cause by a noisy or “READ-ID” operation. After the completion of the unstable system environment during the power-up or “READ-ID” operation, the device is armed and enters the brown-out condition. exiernal ost Hi ove. ater ihe dev ish enters mo ine The External Host Mode uses seven (7) hardware com- xternal sod thr °, h ne ferna’ fas a0 tor wi ‘S$ mands, which are decoded from the control signal pins, iol access\\ Fi re ti f iotails) by a t mal aie to facilitate the internal flash memory erase, test and (Pl she see f Wed ci it el ais) of an PC cont ile i _-Programming process. The External Host Mode is en- Sov lon a a dora orp MCU n a PC controtie abled on the falling edge of PSEN#. The External Host evelopment board or an Programmer. Mode Commands are enabled on the falling edge of ALE/ When the chip is in the external host mode, Port 0 pins PROG+#. The list in Table 4 outlines all the commands are assigned to be the parallel data input and output pins. and its control signal assignment. Taste 4: Externat Host Move Commanps Operation RST PROG# P2.7 P3.7 | PO[7:0] |P1[7:0]| P3[5:4] /ALE P2[5:0] READ ID H L H HEEL cy et | bo | AL AH CHIP ERASE H L U H H H H L x x x BLOCK ERASE H L U H H H H H x x AIS SECTOR ERASE H L U H H H L H Xx AL AH BYTE PROGRAM H L U H L H H H DI AL AH BURST PROGRAM H L U H L H L H DI AL AH VERIFY (Read) H L H H}| tL] Lt | HI] H } DO } aL AH BYTE

325 POM 2,7

Note: Symbol |! signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of the above input pins are invalid and may result in unexpected behaviors Note: —_IntEn = Interrupt Enable for flash operation completion; L = Logic low level; H = Logic high level; X = Don't care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output; A15 = Only care for the MSB, Le. address bit #15. B1RRe Sion Sioage Teoma

tly, or FlashFlex51 MCU Ha SST89C54 / SST89C58 / SST89C59 Advance Information Vas Voo RST XTALI | oe xm Pened oley f os ° 1 1 ale | Addross Bus Busy/Ready+4 3. Ports 4 adress Bus *Mefa 7 ® mens Las, oon Flash Contrl Signals -{ ,,) ° Peat [ : Ch ae EAt ALE/ PSENE PROGH

225 LL F017

Figure 11: 1/O Pins Assignment For Externat Host Mone Product Identification ; programmed must be in the erased state prior to The READ ID command accesses the Signature Bytes —_ programming. Selection of the Erase command to use, that identifies the device as an SST89C54/58/59 and the prior to programming the device, will be dependent upon manufacturer as SST. External programmers primarily the contents already in the array and the desired pro- use these Signature Bytes, shown in Table 5, in the gramming field size. selection of programming algorithms. The Read ID com- . mand is selected by the byte code of 00h on The CHIP ERASE command erases all bytes in both P2[6:7] and P3[6:7]. See Figure 12 for timing waveforms. memory blocks (16/32/60K and 4k) of the SST89C54/ 58/59. This command ignores the Security Lock status Taste 5: Sianature Bytes TasLe and will erase the Security Byte. The CHIP ERASE [~~~—~—~—CS | Address [Data | © commandis selected by the byte code of 0Eh on P2[6:7] Manufacturer's Code [30h | BFh | and P3[6:7]. See Figure 13 for timing waveforms. SST89C54 Device Code The BLOCK ERASE commanderases all bytes in one of SSTB9C5B Device Code the memory blocks (16/32/60K or 4K) of the SST89C54/ SST89C5O Device Code 58/59. This command will not enable if the Security Byte is enabled on the selected memory block. The selection S25 GPM TSS of the memory block to be erased is determined by A15 External Host Mode Commands (P3.5). If A15 is a “0”, then the primary flash memory The seven SST89C54/58/59 External Host Mode Com- —_bigck (16/32/60K) is selected. If A15 is a “1”, then the mands are READ ID, CHIP ERASE, BLOCK ERASE secondary flash memory block (4K) is selected. The SECTOR ERASE, BYTE PROGRAM, BURST PRO- —_— BLOCK ERASE command is selected by the byte code GRAM, and VERIFY BYTE. The following is a brief of OFh on P2[6:7] and P3[6:7]. See Figure 14 for the description of the commands. See Table 4 for all signal timing waveforms. logic assignments and Table 7 for all timing parameter values for the External Host Mode Commands. The The SECTOR ERASE command erases all of the bytes critical timing for all Erase and Program commands, is in asector. The sector size for the primary flash memory self-generated by the flash memory controller on-chip. (Address buffer locations 0-3FFFh/7FFFH/EFFFh) is The high-to-low transition of the PROG# signal initiates 128 Bytes. The sector size for the secondary flash the Erase and Program commands, which are synchro- Memory (Address buffer locations FO00h-FFFFh) is 64 nized internally. The Read commands are static reads, bytes. This command will not enable if the Security Byte independent of the PROG# signal level. is enabled on the selected memory block. The selection . of the memory sector to be erased is determined by The following three commands are for erasing all or part P2[0:5] (A8-A13) and P3[4:5] (A14 & A15). The SEC- of the memory array. All the data in the memory array will TOR ERASE command is selected by the byte code of be erased to FFh. Memory addresses that are to be ODh on P2[6:7] and P3{6:7]. See Figure 15 for timing waveforms. ‘©1999 Silicon Slorage Techrowgyna SSS TO 18 R522 199

SST89C54 / SST89C58 / SST89C59 aa Advance Information The following two Program commands are forprogram- — 1._ PSEN# goes low while RST is high. This will get ming new data into the memory array. Selection of which the machine in External Host Mode, re-configur- Program command to use for programming will be de- ing the pins. pendent upon the desired programming field size. The ni Program commands will not enable if the Security Byte 2: A read command I issued ara held for 1 ms. is enabled on the selected memory block. Is 1s actually a natural step for the programmer, but will also serve as the arming command. The BYTE PROGRAM command programs data into a single byte. Ports P0[0:7] are used for data in. The After the above snebled Bi a oner Reeatriost Mode memory location is selected by P1[0:7], P2[0:5], and ‘erecaived allothe A fe val He iv ‘ead _| ds rewaive 4 P3[4:5] (AO-A15). The BYTE PROGRAM command is © recelved, other External Host commands receive selected by the byte code of 07h on P2{6:7] and P3{6:7]. are ignored. See Figure 16 for timing waveforms. Programming a SST89C54/58/59 The BURST PROGRAM command programs datatoan ‘To program new data into the memory array, supply 5 entire row, sequentially byte by byte. Ports PO[0:7] are volts to Vpp and RST, and perform the following steps. used for data in. The memory location is selected by P1[0:7], P2[0:5], and P3[4:5] (AO-A15). The BYTE 1: Enable RST, and denne in sequence per the PROGRAM command is selected by the byte code of appropriate timing diagram. 05h on P2[6:7] and P3[6:7]. See Figure 17 for timing 2. Raise EA# High (either Vin or Vu). aveforms. wav 3. Read the device and manufacturer ID using the The VERIFY BYTE command allows the user to verify READ ID command to ensure the correct that the SST89C54/58/59 correctly performed an Erase programming algorithm. or Program command. Ports PO[0:7] are used fordata yin ,; F out. The memory locationis selected by P1[0:7], P2[0:5], ~ Verify that the memory blocks or ectors or pro- and P3[4:5] (A0-A15). This command will not enable if grammingisint e erased State, i they are not the Security Byte is enabled on the selected memory erased, then erase them using the appropriate block. See Figure 18 for timing waveforms. rase command. If an External Host Mode Command is issued to a 5. mejeatmme memory rocation using the address lines secured memory block, the device will immediately reset (P1[0:7], P2[0:5], P3[4:5)). and be ready for another command. 6. Present the data in on PO[0:7]. External Host Mode Clock Source 7. Pulse ALE/PROG#. During External Host Mode, an internal oscillator will 8. Wait for low to high transition on READY/BUSY# provide clocking for the SST89C 54/58/59. The on-chip (P3(3)). oscillator will be turned on as the SST89C54/58/59 9 R 5—8 until ing is finish enters External Host Mode; i.e. when PSEN goes low . Repeat steps 5 — 8 until programming is finished. while RST is high. The oscillator will have a center 10. Verify the flash memory contents. frequency of 10 MHz and will provide both clocking for the Flash Control Unit as well as timing references for Program and Erase operations. During External Host Hawleher Status Detection (Ext. Host Mode, the controller core is being held in reset. Upon exit . . 5 The SST89C54/58/59 provide two firmware means for of External Host Mode, the nternaloscillatoristumedoff. a" gytemal host to detect the completion of a flash The same oscillator also provides time base for the memory operation, therefore the external host can opti- watchdog timer and timing references for IAP Mode __ mize the system Program or Erase cycle of the embed- Program and Erase operations. See more detailed de- ded flash memory. The end of a flash memory operation scription in later sections. cycle (Erase or Program) canbe detected by: 1) monitor- ing the Ready/Busy# bit at Port 3.3; 2) monitoring the Arming Command Data# Polling bit at Port 0.7 or Port 0.3. An arming command must take place before External Host Commands will be recognized by the SST89C54/ 58/59. This is to prevent accidental triggering of External Host Commands due to noise or programmer error. The arming command is as follows: BiaRe Silom Siomge oem

u SST89C54 / SST89C58 / SST89C59 Advance Information The progress of the flash memory programming canbe _ its “0”. During a Burst Program operation, the Verify monitored by the Ready/Busy# output signal. P3.3 is Byte command is reading the data of the last byte driven low, sometime after ALE/PROG#goes lowduring Programmed, not the data at the address specified. a flash memory operation to indicate the Busy# status of The true data will be read from PO.7, when the device the flash programming controller. P33 is driven high completes each Byte Program among the Burst Pro- when the flash programming operation is completed to grams to indicate the Ready status to receive the next indicate the Ready status. byte. When the external host detects the Ready status During a Burst Program operation, P3.3 is driven high _fter a byte among the burst is programmed, it should (Ready) inbetweeneachByte ProgramamongtheBurst _then put the data/address (in the same page) of the next Programsto indicate the ready status toreceivethenext byte on the bus and drive ALE/PROG# low (pulse) byte. When the external host detects the Ready status immediately, before the time-out limit expires (See pro- after a byte among the burst is programmed, it may then gramming time spec. for details.). The true data will be put the data/address (in the same page) of the next byte read from P0.3, when the Burst Program command is on the bus and drive ALE/PROG# low (pulse) immedi. _ terminated and the device is ready for the next operation. ately, before the time-out limit expires The termination of the Burst Program can be accom- ; plished by: 1) Change to a new X-Addresses (Note: the Data# Polling (P0.7 & P0.3) X-Address range are different for the 4Kx8 flash block During a Burst Program operation, any attempts to read and for the 16/32/60K x 8 flash block.); 2) Change to a (Verify Byte), while the device is busy programming the new command that requires a negative transition of the byte among the Burst Programs, will receive the comple- ALE/PROG# (i.e. any Erase or Program command); 3) ment of the data of the last byte programmed (logic low, Wait for time out limit expires (20 ps); when programming the next byte. Flash Memory Programming with External Host Mode (Figures 12-18) RST TSU PSEN# Se EA# = TRD TRD P2[6:7] ,P3[6:7] [Koh OK 0H >*K P3[5:4] ,P2[5:0],P1 [SX 30h KH FX PO [XK BFh Kaveh XK 825 ILL F2.10 Figure 12: Reap ID Read chip signature and identification registers at the addressed location. BS ioea con SoageTemoeeR Re

SST89C54 / SST89C58 / SST89C59 ae Advance Information ast PSEN# = \\_ G I: ALE/PROG# SS | Tce P33 Sr LY P2{6.7], P3[6:7]

325 ILL F031

Figure 13: Cup Erase Erase both flash memory blocks. Security lock is ignored and the security byte is erased too. a a PSEN# \\ gg —Htesd-— ALEPROGH ar TproG DH | + Tpe P33 5 P2[6:7], P3{6:7] P35 es | 3251LL Fos. Figure 14: Block Erase Erase one of the flash memory blocks, if the security lock is not activated on that flash memory block. The highest address bit (A15) determines which block is erased. For example, if A15 is “O", primary flash memory block is erased. ‘51989 Silicon Storage Technology, Ine 2 3e522 1798

stn, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ae Advance Information PSEN# Tg. $$$ Es ALE/PROGH a a I——5 TPROG >| Tp, TOH, TDH, P33 Ss | Fest Rept Rep = X address 2 Xaddress Y address Po SS | 32K Block —® X address = AH, AL{7], AL{6]; Y address = AL(5:0] sess Fors 4K Block —e X address = AH, ALI7, 6,5]; Y address = AL[4:0] Ficure 17: Burst PRocRaM Program the entire addressed row by burst programming each byte sequentially within the row if the byte location has been successfully erased and not yet programmed. This operation is only allowed when the security lock is not activated on that flash memory block. RST TSU PSEN# ALE/PROG# EA# Toa Pa[7:6], Pa7:6) L_X Ph TAHA PO C po Pr LX p3[s:4], P20] LK 325 ILL FO8.7 Figure 18: VERIFY BYTE Read the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. ‘51989 Silicon Storage Technology, Ine 23 3e522 1798

tty, or FlashFlex51 MCU i SST89C54 / SST89C58 / SST89C59 Advance Information IN-APPLICATION PROGRAMMING MODE In-Application Programming Mode Commands Allofthe following commands can only be initiated in the The SST89C54/58/59 offers 20/36/68 KByte of in-appli- IAP Mode. In all situations, writing the control byte to the cation re-programmable flash memory. During In-Appli- (SFCM) register will initiate all of the operations. All cation Programming, the CPU of the microcontroller commands (except CHIP ERASE) will not be enabled if enters IAP Mode. The two blocks of flash memory allows the Security Byte is set and security features are enabled the CPU to concurrently execute user code from one on the selected memory block. The critical timing for all block, while the other is being reprogrammed. The CPU Erase and Program commands, is self-generated by the may also fetch code from an external memory while all Flash memory controller on-chip. external program code execution being enabled (EA# = data into the memory array. The portion of the memory b " 7 = array to be programmed should be in the erased state, ) oF disabled (EA#=H). The mailbox registers (SFCM, FFh. If the memory is not erased, then erase it with the SFAL, SFAH, SFDT and SFCF) located in the Special 7 ry nea Function Register (SFR), control and monitor the appropriate Erase command. Warning: do not write device's erase and program process. (program or erase) to a block that the code is currently . fetching from. This can “hang” the CPU and may even There are six (6) IAP commands plus a setup command, corrupt program data as it is being executed. which can be issued via the command mailbox register, - SFCM at SFR location B2h. A pair of mailbox register Marnory blocks (1QB264K ane ak) “tne command addresses the memory array of the SuperF lash blocks: ignores the Security Lock status and will erase the SFAL, low order address at SFR location B3h, and Security Byte and Re-Map Byte. The CHIP ERASE SFAH, the high order address at SFR location B4h. Data - initiated as f 10 — is buffered through the SFDT register at SFR location Command's initiated as Tollows: B5h. SFCF, the configuration register at SFR location 1.) Move 55h to the SuperFlash Data Register (SFDT) B6h, provides security lock status program counter and (i.e. “MOV SFDT, #55h” where SFDT is the register visibility to the secondary flash memory block. The list in address). This serves as a dual level precautionary Table 6 outlines all the commands and their associated measure to prevent accidental chip erasure. bit settings of the mailbox registers. 2.) Move 5Dh or DDh to the SuperFlash Command Register (SFCM) (i.e., “MOV SFCM, #5Dh or MOV In-Application Programming Mode Clock Source SFCM, #0DDh’). This is a “setup command” se- During IAP Mode, both the CPU core and the flash quence prior to Program and Erase operations to controller unit run off the external clock input. However, prevent inadvertent program or erase within the an internal oscillator will provide timing references for SuperFlash memory. Program and Erase operations. In fact, the timing of 3.) Move the termination mode FIE and Chip Erase Program and Erase operations will be identical between command FCM to the SuperFlash Command Regis- External Host Mode and In-Application Mode. The inter- ter (SFCM) (i.e. MOV SFCM, #87h or MOV SFCM, nal oscillator is only turned on when required, it is turned #07h). If FIE is set, INT1# will interrupt the system off as soon as the Flash operation completes. when the erase is complete. Otherwise you must poll the system to determine when the erase is complete. Setup Command The Setup Command provides additional protection against code corruption of the SuperFlash memory. A Setup Command byte, 5Dh or DDh, must be pro- grammed into the SFCM register prior to issuing each of the IAP Mode command, otherwise, the IAP Mode com- mands will be ignored. The Setup Command is required for each individual IAP Command (except VERIFY BYTE) and is canceled after an execution of the IAP command. The Setup Command must be reinitialized when the system resets, including Watchdog timeout, or when the device exits from an idle or power down mode. {© 10999 Silicon Storage Technology, Inc 2A 325-22 1198

stn, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ae Advance Information The BLOCK ERASE commanderases all bytes in one of 4.) Move 5Dh or DDh to the SuperFlash Command the two memory blocks (16/32/64K or 4K). The selection Register (SFCM) (i.e., “MOV SFCM, #5Dh or MOV of the memory block to be erased is determined by the SFCM, #0DDh’). This is an “setup command” se- “A15" bit (SFAH[7]) of the SuperFlash Address Register. quence prior to Program and Erase operations to If (SFAH[7]) is a “O”, the primary flash memory block is prevent inadvertent program or erase within the selected (16/32/64K). If (SFAH[7]) isa‘“1”, thesecondary SuperFlash memory. flash memory block is selected (4K). The BLOCK 5.) Move the termination mode FIE and Byte Program ERASE command is initiated as follows: command FCM to (SFCM) (i.e. MOV SFCM, #8Eh or 1.) Move the block address to (SFAH) (i.e. MOV SFAH, MOV SFCM, #0Eh). If FIE is set, INT1# will interrupt the system when the program is complete. Otherwise #80h or MOV SFAH, #00h). you must poll the SFCF[3] register to determine when 2.) Move 55h to the SuperFlash Data Register (SFDT) the program is complete (ie. “MOV SFDT, #55h” where SFDT is the register Prog} piete. address). This serves as a dual level precautionary The BURST PROGRAM command programs data to an measure to prevent accidental erasure. entire row, sequentially byte by byte. The BURST PRO- 3.) Move 5Dh or DDh to the SuperFlash Command GRAM command is initiated as follows: Register (SFCM) (i.e., “MOV SECM, #5Dh or MOV , quence prior to Program and Erase operations to 3) Move the data to (SFDT) . prevent inadvertent program or erase within the 4) Move 5Dh or DDh to the SuperFlash C nd SuperFlash memory. Register (OFCOM) (re. MOV SECM, ASDh or MOV 4.) Move the termination mode FIE and Block Erase SroM, #oDDr" We. hana pale tse command FCM to (SECM) (i.e. MOV SFCM, #8Fh or uence rior to Pr ram and Erase operations to MOV SFCM, #0Fh). If FIE is set, INT1# will interrupt q ‘ Ls ‘vert he pe thin th the system when the erase is complete. Otherwise you Bupertl ish ‘ertent program or erase wilhin the must poll the SFCF[3] register to determine whenthe upert lash memory. erase is complete. .) Move the termination mode FIE and Burst Program command FCM to (SFCM) (i.e. MOV SFCM, #8Ah or The SECTOR ERASE command erases all of the bytes in MOV SFCM, #0Ah). If FIE is set, INT1# will interrupt a sector. The sector size for the primary flash memory the system when the program is complete. Otherwise (Address buffer locations 0-3FFFh/7FFFh/EFFFh) is 128 you must poll the SFCF[3] register to determine when bytes. The sector size for the secondary flash memory the program is complete. (Address buffer locations FO00h-FFFFh) is 64 bytes. The 6.) Wait for interrupt or poll for end of burst. SECTOR ERASE command is initiated as follows: 7.) If another Burst Program is needed return to step 4 1.) Move the sector address to (SFAH) and to (SFAL). (same row). 2.) Move 5Dh or DDh to the SuperFlash Command The VERIFY BYTE command allows the user to verify that Register (SFCM) (i.e., “MOV SFCM, #5Dh or MOV the SST89C54/58/59 has correctly performed an Erase or SFCM, #0DDh’). This is an “setup command” se- Program command. The VERIFY BYTE command is quence prior to Program and Erase operations to initiated as follows: prevent inadvertent program or erase within the 1.) Move the high order address byte AH to (SFAH). Superflash memory. 2.) Move the low order address byte AL to (SFAL) 3.) Move the termination mode FIE and Sector Erase 3) Move the termination mode FIE and Verify Byte com- MOV SFCM, #0Bh). If FIE is set, INT1# will interrupt SFCM, #0Ch) -_ , the system when the erase is complete. Otherwise you , . must poll the SFCF[3] register to determine when the Polling erase is complete. A command that uses the polling method to signify the The BYTE PROGRAM command programs data into a completion of an operation must check the BUSY bit single byte. The BYTE PROGRAM command is initiated (SFCF[3]). Copy the (SFCF) register into temporary as follows: memory and mask bit3. Once it is isolated, the status of the . BUSY bit can be checked. 1.) Move the high order address byte AH to (SFAH). 2.) Move the low order address byte AL to (SFAL). MOVC instruction may also be used for verification of the 3.) Move the data to the (SFDT). Programming and Erase operation of the flash memory. 15 1999 Silicon Storage Technology, Ine 25 32522 198

tty, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information Taste 6: IN-APPLICATION PROGRAMMING Mope CommANDS Operation SFAH SFAL SFDT SFCM' SFCM? CHIP ERASE x x 55h 5Dh/DDh 87h/07h BLOCK ERASE 80h/00h x 55h 5Dh/DDh 8Fh/OFh SECTOR ERASE AH AL x 5Dh/DDh 8Bh/0OBh BYTE PROGRAM AH AL DI 5Dh/DDh S8Eh/0Eh BURST PROGRAM AH AL DI 5Dh/DDh 8Ah/0Ah VERIFY (Read) AH AL DO - 8Ch/0Ch BYTE 325 POM TS.12 Notes: _X = Don't care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output 1, The value 5Dh or DDh for SFCM is needed before performing any Program and Erase operations. It serves as an “setup command” sequence 2. SFCM(7:0) 8X/OX = Interrupt/Polling Enable for flash operation completion Taste 7: FLasH Memory PRoGRAMMING/VERIFICATION PaRAMETERS (Ty = 0°CTo +125°C, Vpp = 5Vt10%, Vss = OV) [Parameter 249 [symbol | Min’ | Max. | Unt | Reset Setup Time pot Ps Read ID Command Setup Time Pots ts Read ID Command Wiath ©) = PSEN# Setup Time | tes | 5s Chip Erase Time a Block Erase Time a a Sector Erase Time [tse rs Program Setup Tine [Trost] i sd Byte Program Time ©) [ote Ps Verify Command Setup time [oon | Hs Verify High Order Address Setup Time | Taxa “| 35+) Sid Verify Low Order Address Setup Time [Tara | 85 | Ts Burst Program 67) Burst Program Recovery [| Teverev | Ts Note: 325 POM 4.14 1. All timing numbers are pre-simulation and subject to change before silicon verification. 2. All signals that align together in the timing diagrams should be derived from the same clock edge. Set up and hold times are not critical if they are within 10ns. 3. Reading operation is combinatorial. Sequence of timing edges are not important. The latest valid signal determines the access time. 4. All timing measurements are from the 50% of the input to 50% of the output. 5. All input waveforms have rise and fall time of ns. 6. Don't Program (write “O") any byte twice before next erase. 7. Timing is based on 126ns clock cycles. {© 10999 Silicon Storage Technology, Inc 26 325-22 1198

; stn, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ae Advance Information Vss Vop RST A

6 Data

RXD. ©. 1 T2EX THO 4 1 2 INTO +4 2 Portt} $ INTIO OHS 4 10 4 Port 3 5 Tis 6 WR 6 7 RDF 7: ° Port 2 [ ot peer z EA# ALE/ PSEN# PROG#

325 ILL Food

Figure 19: In-ApPLicATION PROGRAMMING MopE I/O AssiGNMENT TIMERS/COUNTERS SERIAL I/O (UART) The SST89C54/58/59 have three 16-bit registers that The SST89C 54/58/59 Serial I/O ports is a full duplex port canbeusedas either timers or eventcounters. Thethree that allows data to be transmitted and received simulta- Timers/Counters are the Timer 0 (TO), Timer 1 (T1), and neously in hardware by the transmit and receive regis- Timer 2 (T2) registers. These three registers are located ters, respectively, while the software is performing other in the SFR as pairs of 8-bit registers. The low byte of the tasks. The Serial I/O port performs the function of an TO register is stored in the Timer 0 LSB (TLO) special UART (Universal Asynchronous Receiver/Transmitter) function register and the high byte of the TO register is chip. The transmit and receive registers are both located stored in the Timer 0 MSB (THO) special function regis- inthe Serial Data Buffer (SBUF special function register. ter. The low byte of the T1 register is stored in the Timer Writing to the SBUF register loads the transmit register, LSB (TI1) special function register and the high byte of and reading from the SBUF register obtains the contents the T1 register is stored inthe Timer 1 MSB(TH1) special of the receive registers. function register. The low byte of the T2 register is stored - 5 - . x " The Serial /O porthas four modes of operation which are hah byte of tho Trea special function register ange selected by the Serial Port Mode Specifier (SMO and (TH2) special function register $M1) bits of the Serial Port Control (SCON) special pe egister. function register. In all four modes, transmission is initi- ated by any instruction that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) special function register is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set. ‘1900 Slicon Storage Technology Ins——SSSCSCSCSSSSSSSCS 8 TT 7 32522 198

tly, or FlashFlex51 MCU i SST89C54 / SST89C58 / SST89C59 Advance Information INTERRUPT WATCHDOG TIMER The SST89C54/58/59 provide 6 interrupt sources, which The SST89C54/58/59 offer an enhanced programmable include two external interrupts (INTO# and INT1#), three watchdog timer for fail safe protection against software Timer/Counter Interrupts (TFO, TF1, and TF2), and one “hang” and allows an automatic recovery from such from the serial port (SI or Tl). The Interrupt Enable (IE) software upset. special function register is the source of the interrupts. To protect the system against software “hang”, theuser’s Each of the bits that generate the interrupts may be set reqrarn has i Tetrosn the watehdlo titver ‘within & or cleared by software with the same result as setting or oeevinush rogrammed time period. If The software fails clearing the bits through hardware. Therefore, interrupts i do thie ie ical retresh a intexnal hartware reset may be generated or canceled by software. Also, inter- will be initiated The software can be designed such that tupts can be enabled or disabled by setting or clearing the watchdo: times out if the program does not work individual bits of the IE register. The SST89C54/S8/59 roperly. It algo times out if asoftware error is based on also contain a global enable bit which allows all of the the hardware "elated probleme interrupts to be enabled or disabled by setting or clearing p : the EA bit of the IE register. Please refer to the The watchdog timer in the SST89C54/58/59 share the SST89C54/58/59 User's Manual for a more detailed same time base with the flash controller unit. When the description of the Interrupt System. flash controller unit is operating, the time base will be re- started by the hardware periodically, hence elongate the Interrupt Priority Levels time-out period of the watchdog timer. The higher most Individual interrupts can be programmed as a low- prior- 8-bits of the time base register are used as the reload ity or a high priority interrupt by setting or clearing the register of the watchdog timer. Corresponding bit in the Interrupt Priority (IP) special Figure 20 provides a block diagram of the Watchdog function register. A 0 value is designated a low priority Timer. Two SFRs (WDTC and WDTD) control watchdog and a 1 value is the high priority. Please refer to the timer operation. During idle mode, WDT operation is SST89C54/58/59 User's Manual for a more vivid temporarily suspended, and resumes upon an interrupt description about Interrupt Priority Levels. exit from idle. 64ms WOT Reset Ext. RST es

325 LL F103

Fiaure 20: Biock Diacram of ProaRamMaABLE WarTcHDoG TIMER {© 10999 Silicon Storage Technology, Inc 28 R522 199

; stn, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information SECURITY LOCK Both memory blocks may be “soft” locked, allowing In- . A Application Programming. This feature allows the device The Security feature protects against software piracy to enter IAP Mode executing from internal memory, but and prevents the contents ofthe flash from being read by inhibits the device from entering IAP Mode executing unauthorized parties. It also protects against code cor- trom external memory or External Host Mode. Table 9 Tuption resulting from accidental erasing and program- ligt the security lock options and commands allowed for ming to the internal flash memory locations. The security each option bits are located in the highest address location, FFFFh, . of the SST89C54/58/59 program memory space. Only ACTIVATION AND DEACTIVATION OF THE bits [3:0] are used for security coding, bits [6:4] are SECURITY LOCK reserved, and bit [7] is used to enable “Interrupt Re- mapping (REMC)”. Refer to the Memory Organization For both External Host and In-Application Programming section for details on flash memory re-mapping. modes, the security bits, XXXXBBBBb', XXXX0101b - we arti F X5h) or XXXX001 1b (X3h), must first be programmed When the security lock is activated, the MOVC instruc- ( 4 tions executed from external program memory or un- tiawe aoaress spcation fone 13 13D the ale ra locked flash memory are disabled from fetching code Gos a ates of Block 1 "ak bi SE 2] abn ne 0 bytes from locked memory blocks (See Table 8). The edt Je fin - eke , ton an K poo an %) MA dare security lock can either “hard” lock both flash memory USeato bits he sb States of Bloc! ot ‘ are i sat le blocks or just “hard” lock the secondary flash memory pai jas iylo oie nctivate ate tle dress location block (Block 1) independently. Whenthe memoryblocks f° S reeet y lock is activated following a success- are locked, the following commands are not allowed on ul system reset. the locked flash memory blocks: To deactivate the security lock, the security byte at . location FFFFh is programmed with a value of, . Boor canoe XXXX1111b (XFh), via the CHIP ERASE operation. The + PROGRAM BYTE default value of the security byte is XFh. + BURST PROGRAM + VERIFY BYTE Tase 8: INTERNAL AND ExTERNAL Proaram Memory Access with Security Lock ActivaTeD MOVC INSTRUCTIONS ACCESS TO LOCKED ACCESS TO UNLOCKED EXECUTED FROM PROGRAM MEMORY OR EXTERNAL PROGRAM MEMORY iocked program memory Taste 9: Security Lock Options Security |SFC! Block| Sector} Byte Burst | Verify Description Bits [6:5] Erase| Erase |Program|Program| Byte xxxxiitib[ oo | x | x [Ty | y [| y [oy Jy | no lock, (default XxxxBBBBb| 11 [| x [ x | N [ N [| N [TN [TN | both blocks locked XXXX0011b | Of x | o | y | y [oy Ty fy J only block 1 (4KB) is locked x fa f[n{n {on Ton [Tw] XXXX0101b | 10 both blocks are accessible PoP PNT NTN TON TN | botnet pace

325 POM T69

Note: Security Bits = Value of Security Bits [3:0] at location FFFFh; SFCF[6:5] = Bit 5 and 6 of SFCF register are read only bits; EA# = Ext. Access enable input pin: 1 — running code from internal memory, 0 - running code from external enable; blkSel = Block Select signal (internal): 1 - block 1 (4Kx8), 0 — block 0 (32Kx8); X = don't care; Y = command allowed; N = command not allowed ‘SFCF [6:5] represents the Security Lock Decoding bits of the SuperFlash Configuration (SFCF) special function register and they are read only bits. The bits are only updated out of reset, i.e. dynamic changes to address location FFFFh is not tracked until a reset cycle, with the exception that SFCF [6:5] are cleared upon successful completion of a CHIP ERASE 1 XXXXBBBBb — B denotes any combination of binary values that do not unlock or partially lock the device. Sess SHconsireae Teme

tty, or FlashFlex51 MCU uuu SST89C54 / SST89C58 / SST89C59 Advance Information In-Application Programming Mode Power-On Reset The security locks option, XXXX0101b, “soft” locks both flash At initial power up, the port pins will be in a random state until memory blocks. This lock option allows the user toupdate the _ the oscillator has started and the internal reset algorithm has code in the locked flash memory blocks under a pre-deter- _ written one’s to all the pins. Powering up the device without a mined secure environment. When both flash memory blocks _ valid resetcould cause the CPUto start executing instructions are “soft” locked, the software code executingfromoneinternal from an indeterminate location. Such undefined states may flash memory block can perform In-Application Programming _ inadvertently corrupt the code in the flash. onthe other block. In other words, code residing in Block 1 may To ensure a good power-on reset, it is required that the Vop Liecoolon pork through the carninard hiitoy reais rise time does not exceed 1 ms and the oscillator start up time SFCM, and executed from the internal program memory can does notexceed 10 ms. Figure 22 shows the maximum delay : ° time allowed between initial power up and reset. Vpp should be operated on both Block 0 and Block 1: BLOCK ERASE, lag no more than 10 ns behind RST at voltages above 1.4 V. SECTOR ERASE, BYTE PROGRAM, BURST PROGRAM AS ges adi nt and VERIFY BYTE. common method to extend the RST signal is to implement aRC circuit by connecting the RST pin to Vpp through a 10 uF The security bits, XXXXBBBBb (both blocks “hard” locked), capacitor and to Vss through an 8.2K resistor as shown in prohibits In-Application Programming (IAP) to the flash Figure 21. This method maintains the necessary relationship memory blocks. (XXXXBBBBb—B denotes any combination between Vpp and RST to avoid programming at an indetermi- of binary values that does not unlock or partially lock the nate location, which may cause code corruption in the flash. device). Only the CHIP ERASE operation will erase both . A blocks including the security bits. If the security bits, ve oe ae acts eet hawan, me XXXX0011b (only Block 1 is locked), In-Application Program- . ming is only allowed in Block 0. protects the’ flash during aPower-OnResetorduring aBrown- Out condition. The internal Power-On Reset/ Brown-Out ACHIP ERASE operation can deactivate, or change the level circuit further prevents inadvertent information to be pro- of, the security lock after it is set. CHIP ERASE will set the grammed to the flash. It should be noted that the internal security byte to the value of XFh. The In-Application Program- | Power-On Reset/ Brown-Out protection circuit only provides ming operation with program code execution from either inter- additional protection for the flash, an external circuit is still nal flash memory or external program code storage can write necessary to ensure both the flash and the CPU resets anew lock option to the security bits, and the new security lock —_ properly. will activate on the next system reset. VoD External Host Mode + If the security lock is activated, the following External Host 10KF oo Mode commands are not allowed on the locked flash memory blocks: SECTOR ERASE, BLOCK ERASE, BYTE PRO- GRAM, BURST PROGRAM, and VERIFY BYTE. Only the CHIP ERASE operation can deactivate, orchange level of, the SSTE9C5A/S8/S security lock after it is set. CHIP ERASE will setthe security bits RST to the value of XXXX1111b. a2ka RESET | Asystem reset initializes the MCU and begins program execu- ss tion at program memory location 0000h. The reset input for the V — SST89C54/58/59 is the RST pin. In order to reset the Ficure 21: Power-On Reser Circurr SST89C54/58/59, a logic level high mustbe applied tothe RST pin for at least two machine cycles (24 clocks), after the 1a oscillator becomes stable. ALE, PSEN# are weakly pulled high Vpp : during reset. During reset, ALE and PSEN# output a high level inorderto perform correct reset. This level must notbe affected RST 14V by externalelement. Asystem resetwill notaffect the 256 bytes of on-chip RAM while the SST89C54/58/59 is running, how- Tyr <10ns ever, the contents of the on-chip RAM during power up are aes Lraes indeterminate. All Special Function Registers (SFR) return to their reset values, which are outlined in Tables 3a to 3c. Ficure 22: Minimum Vpp To RST For Power-On Reset ©1999 Siicon Storage Technology,Inc SSCS 30 e522 198

SST89C54 / SST89C58 / SST89C59 ae Advance Information POWER-SAVING MODES tupts, timers and serial port). Idle mode is initiated by software. The Power Down and Standby (Stop Clock) The FlashFlex51 Family of MCUs provide three power- modes are similar, both reduce device current drain to saving modes of operation for applications where power approximately 15 microamperes. However, entry to the consumption is critical. The three power-saving modes two modes is different, Power Down mode is entered by are Idle, Power Down and Standby (Stop Clock) modes. software, while Standby (Stop Clock) mode is controlled In the Idle mode, the current drain is approximately 25% by hardware (gating on and off the system clock). Table ofthe current drain when the device is fully active, and the 10 below outlines the different power-saving modes, clock signal is gated off to the MCU, but remains operat- indicating entry and exit procedures and functionality ing to all other functions within the device (e.g., inter- within the MCU during the power-saving modes. Taste 10: FLasHFLEXx51 Power Savina Moves Idle Mode Software 25% of Ipp level when | CLK running. Interrupts, | Enabled interrupt or (Set IDL bit in device is fully active serial port and timers/ _| hardware reset. PCON) counters continue to be | Start of interrupt clears clocked, but the MCU IDL bit and exits Idle clock is gated off. ALE | mode, and after the and PSEN# sigs ata _| ISR RET! instruction, HIGH level during Idle. | the program resumes All registers remain normal processing unchanged. (note 1). A hardware reset starts the device similar to power-on reset. (See note 2.) Power Down Mode Software Approximately 15 CLK gated Off to MCU, | External interrupt or (Set PD bit in microamps. And Vop serial port, timer/ hardware reset. PCON) can be reduced by ext. | counters and internal | From external hardware to 2V during | interrupts. On-chip interrupt, on-chip RAM (after entry and before | SRAM and SFR data is | and SFRs retain their exit) power down mode. | maintained. ALE and | data. Once the ISR PSEN# signals at a ends, normal process- LOW level during ing (note 1) resumes. Power Down. A hardware reset starts the device similar to power-on reset. Standby (Stop Clock) | External hardware Approximately 15 Internal state of the Gate ON external Mode gates OFF the external | microamps. And Vop _| MCU is totally pre- clock, and begin clock input to the MCU. | can be reduced by ext. | served. executing at next clock This gating shall be hardware to 2V during in normal processing. synchronized with an (after entry and before input clock transition exit) power down mode. (low-to-high or high-to- low). 325 PGM 18.2 Notes: 1. Normal processing refers to program execution beginning at the instruction following the ‘one that invoked this particular power reduction mode. 2. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. If needed in a specific application, a user could consider placing two or three NOP instructions after the instructions that invoke idle mode to eliminate any problems rage SticonStoageTecmeg ER

tly, or FlashFlex51 MCU i SST89C54 / SST89C58 / SST89C59 Advance Information CLOCK INPUT OPTIONS low times specified on the data sheet must be observed, but there are no requirements on the duty cycle of the Shown in Figure 23 are the input and output of an inverter external clock signal. arene which can be configured for use as an on-chip At start-up, the external oscillator may encounter up toa . 100 pF load at XTAL1 due to interaction between the When driving the device from an external clock source, amplifier and its feedback capacitance. However, the XTAL2 should be left disconnected and XTAL1 should capacitance will not exceed 20 pF once the external be driven. The internal clocking circuitry is through a flip- signal meets the Vit and Vin specifications. flop (divide-by-two). Minimum and maximum high and ba) XTAL2 NC—xTAL2 LJ EXTERNAL XTAL OSCILLATOR XTAL1 co SIGNAL Vss Vss C1, C2 = 30 pF + 10 pF for Crystals For Ceramic Resonators, contact resonator manufacturer. Using the On-Chip Oscillator External Clock Drive BULFi22 Figure 23: OscitLator CHARACTERISTICS {© 10999 Silicon Storage Technology, Inc 32 325-22 1198

getty, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Voltage ON EAH PIN tO VSS... cceccseocseennessnesetnntisnninnnnnennnttnnnnsnnnssninntnsnninniistiinstnsnnisnnisnnnsnnssnsnnnerneens “OV tO +14.0V Transient Voltage (<20ns) on Any Other Pin to Vg ou... cecssseeessnnseseinnestiensestennieineniesusutaee TOV to +6.5V Output Short Circuit Current) oo ccsssssemsnannenennnsnenmaninsenenenauenanetininuenenenuanieuennensnennaeunenenneenen 100 MA Note “ Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption.) NOTICE: This specification contains preliminary information on new products in production. The specifications are subject to change without notice Operation Range TasLe 11: OPERATING RANGE [Symbol [Description —~—S~d Sins | Sax [CC Ta Ambient Temperature Under Bias Standard 0 +70 °C Industrial -40 +85 °C Vop Supply Voltage 27 5.5 Vv fosc Oscillator Frequency 0 33 MHz For In-Application Programming 0.25 33 MHz 325 PEM T10.1 Taste 12: Reviasitity CHARACTERISTICS [ Symbol | Parameter | Minimum Specification | Units | Test Method Nenp Endurance 10,000 Cycles | JEDEC Standard A117 Tor”) Data Retention 100 Years | JEDEC Standard A103 Vzap_Hem'") ESD Susceptibility 2000 Volts | JEDEC Standard A114 Human Body Model Vzap_wm'") ESD Susceptibility 300 Volts | JEDEC Standard A115 Machine Model tory) Latch Up 100+lpp mA JEDEC Standard 78 Note: (This parameter is measured only for initial qualification and after a design or process change that 325 POM T11.4 could affect this parameter. Sree StconsireaeTemeeME

aan SST89C54 / SST89C58 / SST89C59 Advance Information Taste 13a: DC EvectricaL CHARACTERISTICS Tams = O°Cto + 70°Cor -40°CT0 +85°C 33MHz vevices; 5V 10%; Vss = OV Si a ll hal [Min [| Max | [vu | inputowvottage 45 <Von<56 | 05 | o2vpp-01| v | P| iowisnern | imeem | | vo | | Ports 1.5, 1.6, 1.7) lol = 16 mA 1.0 Vv Vot Output Low Voltage Vop = 4.5V (Ports 1, 2, 3)5 lo. = 100 pA! 0.3 Vv lo. = 1.6 mA? 0.45 Vv lo. = 3.5 mA! 1.0 Vv Vou Output Low Voltage Vop = 4.5V we | witaerein» —[tamins || ae fy | lo. =3.2 mA? 0.45 Vv Vou Output High Voltage Vop = 4.5V (Ports 1, 2,3, ALE, PSEN#) 2 lon = -10 pA Vop - 0.3 Vv lon = -30 pA Vop - 0.7 Vv lon = -60 HA Vop - 1.5 Vv Voi Output High Voltage Vop = 4.5V (Port 0 in External Bus Mode) 2 lon = -200 pA Vop - 0.3 Vv lon = -3.2 MA Vop - 0.7 Vv Ports 1, 2, 3 [Bearers [eee Ports 1, 2, 3)$ Sa Sal Vpp-0.3 [Cio | PinCapacitance’ ss |@ tMHz,25°C | TSF Power Supply Current 7 Vop = 5V In-Application Mode @ 12 MHz 70 mA @ 33 MHz 88 mA Active Mode @ 12 MHz 25 mA @ 33 MHz 45 mA Idle Mode @ 12 MHz 9.5 mA @ 33 MHz 15.5 MA Standby (Stop Clock) Mode Tamb =0°C to + 70°C 100 HA Tamb =-40°C to +85°C, 125 HA Power Down Mode Vop = 2V Tamb =0°C to + 70°C 40 HA Tamb =-40°C to +85°C 50 HA

325 PGM T1243

{© 10999 Silicon Storage Technology, Inc 34 Taeae 188

stn, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 aM Advance Information Taste 138: DC EtectricaL CHARACTERISTICS Tams = O°CTo + 70°Cor -40°CTo +85°C, 12 MHz vevices; 3V +10%; Vss = OV a a he [| Min [Max | [vy | inputtowVottage | 2:7<Von<33 | 05 | ov | vy | VoL Output Low Voltage Vop = 2.7 V (Ports 1, 2, 3) 5 lo. = 100 pA" 0.3 Vv i caemat lo. = 3.5 mA! 1.0 Vv Pe frets eins [teem | |e | (Port 0, ALE, PSEN#) 45 lo. = 200 pA ' 0.3 Vv lo. = 3.2 mA! 0.45 Vv Vou Output High Voltage Vop = 2.7V (Ports 1, 2,3, ALE, PSEN#) 2 loH = -10 pA Vop - 0.3 Vv lon = -30 PA Vop - 0.7 Vv lon = -60 pA Vop - 1.5 Vv po" | etntttewe see | yess || (Port 0 in External Bus Mode) 2 lon = -200 pA Vop - 0.3 Vv lon = -3.2 MA Vop - 0.7 Vv ae a Tee Ports 1, 2, 3) eer eee Pe Ports 1, 2, 3) 3 Gc ca Vpp-0.3 [Rast | RSTPulldownResistor S| | | 28H kD [Cio | PinCapacitance® — T@ A MHz.25°C [TOF Power Supply Current 7 Vop = 3V In-Application Mode 70 mA Active Mode 22 mA Idle Mode 65 mA Standby (Stop Clock) Mode Tam =0°C to + 70°C 70 LA Tamb =-40°C to +85°C. 88 LA Power Down Mode Vop = 2V Tamb =0°C to + 70°C 40 pA Tam =-40°C to +85°C. 50 LA

225 PM T1285

‘© ToaD Sincon Storage TOCHIGI NTS 1155 5 rE

tlt, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 aM Advance Information AC ELECTRICAL CHARACTERISTICS AC Characteristics: (Over Operating Conditions; Load Capacitance for Port 0, ALE, and PSEN# = 100 pF; Load Capacitance for All Other Outputs = 80 pF) Taste 14: AC Evectricat CHARACTERISTICS Tame = 0°CTo +70°c or -40°c To +85°C, Vbp = 3V 10% @ 12 MHz, 5V +10% @ 33 MHz, Vss = 0 Symbol Parameter | Min | Max | Min | Max | Min. [ Max. | [van | OscilatorFrequency | | | TT to we [Tou | ALEPusewietn | t27_ [Tao | Tatura PTs i cP Touc. -25 i ced al PO Touct -25 i 4Tccl - 65 ns peer eT ee Te Toot - 25 [Teer | PSEN#Pusewisth | 205 || 46 | Tau -45 | Ts i cl a 35 3Teuct - 55 | Texx | inputinstrHold aterPsen# | [| TT ts pe [ewer TT ee Toot -25 paren TT

7 STexct - 80

| Teaz | PSEN#Lowto Address Flot | | 10 [| | io [ts [Tari | _—RD#Pusewith | don | | ee | | Stan -1o0 | Ts [Tmwi | WitePusewidh wee) | 4oo | | a2 | | éraa-wo | | os i ca al ea

61 STect - 90

| Tauox | DataHodaferAD# | oo | | oo TT ts pee [mews [eT Te | ee 35 2Tect - 25 pe [emer [Te | Be Toc. -90 [we | Meevoer | OT] fof | ae | Tec. -90 [Tum | ALELowtoRD#orwR#Low | 200 | 300 | 40 | 140 | 3Tac-50 | STaa+50 | rs | [om | Mewwerovownnioy |e | te | | eae | |e Tou. - 75 [om [reveewrowm |S | TT | eee || ee | Toc. -30 [wo [| Omen Te | fe] | ee |

3 Toot -27

perme [el | ee TT | Tevet - 70 [Tas | AD#LowtoAddressFloat | | o [ | o fo | os i and al PP Toc. -25 Toret +25 [ia [__vewrat [CC Note: 1. Refer to Figure 15 for minimum timing requirements for Power-On Reset. 25 PEM TIS.4 15 1999 Silicon Storage Technology, Ine 37 32522 198

git, FlashFlex51 MCU or SST89C54 / SST89C58 / SST89C59 ane Advance Information PRODUCT ORDERING INFORMATION Product Identification Descriptor Device Speed Suffix1 Suffix 2 SST89C5X - 33 - X - XX XXXXXA l C-Spec Identification Code C-Spec Revision C-Spec Tracking No. ——— Package Modifier |= 40 pins J=44 pins Package Type P = PDIP N= PLCC TQ = TQFP Operation Temperature C = Commercial = 0° to 70°C | = Industrial = -40° to 85°C. Blank = Initial release A = First enhancement Operating Frequency 33 = 0-33 MHz Memory Size 4* = C51 Core + 16(20) KByte 8* = C51 Core + 32(36) KByte 9* = C51 Core + 60(64) KByte * = 4K additional flash can be enabled via VISIBLE bit in SFCF Device Family C51 Core BIR—e Sion Sioage Teen

efit, or FlashFlex51 MCU aa SST89C54 / SST89C58 / SST89C59 Advance Information Part Number Valid Combinations SST89C54 Valid combinations Part Number Package Pins Voo Speed _Temperature SST89C54-33-C-PI PDIP 40 2.7-5.5 0-33MHz Commercial SST89C54-33-C-NJ PLCC 44 2.7-5.5 _0-33MHz Commercial SST89C54-33-C-TQU TQFP 44 2.7-5.5 _0-33MHz Commercial SST89C54-33-I-PI PDIP. 40 2.7-5.5 0-33MHz Industrial SST89C54-33-I-NJ PLCC 44 2.7-5.5 0-33MHz Industrial SST89C54-33-I-TQJU TQFP 44 2.7-5.5 0-33MHz Industrial SST89C58 Valid combinations Part Number Package Pins Voo Speed _ Temperature SST89C58-33-C-PI PDIP 40 2.7-5.5 _0-33MHz Commercial SST89C58-33-C-NJ PLCC 44 2.7-5.5 0-33MHz Commercial SST89C58-33-C-TQU TQFP 44 2.7-5.5 _0-33MHz Commercial SST89C58-33-I-PI PDIP 40 2.7-5.5 _0-33MHz Industrial SST89C58-33-I-NJ PLCC 44 2.7-5.5 _0-33MHz Industrial SST89C58-33-I-TQU TQFP 44 2.7-5.5 0-33MHz Industrial SST89C59 Valid combinations Part Number Package Pins Voo Speed _ Temperature SST89C59-33-C-PI PDIP 40 2.7-5.5 _0-33MHz Commercial SST89C59-33-C-NJ PLCC 44 2.7-5.5 _0-33MHz Commercial SST89C59-33-C-TQU TQFP 44 2.7-5.5 0-33MHz Commercial SST89C59-33-I-PI PDIP 40 2.7-5.5 _ 0-33MHz Industrial SST89C59-33-I-NJ PLCC 44 2.7-5.5 _0-33MHz Industrial SST89C59-33-I-TQU TQFP 44 2.7-5.5 _0-33MHz Industrial Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability and to determine availability of new combinations. ‘©7989 Slicon Storage Technology, Inc 2 R522 199

(ty, FlashFlex51 MCU SST89C54 / SST89C58 / SST89C59 aM Advance Information Part Number Cross-Reference Guide Intel ssT package 187054 16K EPROM & 256B RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ i87C58 32K EPROM & 256B RAM SST89C58 4K Flash, 32K Flash & 256B RAM DLQ i87L54 16K ROM (OTP) & 256B RAM — SST89C54 4K Flash, 16K Flash & 2568 RAM La i87L58 32K ROM (OTP) & 256BRAM — SST89C58 4K Flash, 32K Flash & 256B RAM La i87C51FB 16K EPROM & 256B RAM ‘SST89C54* 4K Flash, 16K Flash & 2568 RAM DLQ i87C51FC 32K EPROM & 256B RAM SST89Css* 4K Flash, 32K Flash & 2568 RAM DLQ Atmel ssT package AT89C52 8K Flash & 2568 RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ ATB9LV52 8K Flash & 2568 RAM SSTa9C54 4K Flash, 16K Flash & 2568 RAM DLQ AT89S53 12K Flash & 256B RAM ssTascs4* 4K Flash, 16K Flash & 2568 RAM DLQ AT89LS53 12K Flash & 256B RAM SST89C54* 4K Flash, 16K Flash & 256B RAM DLQ AT89C55 20K Flash & 256B RAM SST89C58* 4K Flash, 32K Flash & 256B RAM DLQ ATB9LV55 20K Flash & 256B RAM ssTascss* 4K Flash, 32K Flash & 256B RAM DLQ Temic ssT package 80C51 4K ROM & 256B RAM SST89C54" 4K Flash, 16K Flash & 256B RAM DLQ 80C52 8K ROM & 2568 RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ 830154 16K ROM & 256B RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ 83C154D 32K ROM & 256B RAM SST89C58 4K Flash, 32K Flash & 2568 RAM DLQ 87051 4K EPROM & 2568 RAM ‘SST89C54* 4K Flash, 16K Flash & 2568 RAM DLQ 87C52 8K EPROM & 256B RAM SST89C54 4K Flash, 16K Flash & 256B RAM DLQ Philips ssT package Pg0cs4 16K ROM & 256B RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ Pg0css 32K ROM & 2568 RAM SSTa9C5s 4K Flash, 32K Flash & 2568 RAM DLQ P87C54 16K EPROM & 256B RAM SST89C54 4K Flash, 16K Flash & 256B RAM DLQ P87c58 32K EPROM & 256B RAM ‘SST89C58 4K Flash, 32K Flash & 2568 RAM DLQ 870524 16K EPROM & 512B RAM SST89C54* 4K Flash, 16K Flash & 2568 RAM DLQ P87C528 32K EPROM & 512B RAM SST89C58* 4K Flash, 32K Flash & 2568 RAM DLQ P83cs24 16K ROM & 512B RAM ‘SST89C54* 4K Flash, 16K Flash & 2568 RAM DL P83C528 32K MROM & 512B RAM SST89C58" 4K Flash, 32K Flash & 256B RAM DLQ P89CE558 32K Flash & 1K RAM SST89C58" 4K Flash, 32K Flash & 2568 RAM Winbond ssT package w7scs4 16K MROM & 256B RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ W78C58 32K MROM & 256B RAM SST89C58 4K Flash, 32K Flash & 256B RAM DLQ W78E54 16K EEPROM & 2568 RAM ‘SST89C54 4K Flash, 16K Flash & 2568 RAM DLQ W78E58 32K EEPROM & 256B RAM SST89C58 4K Flash, 32K Flash & 2568 RAM DLQ Issi ssT package Issocs2 8K ROM & 256B RAM SST89C54 4K Flash, 16K Flash & 256B RAM DLQ Dallas ssT package Ds83c520 16K MROM & 256B RAM SST89C54* 4K Flash, 16K Flash & 2568 RAM DLQ Ds87c520 16K EPROM (OTP ) & ‘SST89C54* 4K Flash, 16K Flash & 2568 RAM DLQ 256B RAM Siemens ssT package C501-1R 8K ROM & 2568 RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DL C501-1E 8K ROM (OTP) & 256B RAM SST89C54 4K Flash, 16K Flash & 2568 RAM DL C513A-H 12K EPROM & 512B RAM SST89C54" 4K Flash, 16K Flash & 256B RAM L C503-1R 8K ROM & 256B RAM ‘SST89C54* 4K Flash, 16K Flash & 2568 RAM L ©504-2R 16K ROM & 512B RAM ssTscs4* 4K Flash, 16K Flash & 2568 RAM Q D: PDIP L: PLCC Q: TQFP NOTE: The SST89C58 can be substituted for any SST89C54 listing above. NOTE: The SST89C59 can be substituted for any SST89C54 or SSTS9CSS listing above. * Indicates SST similar function and not direct replacement/socket compatible Sess Stconsireae Teme

efit, or FlashFlex51 MCU Advance Information PACKAGING DIAGRAMS i Index Va " Pa ii o] ij Optional Ejector Pin Indentaton Stow or vv Conventional Mold Only 800 Bad c3 mm oss 2085 r ce 20 4 PLCS. | i ¢ teow. pt Base Plane ty a Seating Plane

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| | T ve | 5 = aoe ey ms ea os so08sc s00 Bsc Note: 1. Complies with JEDEC publication 2 MS-011 AC dimensions, although some dimensions may be more stringent. 2.Alllinear dimensions are in inches (min/max) 3, Dimensions do not include mold flash, Maximum allowable mold flash is 010 inches. so pipPOALLA 40-Leap Ptastic Duat-in-Line Packace (PDIP) SST Packace Cope: PI TOP VIEW SIDE VIEW BOTTOM VIEW $85

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020 Min

ase. m 228 a2 A4PLCCNHIULS ies 180 Note: 1, Complies with JEDEC publication 95 MS-018 AC dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 44-Leap Ptastic Leap Cuip Carrier (PLCC) SST Packace Cove: NJ {© 10999 Silicon Storage Technology, Inc is 325-22 1198

SST89C54 / SST89C58 / SST89C59 ae Advance Information AUT: sD OOAOHAAAAAs DOT fa Le 070 == | == i | == oo =o == i F580 sc 1 . = == 09 == | = da oof Pin 1 Index =e a o7 oo | pos 2 2 oe TaN 1 7.00 ref HUW ‘WHOOOWOOOOENs edly BSC 3s 108 44.LTOFP-TQU-ILLO 12.0 BSC Note: 1. Complies with JEDEC publication 95 MS-026 BCB dimensions, although some dimensions may be more stringent. 2. Alllinear dimensions are in mm (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .254 mm. 44-Leap THin Quan Fat Pack (TQFP) SST Packace Cove: TQU ‘51989 Silicon Storage Technology, Ine 5 3e522 1798