SST25LF080A-33-4E-S2AE

SST25LF080A SST | Alldatasheet

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©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. EOL Product Data Sheet FEATURES:

• Single Voltage Read and Write Operations – 3.0-3.6V  Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3  33 MHz Max Clock Frequency  Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention  Low Power Consumption: – Active Read Current: 7 mA (typical) – Standby Current: 8 µA (typical)  Flexible Erase Capability – Uniform 4 KByte sectors – Uniform 32 KByte overlay blocks  Fast Erase and Byte-Program: – Chip-Erase Time: 70 ms (typical) – Sector- or Block-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical)  Auto Address Increment (AAI) Programming – Decrease total chip programming time over Byte-Program operations  End-of-Write Detection – Software Status  Hold Pin (HOLD#) – Suspends a serial sequence to the memory without deselecting the device  Write Protection (WP#) – Enables/Disables the Lock-Down function of the status register  Software Write Protection – Write protection through Block-Protection bits in status register  Temperature Range – Commercial: 0°C to +70°C – Industrial: -40°C to +85°C – Extended: -20°C to +85°C  Packages Available – 8-lead SOIC 200 mil body width  All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION SST’s serial flash family features a four-wire, SPI-com- patible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25LF080A SPI serial flash memories are manufactured with SST’s proprietary, high perfor- mance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reli- ability and manufacturability compared with alternate approaches. The SST25LF080A devices significantly improve perfor- mance, while lowering power consumption. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given volt- age range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25LF080A devices operate with a single 3.0-3.6V power supply. The SST25LF080A devices are offered in an 8-lead SOIC package with 200 mil body width. See Figure 1 for pin assignments.

8 Mbit SPI Serial Flash

SST25LF080A8Mb Serial Peripheral Interface (SPI) flash memory

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 1248 B1.0 I/O Buffers and Data Latches SuperFlash MemoryX - Decoder Control Logic Address Buffers and Latches CE# Y - Decoder SCK SI SO WP# HOLD# Serial Interface FUNCTIONAL BLOCK DIAGRAM

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 PIN DESCRIPTION FIGURE 1: P IN ASSIGNMENTS FOR 8-LEAD SOIC TABLE 1: P IN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication wi th SPI flash memory without resetting the device. VDD Power Supply To provide power suppl y voltage: 3.0-3.6V for SST25LF080A VSS Ground T1.0 1248 CE# SO WP# VSS VDD HOLD# SCK SI Top View 1248 08-soic P1.0

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 PRODUCT IDENTIFICATION MEMORY ORGANIZATION The SST25LF080A SuperFlash memory array is orga- nized in 4 KByte sectors with 32 KByte overlay blocks. DEVICE OPERATION The SST25LF080A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25LF080A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. FIGURE 2: SPI P ROTOCOL TABLE 2: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 00000H BFH Device ID SST25LF080A 00001H 80H T2.0 1248 1248 F02.0 MODE 3 SCK SI SO CE# MODE 3 DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE 0MODE 0 HIGH IMPEDANCE MSB MSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Hold Operation HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 3 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high- impedance state while SI and SCK can be V IL or VIH. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 18 for Hold timing. FIGURE 3: H OLD CONDITION WAVEFORM Write Protection SST25LF080A provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down func- tion of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down func- tion of the BPL bit is disabled. Active Hold Active Hold Active 1248 F03.0 SCK HOLD# TABLE 3: C ONDITIONS TO EXECUTE WRITE-STATUS- REGISTER (WRSR) INSTRUCTION WP# BPL Execute WRSR Instruction L 1 Not Allowed L0 A l l o w e d HX A l l o w e d T3.0 1248

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Status Register The software status register provides status on whether the flash memory array is available for any Read or Write oper- ation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indi- cates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the inter- nal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automati- cally reset under the following conditions:  Power-up  Write-Disable (WRDI) instruction completion  Byte-Program instruction completion  Auto Address Increment (AAI) programming reached its highest memory address  Sector-Erase instruction completion  Block-Erase instruction completion  Chip-Erase instruction completion TABLE 4: S OFTWARE STATUS REGISTER Bit Name Function Default at Power-up Read/Write

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled

2 BP0 Indicate current level of block write protection (See Table 5) 1 R/W

3 BP1 Indicate current level of block write protection (See Table 5) 1 R/W

4:5 RES Reserved for future use 0 N/A

6 AAI Auto Address Increment Programming status

1 = AAI programming mode 0 = Byte-Program mode

7 BPL 1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable 0R / W T4.0 1248

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After power-up, BP1 and BP0 are set to 1. Block Protection Lock-Down (BPL) WP# pin driven low (V IL), enables the Block-Protection- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (V IH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. TABLE 5: S OFTWARE STATUS REGISTER BLOCK PROTECTION1 1. Default at power-up for BP1 and BP0 is ‘11’. Protection Level Status Register Bit Protected Memory Area BP1 BP0 8 Mbit 00 0 N o n e 1 (1/4 Memory Array) 0 1 0C0000H-0FFFFFH 2 (1/2 Memory Array) 1 0 080000H-0FFFFFH 3 (Full Memory Array) 1 1 000000H-0FFFFFH T5.0 1248

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25LF080A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 6. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. TABLE 6: D EVICE OPERATION INSTRUCTIONS 1 1. A MS = Most Significant Address AMS = A19 for SST25LF080A Address bits above the most significant bit of each density can be VIL or VIH Cycle Type/ Operation2,3 2. Operation: S IN = Serial In, SOUT = Serial Out 3. X = Dummy Input Cycles (V IL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) Max Freq MHz Bus Cycle4 4. One bus cycle is eight clock periods. 123 4 5 6 SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT Read 20 03H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z X D OUT High-Speed-Read 0BH Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z X Hi-Z X D OUT Sector-Erase5,6 5. Sector addresses: use A MS-A12, remaining addresses can be VIL or VIH 6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. 20H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - Block-Erase5,7 7. Block addresses for: use A MS-A15, remaining addresses can be VIL or VIH 52H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z - - Chip-Erase6 6 0 H H i - Z - ----- - - Byte-Program6 02H Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z D IN Hi-Z Auto Address Increment (AAI) Single-Byte Program6,8 8. To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be programmed. AFH Hi-Z A 23-A16 Hi-Z A 15-A8 Hi-Z A 7-A0 Hi-Z D IN Hi-Z Read-Status-Register (RDSR) 05H Hi-Z X D OUT -N o t e 9 9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. -N o t e 9 -N o t e 9 Enable-Write-Status-Register (EWSR)10 10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. Write-Status-Register (WRSR)10 01H Hi-Z Data Hi-Z - - -. - - - W r i t e - E n a b l e ( W R E N ) 0 6 H H i - Z - ----- - - W r i t e - D i s a b l e ( W R D I ) 0 4 H H i - Z - ----- - - Read-ID 90H or ABH Hi-Z 00H Hi-Z 00H Hi-Z ID Addr11 11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer and Device ID output stream is continuous until terminated by a low to high transition on CE# Hi-Z X D OUT12 12. Device ID = 80H for SST25LF080A T6.0 1248

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Read (20 MHz) The Read instruction supports up to 20 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until ter- minated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 8 Mbit density, once the data from address location 0FFFFFH had been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit com- mand, 03H, followed by address bits [A 23-A0]. CE# must remain active low for the duration of the Read cycle. See Figure 4 for the Read sequence. FIGURE 4: R EAD SEQUENCE 1248 F04.0 CE# SO SI SCK ADD. 012345678 ADD. ADD.03 HIGH IMPEDANCE 15 16 23 24 31 32 39 40 7047 48 55 56 63 64 N+2 N+3 N+4N N+1 DOUT MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 High-Speed-Read (33 MHz) The High-Speed-Read instruction supporting up to 33 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A 23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 5 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will auto matically increment to the beginning (wrap-around) of the address space, i.e. for

8 Mbit density, once the data from address location

0FFFFFH has been read, the next output will be from address location 000000H. FIGURE 5: H IGH-SPEED-READ SEQUENCE 1248 F05.0 CE# SO SI SCK ADD. 012345678 ADD. ADD.0B HIGH IMPEDANCE 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4N N+1 X MSB MSBMSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 8071 72 DOUT Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V IL or VIH)

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The Byte- Program instruction is initiated by executing an 8-bit com- mand, 02H, followed by address bits [A 23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait T BP for the completion of the internal self-timed Byte-Program operation. See Figure 6 for the Byte-Program sequence. FIGURE 6: B YTE-PROGRAM SEQUENCE 1248 F06.0 CE# SO SI SCK ADD. 012345678 ADD. ADD. D IN02 HIGH IMPEDANCE 15 16 23 24 31 32 39 MODE 0 MODE 3 MSBMSBMSB LSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total program- ming time when the entire memory array is to be pro- grammed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when ini- tiating an AAI program instruction. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A 23-A0]. Following the addresses, the data is input sequentially from MSB (Bit 7) to LSB (Bit 0). CE# must be driven high before the AAI program instruction is executed. The user must poll the BUSY bit in the software status register or wait T BP for the completion of each inter- nal self-timed Byte-Program cycle. Once the device com- pletes programming byte, the next sequential address may be program, enter the 8-bit command, AFH, followed by the data to be programmed. When the last desired byte had been programmed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the WRDI command, the user must poll the Status register to ensure the device completes programming. See Figure 7 for AAI programming sequence. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable- Latch bit (WEL = 0). FIGURE 7: A UTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE CE# SI SCK A[23:16] A[15:8] A[7:0]AF Data Byte 1 AF Data Byte 2 CE# SI SO SCK Write Disable (WRDI) Instruction to terminate AAI Operation Read Status Register (RDSR) Instruction to verify end of AAI Operation 04Last Data ByteAF 05 D OUT MODE 3 MODE 0 TBP TBP TBP 1248 F07.0 0 1 2 3 4 5 6 7 8 3 23 33 43 53 63 73 83 915 16 23 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 012345670123456789 1 0 1 1 1 2 1 3 1 4 1 5 0123456789 1 0 1 1 1 2 1 3 1 4 1 5

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A 23-A0]. Address bits [A MS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is exe- cuted. The user may poll the Busy bit in the software status register or wait T SE for the completion of the internal self- timed Sector-Erase cycle. See Figure 8 for the Sector- Erase sequence. FIGURE 8: S ECTOR-ERASE SEQUENCE Block-Erase The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A 23-A0]. Address bits [AMS-A15] (AMS = Most significant address) are used to determine block address (BA X), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait T BE for the completion of the internal self-timed Block- Erase cycle. See Figure 9 for the Block-Erase sequence. FIGURE 9: B LOCK-ERASE SEQUENCE CE# SO SI SCK ADD. 012345678 ADD. ADD.20 HIGH IMPEDANCE 15 16 23 24 31 MODE 0 MODE 3 1248 F08.0 MSBMSB CE# SO SI SCK ADD. 012345678 ADD. ADD.52 HIGH IMPEDANCE 15 16 23 24 31 MODE 0 MODE 3 1248 F09.0 MSB MSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait T CE for the completion of the internal self-timed Chip-Erase cycle. See Figure 10 for the Chip-Erase sequence. FIGURE 10: C HIP-ERASE SEQUENCE Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows read- ing of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read- Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 11 for the RDSR instruction sequence. FIGURE 11: R EAD-STATUS-REGISTER (RDSR) SEQUENCE CE# SO SI SCK 01234567 HIGH IMPEDANCE MODE 0 MODE 3 1248 F10.0 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1248 F11.0 MODE 3 SCK SI SO CE# Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE 0 HIGH IMPEDANCE Status Register Out MSB MSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. FIGURE 12: W RITE ENABLE (WREN) SEQUENCE Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write- Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE# must be driven high before the WRDI instruction is executed. FIGURE 13: W RITE DISABLE (WRDI) SEQUENCE Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write- Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write- Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. CE# SO SI SCK 01234567 HIGH IMPEDANCE MODE 0 MODE 3 1248 F12.0 MSB CE# SO SI SCK 01234567 HIGH IMPEDANCE MODE 0 MODE 3 1248 F13.0 MSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-Status-Register instruction must be executed immediately after the execution of the Enable- Write-Status-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register val- ues. The Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lock- down the status register, but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 bits in the status reg- ister can all be changed. As long as BPL bit is set to 0 or WP# pin is driven high (V IH) prior to the low-to-high transi- tion of the CE# pin at the end of the WRSR instruction, the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 and BP1 bit at the same time. See Table 3 for a summary description of WP# and BPL functions. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruction sequences. FIGURE 14: E NABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE 1248 F14.0 MODE 3 HIGH IMPEDANCE MODE 0 STATUS REGISTER IN 76543210 MSBMSBMSB MODE 3 SCK SI SO CE# MODE 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 Read-ID The Read-ID instruction identifies the devices as SST25LF080A and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A 23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manu- facturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#. FIGURE 15: R EAD-ID SEQUENCE 1248 F15.0 CE# SO SI SCK 012345678

00 ADD 190 or AB

15 16 23 24 31 32 39 40 47 48 55 56 63 BF Device ID BF Device ID Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. Device ID = 80H for SST25LF080A 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. HIGH IMPEDANCE MODE 3 MODE 0 MSB MSB MSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than t hose listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) 1. Output shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp V DD Commercial 0°C to +70°C 3.0-3.6V Industrial -40°C to +85°C 3.0-3.6V Extended -20°C to +85°C 3.0-3.6V AC CONDITIONS OF TEST See Figures 20 and 21 TABLE 7: DC O PERATING CHARACTERISTICS Symbol Parameter Limits Test ConditionsMin Max Units IDDR Read Current 12 mA CE#=0.1 V DD/0.9 VDD@20 MHz, SO=open IDDR1 Read Current 15 mA CE#=0.1 V DD/0.9 VDD@33 MHz, SO=open IDDW Program and Erase Current 30 mA CE#=V DD ISB Standby Current 15 µA CE#=V DD, VIN=VDD or VSS ILI Input Leakage Current 1 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V V DD=VDD Min VIH Input High Voltage 0.7 V DD VV DD=VDD Max VOL Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min VOH Output High Voltage V DD-0.2 V I OH=-100 µA, VDD=VDD Min T7.1 1248 TABLE 8: R ECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units T PU-READ1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. VDD Min to Read Operation 10 µs TPU-WRITE1 VDD Min to Write Operation 10 µs T8.0 1248

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 TABLE 9: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum COUT1 Output Pin Capacitance V OUT = 0V 12 pF CIN1 Input Capacitance V IN = 0V 6 pF T9.0 1248 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. TABLE 10: R ELIABILITY CHARACTERISTICS Symbol Parameter Minimum Spec ification Units Test Method NEND1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 + I DD mA JEDEC Standard 78 T10.0 1248 TABLE 11: AC O PERATING CHARACTERISTICS Limits

20 MHz 33 MHz

Symbol Parameter Min Max Min Max Units FCLK Serial Clock Frequency 20 33 MHz TSCKH Serial Clock High Time 20 13 ns TSCKL Serial Clock Low Time 20 13 ns TCES1 1. Relative to SCK. CE# Active Setup Time 20 12 ns TCEH1 CE# Active Hold Time 20 12 ns TCHS1 CE# Not Active Setup Time 10 10 ns TCHH1 CE# Not Active Hold Time 10 10 ns TCPH CE# High Time 100 100 ns TCHZ CE# High to High-Z Output 20 14 ns TCLZ SCK Low to Low-Z Output 0 0 ns TDS Data In Setup Time 5 3 ns TDH Data In Hold Time 5 3 ns THLS HOLD# Low Setup Time 10 10 ns THHS HOLD# High Setup Time 10 10 ns THLH HOLD# Low Hold Time 15 10 ns THHH HOLD# High Hold Time 10 10 ns THZ HOLD# Low to High-Z Output 20 14 ns TLZ HOLD# High to Low-Z Output 20 14 ns TOH Output Hold from SCK Change 0 0 ns TV Output Valid from SCK 20 12 ns TSE Sector-Erase 25 25 ms TBE Block-Erase 25 25 ms TSCE Chip-Erase 100 100 ms TBP Byte-Program 20 20 µs T11.0 1248

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 FIGURE 16: S ERIAL INPUT TIMING DIAGRAM FIGURE 17: S ERIAL OUTPUT TIMING DIAGRAM HIGH-Z HIGH-Z CE# SO SI SCK MSB LSB TDS TDH TCHH TCES TCEH TCHS TSCKR TSCKF TCPH 1248 F16.0 1248 F17.0 CE# SI SO SCK MSB TCLZ TV TSCKH TCHZ TOH TSCKL LSB

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 FIGURE 18: H OLD TIMING DIAGRAM FIGURE 19: P OWER-UP TIMING DIAGRAM THZ TLZ THHH THLS THLH THHS 1248 F18.0 HOLD# CE# SCK SO SI Time VDD Min VDD Max VDD Device fully accessibleTPU-READ TPU-WRITE Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. 1248 F19.1

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 FIGURE 20: AC I NPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 21: A T EST LOAD EXAMPLE 1248 F20.0 REFERENCE POINTS OUTPUTINPUT VHT VLT VHT VLT VIHT VILT AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 1248 F21.0 TO TESTER TO DUT CL

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 PRODUCT ORDERING INFORMATION Valid combinations for SST25LF080A SST25LF080A-33-4C-S2AE SST25LF080A-33-4I-S2AE SST25LF080A-33-4E-S2AE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. SST 25 LF 080 A - 33 - 4C - S2A E XX XXX X X X X - XXX -X X - XXX X Environmental Attribute E1 = non-Pb Package Modifier A = 8 leads or contacts Package Type S2 = SOIC 200 mil body width Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Operating Frequency 33 = 33 MHz Device Density 080 = 8 Mbit Voltage L = 3.0-3.6V Product Series 25 = Serial Peripheral Interface flash memory 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 PACKAGING DIAGRAMS 8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 200 MIL BODY WIDTH (5.2MM X 8MM) SST PACKAGE CODE: S2A 2.16 1.75 08-soic-EIAJ-S2A-3 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0.1 mm 3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. TOP VIEW SIDE VIEW END VIEW 5.40 5.15 8.10 7.70 5.40 5.15 Pin #1 Identifier 0.50 0.35

1.27 BSC

0.25 0.05 0.25 0.19 0.80 0.50 1mm

©2006 Silicon Storage Technology, Inc. S71248-06-EOL 1/06 TABLE 12: R EVISION HISTORY Number Description Date 00  Initial release of data sheet Oct 2003 01  2004 Data Book Dec 2003 02  Changes to Table 7 on page 18 – Added I DDR1 – Changed I DDR to from 10 mA to 12 mA  Clarified comments in Figure 19 on page 21  Updated the S2A mechanical outline Mar 2004 03  Added Commercial and Extended temperatures and associated MPNs May 2004 04  Revised Absolute Max. Stress Ratings for Surface Mount Solder Reflow Temp.  Migrated document from Advance Information to Data Sheet Nov 2005 05  Added footnote to Product Ordering Information  Removed leaded part numbers Jan 2006 06  End-of-Life data sheet for all devices in S71248  Recommended replacement devices are SST25VF080B found in S71296. Jan 2006