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SST55LC100

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CompactFlash Card Controller

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©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Some content is reproduced from the CompactFlash Specification (2.0) by permission of the CompactFlash Association. Other content is reproduced from the ATA/ATAPI-6 (T13/1410D revision 3b) spec- ification by permission of the National Committee for Information Technology Standards. These specifications are subject to change without notice. Advance Information FEATURES:

CompactFlash Association Specification Revision 2.0 standard Interface for standard NAND Flash Media – Flash Media Interface: 8-bit or 16-bit access - Supports up to 8 flash media devices directly – Supports Single-Level Cell (SLC) Low power, 3.3V core operation 5.0V or 3.3V host interface through V DDQ pins Low current operation: – Active mode: 25 mA/35 mA (3.3V/5.0V) (typical) – Sleep mode: 40 µA/50 µA (3.3V/5.0V) (typical) 20-byte Unique ID for Enhanced Security – Factory Pre-programmed 10-byte Unique ID – User-Programmable 10-byte ID Power Management Unit – Immediate disabling of unused circuitry Integrated Power-on Reset Circuit – Industrial Controller requires external POR# signal Pre-programmed Embedded Firmware – Performs self-initialization on first system Power-on – Executes industry standard CF commands – Implements dynamic wear-leveling algorithms to substantially increase the longevity of flash media – Embedded Flash File System – Built-in ECC corrects up to 3 random 12-bit symbols of error per 512-byte sector S t a r t U p T i m e – Sleep to Read: 200 ns – Sleep to Write: 200 ns Multi-tasking Technology enables Fast Sustained Read and Write Performance – Up to 10 MB/sec Automatic Recognition and Initialization of Flash Media Devices – Seamless integration into a standard SMT manufacturing process Commercial and Industrial Temperature Ranges – 0°C to 70°C for Commercial operation – -40°C to +85°C for Industrial operation Packages Available – 84-ball TFBGA: non-Pb only – 100-lead TQFP: non-Pb only All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST55LC100 CompactFlash Card Controller is the heart of a high-performance, flash media-based Compact- Flash card solution. The SST55LC100 recognizes the con- trol, address, and data signals on the CompactFlash bus and translates them into memory accesses to the standard NAND-type flash media. The SST55LC100 device sup- ports the Single Level Cell (SLC) media only. This technol- ogy suits solid state mass storage applications offering new, expanded functionality while enabling smaller, lighter designs with lower power consumption. The CompactFlash interface is widely used in products such as portable and desktop computers, digital cameras, music players, handheld data collection scanners, PDAs, handy terminals, personal communicators, audio record- ers, monitoring devices, and set-top boxes. The SST55LC100 supports CFA Specification Revision 2.0 commands standard with up to PIO Mode-4. Utilizing SST’s proprietary SuperFlash embedded memory technology, the CompactFlash card controller is pre-pro- grammed with an embedded flash file system which, upon initial power-up, recognizes the flash media devices, sets up a bad block table, executes all the necessary handshak- ing routines for flash media support, and, finally, performs the low-level format. This technology enables a very fast, completely seam- less integration of flash drives into an embedded design. For added manufacturing flexibility, system debug, re-ini- tialization, and user customization can be accomplished through the CompactFlash interface. The SST55LC100 CompactFlash Card Controller offers sustained read and write performance up to 10.0 MB/sec. The device can support up to 8 flash media devices directly for up to 8 GByte of maximum CompactFlash Card capacity. The CompactFlash card controller comes packaged in an industry standard 100-lead TQFP package or 84-ball BGA package for easy integration into an SMT manufacturing process. CompactFlash Card Controller SST55LC100 SST55LC100Compact Flash Card Controller

1.0 GENERAL DESCRIPTION

The CompactFlash card controller contains a microcontrol- ler and embedded flash file system integrated in TQFP or TFBGA packages. Refer to Figure 2-1 for the Compact- Flash card controller block diagram. The controller inter- faces with the host system allowing data to be written to and read from the flash media.

1.1 Performance-optimized CompactFlash

The heart of the CompactFlash card is the CompactFlash card controller which translates standard CF signals into flash media data and control signals. The following compo- nents contribute to the CompactFlash card controller’s operation.

1.1.1 Microcontroller Unit (MCU)

The MCU translates CF commands into data and control signals required for flash media operation.

1.1.2 Internal Direct Memory Access (DMA)

The CompactFlash card controller uses internal DMA allowing instant data transfer from buffer to flash media. This implementation eliminates microcontroller overhead associated with the traditional, firmware-based approach, thereby increasing the data transfer rate.

1.1.3 Power Management Unit (PMU)

The power management unit controls the power consump- tion of the CompactFlash card controller. The PMU dramat- ically reduces the power consumption of the CompactFlash card controller by putting the part of the cir- cuitry that is not in operation into sleep mode.

1.1.4 SRAM Buffer

A key contributor to the CompactFlash card controller per- formance is an SRAM buffer. The buffer optimizes the host’s data transfer to and from the flash media.

1.1.5 Embedded Flash File System

The embedded flash file system is an integral part of the CompactFlash card controller. It contains MCU firmware that performs the following tasks: 1. Translates host side signals into flash media writes and reads. 2. Provides dynamic flash media wear leveling to spread the flash writes across all unused memory address space to increase the longevity of flash media. 3. Keeps track of data file structures.

1.1.6 Error Correction Code (ECC)

The CompactFlash card controller utilizes 72-bit Reed- Solomon Error Detection Code (EDC) and Error Correc- tion Code (ECC), which provides the following error immunity for each 512-byte block of data: 1. Corrects up to three random 12-bit symbol errors. 2. Corrects single bursts up to 25 bits. 3. Detects single bursts up to 61 bits and double bursts up to 15 bits. 4. Detects up to six random 12-bit symbol errors.

1.1.7 Serial Communication Interface (SCI)

The Serial Communication Interface (SCI) is designed to report initialization errors and allow manufacturers to debug system failures.

1.1.8 Multi-tasking Interface

The multi-tasking interface enables fast, sustained write performance by allowing concurrent Read, Program, and Erase operations to multiple flash media devices.

2.0 FUNCTIONAL BLOCKS

FIGURE 2-1: C OMPACTFLASH CARD CONTROLLER BLOCK DIAGRAM 1298 B1.0 HOST CF BUS CompactFlash Card Controller Multi-tasking Interface SCI NAND Flash MediaEmbedded Flash File System MCU ECC Internal DMA SRAM Buffer PMU

3.0 PIN ASSIGNMENTS

The signal/pin assignments are listed in Table 3-1. Low active signals have a “#” suffix. Pin types are Input, Output, or Input/Output. Signals whose source is the host are designated as inputs while signals that the CompactFlash card controller sources are outputs. FIGURE 3-1: P IN ASSIGNMENTS FOR 84-BALL TFBGA A B C D E F G H J K 1298 84-tfbga P1.0 SCIDOUT VREG FCE0# FCE3# FCE4# FWE# EXTCLKOUT RESET CE2# FAD15 FAD14 FAD5 FAD4 V DD(IO) FAD10 FAD1 CSEL# PDIAG# FAD7 FAD6 FAD12 FAD3 FAD9 FAD8 IOWR# WP/IOCS16# POR# FAD13 FAD11 FAD2 FAD0 CE1# A10 V SS(Core) VSS(IO) REG# INTRQ WE# WAIT# D15 IORD# D14 D13 D12 INPACK# D11 D10 V SS(IO) OE# SCICLK SCIDIN FCE2# FCLE FCE5# DASP# V DD(Core) FCE1# FRE# FCE6# FALE FWP# EXTCLKIN VDDQ(IO) TOP VIEW (balls facing down) FCE7#/INTCLKEN

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 FIGURE 3-2: P IN ASSIGNMENTS FOR 100-LEAD TQFP 100 RESET VSS (IO) V DDQ (IO) V SS (IO) OE# INPACK# IORD# REG# INTRQ CE1# V SS (Core) EXTCLKIN EXTCLKOUT VSS (IO) FWP# FWE# FCE5# FALE FCE4# FCLE FCE6# V SS (IO) FCE3# FCE2# V DD (IO) FCE0# DNU FRE# DNU V REG DNU FCE1# SCID OUT SCIDIN SCICLK V DD (Core) FCE7#/INTCLKEN VSS (IO) FAD0 FAD8 FAD1 FAD9 FAD2 FAD10 FAD3 FAD11 V SS (IO) DNU VDD (IO) FAD4 FAD12 FAD5 FAD13 FAD6 FAD14 FAD7 FAD15 DNU DNU DNU POR# 1298 100-tqfp P1.0 DASP# V SS (IO) D10 D11 V DDQ (IO) D12 D13 D14 D15 V SS (IO) WE# WAIT# A10 IOWR# CSEL# WP/IOCS16# PDIAG# CE2# V SS (Core) Note: DNU means Do Not Use, must be left unconnected. 100-lead TQFP Top View

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 TABLE 3-1: P IN ASSIGNMENTS (1 OF 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions Host Side Interface A10-A0 (Memory Card mode) G10 H10 II 2 D These address lines along with the REG# signal are used to select the following: The I/O port address registers within the CompactFlash card, the memory mapped port address regis- ters within the CompactFlash card, a byte in the card’s infor- mation structure and its configuration control and status registers. A 10-A0 (PC Card I/O mode) This signal is the same as the PC Card Memory mode signal. A2-A0 (True IDE mode) In True IDE mode only A[2:0] are used to select the one of eight registers in the Task File. A 10-A3 61 G10 H10 The remaining address lines should be grounded by the host. BVD1 (Memory Card mode)

54 J9 O I2U, O1

This signal is asserted high as BVD1 is not supported. STSCHG# (PC Card I/O mode) This signal is asserted low to alert the host to changes in the Ready and Write Protect states, while the I/O interface is con- figured. Its use is controlled by the Card Config and Status reg- ister. PDIAG# (True IDE mode) In the True IDE mode, this input/output is the Pass Diagnostic signal in the master/slave handshake protocol. BVD2 (Memory Card mode)

75 B10 O I2U, O1

This signal is asserted high as BVD2 is not supported. SPKR# (PC Card I/O mode) This output line is always driven to a high state in I/O mode since the CompactFlash card controller does not support the audio function. DASP# (True IDE mode) In the True IDE mode, this input/output is the Disk Active/Slave Present signal in the master/slave handshake protocol.

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 CE1#, CE2# (Memory Card mode) K9 II 3 U Card Enable: These input signals are used both to select the card and to indicate to the card whether a byte or a word oper- ation is being performed. CE2# always accesses the Odd Byte of the word. CE1# accesses the Even Byte or the Odd Byte of the word depending on A 0 and CE2#. A multiplexing scheme based on A0, CE1#, CE2# allows 8-bit hosts to access all data on D0-D7. See Tables 8-1, 8-3, 8-7, 8-8, and 8-9. CE1#, CE2# (PC Card I/O mode) Card Enable: This signal is the same as the PC Card Memory mode signal. CS0#, CS1# (True IDE mode) In the True IDE mode CS0# is the chip select for the task file registers while CS1# is used to select the Alternate Status reg- ister and the Device Control register. CSEL# (Memory Card mode)

56 J10 I I2U

This signal is not used for this mode. CSEL# (PC Card I/O mode) This signal is not used for this mode. CSEL# (True IDE mode) This internally pulled up signal is used to configure this device as a master or a slave when configured in the True IDE mode. When this pin is grounded, this device is configured as a mas- ter. When the pin is open, this device is configured as a slave. D 15-D0 (Memory Card mode) E10 D10 C10 I/O I2D, O2 These lines carry the Data, Commands and Status information between the host and the controller. D 0 is the LSB of the Even Byte of the Word. D8 is the LSB of the Odd Byte of the Word. D15-D0 (PC Card I/O mode) This signal is the same as the PC Card Memory mode signal. D15-D0 (True IDE mode) In True IDE mode, all Task File operations occur in Byte-Mode on the low order bus D7-D0 while all data transfers are 16 bit using D15-D0. INPACK# (Memory Card mode)

14 E3 O O1

This signal is not used in this mode. INPACK# (PC Card I/O mode) The Input Acknowledge signal is asserted by the Compact- Flash card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This sig- nal is used by the host to control the enable of any input data buffers between the CompactFlash card and the CPU. Reserved (True IDE mode) In True IDE mode this output signal is not used and should not be connected at the host. TABLE 3-1: P IN ASSIGNMENTS (CONTINUED) (2 OF 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions

19 F1 I I3U

This signal is not used in this mode. IORD# (PC Card I/O mode) This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the CompactFlash card when the card is configured to use the I/O interface. IORD# (True IDE mode) In True IDE mode, this signal has the same function as in PC card I/O mode. IOWR# (Memory Card mode)

57 H9 I I3U

This signal is not used in this mode. IOWR# (PC Card I/O mode) The I/O Write strobe pulse is used to clock I/O data on the card data bus into the CompactFlash card controller registers when the CompactFlash card is configured to use the I/O interface. IOWR# (True IDE mode) In True IDE mode, this signal has the same function as in PC Card I/O mode. OE# (Memory Card mode)

13 D1 I I3U

This is an Output Enable strobe generated by the host inter- face. It is used to read data from the CompactFlash card in Memory mode and to read the CIS and configuration registers. OE# (PC Card I/O mode) In PC Card I/O mode, this signal is used to read the CIS and configuration registers. ATASEL# (True IDE mode) To enable True IDE mode this input should be grounded by the host. Ready (Memory Card mode)

21 G1 O O1

In Memory mode this signal is set high when the Compact- Flash card is ready to accept a new data transfer operation and held low when the card is busy. At power up and at Reset, the Ready signal is held low (busy) until the CompactFlash card has completed its power up or reset function. No access of any type should be made to the CompactFlash card during this time. IREQ# (PC Card I/O mode) I/O Operation - After the CompactFlash card has been config- ured for I/O operation, this signal is used as Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. INTRQ (True IDE mode) In True IDE mode signal is the active high Interrupt Request to the host. REG# (Memory Card mode)

20 G2 I I3U

This signal is used during Memory cycles to distinguish between Common Memory and Register (Attribute) Memory Attribute Memory Select accesses. High for Common Memory, Low for Attribute Memory. REG# (PC Card I/O mode) The signal must also be active (low) during I/O Cycles when the I/O address is on the Bus. Reserved (True IDE mode) In True IDE mode this input signal is not used and should be connected to V DD by the host. TABLE 3-1: P IN ASSIGNMENTS (CONTINUED) (3 OF 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 RESET (Memory Card mode) 1A 2 I I 4 U When the pin is high, this signal Resets the CompactFlash card. The CompactFlash card is Reset only at power up if this pin is left high or open from power-up. The CompactFlash card is also Reset when the Soft-Reset bit in the Card Configuration Option register is set. RESET (PC Card I/O mode) This signal is the same as the PC Card Memory mode signal. RESET# (True IDE mode) In the True IDE mode this input pin is the active low hardware reset from the host. WAIT# (Memory Card mode)

62 F9 O O1

The WAIT# signal is driven low by the CompactFlash Card to signal the host to delay completion of a memory or I/O cycle that is in progress. WAIT# (PC Card I/O mode) This signal is the same as the PC Card Memory mode signal. IORDY# (True IDE mode) In True IDE mode this output signal may be used as IORDY . WE# (Memory Card mode)

63 F10 I I3U

This is a signal driven by the host and used for strobing mem- ory write data to the registers of the CompactFlash card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. WE# (PC Card I/O mode) In PC Card I/O mode, this signal is used for writing the configu- ration registers. WE# (True IDE mode) In True IDE mode this input signal is not used and should be connected to V DD by the host. WP (Memory Card mode)

55 H8 O O2

The CompactFlash card does not have a write protect switch. This signal is held low after the completion of the reset initial- ization sequence. IOIS16# (PC Card I/O mode) When the CompactFlash card is configured for I/O Operation Pin 55 is used for the I/O# Selected is 16-bit Port (IOIS16#) function. A Low signal indicates that a 16 bit or Odd Byte only operation can be performed at the addressed port. IOCS16# (True IDE mode) In True IDE mode this output signal is asserted low when this device is expecting a word data transfer cycle. TABLE 3-1: P IN ASSIGNMENTS (CONTINUED) (4 OF 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 Flash Media Interface FWP# 97 B4 O O5 Active Low Flash Media Chip Write Protect Connect this pin to the NAND flash media Write Protect pin FRE# 84 B7 O O5 Active Low Flash Media Chip Read FWE# 96 A4 O O5 Active Low Flash Media Chip Write FCLE 92 C6 O O5 Active High Flash Media Chip Command Latch Enable FALE 94 B5 O O5 Active High Flash Media Chip Address Latch Enable FAD15 46 K8 I/O I3U/O5 Flash Media Chip High Byte Address/Data Bus pins FAD14 44 K7 FAD13 42 H6 FAD12 40 J5 FAD11 35 H5 FAD10 33 K3 FAD9 31 J3 FAD8 29 J2 FAD7 45 J7 I/O I3U/O5 Flash Media Chip Low Byte Address/Data Bus pins FAD6 43 J6 FAD5 41 K6 FAD4 39 K5 FAD3 34 J4 FAD2 32 H4 FAD1 30 K2 FAD0 28 H3 FCE6# 91 B6 O O4 Active Low Flash Media Chip Enable pin FCE5# 95 C5 FCE4# 93 A5 FCE3# 89 A6 FCE2# 88 C7 FCE1# 80 B8 FCE0# 86 A7 FCE7#/INTCLKEN 26 J1 I/O I3D/O4 Active Low Flash Media Chip Enable pin This pin is sensed during the Power-on Reset (POR) to select an Internal Clock mode. If this pin is pulled up during the Power-on Reset then the Internal Clock is selected. Serial Communication Interface (SCI) SCICLK 77 C9 I I3U SCI interface clock SCIDIN 78 C8 I I3U SCI interface data input SCIDOUT 79 A9 O O4 SCI interface data output TABLE 3-1: P IN ASSIGNMENTS (CONTINUED) (5 OF 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 External Clock Option FCE7#/INTCLKEN 26 J1 I/O I3D/O4 Active Low Flash Media Chip Enable pin This pin is sensed during the Power-on Reset (POR) to select an Internal Clock mode. If this pin is pulled up during the Power-on Reset then the Internal Clock is selected. EXTCLK IN 100 B3 I I4Z External Clock source input pin EXTCLKOUT 99 A3 O O4 External Clock source output pin Miscellaneous V DD (core) 76 B9 PWR V DD (3.3V) VDD (IO) 38 K4 PWR V DD (3.3V) VDDQ (IO) 7 B1 PWR V DDQ (5V/3.3V) for Host interface VREG 82 A8 O O5 Voltage Regulator Output VSS (core) 25 G7 PWR Ground for core VSS (IO) 2 PWR Ground for I/O POR# 50 H7 I Analog Input Power-on Reset (POR): Active Low DNU 37 Do Not Use, must be left unconnected. T3-1.0 1298 1. Please refer to Section 10.1 for details. I = Input 0 = Output 2. Analog input for supply voltage detection TABLE 3-1: P IN ASSIGNMENTS (CONTINUED) (6 OF 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions

4.0 CAPACITY SPECIFICATION

Table 4-1 shows the default capacity and specific settings for heads, sectors, and cylinders. Users can reduce the default settings in the drive ID table (see Table 9-8) for customization. If the total number of bytes is less than the default, the remaining space could be used as spares to increase the flash drive endurance.

4.1 Functional Specifications

Table 4-2 shows the performance and the maximum capacity supported by each controller. TABLE 4-1: D EFAULT COMPACTFLASH CARD SETTINGS Capacity Total Bytes Cylinders Heads Sectors

16 MB 16,056,320 490 2 32

32 MB 32,112,640 490 4 32

64 MB 64,225,280 980 4 32

128 MB 128,450,560 980 8 32

256 MB 256,901,120 980 16 32

512 MB 512,483,328 993 16 63

1 GB 1,024,966,656 1986 16 63

2 GB 2,048,901,120 3970 16 63

4 GB 4,110,188,544 7964 16 63

6 GB 6,146,703,360 11910 16 63

8 GB 8,195,604,480 15880 16 63

T4-1.0 1298 TABLE 4-2: F UNCTIONAL SPECIFICATION Functions SST55LC100 CompactFlash Card Supported Capacity up to 8 GB CompactFlash Card Performance-Sustained Write speed Up to 10.0 MB/sec CompactFlash Card Performance-Sustained Read speed Up to 10.0 MB/sec T4-2.0 1298

5.0 MANUFACTURING SUPPORT

The CompactFlash card controller firmware contains a list of supported standard NAND flash media devices. Upon initial Power-on, the controller scans all connected flash media devices and reads their device ID. If the device ID matches the listed flash media devices in the CompactFlash card controller, the controller performs drive recogni- tion based on the algorithm provided by the flash media suppliers, including setting up the bad block table, execut- ing all the necessary handshaking routines for flash media support, and, finally, performing the low-level format. For Power-up timing specifications, please refer to Table 10-2. Please contact SST for the most current list of supported NAND Flash media devices. In the event that the NAND flash media device ID is not recognized by the CompactFlash card controller, the user has an option of adding this device to the controller device table through the manufacturing interface provided by SST. Please contact SST for the CompactFlash card controller manufacturing interface software. If the drive initial- ization fails, and a visual inspection is unable to determine the problem, the SST55LC100 CompactFlash card con- troller provides a comprehensive interface for manufacturing flow debug. This interface not only allows debug of the failure and manual reset of the initialization process, but also allows customization of user definable options.

5.1 CF Interface

The CompactFlash interface can be used for manufacturing support. SST provides an example of a DOS-based solution (an executable routine downloadable from SST’s web site) for manufacturing debug and rework.

5.2 Serial Communication Interface (SCI)

For additional manufacturing flexibility, the SCI bus can be used for manufacturing error reporting. The SCI consists of 3 active signals: SCIDOUT, SCIDIN, and SCICLK.

6.0 EXTERNAL CLOCK INTERFACE

The external clock interface allows CompactFlash card controller operation from an external clock source gener- ated by an RC circuit. Do not use a free running clock as input to the EXTCLKIN pin; an RC circuit must be used. Contact SST for reference circuit and recommended external clock settings. While the controller has an internal clock source, the external clock source allows slowing of the system clock oper- ation to limit the peak current and overcome additional bus loading. The external clock interface consists of three signals: INTCLKEN, EXTCLKIN, and EXTCLKOUT. The INTCLKEN pin selects between external and internal clock sources for the CompactFlash card controller. If this pin is pulled high before device Power-on, then the internal clock source is selected; otherwise, the external clock source is selected. The EXTCLKIN and EXTCLKOUT signals are the input and output clock signals, respectively.

7.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS

Please contact SST to obtain CompactFlash reference design schematics including the POR# circuit for commer- cial and industrial CompactFlash offerings. FIGURE 7-1: P OWER-ON AND BROWN-OUT RESET TIMING (COMMERCIAL TEMPERATURE) FIGURE 7-2: P OWER-ON AND BROWN-OUT RESET TIMING (INDUSTRIAL TEMPERATURE ) TABLE 7-1: P OWER-ON AND BROWN-OUT RESET TIMING (COMMERCIAL TEMPERATURE ) Item Symbol Min Max Units VDD/POR# Rise Time1 1. V DD Rise Time should be greater than or equal to POR# Rise Time. TR 200 ms VDD/POR# Fall Time2 2. V DD Fall Time should be slower than or equal to POR# Fall Time. TF 200 ms T7-1.0 1298 TABLE 7-2: P OWER-ON AND BROWN-OUT RESET TIMING (INDUSTRIAL TEMPERATURE) Item Symbol Min Max Units POR Wait Time T W 0.1 ms Brown-out Delay Time T D 30 µs T7-2.0 1298 1298 F01.1 VDD/POR# TR 90% 10% TF 90% 10% VDD TW 90% POR# 1298 F01b.0 TD 90%

8.0 CARD CONFIGURATION

The CompactFlash cards are identified by appropriate information in the Card Information Structure (CIS). The fol- lowing configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, these registers provide a method for accessing status information about the Compact- Flash card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate use in I/O cards. Note: The location of the card configuration registers should always be read from the CIS locations 0000H to 0198H. No writes should be performed to the CompactFlash card attribute memory except to the card configuration register addresses. All other attribute memory locations are reserved. TABLE 8-1: R EGISTERS AND MEMORY SPACE DECODING CE2# CE1# REG# OE# WE# A 10 A9 A8-A4 A3 A2 A1 A0 Selected Space 1 1 X X X X X X X XXXX S t a n d b y X 0 0 0 1 0 1 XX X X X 0 Configuration Registers Read 1 0 1 0 1 X X X X XXXX C o m m o n M e m o r y R e a d ( 8 b i t D 7-D0) 0 1 1 0 1 X X X X XXXX C o m m o n M e m o r y R e a d ( 8 b i t D 15-D8) 0 0 1 0 1 X X XX X X X 0 Common Memory Read (16 bit D 15-D0) X 0 0 1 0 0 1 XX X X X 0 Configuration Registers Write 1 0 1 1 0 X X X X XXXX C o m m o n M e m o r y W r i t e ( 8 b i t D 7-D0) 0 1 1 1 0 X X X X XXXX C o m m o n M e m o r y W r i t e ( 8 b i t D 15-D8) 0 0 1 1 0 X X XX X X X 0 Common Memory Write (16 bit D 15-D0) X 0 0 0 1 0 0 XX X X X 0 Card Information Structure Read 1 0 0 1 0 0 0 XX X X X 0 Invalid Access (CIS Write) 1 0 0 0 1 X X XX X X X 1 Invalid Access (Odd Attribute Read) 1 0 0 1 0 X X XX X X X 1 Invalid Access (Odd Attribute Write) 0 1 0 0 1 X X X X XXXX I n v a l i d A c c e s s ( O d d A t t r i b u t e R e a d ) 0 1 0 1 0 X X X X XXXX I n v a l i d A c c e s s ( O d d A t t r i b u t e W r i t e ) T8-1.0 1298 TABLE 8-2: C ONFIGURATION REGISTERS DECODING CE2# CE1# REG# OE# WE# A 10 A9 A8-A4 A3 A2 A1 A0 Selected Register X 0 0 0 1 0 1 00 0 0 0 0 Configuration Option Reg Read X 0 0 1 0 0 1 00 0 0 0 0 Configuration Option Reg Write X 0 0 0 1 0 1 00 0 0 1 0 Card Status Register Read X 0 0 1 0 0 1 00 0 0 1 0 Card Status Register Write X 0 0 0 1 0 1 00 0 1 0 0 Pin Replacement Register Read X 0 0 1 0 0 1 00 0 1 0 0 Pin Replacement Register Write X 0 0 0 1 0 1 00 0 1 1 0 Socket and Copy Register Read X 0 0 1 0 0 1 00 0 1 1 0 Socket and Copy Register Write T8-2.0 1298

8.1 Attribute Memory Function

Attribute memory is a space where CompactFlash card identification and configuration information are stored, and is limited to 8-bit wide accesses only at even addresses. The card configuration registers are also located here. For the Attribute Memory Read function, signals REG# and OE# must be active and WE# inactive during the cycle. As in the Main Memory Read functions, the signals CE 1# and CE2# control the Even Byte and Odd Byte address, but only the Even Byte data is valid during the Attribute Memory access. Refer to Table 8-3 below for signal states and bus validity for the Attribute Memory function. Note: The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations.

8.2 Configuration Option Register (Address 200H in Attribute Memory)

The Configuration Option register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the CompactFlash card. SRESET Soft Reset - Setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the CompactFlash card in the Reset state. Setting this bit to one (1) is equivalent to assertion of the RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the CompactFlash card in the same un- configured Reset state as following power-up and hardware reset. This bit is set to zero (0) by power-up and hardware reset. Using the PCMCIA Soft Reset is considered a hard Reset by the ATA Commands. Contrast with Soft Reset in the Device Control register. LevlREQ This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse mode is selected. Set to zero (0) by Reset. Conf5-Conf0 Configuration Index. Set to zero (0) by reset. It’s used to select operation mode of the CompactFlash card as shown below. Note: Conf5 and Conf4 are reserved and must be written as (0). TABLE 8-3: A TTRIBUTE MEMORY FUNCTION Function Mode REG# CE2# CE1# A 10 A9 A0 OE# WE# D 15-D8 D7-D0 Standby mode X V IH VIH X X X X X High Z High Z Read Byte Access CIS ROM (8 bits) V IL VIH VIL VIL VIL VIL VIL VIH High Z Even Byte Write Byte Access CIS (8 bits) (Invalid) V IL VIH VIL VIL VIL VIL VIH VIL Don’t Care Even Byte Read Byte Access Configuration (8 bits) V IL VIH VIL VIL VIH VIL VIL VIH High Z Even Byte Write Byte Access Configuration (8 bits) V IL VIH VIL VIL VIH VIL VIH VIL Don’t Care Even Byte Read Word Access CIS (16 bits) V IL VIL VIL VIL VIL XV IL VIH Not Valid Even Byte Write Word Access CIS (16 bits) (Invalid) V IL VIL VIL VIL VIL XV IH VIL Don’t Care Even Byte Read Word Access Configuration (16 bits) V IL VIL VIL VIL VIH XV IL VIH Not Valid Even Byte Write Word Access Configuration (16 bits) V IL VIL VIL VIL VIH XV IH VIL Don’t Care Even Byte T8-3.0 1298 O p e r a t i o n D 7D 6D 5D 4D 3D 2D 1D 0 R/W SRESET LevlREQ Conf5 Con f4 Conf3 Conf2 Conf1 Conf0

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 Changed Indicates that one or both of the Pin Replacement register CRdy or CWProt bits are set to one (1). When the Changed bit is set, Pin 46 (STSCHG#) is held low if the SigChg bit is a One (1) and the CompactFlash card is configured for the I/O interface. SigChg This bit is set and reset by the host to enable and disable a state-change “signal” from the Status register, the Changed bit control pin 46 the Changed Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46 (STSCHG#) signal will be held high while the CompactFlash card is configured for I/O. IOis8 The host sets this bit to a one (1) if the CompactFlash card is to be configured in an 8-bit I/O mode. The CompactFlash card is always configured for both 8- and 16-bit I/O, so this bit is ignored. XE#: This bit has value 0 and is not writeable. Audio: This bit should always be zero for CompactFlash cards. PwrDwn This bit indicates whether the host requests the CompactFlash card to be in the power saving or active mode. When the bit is one (1), the CompactFlash card enters a power down mode. When zero (0), the host is requesting the CompactFlash card to enter the active mode. The PCMCIA Ready value becomes BUSY when this bit is changed. Ready will not become ready until the power state requested has been entered. The CompactFlash card automatically powers down when it is idle and powers back up when it receives a command. Int This bit represents the internal state of t he interrupt request. This value is available whether or not I/O interface has been configured. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the -IEn bit in the Device Control register, this bit is a zero (0). TABLE 8-4: C ARD CONFIGURATIONS Conf5 Conf4 Conf3 Conf2 Co nf1 Conf0 Disk Card Mode 0 0 0 0 0 0 Memory Mapped 0 0 0 0 0 1 I/O Mapped, any 16 Byte system decoded boundary 0 0 0 0 1 0 I/O Mapped, 1F0H-1F7H/3F6H-3F7H 0 0 0 0 1 1 I/O Mapped, 170H-177H/376H-377H T8-4.0 1298 TABLE 8-5: C ARD CONFIGURATION AND STATUS REGISTER ORGANIZATION O p e r a t i o n D 7D 6D 5D 4D 3D 2D 1D 0 Read Changed SigChg IOis8 XE# Audio PwrDwn Int 0 Write 0 SigChg IOis8 XE# Audio PwrDwn 0 0

8.3 Pin Replacement Regi ster (Address 204H in Attribute Memory)

CRDY/BSY# This bit is set to one (1) when the bi t RDY/BSY# changes state. This bit can also be written by the host. CWProt This bit is set to one (1) when the RWprot changes state. This bit may also be written by the host. RDY/BSY# This bit is used to dete rmine the internal state of the RDY/BSY# signal. This bit may be used to determine the state of the Ready/-Busy as this pin has been reallocated for use as Interrupt Request on an I/O card. When written, this bit acts as a mask for writing the corresponding bit CRDY/BSY#. WProt: This bit is always zero (0). When written, this bit acts as a mask for writing the corresponding bit CWProt. MRDY/BSY# This bit acts as a mask for writing the corresponding bit CRDY/BSY#. MWProt: This bit when written acts as a mask for writing the corresponding bit CWProt.

8.4 Socket and Copy Register (Addre ss 206H in Attribute Memory)

This register contains additional configuration information. This register is always written by the system before writ- ing the card’s Configuration Index register. Reserved This bit is reserved for future standardization. This bit must be set to zero (0) by the software when the register is written. Drive # This bit indicates the drive number of the card for twin card configuration. Twin card configuration is currently not supported X The socket number is ignored by the CompactFlash card. Operation D7 D6 D5 D4 D3 D2 D1 D0 Read 0 0 CRDY/BSY# CWProt 1 1 RDY/BSY# WProt Write 0 0 CRDY/BSY# CWProt 0 0 MRDY/BSY# MWProt TABLE 8-6: P IN REPLACEMENT CHANGED BIT/MASK BIT VALUES Initial Value of (C) Status Written by Host Final “C” Bit Comments“C” Bit “M” Bit

0 X 0 0 Unchanged

1 X 0 1 Unchanged

T8-6.0 1298 SOCKET AND COPY REGISTER ORGANIZATION: O p e r a t i o n D 7D 6D 5D 4D 3D 2D 1D 0 R e a d R e s e r v e d 00 D r i v e # 0000 W r i t e 000 D r i v e # XXXX

8.5 I/O Transfer Function

8.5.1 I/O Function

The I/O transfer to or from the CompactFlash card can be either 8 or 16 bits. When a 16-bit accessible port is addressed, the signal IOIS16# is asserted by the CompactFlash card. Otherwise, the IOIS16# signal is de- asserted. When a 16 bit transfer is attempted, and the IOIS 16# signal is not asserted by the CompactFlash card, the system must generate a pair of 8-bit references to access the word’s Even Byte and Odd Byte. The Compact- Flash card permits both 8 and 16 bit accesses to all of its I/O addresses, so IOIS16# is asserted for all addresses to which the CompactFlash card responds.

8.6 Common Memory Transfer Function

8.6.1 Common Memory Function

The Common Memory Transfer to or from the CompactFlash card can be either 8 or 16 bits. The CompactFlash card permits both 8 and 16 bit accesses to all of its Common Memory addresses. TABLE 8-7: I/O F UNCTION Function Code REG# CE2# CE1# A 0 IORD# IOWR# D 15-D8 D7-D0 Standby mode X VIH VIH X X X High Z High Z Byte Input Access (8 bits) VIL VIH VIL VIL VIL VIH High Z Even Byte VIL VIH VIL VIH VIL VIH High Z Odd Byte Byte Output Access (8 bits) VIL VIH VIL VIL VIH VIL Don’t Care Even Byte VIL VIH VIL VIH VIH VIL Don’t Care Odd Byte Word Input Access (16 bits) VIL VIL VIL VIL VIL VIH Odd Byte Even Byte Word Output Access (16 bits) VIL VIL VIL VIL VIH VIL Odd Byte Even Byte I/O Read Inhibit VIH X X X VIL VIH Don’t Care Don’t Care I/O Write Inhibit VIH X X X VIH VIL High Z High Z High Byte Input Only (8 bits) VIL VIL VIH X VIL VIH Odd Byte High Z High Byte Output Only (8 bits) VIL VIL VIH X VIH VIL Odd Byte Don’t Care T8-7.0 1298 TABLE 8-8: C OMMON MEMORY FUNCTION Function Code REG# CE2# CE1# A 0 OE# WE# D 15-D8 D7-D0 Standby mode X VIH VIH X X X High Z High Z Byte Read Access (8 bits) V IH VIH VIL VIL VIL VIH High Z Even Byte VIH VIH VIL VIH VIL VIH High Z Odd Byte Byte-Write Access (8 bits) V IH VIH VIL VIL VIH VIL Don’t Care Even Byte VIH VIH VIL VIH VIH VIL Don’t Care Odd Byte Word Read Access (16 bits) VIH VIL VIL X VIL VIH Odd Byte Even Byte Word-Write Access (16 bits) VIH VIL VIL X VIH VIL Odd Byte Even Byte Odd Byte Read Only (8 bits) VIH VIL VIH X VIL VIH Odd Byte High Z Odd Byte-Write Only (8 bits) VIH VIL VIH X VIH VIL Odd Byte Don’t Care T8-8.0 1298

8.7 True IDE Mode I/O Transfer Function

8.7.1 True IDE Mode I/O Function

The CompactFlash card can be configured in a True IDE mode of operation. The CompactFlash card is configured in this mode only when the OE# input signal is grounded by the host during the power off to power on cycle. In this True IDE mode the PCMCIA protocol and configuration are disabled and only I/O operations to the Task File and Data register are allowed. In this mode no Memory or Attribute registers are accessible to the host. CompactFlash cards permit 8 bit data accesses if the user issues a Set Feature Command to put the device in 8-bit mode. Note: Removing and reinserting the CompactFlash card while the host computer’s power is on will reconfigure the CompactFlash to PC Card ATA mode from the original True IDE mode. To configure the CompactFlash card in True IDE mode, the 50-pin socket must be power cycled with the CompactFlash card inserted and OE# (output enable) asserted. Table 8-9 defines the function of the operations for the True IDE mode. TABLE 8-9: T RUE IDE MODE I/O FUNCTION Function Code CE2# CE1# A 0-A2 IORD# IOWR# D 15-D8 D7-D0 Invalid mode VIL VIL X X X High Z High Z Standby mode VIH VIH X X X High Z High Z Task File Write VIH VIL 1-7H VIH VIL Don’t Care Data In Task File Read VIH VIL 1-7H VIL VIH High Z Data Out Data Register Write VIH VIL 0 VIH VIL Odd Byte In Even Byte In Data Register Read VIH VIL 0 VIL VIH Odd Byte Out Even Byte Out Control Register Write VIL VIH 6H VIH VIL Don’t Care Control In Alt Status Read VIL VIH 6H VIL VIH High Z Status Out Drive Address VIL VIH 7H VIL VIH High Z Data Out T8-9.0 1298

9.0 SOFTWARE INTERFACE

9.1 CF-ATA Drive Register Set Definition and Protocol

The CompactFlash card can be configured as a high performance I/O device through: 1. Standard PC-AT disk I/O address spaces 1F0H-1F7H, 3F6H-3F7H (primary); 170H-177H, 376H-377H (secondary) with IRQ 14 (or other available IRQ) 2. Any system decoded 16 Byte I/O block using any available IRQ 3. Memory space The communication to or from the CompactFlash card is done using the Task File registers which provide all the necessary registers for control and status information. The CompactFlash interface connects peripherals to the host using four register mapping methods. The following is a detailed description of these methods.

9.1.1 I/O Primary and Secondary Address Configurations

Note: Address lines which are not indicated are ignored by the CompactFlash card for accessing all the registers in this table. TABLE 9-1: I/O C ONFIGURATIONS Standard Configurations Config Index I/O or Memory Address Description

0 Memory 0H-FH, 400H-7FFH Memory Mapped

1 I/O XX0H-XXFH I/O Mapped 16 Contiguous registers

2 I/O 1F0H-1F7H, 3F6H-3F7H Primary I/O Mapped

3 I/O 170H-177H, 376H-377H Secondary I/O Mapped

T9-1.0 1298 TABLE 9-2: P RIMARY AND SECONDARY I/O DECODING REG# A 9-A4 A3 A2 A1 A0 IORD#=0 IOWR#=0 Note

01 F ( 1 7 ) H 0 0 0 0 Even RD Data Even WR Data 1,2

Register 0 is accessed with CE1# low and CE2# low (and A 0 = Don’t Care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with CE1# low and CE2# high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers which lie at offset 1. When accessed twice as byte register with CE1# low, the first byte to be accessed is the Even Byte of the word and the sec- ond byte accessed is the Odd Byte of the equivalent word access. 2. A byte access to register 0 with CE1# high and CE2# lo w accesses the error (read) or feature (write) register. 0 1F(17)H 0 0 0 1 Error register Features 1,2 0 1F(17)H 0 0 1 0 Sector Count Sector Count 0 1 F ( 1 7 ) H 0011 S e c t o r N o . S e c t o r N o . 0 1F(17)H 0 1 0 0 Cylinder Low Cylinder Low 0 1F(17)H 0 1 0 1 Cylinder High Cylinder High 0 1F(17)H 0 1 1 0 Select Card/Head Select Card/Head 0 1F(17)H 0 1 1 1 Status Command 0 3F(37)H 0 1 1 0 Alt Status Device Control 0 3F(37)H 0 1 1 1 Drive Address Reserved T9-2.0 1298

9.1.2 Contiguous I/O Mapped Addressing

When the system decodes a contiguous block of I/O regist ers to select the CompactFla sh card, the registers are accessed in the block of I/O space decoded by the system as follows: Note: Address lines which are not indicated are ignored by the CompactFlash card for accessing all the registers in this table. TABLE 9-3: C ONTIGUOUS I/O DECODING REG# A 3 A2 A1 A0 Offset IORD#=0 IOWR#=0 Notes 0 0000 0 E v e n R D D a t a E v e n W R D a t a 1 1. Register 0 is accessed with CE1# low and CE2# low (and A 0 = Don’t Care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with CE1# low and CE2# high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with CE1# low, the first byte to be accessed is the Even Byte of the word and the second byte accessed is the Odd Byte of the equivalent word access. A byte access to register 0 with CE1# high and CE2# low accesses the error (read) or feature (write) register. 0 0001 1 E r r o r F e a t u r e s 2 2. Registers at offset 8, 9, and D are non-overlappi ng duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the Odd Byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred Odd Byte then Even Byte. Repeated byte accesses to register 8 or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word accesses to register 8, 9, or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not sup- ported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (Even then Odd) Bytes from the data buffer. Byte accesses to register 9 access only the Odd Byte of the data. 0 0010 2 S e c t o r C o u n t S e c t o r C o u n t 0 0011 3 S e c t o r N o . S e c t o r N o . 0 0100 4 C y l i n d e r L o w C y l i n d e r L o w 0 0101 5 C y l i n d e r H i g h C y l i n d e r H i g h 0 0110 6 S e l e c t C a r d / H e a d S e l e c t C a r d / H e a d 0 0111 7 S t a t u s C o m m a n d 0 1000 8 D u p . E v e n R D D a t a D u p . E v e n W R D a t a 0 1001 9 D u p . O d d R D D a t a D u p . O d d W R D a t a 2 0 1101 D D u p . E r r o r D u p . F e a t u r e s 2 0 1110 E A l t S t a t u s D e v i c e C t l 0 1111 F D r i v e A d d r e s s R e s e r v e d T9-3.0 1298

9.1.3 Memory Mapped Addressing

When the CompactFlash card registers are accessed via memory references, the registers appear in the common memory space window: 0-2 KByte as follows: TABLE 9-4: M EMORY MAPPED DECODING REG# A 10 A9-A4 A3 A2 A1 A0 Offset OE#=0 WE#=0 Notes 1 0 X 0 0 0 0 0 Even RD Data Even WR Data 1,2 1. Register 0 is accessed with CE1# low and CE2# low as a word register on the combined Odd Data Bus and Even Data Bus (D15- D0). This register may also be accessed by a pair of byte accesses to the offset 0 with CE1# low and CE2# high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with CE1# low, the first byte to be accessed is the Even Byte of the word and the second byte accessed is the Odd Byte of the equivalent word access. A byte access to address 0 with CE1# high and CE2# low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlappi ng duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the Odd Byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred Odd Byte then Even Byte. Repeated byte accesses to register 8 or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not sup- ported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (Even then Odd) Bytes from the data buffer. Byte accesses to register 9 access only the Odd Byte of the data. 1 0 X 0 0 0 1 1 Error Features 1,2 1 0 X 0 0 1 0 2 Sector Count Sector Count 1 0 X 0 0 1 1 3 Sector No. Sector No. 1 0 X 0 1 0 0 4 Cylinder Low Cylinder Low 1 0 X 0 1 0 1 5 Cylinder High Cylinder High 1 0 X 0 1 1 0 6 Select Card/Head Select Card/Head 1 0 X 0 1 1 1 7 Status Command 1 0 X 1 0 0 0 8 Dup. Even RD Data Dup. Even WR Data 1 0 X 1 0 0 1 9 Dup. Odd RD Data Dup. Odd WR Data 2 1 0 X 1 1 0 1 D Dup. Error Dup. Features 2 1 0 X 1 1 1 0 E Alt Status Device Ctl 1 0 X 1 1 1 1 F Drive Address Reserved 1 1 X X X X 0 8 Even RD Data Even WR Data 3. Accesses to even addresses between 400H and 7FFH access register 8. Accesses to odd addresses between 400H and 7FFH access register 9. This 1 KByte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data register FIFO and does not allow random access to the data buffer within the CompactFlash card. A word access to address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus. 1 1 X X X X 1 9 Odd RD Data Odd WR Data 3 T9-4.0 1298

9.1.4 True IDE Mode Addressing

When the CompactFlash card is configured in the True IDE mode, the I/O decoding is as follows:

9.1.5 CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the Com- pactFlash device. These registers are often collectively referred to as the “task file.” Note: In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset address may be accessed at its normal address and also the corresponding even address (normal address -1) using data bus lines (D15-D8) when CE1# is high and CE2# is low unless IOIS16# is high (not asserted) and an I/O cycle is being performed.

9.1.5.1 Data Register (Address - 1F0H[170H];Offset 0,8,9)

The Data register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash card data buffer and the Host. This register overlaps the Error register. The table below describes the combinations of data register access and is provided to assist in understanding the overlapped Data register and Error/Feature register rather than to attempt to define general PCMCIA word and byte access modes and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for I/O and Memory cycles. Note: Because of the overlapped registers, access to the 1F1H, 171H or offset 1 are not defined for word (CE2#=0 and CE1#=0) operations. These accesses are treated as accesses to the Word Data register. The dupli- cated registers at offsets 8, 9 and DH have no restrictions on the operations that can be performed by the socket. TABLE 9-5: T RUE IDE MODE I/O DECODING CE2# CE1# A 2 A1 A0 IORD#=0 IOWR#=0 1 0 0 0 0 RD Data WR Data 1 0 0 0 1 Error register Features 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector No. Sector No. 1 0 1 0 0 Cylinder Low Cylinder Low 1 0 1 0 1 Cylinder High Cylinder High 1 0 1 1 0 Select Card/Head Select Card/Head 1 0 1 1 1 Status Command 0 1 1 1 0 Alt Status Device Control T9-5.0 1298 Data Register CE2# CE1# A 0 Offset Data Bus Word Data Register 0 0 X 0,8,9 D 15-D0 Even Data Register 1 0 0 0,8 D 7-D0 Odd Data Register 1 0 1 9 D 7-D0 Odd Data Register 0 1 X 8,9 D 15-D8 Error / Feature Register 1 0 1 1, DH D 7-D0 Error / Feature Register 0 1 X 1 D 15-D8 Error / Feature Register 0 0 X DH D 15-D8

9.1.5.2 Error Register (Address - 1F1H[171H]; Offset 1, 0DH Read Only)

This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: This register is also accessed on data bits D15-D8 during a write operation to offset 0 with CE2# low and CE1# high. Symbol Function Bit 7 (BBK) This bit is set w hen a Bad Block is detected. Bit 6 (UNC) This bit is set when an Uncorrectable Error is encountered. Bit 5 This bit is 0. Bit 4 (IDNF) The requested sector ID is in error or cannot be found. Bit 3 This bit is 0. Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash card status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. Bit 1 This bit is 0. Bit 0 (AMNF) This bit is set in case of a general error.

9.1.5.3 Feature Register (Address - 1F1H[171H]; Offset 1, 0DH Write Only)

This register provides information regarding features of the CompactFlash card that the host can utilize. This register is also accessed on data bits D15-D8 during a write operation to Offset 0 with CE2# low and CE1# high.

9.1.5.4 Sector Count Register (Address - 1F2H[172H]; Offset 2)

This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the CompactFlash card. If the value in this register is zero, a count of 256 sectors is speci- fied. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request.

9.1.5.5 Sector Number (LBA 7-0) Register (Address - 1F3H[173H]; Offset 3)

This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any CompactFlash card data access for the subsequent command.

9.1.5.6 Cylinder Low (LBA 15-8) Register (Address - 1F4H[174H]; Offset 4)

This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of then Logical Block Address.

9.1.5.7 Cylinder High (LBA 23-16) Register (Address - 1F5H[175H]; Offset 5)

This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. This register is also accessed on data bits D15-D8 during a write operation to offset 0 with CE2# low and CE1# high. D7 D6 D5 D4 D3 D2 D1 D0 Reset Value BBK UNC 0 IDNF 0 ABRT 0 AMNF 0000 0000b

9.1.5.8 Drive/Head (LBA 27-24) Register (Address 1F6H[176H]; Offset 6)

The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined as follows: Symbol Function Bit 7 This bit is set to 1. Bit 6 LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block mode, the Logical Block Address is interpreted as follows: LBA7-LBA0: Sector Number register D7-D0. LBA15-LBA8: Cylinder Low register D7-D0. LBA23-LBA16: Cylinder High register D7-D0. LBA27-LBA24: Drive/Head register bits HS3-HS0. Bit 5 This bit is set to 1. Bit 4 (DRV) DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card) 1 is selected. The CompactFlash card is set to be Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register. Bit 3 (HS3) When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode. Bit 2 (HS2) When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. Bit 1 (HS1) When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. Bit 0 (HS0) When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode. D7 D6 D5 D4 D3 D2 D1 D0 Reset Value

1 LBA 1 DRV HS3 HS2 HS1 HS0 1010 0000b

9.1.5.9 Status & Alternate Status Registers (Address 1F7H[177H]&3F6H[376H]; Offsets 7 & E)

These registers return the CompactFlash card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are described as follows: Symbol Function Bit 7 (BUSY) The busy bit is set when the CompactFlash card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. Bit 6 (RDY) RDY indicates whether the device is capable of performing CompactFlash card operations. This bit is cleared at power up and remains cleared until the CompactFlash card is ready to accept a command. Bit 5 (DWF) This bit, if set, indicates a write fault has occurred. Bit 4 (DSC) This bit is set when the CompactFlash card is ready. Bit 3 (DRQ) The Data Request is set when the CompactFlash card requires that information be transferred either to or from the host through the Data register. Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. Bit 1 (IDX) This bit is always set to 0. Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers.

9.1.5.10 Device Control Register (Address - 3F6H[376H]; Offset E)

This register is used to control the CompactFlash card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY . The bits are defined as follows: Symbol Function Bits 7-3 These bits are ignored by the CompactFlash card. Bit 2 (SW Rst) This bit is set to 1 in order to force the CompactFlash card to perform an ATA Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration registers (Sections 8.2 to 8.4) as a hardware reset does. The card remains in Reset until this bit is reset to ‘0.’ Bit1(-IEn) The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash card are disabled. This bit also controls the Int bit in the Configuration and Status register. This bit is set to 0 at Power-on and Reset. Bit0 This bit is ignored by the CompactFlash card. D7 D6 D5 D4 D3 D2 D1 D0 Reset Value BUSY RDY DWF DSC DRQ CORR 0 ERR 1000 0000b D7 D6 D5 D4 D3 D2 D1 D0 Reset Value XXXXX S W R s t - I E n 0 0000 1000b

9.1.5.11 Card (Drive) Address Register (Address3F7H[377H]; Offset F)

This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows: Symbol Function Bit 7 X = don’t care Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash card. Following are some possible solutions to this problem for the PCMCIA implementation: 1. Locate the CompactFlash card at a non-conflicting address, i.e. Secondary address (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2. Do not install a Floppy and a CompactFlash card in the system at the same time. 3. Implement a socket adapter which can be programmed to (conditionally) tri-state D7 of I/0 address 3F7H/377H when a CompactFlash card is installed and conversely to tri-state D 6-D0 of I/O address 3F7H/377H when a floppy controller is installed. 4. Do not use the CompactFlash card’s Drive Address register. This may be accom- plished by either a) If possible, program the host adapter to enable only I/O addresses 1F0H-1F7H, 3F6H (or 170H-177H, 176H) to the CompactFlash card or b) if provided use an additional Primary/Secondary configuration in the CompactFlash card which does not respond to access es to I/O locations 3F7H and 377H. With either of these implementations, the host software must not attempt to use informa- tion in the Drive Address register. Bit 6 (-WTG) This bit is 0 when a write operation is in progress, otherwise, it is 1. Bit 5 (-HS3) This bit is the negation of bit 3 in the Drive/Head register. Bit 4 (-HS2) This bit is the negation of bit 2 in the Drive/Head register. Bit 3 (-HS1) This bit is the negation of bit 1 in the Drive/Head register. Bit 2 (-HS0) This bit is the negation of bit 0 in the Drive/Head register. Bit 1 (-nDS1) This bit is 0 when drive 1 is active and selected. Bit 0 (-nDS0) This bit is 0 when the drive 0 is active and selected.

9.2 CF-ATA Command Description

This section defines the software requirements and the format of the commands the host sends to the Compact- Flash cards. Commands are issued to the CompactFlash card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command register. The manner in which a command is accepted varies. There are three classes (see Table 9-6) of command acceptance, all depen- dent on the host not issuing commands unless the CompactFlash card is not busy (BSY=0). Table 9-6 summarizes the CF-ATA command set with the paragraphs that follow describing the individual com- mands and the task file for each. D7 D6 D5 D4 D3 D2 D1 D0 Reset Value X -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0 x111 1110b

1 Check-Power-mode E5H or 98H - - - - D -

1 Execute-Drive-Diagnostic 90H - - - - D -

1 Erase-Sector(s) C0H - Y

7 YY Y 8 Y

1 F l u s h - C a c h e E 7 H ---- D -

2 Format-Track 50H - Y - Y Y Y

1 Identify-Drive ECH - - - - D -

1 Idle E3H or 97H - Y - - D -

1 Idle-Immediate E1H or 95H - - - - D -

1 Initialize-Drive-Parameters 91H - Y - - Y -

1 N O P 0 0 H ---- D -

1 Read-Buffer E4H - - - - D -

1 Read-Multiple C4H - Y Y Y Y Y

1 Read-Sector(s) 20H or 21H - Y Y Y Y Y

1 Read-Verify-Sector(s) 40H or 41H - Y Y Y Y Y

1 Recalibrate 1XH - - - - D -

1 Request-Sense 03H - - - - D -

1 Security-Disable-Password F6H - - - - D -

1 Security-Erase-Prepare F3H - - - - D -

1 Security-Erase-Unit F4H - - - - D -

1 Security-Freeze-Lock F5H - - - - D -

1 S e c u r i t y - S e t - P a s s w o r d F 1 H ---- D -

1 Security-Unlock F2H - - - - D -

1 Set-Features EFH Y - - - D -

1 Set-Multiple-mode C6H - Y - - D -

1 Set-Sleep-mode E6H or 99H - - - - D -

1 Stand-By E2H or 96H - - - - D -

1 Stand-By-Immediate E0H or 94H - - - - D -

1 Translate-Sector 87H - Y Y Y Y Y

2 Write-Buffer E8H - - - - D -

3 Write-Multiple C5H - Y Y Y Y Y

3 Write-Multiple-w/o-Erase CDH - Y Y Y Y Y

2 Write-Sector(s) 30H or 31H - Y Y Y Y Y

2 Write-Sector(s)-w/o-Erase 38H - Y Y Y Y Y

3 Write-Verify 3CH - Y Y Y Y Y

T9-6.0 1298 1. FR = Features register 2. SC = Sector Count register 3. SN = Sector Number register 4. CY = Cylinder registers 5. DH = Card/Drive/Head register 6. LBA = Logical Block Address mode Suppor ted (see command descriptions for use). 7. Y = The register contains a valid parameter for this command. 8. For the Drive/Head register:Y - both the CompactFlash card and head parameters are used; D - only the CompactFlash card parameter is valid and not the head parameter.

9.2.1 Check-Power-Mode - 98H or E5H

This command checks the power mode. Because the CompactFlash card controller can recover from sleep in 200 ns, the device always enters power-saving mode when a command is completed. Co mpactFlash card contro ller sets BSY , sets the Sector Count register to 00H, clears BSY , and generates an interrupt.

9.2.2 Execute Drive Diagnostic - 90H

This command performs the internal diagnostic tests implemented by the CompactFlash card. If in PCMCIA configuration this command runs only on the CompactFlash card which is addressed by the Drive/Head register when the diagnostic command is issued. This is because PCMCIA card interface does not allows for direct inter-drive communication (such as the ATA PDIAG# and DASP# signals). If in True IDE mode the Drive bit is igno red and the diagnostic command is executed by both the master and the slave with the master responding with status for both devices. The Diagnostic codes shown in Table 9-7 are returned in the Error register at the end of the command. B i t - > 76543210 Command (7) 98H or E5H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X B i t - > 76543210 Command (7) 90H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X TABLE 9-7: D IAGNOSTIC CODES Code Error Type 01H No Error Detected 02H Formatter Device Error 03H Sector Buffer Error 04H ECC Circuitry Error 05H Controlling Mi croprocessor Error 8XH Slave Error in True IDE mode T9-7.0 1298

9.2.3 Erase-Sector(s) - C0H

This command is used to pre-erase and condition data sectors in advance of a Write-Without-Erase or Write-Multiple-Without-Erase command. There is no data transfer associated with this command but a Write Fault error status can occur.

9.2.4 Flush-Cache - E7H

This command causes the CompactFlash card controlle r to complete writing da ta from its cache. The CompactFlash card controller then clears BSY and generates an interrupt.

9.2.5 Format-Track - 50H

This command is accepted for host backward compatibility. The CompactFlash card controller expects a sector buffer of data from the host to follow the command with the same protocol as the Write- Sector(s) command although the information in the buffer is not used by the CompactFlash card controller. The use of this command is not recommended. B i t - > 76543210 Command (7) C0H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X B i t - > 76543210 Command (7) E7H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X B i t - > 76543210 Command (7) 50H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) X (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X

9.2.6 Identify-Drive - ECH

The Identify-Drive command enables the host to receive parameter information from the CompactFlash card controller. This command has the same protocol as the Read-Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table 9-8. All reserved bits or words are zero. Table 9-8 gives the definition for each field in the Identify-Drive information. B i t - > 76543210 Command (7) ECH C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X TABLE 9-8: I DENTIFY-DRIVE INFORMATION (1 OF 2) Word Address Default Value Total Bytes Data Field Type Information 0 848AH 2 General configuration bit-significant information 1 bbbbH 1 2 Default number of cylinders 2 0000H 2 Reserved 3 bbbbH 1 2 Default number of heads 4 0000H 2 Number of unformatted bytes per track 5 0000H 2 Number of unformatted bytes per sector 6 bbbbH 1 2 Default number of sectors per track 7-8 nnnnH 2 4 Number of sectors per card (Word 7 = MSW, Word 8 = LSW) 9 xxxxH 2 Vendor Unique 10-14 eeeeH 3 10 User-programmable serial number in ASCII 15-19 ddddH 4 10 SST preset, unique ID in ASCII 20 0002H 2 Buffer type 21 nnnnH 2 2 Buffer size in 512 Byte increments 22 0004H 2 # of ECC bytes passed on Read/Write Long Commands 23-26 aaaaH 5 8 Firmware revision in ASCII. Big Endian Byte Order in Word 27-46 ccccH 6 40 Model number in ASCII. Big Endian Byte Order in Word 47 0001H 2 Maximum number of sectors on Read/Write Multiple command 48 0000H 2 Reserved 49 0A00H 2 Capabilities 50 0000H 2 Reserved 51 0200H 2 PIO data transfer cycle timing mode 52 0000H 2 Reserved 53 0003H 2 Translation parameters are valid 54 nnnnH 2 2 Current numbers of cylinders 55 nnnnH 2 2 Current numbers of heads 56 nnnnH 2 2 Current sectors per track 57-58 nnnnH 2 4 Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW)

9.2.6.1 Word 0: General Configuration

This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a transfer rate greater than 10 MByte/sec and is not MFM encoded.

9.2.6.2 Word 1: Default Number of Cylinders

This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders.

9.2.6.3 Word 3: Default Number of Heads

This field contains the number of translated heads in the default translation mode.

9.2.6.4 Word 4: Number of Unformatted Bytes per Track

This field contains the number of sectors per track in the default translation mode.

9.2.6.5 Word 5: Number of Unformatted Bytes per Sector

This field contains the number of sectors per CompactFlash card controller. This double word value is also the first invalid address in LBA translation mode. This field is only required by CF feature set support.

9.2.6.6 Word 6: Default Number of Sectors per Track

This field contains the number of sectors per track in the default translation mode. 59 0100H 2 Multiple sector setting 60-61 nnnnH 2 4 Total number of sectors addressable in LBA mode 62-63 0000H 4 Reserved (DMA data transfer is not supported in CompactFlash) 64 0003H 2 Advanced PIO Transfer mode supported 65-66 0000H 4 Reserved 67 0078H 2 Minimum PIO transfer cycle time without flow control 68 0078H 2 Minimum PIO transfer cycle time with IORDY flow control 69-79 0000H 22 Reserved 80-81 0000H 4 CF card will not return ATA revision value 82 706AH 2 Features/command sets supported 83 4004H 2 Features/command sets supported 84 4000H 2 Features/command sets supported 85-87 xxxxH 6 Features/comm and sets enabled 88 0000H 2 Reserved 89 xxxxH 2 Time required for Security Erase 90 0000H 2 Time required for Enhanced Security Erase Unit completed 91-127 0000H 74 Reserved 128 xxxxH 2 Security Status 129-159 xxxxH 62 Vendor unique bytes 160-255 0000H 192 Reserved T9-8.0 1298 1. bbbb - default value set by controller. The selections could be user (manufacturer) programmable. 2. nnnn - calculated data based on product configuration 3. eeee - the default value is 2020H 4. dddd - unique number of each device 5. aaaa - any unique SST firmware revision 6. cccc - default value is “xxxx MB CompactFlash Card” TABLE 9-8: I DENTIFY-DRIVE INFORMATION (CONTINUED) (2 OF 2) Word Address Default Value Total Bytes Data Field Type Information

9.2.6.7 Word 7-8: Number of Sectors per Card

This field contains the number of sectors per CompactFlash card. This double word va lue is also the first invalid address in LBA translation mode.

9.2.6.8 Word 10-19: Memory Card Serial Number

The contents of this field are right justified and padded with spaces (20H). The right-most ten bytes are an SST preset, unique ID. The left-most ten bytes are a user-programmable value with a default value of spaces

9.2.6.9 Word 20: Buffer Type

This field defines the buffer capability: 0002H: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the Com- pactFlash card controller.

9.2.6.10 Word 21: Buffer Size

This field defines the buffer capacity in 512 Byte increments. SST’s CompactFlash card controller has up to 8 sec- tor data buffer for host interface.

9.2.6.11 Word 22: ECC Count

This field defines the number of ECC bytes used on each sector in the Read and Write Long commands.

9.2.6.12 Word 23-26: Firmware Revision

This field contains the revision of the firmware for this product.

9.2.6.13 Word 27-46: Model Number

This field contains the model number for this product and is left justified and padded with spaces (20H).

9.2.6.14 Word 47: Read/Write Multiple Sector Count

This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands. SST’s CompactFlash card controller can support up to 2 sectors for Read-Multiple or Write-Multiple commands.

9.2.6.15 Word 49: Capabilities

13 Standby Timer

0: forces sleep mode when host is inactive.

11 IORDY Support

1: CompactFlash card controller supports PIO Mode-4.

9 LBA support

1: CompactFlash card controller supports LBA mode addressing.

8 DMA Support

0: DMA mode is not supported.

9.2.6.16 Word 51: PIO Data Transfer Cycle Timing Mode

This field defines the mode for PIO data transfer. CompactFlash card controller supports up to PIO Mode-4.

9.2.6.17 Word 53: Translation Parameters Valid

0 1: words 54-58 are valid and reflect the current number of cylinders, heads and sectors. 1 1: words 64-70 are valid to support PIO Mode-4.

9.2.6.18 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track

These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode.

9.2.6.19 Word 57-58: Current Capacity

This field contains the product of the current cylinders times heads times sectors.

9.2.6.20 Word 59: Multiple Sector Setting

This field contains a validity flag in the Odd Byte and the current number of sectors that can be transferred per interrupt for R/W Multiple in the Even Byte. The Odd Byte is always 01H which indicates that the Even Byte is always valid. The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this word by default contains a 00H which indicates that R/W Multiple commands are not valid.

9.2.6.21 Word 60-61: Total Sectors Addressable in LBA Mode

This field contains the number of sectors addressable for the CompactFlash card controller in LBA mode only.

9.2.6.22 Word 62-63: Multi-word DMA Transfer Mode

Multi-word DMA Transfer mode is not supported.

9.2.6.23 Word 64: Advanced PIO Data Transfer Mode

0 1: CompactFlash card controller supports PIO Mode-3. 1 1: CompactFlash card controller supports PIO Mode-4.

9.2.6.24 Word 65-66: Multi-word DMA Transfer Mode

Multi-word DMA Transfer mode is not supported.

9.2.6.25 Word 67: Minimum PIO Transfer Cycle Time Without Flow Control

The CompactFlash card controller minimum cycle time is 120 ns.

9.2.6.26 Word 68: Minimum PIO Transfer Cycle Time With IORDY

The CompactFlash card controller minimum cycle time is 120 ns, e.g., PIO Mode-4.

9.2.6.27 Words 82-84: Features/command sets supported

Words 82, 83, and 84 indicate the features and command sets supported. Word 82 Bit Function 15 0: Obsolete 14 1: NOP command is supported 13 1: Read Buffer command is supported 12 1: Write Buffer command is supported 11 0: Obsolete 10 0: Host Protected Area feature set is not supported 9 0: Device Reset command is not supported 8 0: Service interrupt is not supported 7 0: Release interrupt is not supported 6 1: Look-ahead is supported 5 1: Write cache is supported 4 0: Packet Command feature set is not supported 3 1: Power Management feature set is supported 2 0: Removable Media feature set is not supported 1 1: Security Mode feature set is supported 0 0: SMART feature set is not supported Word 83 The values in this word should not be depended on by host implementers. Bit Function 15 0: Provides indication that the features/command sets supported words are not valid 14 1: Provides indication that the features/command sets supported words are valid 13-9 0: Reserved 8 0: Set-Max security extension is not supported 7-5 0: Reserved 4 0: Removable Media Status feature set is not supported 3 0: Advanced Power Management feature set is not supported 2 1: CFA feature set is supported 1 0: Read DMA Queued and Write DMA Queued commands are not supported 0 0: Download Microcode command is not supported Word 84 The values in this word should not be depended on by host implementers. Bit Function 15 0: Provides indication that the features/command sets supported words are valid 14 1: Provides indication that the features/command sets supported words are valid 13-0 0: Reserved

9.2.6.28 Words 85-87: Features/command sets enabled

Words 85, 86, and 87 indicate features/command sets enabled. The host can enable/disable the features or command set only if they are supported in Words 82-84. Word 85 Bit Function 15 0: Obsolete 14 0: NOP command is not enabled 1: NOP command is enabled 13 0: Read Buffer command is not enabled 1: Read Buffer command is enabled 12 0:Write Buffer command is not enabled 1: Write Buffer command is enabled 11 0: Obsolete 10 0: Host Protected Area feature set is not enabled 9 0: Device Reset command is not enabled 8 0: Service interrupt is not enabled 7 0: Release interrupt is not enabled 6 0: Look-ahead is not enabled 1: Look-ahead is enabled 5 0: Write cache is not enabled 1: Write cache is enabled 4 0: Packet Command feature set is not supported 3 1: Power Management feature set is supported 2 0: Removable Media feature set is not supported 1 0: Security Mode feature set has not been enabled via the Security Set Password command 1: Security Mode feature set has been enabled via the Security Set Password command 0 0: SMART feature set is not enabled Word 86 Bit Function 15-9 0: Reserved 8 0: Set-Max security extension is not enabled 7-5 0: Reserved 4 0: Removable Media Status feature set is not enabled 3 0: Advanced Power Management feature set is not enabled via the Set Features command 2 1: CFA feature set is enabled 1 0: Read DMA Queued and Write DMA Queued commands are not enabled 0 0: Download Microcode command is not enabled Word 87 The values in this word should not be depended on by host implementers. Bit Function 15 0: Provides indication that the features/command sets supported words are valid 14 1: Provides indication that the features/command sets supported words are valid 13-0 0: Reserved

9.2.6.29 Word 89: Time required for Security erase unit completion

Word 89 specifies the time required for the Security Erase Unit command to complete. This command shall be sup- ported on CompactFlash Storage Cards that support security.

9.2.6.30 Word 90: Time required for Enhanced security erase unit completion

Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete. This command shall be supported on CompactFlash Storage Cards that support security. Bit Function

8 Security Level

1: Security mode is enabled and the security level is maximum. 0: Security mode is enabled and the security level is high.

5 Enhanced security erase unit feature supported

1: Enhanced security erase unit feature set is supported.

4 Expire

1: Security count has expired and Security Unlock and Security Erase Unit are command aborted until a power-on reset or hard reset. 3F r e e z e 1: Security is frozen. 2L o c k 1: Security is locked.

1 Enable/Disable

1: Security is enabled. 0: Security is disabled.

0 Capability

1: CompactFlash Storage card supports security mode feature set. 0: CompactFlash Storage card does not support security mode feature set. Value Time

0 Value not specified

1-254 (Value * 2) minutes 255 >508 minutes Value Time 1-254 (Value * 2) minutes 255 >508 minutes

9.2.6.32 Idle - 97H or E3H

This command causes the CompactFlash card controller to set BSY , enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic Power-down mode is enabled. If the sector count is zero, the automatic Power-down mode is also enabled, the timer count is set to 1, with each count being 5 ms. Note that this time base (5 msec) is different from the ATA specification.

9.2.6.33 Idle-Immediate - 95H or E1H

This command causes the CompactFlash card controller to set BSY , enter the Idle mode, clear BSY and generate an interrupt. B i t - > 76543210 Command (7) 97H or E3H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) Timer Count (5 msec increments) Feature (1) X B i t - > 76543210 Command (7) 95H or E1H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.34 Initialize-Drive-Parameters - 91H

This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Drive/Head registers are used by this command.

9.2.6.35 NOP - 00H

This command always fails with the CompactFlash card controller returning command aborted.

9.2.6.36 Read-Buffer - E4H

The Read-Buffer command enables the host to read the current contents of the CompactFlash card controller’s sector buffer. This command has the same protocol as the Read-Sector(s) command B i t - > 76543210 Command (7) 91H C/D/H (6) X 0 X Drive Max Head (no. of heads-1) Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) Number of Sectors Feature (1) X B i t - > 76543210 Command (7) 00H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X B i t - > 76543210 Command (7) E4H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.37 Read-Multiple - C4H

Note: The current revision of the CompactFlash card controller can support up to a block count of 1 as indicated in the Identify-Drive Command information. The Read-Multiple command is similar to the Read-Sector(s) command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the Read-Sectors operation except that the number of sectors defined by a Set Multiple command are transferred wi thout intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set- Multiple-Mode command, which must be executed prior to the Read-Multiple command. When the Read-Multiple command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = remainder (sector count/block count). If the Read-Multiple command is attempted before the Set-Multiple-Mode command has been executed or when Read-Multiple commands are disabled, the Read-Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read-Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read-Sector(s) command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. At command completion, the Command Block registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. B i t - > 76543210 Command (7) C4H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X

9.2.6.38 Read-Sector(s) - 20H or 21H

This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. When this command is issued and after each sector of data (except the last one) has been read by the host, the CompactFlash card controller sets BSY , puts the sector of data in the buffer, sets DRQ, clears BSY , and generates an interrupt. The host then reads the 512 Bytes of data from the buffer. At command completion, the Command Block registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. B i t - > 76543210 Command (7) 20H or 21H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X

9.2.6.39 Read-Verify-Sector(s) - 40H or 41H

This command is identical to the Read-Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the CompactFlash card controller sets BSY . When the requested sectors have been verified, the CompactFlash card controlle r clears BSY and generates an interrupt. Upon command completion, the Command Block registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count register contains the number of sectors not yet verified.

9.2.6.40 Recalibrate - 1XH

This command is effectively a NOP command to the CompactFlash card controller and is provided for compatibility purposes. B i t - > 76543210 Command (7) 40H or 41H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X B i t - > 76543210 Command (7) 1XH C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.41 Request-Sense - 03H

This command requests extended error information for the previous command. Table 9-9 defines the valid extended error codes for the CompactFlash card controller. The extended error code is returned to the host in the Error register. B i t - > 76543210 Command (7) 03H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X TABLE 9-9: E XTENDED ERROR CODES Extended Error Code Description 00H No Error Detected 01H Self Test OK (No Error) 09H Miscellaneous Error 20H Invalid Command 21H Invalid Address (Requested Head or Sector Invalid) 2FH Address Overflow (Address Too Large) 35H, 36H Supply or generated Voltage Out of Tolerance 11H Uncorrectable ECC Error 18H Corrected ECC Error 05H, 30-34H, 37H, 3EH Self Test or Diagnostic Failed 10H, 14H ID Not Found 3AH Spare Sectors Exhausted 1FH Data Transfer Error / Aborted Command 0CH, 38H, 3BH, 3CH, 3FH Corrupted Media Format 03H Write / Erase Failed T9-9.0 1298

9.2.6.42 Security-Disable-Password - F6H

This command requests a transfer of a single sector of data from the host. Table 9-10 defines the content of this sector of information. If the password selected by Word 0 matches the password previously saved by the device, the device disables the lock mode. This command does not change the Master password that may be reactivated later by setting a User password.

9.2.6.43 Security-Erase-Prepare - F3H

This command is issued immediately before the Security-Erase-Unit command to enable device erasing and unlocking. This command prevents accidental erasure of the data in the flash media. B i t - > 76543210 Command (7) F6H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X TABLE 9-10: S ECURITY PASSWORD DATA CONTENT Word Content

0 Control Word

Bit 0: Identifier 0: Compare User Password 1: Compare Master Password Bit 1-15: Reserved 1-16 Password (32 Bytes) 17-256 Reserved T9-10.0 1298 B i t - > 76543210 Command (7) F3H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.44 Security-Erase-Unit - F4H

This command requests transfer of a single sector of data from the host. Table 9-10 defines the content of this sector of information. If the password does not match the password previously saved by the CompactFlash card cont roller, the CompactFlash card cont roller rejects the command with command aborted. The Security-Erase-Prepare command should be completed immediately prior to the Security- Erase-Unit command. If the CompactFlash card controller receives a Security-Erase-Unit command without an immediately prior Security-Erase-Prepare command, the CompactFlash card controller aborts the Security-Erase-Unit command.

9.2.6.45 Security-Freeze-Lock - F5H

The Security-Freeze-Lock command sets the CompactFlash card controller to Frozen mode. After command completion, any other commands that update the CompactFlash card controller Lock mode are rejected. Frozen mode is disabled by power off or hardware reset. If Security-Freeze-Lock is issued when the CompactFlash card controller is in Frozen mode, the command executes and the CompactFlash card controller remains in Frozen mode. After command completion, the sector count register should be set to 0. Commands disabled by Security-Freeze-Lock are: - Security-Set-Password - Security-Unlock - Security-Disable-Password - Security-Erase-Unit If security mode feature set is not supported, this command will be handled as an invalid command. B i t - > 76543210 Command (7) F4H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X B i t - > 76543210 Command (7) F5H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.46 Security-Set-Password - F1H

This command requests a transfer of a single sector of data from the host. Table 9-11 defines the content of the sector of information. The data transferred controls the function of this command. Table 9-12 defines the interaction of the identifier and security level bits. B i t - > 76543210 Command (7) F1H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X TABLE 9-11: S ECURITY PASSWORD DATA CONTENT Word Content Bit 0: Identifier 0: Compare User Password 1: Compare Master Password Bit 1-15: Reserved 1-16 Password (32 Bytes) 17-256 Reserved T9-11.0 1298 TABLE 9-12: I DENTIFIER AND SECURITY LEVEL BIT INTERACTION Identifier Level Command result User High The password supplied with the command is saved as the new User password. The lock mode will be enabled from the next Power-on or hardware reset. The CompactFlash card controller will then be unlocked by either the User password or the previously set Master password. User Maximum The password supplied with the command is saved as the new user password. The Lock mode will be enabled from the next Power-on reset or hardware reset. The Compact- Flash card controller will then be unlocked by only the User password. The Master password previously set is still stored in the CompactFlash card controller will not be used to unlock the CompactFlash card controller. Master High or Maximum This combination sets a Master password but does not enable or disable the Lock mode. The security level is not changed. T9-12.0 1298

9.2.6.47 Security-Unlock - F2H

This command requests transfer of a single sector of data from the host. Table 9-11 defines the content of this sector of information. If th e identifier bit is set to Master and th e device is in high security level, then the password supplied is compared with the stored Master password. If the device is in the maximum security level, then the unlock command will be rejected. If the identifier bit is set to user, then the device compares the supplied password with the stored User password. If the password compare fails, the device returns “command aborted” to the host and decrements the unlock counter. This counter is initially set to five an d is decremented for each password mismatch when Security-Unlock is issued and the device is locked. Once this coun ter reaches zero, the Security-Unlock and Security- Erase-Unit commands are command aborted until after a Power-on reset or a hardware reset is received. Security-Unlock commands issued when the device is unlocked have no effect on the unlock counter.

9.2.6.48 Seek - 7XH

This command is effectively a NOP command to the CompactFlash card controller although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. B i t - > 76543210 Command (7) F2H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X B i t - > 76543210 Command (7) 7XH C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) X (LBA 7-0) Sec Cnt (2) X Feature (1) X

9.2.6.49 Set-Features - EFH

This command is used by the host to establish or select certain features. Table 9-13 defines all features that are supported. B i t - > 76543210 Command (7) EFH C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) Config Feature (1) Feature TABLE 9-13: F EATURES SUPPORTED Feature Operation 01H Enable 8-bit data transfers. 02H1 1. SST CompactFlash card controller does not implement cache operations. These commands are returned with no error. Enable Write cache 03H Set transfer mode based on value in Sector Count register. Table 9-14 defines the values. 09H Enable Extended Power Operations 0AH NOP - Accepted for backward compatibility. 55H1 Disable Read Look Ahead. 66H Disable Power-on Reset (POR) establishment of defaults at software reset. 69H NOP - Accepted for backward compatibility. 81H Disable 8-bit data transfer. 82H

1 Disable Write Cache

89H Disable Extended Power operations 8AH NOP - Accepted for backward compatibility. 96H NOP - Accepted for backward compatibility. 97H Accepted for backward compatibility. Us e of this Feature is not recommended. 9AH 2. SST CompactFlash card controller has fixed power consumption. The command will be accepted and returned with no error. Set the host current source capability Allows trade-off between current drawn and Read/Write speed BBH 4 Bytes of data apply on Read/Write-Long-Sector commands. AAH Enable Read-Look-Ahead CCH Enable Power-on Reset (POR) establishment of defaults at software reset. T9-13.0 1298

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 Features 01H and 81H are used to enable and clear 8-bit data transfer mode. If the 01H feature command is issued all data tran sfers will occur on the low order D 7-D0 data bus and the IOCS16# signal will not be asserted for data register accesses. Feature 03H allows the host to select the transfer mode by specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One PIO mode is selected at all times. The host may change the selected modes by the Set-Features command. Features 66H and CCH can be used to enable and disable whether the Power-on Reset (POR) Defaults will be set when a software reset occurs. TABLE 9-14: T RANSFER MODE VALUES Mode Bits [7:3] Bits [2:0] PIO default mode 00000b 000b PIO default mode, disable IORDY 00000b 001b PIO flow control transfer mode 00001b mode 1 1. Mode = transfer mode number, all other values are not valid Reserved Other N/A T9-14.0 1298

9.2.6.50 Set-Multiple-Mode - C6H

This command enables the CompactFlash card controller to perform Read and Write-Multiple operations and establishes the block count for these commands. The Sector Count register is loaded with the number of sectors per block. Upon receipt of the command, the CompactFlash card controller sets BSY to 1 and checks the Sector Count register. If the Sector Count register contains a valid value (see Section 9.2.6.14 for details) and the block count is supported, the value is loaded for all subsequent Read-Multiple and Write-Multiple commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and Read-Multiple and Write-Multiple commands are disabled. If the Sector Count register contains 0 when the command is issued, Read and Write-Multiple commands are disabled. At power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write-Multiple disabled.

9.2.6.51 Set-Sleep-Mode - 99H or E6H

This command causes the CompactFlash card controller to set BSY , enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 15 milliseconds. B i t - > 76543210 Command (7) C6H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) Sector Count Feature (1) X B i t - > 76543210 Command (7) 99H or E6H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.52 Standby - 96H or E2H

This command causes the CompactFlash card controller to set BSY , enter the Sleep mode (which corresponds to the ATA Standby mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required).

9.2.6.53 Standby-Immediate - 94H or E0H

This command causes the CompactFlash card controller to set BSY , enter the Sleep mode (which corresponds to the ATA “Standby” mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). B i t - > 76543210 Command (7) 96H or E2H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X B i t - > 76543210 Command (7) 94H or E0H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.54 Translate-Sector - 87H

This command allows the host a method of determining the exact number of times a user sector has been erased and programmed. The controller responds with a 512 Byte buffer of information containing the desired cylinder, head, and sector, including its logical address, and the Hot Count, if available, for that sector. Table 9-15 represents the information in the buffer. Please note that this command is unique to the CompactFlash card controller.

9.2.6.55 Write-Buffer - E8H

The Write-Buffer command enables the host to overwrite contents of the CompactFlash card controller’s sector buffer with any data pattern des ired. This command has the same protocol as the Write-Sector(s) command and transfers 512 Bytes. B i t - > 76543210 Command (7) 87H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) X Feature (1) X TABLE 9-15: T RANSLATE-SECTOR INFORMATION Address Information 00H-01H Cylinder MSB (00H), Cylinder LSB (01H) 02H Head 03H Sector 04H-06H LBA MSB (04H) - LSB (06H) 07H-12H Reserved 13H Erased Flag (FFH) = Erased; 00H = Not Erased 14H-17H Reserved 18H-1AH Hot Count MSB (18H) - LSB (1AH) 1. A value of 0 indicates Hot Count is not supported. 1BH-1FFH Reserved T9-15.0 1298 B i t - > 76543210 Command (7) E8H C/D/H (6) XD r i v e X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X

9.2.6.56 Write-Multiple - C5H

Note: The current revision of the CompactFlash card controller can support up to a block count of 1 as indicated in the Identify-Drive Command information. This command is similar to the Write-Sectors co mmand. The CompactFlash card controller sets BSY within 400 ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write-Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set- Multiple-Mode command, which must be executed prior to the Write-Multiple command. When the Write-Multiple command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = remainder (sector count/block). If the Write-Multiple command is attempted before the Set-Multiple-Mode command has been executed or when Write-Multiple commands ar e disabled, the Write-Multiple operation will be rejected with an aborted command error. Errors encountered during Write-Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count register contains the residual number of sectors that need to be transferred for successful completion of the command e.g. each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count register contains 6 and the address is that of the third sector. B i t - > 76543210 Command (7) C5H C/D/H (6) 1L B A1 D r i v e H e a d Cyl High (5) Cylinder High Cyl Low (4) Cylinder Low Sec Num (3) Sector Number Sec Cnt (2) Sector Count Feature (1) X

9.2.6.57 Write-Multiple-Without-Erase - CDH

This command is similar to the Write-Multiple command with the exception that an implied Erase before Write operation is not performed. The sectors should be pre-erased with the Erase-Sector(s) command before this command is issued. If the sectors are not pre-erased with the Erase-Sector(s) command, a normal Write-Multiple operation will occur.

9.2.6.58 Write-Sector(s) - 30H or 31H

This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. When this command is accepted, the CompactFlash card controller sets BSY , then sets DRQ and clears BSY , then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the fi rst sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. B i t - > 76543210 Command (7) CDH C/D/H (6) 1L B A1 D r i v e H e a d Cyl High (5) Cylinder High Cyl Low (4) Cylinder Low Sec Num (3) Sector Number Sec Cnt (2) Sector Count Feature (1) X B i t - > 76543210 Command (7) 30H or 31H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X

9.2.6.59 Write-Sector(s)-Without-Erase - 38H

This command is similar to the Write-Sector(s) command with the exception that an implied Erase before Write operation is not performed. This command has the same protocol as the Write-Sector(s) command. The sectors should be pre-erased with the Erase-Sector(s) command before this command is issued. If the sector is not pre-erased with the Erase-Sector(s) command, a normal Write-Sector operation will occur.

9.2.6.60 Write-Verify - 3CH

This command is similar to the Write-Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write-Sector(s) command. B i t - > 76543210 Command (7) 38H C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X B i t - > 76543210 Command (7) 3CH C/D/H (6) 1 LBA 1 Drive Head (LBA 27-24) Cyl High (5) Cylinder High (LBA 23-16) Cyl Low (4) Cylinder Low (LBA 15-8) Sec Num (3) Sector Number (LBA 7-0) Sec Cnt (2) Sector Count Feature (1) X

9.2.7 Error Posting

The following table summarizes the valid status and error value for all the CF-ATA Command set. Note: V = valid on this command TABLE 9-16: E RROR AND STATUS REGISTER Error Register Status Register Command BBK UNC IDNF ABRT AMNF DRDY DWF DSC CORR ERR Check-Power-mode V V V V V Execute-Drive-Diagnostic1 1. See Table 9-7 VVV E r a s e - S e c t o r ( s ) V VVVVVV V Flush-Cache V V V V V F o r m a t - T r a c k VVVVVV V Identify-Drive V V V V V I d l e V VVV V Idle-Immediate V V V V V Initialize-Drive-Parameters V V V NOP V V V V Read-Buffer V V V V V R e a d - M u l t i p l e VVVVVVVVVV Read-Sector(s) VVVVVVVVVV Read-Verify-Sectors VVVVVVVVVV R e c a l i b r a t e V VVV V Request-Sense VVVV Security-Disable-Password V VVV V Security-Erase-Prepare V V V V V Security-Erase-Unit V V V V V Security-Freeze-Lock V V V V V Security-Set-Password V V V V V S e c u r i t y - U n l o c k V VVV V S e e k VV VVV V Set-Features V V V V V Set-Multiple-mode V V V V V Set-Sleep-mode V V V V V Stand-By V V V V V Stand-By-Immediate V V V V V T r a n s l a t e - S e c t o r V VVVVVV V Write-Buffer V V V V V W r i t e - M u l t i p l e V VVVVVV V W r i t e - M u l t i p l e - w / o - E r a s e V VVVVVV V W r i t e - S e c t o r ( s ) V VVVVVV V W r i t e - S e c t o r ( s ) - w / o - E r a s e V VVVVVV V W r i t e - V e r i f y V VVVVVV V Invalid-Command-Code V V V V V T9-16.0 1298

10.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings (Applied conditions greater than t hose listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) 1. Please refer to Table 3-1 for pin assignment information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. TABLE 10-1: A BSOLUTE MAXIMUM POWER PIN STRESS RATINGS Parameter Symbol Conditions Input Power V DDQ VDD -0.3V min to 6.5V max -0.3V min to 4.0V max Voltage on any flash media interface pin with respect to VSS -0.5V min to VDD + 0.5V max Voltage on all other pins with respect to VSS -0.5V min to VDDQ + 0.5V max T10-1.0 1298 OPERATING RANGE Range Ambient Temperature V DD VDDQ AC CONDITIONS OF TEST See Figure 10-1 Note: All AC specifications are guaranteed by design. TABLE 10-2: R ECOMMENDED SYSTEM POWER-ON TIMING Symbol Parameter Typical Maximum Units TPU-INITIAL Drive Initialization to Ready 3 sec + (0.5 sec/GByte) 20 sec TPU-READY11 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. Host Power-on/Reset to Ready Operation 200 ms TPU-WRITE11 Host Power-on/Reset to Write Operation 200 ms T10-2.0 1298

10.1 DC Characteristics

TABLE 10-3: C APACITANCE (TA = 25°C, f=1 MHz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance V I/O = 0V 15 pF CIN1 Input Capacitance V IN = 0V 9 pF T10-3.0 1298 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. TABLE 10-4: R ELIABILITY CHARACTERISTICS Symbol Parameter Minimum Spec ification Units Test Method ILTH1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. Latch Up 100 + I DD mA JEDEC Standard 78 T10-4.0 1298 TABLE 10-5: DC C HARACTERISTICS FOR MEDIA INTERFACE Symbol Type Parameter Min Max Units Conditions VIH3 I3 Input Voltage 2.0 V V DD=VDD Max VIL3 0.8 V DD=VDD Min IIL3 I3Z Input Leakage Current -10 10 uA IU3 I3U Input Pull-Up Current -8 -50 uA ID3 I3D Input Pull-Down Current 30 200 uA VT+4 I4 Input Voltage Schmitt Trigger 2.5 V VT- 4 0.75 IIL4 I4Z Input Leakage Current -10 10 uA IU4 I4U Input Pull-Up Current -8 -50 uA VOH4 Output Voltage 2.4 V I OH4=IOH4 Min VOL4 0.4 I OL4=IOL4 Max IOH4 Output Current -1.5 mA V DD=VDD Min IOL4 Output Current 1.5 mA V DD=VDD Min VOH5 Output Voltage 2.4 V I OH5=IOH5 Min VOL5 0.4 I OL5=IOL5 Max IOH5 Output Current -3 mA V DD=VDD Min IOL5 Output Current 3 mA V DD=VDD Min T10-5.0 1298

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 TABLE 10-6: DC C HARACTERISTICS FOR HOST INTERFACE Symbol Type Parameter Min Max Units Conditions VIH1 I1 Input Voltage 2.0V V V DDQ=VDDQ Max VIL1 0.8V V DDQ=VDDQ Min IIL1 I1Z Input Leakage Current -10 10 uA IU1 I1U Input Pull-Up Current -110 -1 uA VT+2 I2 Input Voltage Schmitt Trigger 2.0 V V DDQ=VDDQ Max VT- 2 0.8 V DDQ=VDDQ Min IIL2 I2Z Input Leakage Current -10 10 uA IU2 I2U Input Pull-Up Current -110 -1 uA VOH1 Output Voltage 2.4 V I OH1=IOH1 Min VOL1 0.4 I OL1=IOL1 Max IOH1 Output Current -4 mA V DDQ=VDDQ Min IOL1 Output Current 4 mA V DDQ=VDDQ Min VOH2 Output Voltage 2.4 V I OH2=IOH2 Min VOL2 0.4 I OL2=IOL2 Max IOH2 Output Current -6 mA V DDQ=3.135V-3.465V IOL2 Output Current 6 mA V DDQ=3.135V-3.465V IOH2 Output Current -8 mA V DDQ=4.5V-5.5V IOL2 Output Current 8 mA V DDQ=4.5V-5.5V VOH6 Output Voltage for DASP# pin 2.4 V I OH6=IOH6 Min VOL6 0.4 I OL6=IOL6 Max IOH6 Output Current for DASP# pin -3 mA V DDQ=3.135V-3.465V IOL6 Output Current for DASP# pin 8 mA V DDQ=3.135V-3.465V IOH6 Output Current for DASP# pin -3 mA V DDQ=4.5V-5.5V IOL6 Output Current for DASP# pin 12 mA V DDQ=4.5V-5.5V IDD1,2 PWR Power supply current (T A = 0°C to +70°C) 50 mA V DD=VDD Max; VDDQ=VDDQ Max IDD1,2 PWR Power supply current (T A = -40°C to +85°C) 100 mA V DD=VDD Max; VDDQ=VDDQ Max ISP PWR Sleep/Standby/Idle current (T A = 0°C to +70°C) 100 µA V DD=VDD Max; VDDQ=VDDQ Max ISP PWR Sleep/Standby/Idle current (T A = -40°C to +85°C) 200 µA V DD=VDD Max; VDDQ=VDDQ Max T10-6.0 1298 1. Sequential data transfer for 1 sector read data from host interface and write data to media. 2. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter.

10.2 AC Characteristics

FIGURE 10-1: AC I NPUT/OUTPUT REFERENCE WAVEFORMS 1298 F02.0 REFERENCE POINTS OUTPUTINPUT VIT VIHT VILT VOT AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test

10.2.1 Attribute Memory Read Timing Specification

The Attribute Memory access time is defined as 100 ns. Detailed timing specifications are shown in Table 10-7. FIGURE 10-2: A TTRIBUTE MEMORY READ TIMING DIAGRAM TABLE 10-7: A TTRIBUTE MEMORY READ TIMING Speed Version 100 ns Item Symbol IEEE Symbol Min 1 1. D OUT signifies data provided by the CompactFlash card to the system. The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations. All AC specifications are guaranteed by design. Max1 Units Read Cycle Time tc(R) tAVAV 100 ns Address Access Time ta(A) tAVQV 100 ns Card Enable Access Time ta(CE) tELQV 100 ns Output Enable Access Time ta(OE) tGLQV 50 ns Output Disable Time from CE# tdis(CE) tEHQZ 50 ns Output Disable Time from OE# tdis(OE) tGHQZ 50 ns Address Setup Time tsu(A) tAVGL 10 ns Output Enable Time from CE# ten(CE) tELQNZ 5 ns Output Enable Time from OE# ten(OE) tGLQNZ 5 ns Data Valid from Address Change tv(A) tAXQX 0 ns T10-7.0 1298 1298 F03.0 An tc(R) ta(A) ta(CE) ta(OE) DOUT tdis(OE) tdis(CE) tv(A) ten(CE) ten(OE) tsu(A) REG# CE# OE# DOUT

10.2.2 Configuration Register (Attribute Memory) Write Timing specification

The card configuration write access time is defined as 100 ns. Detailed timing specifications are shown in Table 10-8. FIGURE 10-3: C ONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIMING DIAGRAM TABLE 10-8: C ONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIMING Speed Version 100 ns Item Symbol IEEE Symbol Min 1 1. D IN signifies data provided by the system to the CompactFlash card. All AC specifications are guaranteed by design. Max1 Units Write Cycle Time tc(W) tAVAV 100 ns Write Pulse Width tw(WE) tWLWH 60 ns Address Setup Time tsu(A) tAVWL 10 ns Write Recovery Time trec(WE) tWMAX 15 ns Data Setup Time for WE tsu(DWE#H) tDVWH 40 ns Data Hold Time th(D) tWMDX 15 ns T10-8.0 1298 1298 F04.0 Reg# DIN Valid tsu(D-WEH) tw(WE) tsu(A) trec(WE) tc(W) th(D) An WE# CE# OE# DIN

10.2.3 Common Memory Read Timing Specification

FIGURE 10-4: C OMMON MEMORY READ TIMING DIAGRAM TABLE 10-9: C OMMON MEMORY READ TIMING Item Symbol IEEE Symbol Min 1 1. All AC specifications are guaranteed by design. Max1 Units Output Enable Access Time ta(OE) tGLQV 50 ns Output Disable Time from OE tdis(OE) tGHQZ 50 ns Address Setup Time tsu(A) tAVGL 10 ns Address Hold Time th(A) tGHAX 15 ns CE Setup before OE tsu(CE) tELGL 0 ns CE Hold following OE th(CE) tGHEH 15 ns T10-9.0 1298 1298 F05.0 REG# th(CE) tdis(OE) tsu(CE) ta(OE) tsu(A) th(A) An CE# OE# DOUT DOUT

10.2.4 Common Memory Write Timing Specification

FIGURE 10-5: C OMMON MEMORY WRITE TIMING DIAGRAM TABLE 10-10: C OMMON MEMORY WRITE TIMING Item Symbol IEEE Symbol Min 1 1. All AC specifications are guaranteed by design. Max1 Units Data Setup before WE tsu(DWE#H) tDVWH 40 ns Data Hold following WE th(D) tWMDX 15 ns WE Pulse Width tw(WE) tWLWH 60 ns Address Setup Time tsu(A) tAVWL 10 ns CE Setup before WE tsu(CE) tELWL 0 ns Write Recovery Time trec(WE) tWMAX 15 ns Address Hold Time th(A) tGHAX 15 ns CE Hold following WE th(CE) tGHEH 15 ns T10-10.0 1298 1298 F06.0 REG# th(CE) trec(WE) th(D) tsu(CE) tw(WE) tsu(D-WEH) DIN Valid tsu(A) th(A) An CE# WE# DIN

10.2.5 I/O Input (Read) Timing Specification

Note: The maximum load on -INPACK and IOIS16# is 1 LSTTL with 50pF total load. FIGURE 10-6: I/O R EAD TIMING DIAGRAM TABLE 10-11: I/O R EAD TIMING Item Symbol IEEE Symbol Min 1 1. All AC specifications are guaranteed by design. Max1 Units Data Delay after IORD td(IORD) tlGLQV 100 ns Data Hold following IORD th(IORD) tlGHQX 0 ns IORD Width Time tw(IORD) tlGLIGH 165 ns Address Setup before IORD tsuA(IORD) tAVIGL 70 ns Address Hold following IORD thA(IORD) tlGHAX 20 ns CE Setup before IORD tsuCE(IORD) tELIGL 5 ns CE Hold following IORD thCE(IORD) tlGHEH 20 ns REG Setup before IORD tsuREG(IORD) tRGLIGL 5 ns REG Hold following IORD thREG(IORD) tlGHRGH 0 ns INPACK Delay Falling from IORD tdfINPACK(IORD) tlGLIAL 0 45 ns INPACK Delay Rising from IORD tdrINPACK(IORD) tlGHIAH 45 ns IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35 ns IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35 ns T10-11.0 1298 1298 F07.0 REG# tdrINPACK(IORD) tdfINPACK(IORD) tdrIOIS16(ADR) thA(IORD) thREG(IORD) thCE(IORD) td(IORD) th(IORD) DOUT tw(IORD) tsuA(IORD) tsuREG(IORD) tsuCE(IORD) An CE# IORD# INPACK# IOIS16# DOUT tdfIOIS16(ADR)

10.2.6 I/O Output (Write) Timing Specification

Note: The maximum load on -INPACK, and IOIS16# is 1 LSTTL with 50pF total load. FIGURE 10-7: I/O W RITE TIMING DIAGRAM TABLE 10-12: I/O W RITE TIMING Item Symbol IEEE Symbol Min 1 1. All AC specifications are guaranteed by design. Max1 Units Data Setup before IOWR tsu(IOWR) tDVIWH 60 ns Data Hold following IOWR th(IOWR) tlWHDX 30 ns IOWR Width Time tw(IOWR) tlWLIWH 165 ns Address Setup before IOWR tsuA(IOWR) tAVIWL 70 ns Address Hold following IOWR thA(IOWR) tlWHAX 20 ns CE Setup before IOWR tsuCE(IOWR) tELIWL 5 ns CE Hold following IOWR thCE(IOWR) tlWHEH 20 ns REG Setup before IOWR tsuREG(IOWR) tRGLIWL 5 ns REG Hold following IOWR thREG(IOWR) tlWHRGH 0 ns IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35 ns IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35 ns T10-12.0 1298 1298 F02-6.0 REG# tdrIOIS16(ADR) thA(IOWR) thREG(IOWR) thCE(IOWR) tw(IOWR) tdfIOIS16(ADR) tsu(IOWR) th(IOWR) DIN Valid tsuA(IOWR) tsuREG(IOWR) tsuCE(IOWR) An CE# IOWR# IOIS16# DIN

10.2.7 True IDE Mode I/O Input (Read) Timing Specification

Note: The maximum load on IOIS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. FIGURE 10-8: T RUE IDE MODE I/O READ TIMING DIAGRAM TABLE 10-13: T RUE IDE MODE I/O READ TIMING DIAGRAM Item Symbol IEEE Sy mbol Min Max Units Data Delay after IORD td(IORD) tlGLQV 50 ns Data Hold following IORD th(IORD) tlGHQX 5 ns IORD Width Time tw(IORD) tlGLIGH 70 ns Address Setup before IORD tsuA(IORD) tAVIGL 25 ns Address Hold following IORD thA(IORD) tlGHAX 10 ns CE Setup before IORD tsuCE(IORD) tELIGL 10 ns CE Hold following IORD thCE(IORD) tlGHEH 5 ns IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 20 ns IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 20 ns T10-13.0 1298 1298 F02-7.0 CE# tdrIOIS16(ADR) tdfIOIS16(ADR) thA(IORD) thCE(IORD) td(IORD) th(IORD) tsuA(IORD) tsuCE(IORD) tw(IORD) An IORD# IOIS16# DOUT DOUT

10.2.8 True IDE Mode I/O Output (Write) Timing Specification

Note: The maximum load on IOIS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. FIGURE 10-9: T RUE IDE MODE I/O WRITE TIMING DIAGRAM TABLE 10-14: T RUE IDE MODE I/O WRITE TIMING Item Symbol IEEE Symbol Min 1 1. All times are in nanoseconds. Max1 Data Setup before IOWR tsu(IOWR) tDVIWH 20 Data Hold following IOWR th(IOWR) tlWHDX 10 IOWR Width Time tw(IOWR) tlWLIWH 70 Address Setup before IOWR tsuA(IOWR) tAVIWL 25 Address Hold following IOWR thA(IOWR) tlWHAX 10 CE Setup before IOWR tsuCE(IOWR) tELIWL 10 CE Hold following IOWR thCE(IOWR) tlWHEH 5 IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 20 IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 20 T10-14.0 1298 1298 F02-8.0 CE# tdrIOIS16(ADR) tdfIOIS16(ADR) thA(IOWR) thCE(IOWR) th(IOWR)tsu(IOWR) DIN Valid tsuA(IOWR) tsuCE(IOWR) tw(IOWR) An IORD# IOIS16# DIN

10.2.9 Media Side Interfac e I/O Timing Specifications

Note: All AC specifications are guaranteed by design. TABLE 10-15: T IMING PARAMETERS Symbol Parameter Min Max Units TCLS FCLE Setup Time 20 - ns TCLH FCLE Hold Time 40 - ns TCS FCE# Setup Time 40 - ns TCH FCE# Hold Time for Command/Data Write Cycle 40 - ns TCHR FCE# Hold Time for Sequential Read Last Cycle - 40 ns TWP FWE# Pulse Width 20 - ns TWH FWE# High Hold Time 20 - ns TWC Write Cycle Time 40 - ns TALS FALE Setup Time 20 - ns TALH FALE Hold Time 40 - ns TDS FAD[15:0] Setup Time 20 - ns TDH FAD[15:0] Hold Time 20 - ns TRP FRE# Pulse Width 20 - ns TRR Ready to FRE# Low 40 - ns TRES FRE# Data Setup Access Time 20 - ns TRC Read Cycle Time 40 - ns TREH FRE# High Hold Time 20 - ns TRHZ FRE# High to Data Hi-Z 5 - ns T10-15.0 1298

11.0 APPENDIX

11.1 Differences between CF-ATA and PC Card-ATA/True IDE

This section details differences between CF-ATA vs. PC Card ATA and the differences between CF-ATA vs. True IDE.

11.1.1 Electrical Differences

11.1.1.1 TTL Compatibility

CF is not TTL compatible, it is a purely CMOS interface. Refer to Section 2.3.2 of this specification.

11.1.1.2 Pull Up Resistor Input Leakage Current

The minimum pull up resistor input leakage current is 50K ohms rather than the 10K ohms stated in the PCMCIA specification.

11.1.2 Functional Differences

11.1.2.1 Additional Set Features Codes in CF-ATA

The following Set Features codes are not PC Card ATA or True IDE, but provide additional functionality in CF-ATA. 69H, Accepted for backward compatibility 96H, Accepted for backward compatibility 97H, Accepted for backward compatibility 9AH, Set the host current source capability

11.1.2.2 Additional Commands in CF-ATA

The following commands are not standard PC Card ATA commands, but provide additional functionality in CF-ATA. The command codes for the commands below are defined as vendor unique in PC Card ATA/True IDE. C0H, Erase-Sectors 87H, Translate-Sector F5H, Wear-Level The command codes for the commands below are defined as reserved in PC Card ATA/True IDE: 03H, Request-Sense 38H, Write-Without-Erase CDH, Write-Multiple-Without-Erase

11.1.2.3 Idle Timer

The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified in PC Card ATA/True IDE.

11.1.2.4 Recovery from Sleep Mode

For CF devices, recovery from sleep mode is accomplis hed by simply issuing another command to the device. A hardware or software reset is not required.

12.0 PRODUCT ORDERING INFORMATION

12.1 Valid Co mbinations

Valid combinations for SST55LC100 SST55LC100-45-C-TQWE SST55LC100-45-C-BWE SST55LC100-45-I-TQWE SST55LC100-45-I-BWE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. SST 55 LC 100 - 45 - C - TQW E XX XX XXX -X X -X -X X X X Environmental Attribute E1 = non-Pb Package Modifier W = 100 leads or 84 ball positions (100 possible) Package Type TQ = TQFP B = TFBGA Operation Temperature C = Commercial: 0°C to +70°C I = Industrial: -40°C to +85°C Frequency 45 = 45 MHz Product Series 100 Function C = CompactFlash Controller Voltage L = 3.3V Product Series 55 = Media Controller 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

13.0 PACKAGING DIAGRAM

84-BALL THIN, FINE-PITCH, BALL GRID ARRAY (TFBGA) SST PACKAGE CODE: BW A1 CORNER K J H G F E D C B AA B C D E F G H J K BOTTOM VIEWTOP VIEW 9.0 ± 0.1 0.45 ± 0.05 (84X) A1 CORNER 9.0 ± 0.1 0.8 7.2 84-tfbga-BW-9x9-450mic-2 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registere d. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm (± 0.05 mm) 1mm SIDE VIEW SEATING PLANE 0.35 ± 0.05 1.1 ± 0.1 0.12 0.8 7.2

CompactFlash Card Controller SST55LC100 ©2005 Silicon Storage Technology, Inc. S71298-00-000 10/05 100-LEAD THIN QUAD FLAT PACK (TQFP) SST PACKAGE CODE: TQW TABLE 13-1: R EVISION HISTORY Number Description Date 00 Initial release of the data sheet (Advance Information) Oct 2005 .45 .75 1.00 nominal 0˚- 7˚ .95 1.05 .05 .15 DETAIL NOTE: 1. Complies with JEDEC publication 95 MS-026 variant AED dimensions although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is 0.25 mm. TOP VIEW 100-tqfp-TQW-0 0.17 0.27 0.50 BSC Pin #1 Identifier 14.00 BSC 16.00 BSC 14.00 BSC 16.00 BSC .09 .20 1.10 ± 0.10

14.0 PCMCIA STANDARD

CompactFlash memory cards are fully electrically compatible with the PCMCIA specifications listed below. These specifications may be obtained from: PCMCIA 2635 North First St. Ste. 209 San Jose, CA 95131 USA Phone: 408-433-2273 Fax: 408-433-9558

15.0 COMPACTFLASH SPECIFICATION

CompactFlash memory cards are fully compatible with the CompactFlash Specification published by the Compact- Flash Association. Contact the CompactFlash Association for more information. CompactFlash Association P .O. Box 51537 Palo Alto, CA 94303 USA Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, CA 94086 Telephone 408-735-9110 Fax 408-735-9036 www.SuperFlash.com or www.sst.com

Product Information

SST55LC100 specifications and overview.

Summary

CompactFlash Card Controller

Description

CompactFlash Card Controller

Source title SST55LC100 Datasheet(PDF) - Silicon Storage Technology, Inc

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