SST32HF1622C-70-4C-LSE

SST32HF1642 SST | Alldatasheet

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©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Preliminary Specifications FEATURES:

• ComboMemories organized as: – SST32HF1622C: 1M x16 Flash + 128K x16 SRAM – SST32HF1642x: 1M x16 Flash + 256K x16 SRAM – SST32HF1682: 1M x16 Flash + 512K x16 SRAM – SST32HF3242x: 2M x16 Flash + 256K x16 SRAM – SST32HF3282: 2M x16 Flash + 512K x16 SRAM  Single 2.7-3.3V Read and Write Operations  Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash  Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention  Low Power Consumption: – Active Current: 15 mA (typical) for Flash or SRAM Read – Standby Current: - SST32HFx2: 60 µA (typical) - SST32HFx2C: 12 µA (typical)  Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks  Erase-Suspend/Erase-Resume Capabilities  Security-ID Feature – SST: 128 bits; User: 128 bits  Hardware Block-Protection/WP# Input Pin – Top Block-Protection (top 32 KWord)  Fast Read Access Times: – Flash: 70 ns –S R A M : 7 0 n s  Latched Address and Data for Flash  Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical)  Flash Automatic Erase and Program Timing – Internal V PP Generation  Flash End-of-Write Detection – Toggle Bit – Data# Polling  CMOS I/O Compatibility  JEDEC Standard Command Set  Package Available – 63-ball LFBGA (8mm x 10mm x 1.4mm) – 62-ball LFBGA (8mm x 10mm x 1.4mm)  All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST32HFx2/x2C ComboMemory devices integrate a CMOS flash memory bank with a CMOS SRAM mem- ory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology. The SST32HF16x2/32x2 devices use a PseudoSRAM. The SST32HF16x2C/3242C devices use standard SRAM. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 µsec. To protect against inadvertent flash write, the SST32HFx2/x2C devices contain on-chip hardware and software data protection schemes. The SST32HFx2/x2C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HFx2/x2C devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program opera- tions in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HFx2/x2C provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automati- cally latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Pro- gram cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C SST32HF16x2x / 32x2x / 6482x16/32/64Mb Flash + 4/8Mb SRAM, 32Mb Flash + 8Mb SRAM (x16) MCP ComboMemories

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 The SST32HFx2/x2C devices are suited for applications that use both flash memory and (P)SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HFx2/x2C devices significantly improve performance and reliability while lowering power consumption when compared with multiple chip solutions. The SST32HFx2/x2C inherently use less energy during Erase and Program operations than alternative flash tech- nologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since, for any given voltage range, SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hard- ware does not have to be modified or de-rated as is neces- sary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. Device Operation The SST32HFx2/x2C use BES1#, BES2 and BEF# to con- trol operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the SRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consump- tion and loading. The device goes into standby when BEF# and BES1# bank enables are raised to V IHC (Logic High) or when BEF# is high and BES2 is low. Concurrent Read/Write Operation The SST32HFx2/x2C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alter- ation code to be executed from SRAM, while altering the data in flash. See Figure 26 for a flowchart. The following table lists all valid states. The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these com- mands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST32HFx2/x2C devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 6 for further details. C ONCURRENT READ/WRITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 Flash Word-Program Operation The flash memory bank of the SST32HFx2/x2C devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three- byte load sequence for Software Data Protection. The sec- ond step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs last. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Pro- gram operation, once initiated, will be completed, within 10 µs. See Figures 7 and 8 for WE# and BEF# controlled Pro- gram operation timing diagrams and Figure 21 for flow- charts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. During the command sequence, WP# should be statically held high or low. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector/Block-Erase Operation The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST32HFx2/x2C offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector- Erase operation is initiated by executing a six-byte com- mand sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A MS-A11 are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines A MS-A15 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 12 and 13 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored, WP# should be statically held high or low. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ 2 toggling and DQ 6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Flash Chip-Erase Operation The SST32HFx2/x2C provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for tim- ing diagram, and Figure 25 for the flowchart. Any com- mands issued during the Chip-Erase operation are ignored. Write Operation Status Detection The SST32HFx2/x2C provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The soft- ware detection includes two status bits: Data# Polling (DQ 7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which ini- tiates the internal Program or Erase operation.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either DQ 7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid. Flash Data# Polling (DQ7) When the SST32HFx2/x2C flash memory banks are in the internal Program operation, any attempt to read DQ 7 will produce the complement of the true data. Once the Pro- gram operation is completed, DQ 7 will produce true data. Note that even though DQ7 may have valid data immedi- ately following the completion of an internal Write opera- tion, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent suc- cessive Read cycles after an interval of 1 µs. During inter- nal Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program opera- tion. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 22 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any con- secutive attempts to read DQ 6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ 6 bit will stop toggling. The device is then ready for the next opera- tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ 6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is ini- tiated in a sector/block not selected in Erase-Suspend mode, DQ 6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ 2) is valid after the rising edge of the last WE# (or BEF#) pulse of Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 22 for a flowchart. Note: DQ7 and DQ2 require a valid address when reading status information. Flash Memory Data Protection The SST32HFx2/x2C flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the flash Write operation. This prevents inadvertent writes during power-up or power-down. TABLE 1: W RITE OPERATION STATUS Status DQ 7 DQ6 DQ2 Normal Operation Standard Program DQ7# Toggle No Toggle Standard Erase

0 Toggle Toggle

7# Toggle N/A T1.0 1253

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 Hardware Block Protection The SST32HFx2/x2C support top hardware block pro- tection, which protects the top 32 KWord block of the device. The Boot Block address ranges are described in T able 2. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase oper- ations on that block. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T RP , any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of T RHR is required after RST# is driven high before a valid Read can take place (see Figure 17). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Flash Software Data Protection (SDP) The SST32HFx2/x2C provide the JEDEC approved soft- ware data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HFx2/x2C devices are shipped with the software data protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within T RC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. SRAM Read The SRAM Read operation of the SST32HFx2/x2C is con- trolled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the out- puts. BES1# and BES2 are used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Fig- ure 3, for further details. SRAM Write The SRAM Write operation of the SST32HFx2/x2C is con- trolled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the SRAM. During the Word-Write operation, the addresses and data are ref- erenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. Product Identification The Product Identification mode identifies the devices as the SST32HFx2/x2C and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typi- cally used by programmers, cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, applica- tion of high voltage to pin A 9 may damage this device. Users may use the software Product Identification opera- tion to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 5 and 6 for software operation, Figure 14 for the software ID entry and read timing diagram and Figure 23 for the ID entry command sequence flowchart. TABLE 2: B OOT BLOCK ADDRESS RANGES Product Address Range Top Boot Block SST32HF16x2x 0F8000H-0FFFFFH SST32HF32x2x 1F8000H-1FFFFFH T2.1 1253 TABLE 3: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST32HF16x2x 0001H 234AH SST32HF32x2x 0001H 235AH T3.2 1253

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. This command may also be used to reset the device to Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 6 for software command codes, Figure 15 for timing waveform and Figure 23 for a flowchart. Security ID The SST32HFx2/x2C devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit seg- ments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to pro- gram as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three- byte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details. Design Considerations SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between V DD and VSS, e.g., less than 1 cm away from the V DD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from V DD to VSS should be placed within 1 cm of the VDD pin. I/O Buffers 1253 B1.1 Address Buffers DQ15 - DQ8AMS-A0 WE1# SuperFlash Memory SRAM/ PSRAM Control Logic BES1# BES2 BEF# OE1# RESET# WP# Address Buffers & Latches LBS# UBS# DQ7 - DQ0 Notes: 1. For LS package only: WE# = WEF# and/or WES# OE# = OEF# and/or OES# FUNCTIONAL BLOCK DIAGRAM

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 TABLE 4: P IN DESCRIPTION Symbol Pin Name Functions AMS1 to A0 Address Inputs To provide flash address, A MS-A0. To provide SRAM address, AMS-A0 DQ15-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low BES1# SRAM Memory Bank Enable To activate t he SRAM memory bank when BES1# is low BES2 SRAM Memory Bank Enable To activate t he SRAM memory bank when BES2 is high OEF#2 Output Enable To gate the data output buffers for Flash 2 only OES#2 Output Enable To gate the data output buffers for SRAM 2 only WEF#2 Write Enable To control the Write operations for Flash 2 only WES#2 Write Enable To control the Write operations for SRAM 2 only OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations UBS# Upper Byte Control (SRAM) To enable DQ 15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ 7-DQ0 WP# Write Protect To protect and unprotect se ctors from Erase or Program operation RST# Reset To Reset and return the device to Read mode VSSF2 Ground Flash 2 only VSSS2 Ground SRAM 2 only VSS Ground VDDF Power Supply (Flash) 2.7-3.3 V Power Supply to Flash only VDDS Power Supply (SRAM) 2.7-3.3V Power Supply to SRAM only NC No Connection Unconnected pins T4.2 1253 1. A MS = Most Significant Address AMS = A19 for SST32HF16x2x and A20 for SST32HF32x2x 2. LS package only

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 TABLE 5: O PERATIONAL MODES SELECTION1 Mode BEF# BES1# BES2 2 OE#3 WE#3 LBS# UBS# DQ 0-7 DQ8-15 Full Standby V IH VIH XX X X X H I G H - Z H I G H - Z XV IL XXXX Output Disable V IH VIL VIH VIH VIH XX H I G H - Z H I G H - Z VIL VIH XX V IH VIH VIL VIH XV IH VIH XX H I G H - Z H I G H - Z XV IL Flash Read V IL VIH XV IL VIH XX D OUT DOUT XV IL Flash Write V IL VIH X V IH VIL XX D IN DIN XV IL Flash Erase V IL VIH XV IH VIL XX X X XV IL SRAM Read V IH V IL VIH VIL VIH VIL V IL DOUT DOUT VIH VIL HIGH-Z D OUT VIL VIH DOUT HIGH-Z SRAM Write V IH VIL VIH XV IL VIL VIL DIN DIN VIH VIL HIGH-Z D IN VIL VIH DIN HIGH-Z Product Identification4 VIL VIH X V IL VIH X X Manufacturer’s ID 5 Device ID5 XV IL T5.2 1253 1. X can be V IL or VIH, but no other value. 2. Do not apply BEF# = V IL, BES1# = VIL and BES2 = VIH at the same time 3. OE# = OEF# and OES# WE# = WEF# and WES# for LS package only 4. Software mode only 5. With A MS-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0=0, SST32HF16x2x Device ID = 234AH, is read with A0=1, SST32HF32x2x Device ID = 235AH, is read with A0=1.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 TABLE 6: S OFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA 3 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA X4 30H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA X4 50H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H Query Sec ID5 5555H AAH 2AAAH 55H 5555H 88H User Security ID Word-Program 5555H AAH 2AAAH 55H 5555H A5H WA 6 Data User Security ID Program Lock-Out 5555H AAH 2AAAH 55H 5555H 85H XXH 6 0000H Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 9,10 /Sec ID Exit 5555H AAH 2AAAH 55H 5555H F0H Software ID Exit9,10 /Sec ID Exit XXH F0H T6.2 1253 1. Address format A 14-A0 (Hex). Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST32HF16x2x, Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST32HF32x2x. 2. DQ 15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SA X for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A19 for SST32HF16x2x and A20 for SST32HF32x2x. 5. With A MS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000010H to 000017H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With A MS-A1 =0; SST Manufacturer ID = 00BFH, is read with A 0 = 0, SST32HF16x2x Device ID = 234AH, is read with A0 = 1, SST32HF32x2x Device ID = 235AH, is read with A0 = 1, AMS = Most significant address AMS = A19 for SST32HF16x2x and A20 for SST32HF32x2x. 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 Absolute Maximum Stress Ratings (Applied conditions greater than t hose listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) 1. V DD = VDDF and VDDS 2. Excluding certain with-Pb 32-PLCC units, all packages are 260 °C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information. 3. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp V DD Commercial 0°C to +70°C 2.7-3.3V Extended -20°C to +85°C 2.7-3.3V AC CONDITIONS OF TEST L = 30 pF See Figures 19 and 20

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 TABLE 7: DC O PERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V) Symbol Parameter Limits Test ConditionsMin Max Units IDD Active VDD Current Address input = V ILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open Read OE#=V IL, WE#=VIH Flash 18 mA BEF#=V IL, BES1#=VIH, or BES2=VIL SRAM 30 mA BEF#=V IH, BES1#=VIL , BES2=VIH Concurrent Operation 40 mA BEF#=V IH, BES1#=VIL , BES2=VIH Write1 WE#=VIL Flash 35 mA BEF#=V IL, BES1#=VIH, or BES2=VIL, OE#=VIH SRAM 30 mA BEF#=V IH, BES1#=VIL , BES2=VIH ISB Standby VDD Current SST32HFx2 SST32HFx2C 110 µA µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC IRT Reset VDD Current 30 µA Reset=V SS±0.3V ILI Input Leakage Current 1 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V V DD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V V DD=VDD Max VIH Input High Voltage 0.7 VDD VV DD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V V DD=VDD Max VOLF Flash Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min VOHF Flash Output High Voltage VDD-0.2 V I OH=-100 µA, VDD=VDD Min VOLS SRAM Output Low Voltage 0.4 V IOL =1 mA, V DD=VDD Min VOHS SRAM Output High Voltage 2.2 V IOH =-500 µA, V DD=VDD Min T7.1 1253 1. I DD active while Erase or Program is in progress. TABLE 8: R ECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units T PU-READ1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. Power-up to Read Operation 100 µs TPU-WRITE1 Power-up to Program/Erase Operation 100 µs T8.0 1253 TABLE 9: C APACITANCE (TA = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. I/O Pin Capacitance V I/O = 0V 12 pF CIN1 Input Capacitance V IN = 0V 12 pF T9.0 1253 TABLE 10: F LASH RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Spec ification Units Test Method NEND1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 + I DD mA JEDEC Standard 78 T10.0 1253

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 AC CHARACTERISTICS TABLE 11: SRAM R EAD CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TRCS Read Cycle Time 70 ns TAAS Address Access Time 70 ns TBES Bank Enable Access Time 70 ns TOES Output Enable Access Time 35 ns TBYES UBS#, LBS# Access Time 70 ns TBLZS1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. BES# to Active Output 0 ns TOLZS1 Output Enable to Active Output 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 ns TBHZS1 BES# to High-Z Output 25 ns TOHZS1 Output Disable to High-Z Output 0 25 ns TBYHZS1 UBS#, LBS# to High-Z Output 35 ns TOHS Output Hold from Address Change 10 ns T11.1 1253 TABLE 12: SRAM W RITE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TWCS Write Cycle Time 70 ns TBWS Bank Enable to End-of-Write 60 ns TAWS Address Valid to End-of-Write 60 ns TASTS Address Set-up Time 0 ns TWPS Write Pulse Width 60 ns TWRS Write Recovery Time 0 ns TBYWS UBS#, LBS# to End-of-Write 60 ns TODWS Output Disable from WE# Low 30 ns TOEWS Output Enable from WE# High 0 ns TDSS Data Set-up Time 30 ns TDHS Data Hold from Write Time 0 ns T12.1 1253

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 TABLE 13: F LASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V Symbol Parameter Min Max Units TRC Read Cycle Time 70 ns TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns TCLZ1 BEF# Low to Active Output 0 ns TOLZ1 OE# Low to Active Output 0 ns TCHZ1 BEF# High to High-Z Output 20 ns TOHZ1 OE# High to High-Z Output 20 ns TOH1 Output Hold from Address Change 0 ns TRP1 RST# Pulse Width 500 ns TRHR1 RST# High before Read 50 ns TRY1,2 RST# Pin Low to Read Mode 20 µs T13.1 1253 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations. TABLE 14: F LASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Word-Program Time 10 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and BEF# Setup Time 0 ns TCH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 1. This parameter is measured only for init ial qualification and after a design or process change that could affect this parameter. WE# Pulse Width High 30 ns TCPH1 BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T14.0 1253

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 3: SRAM R EAD CYCLE TIMING DIAGRAM ADDRESSES AMSS-0 DQ15-0 UBS#, LBS# OE# BES1# BES2 TRCS TAAS TBES TOES TBLZS TOLZS TBYES TBYLZS TBYHZS DATA VALID TOHZS TBHZS TOHS 1253 F03.0 TBES Note: AMSS = Most Significant SRAM Address AMSS = A16 for SST32HF1622C, A17 for SST32HFxx42x, and A18 for SST32HFxx82

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 4: SRAM W RITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 TAWS ADDRESSES AMSS3-0 BES1# BES2 WE# UBS#, LBS# TWPS TWRS TWCS TASTS TBWS TBWS TBYWS TODWS TOEWS TDSS TDHS 1253 F04.0 NOTE 2NOTE 2DQ15-8, DQ7-0 VALID DATA IN Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES1# goes Low or BES2 goes high coincident with or a fter WE# goes Low, the output will remain at high impedance. If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A16 for SST32HF1622C, A17 for SST32HFxx42x, and A18 for SST32HFxx82

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 5: SRAM W RITE CYCLE TIMING DIAGRAM (UBS#, LBS# C ONTROLLED)1 ADDRESSES AMSS3-0 WE# BES1# BES2 TBWS TBWS TAWS TWCS TWPS TWRS TASTS TBYWS DQ15-8, DQ7-0 VALID DATA INNOTE 2 NOTE 2 TDSS TDHS UBS#, LBS# 1253 F05.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A16 for SST32HF1622C, A17 for SST32HFxx42x, and A18 for SST32HFxx82

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 12: WE# C ONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM Note: AMSF = Most Significant Flash Address AMSF = A19 for SST32HF16x2x and A20 for SST32HF32x2x This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14.) BAX = Block Address WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence X can be VIL or VIH, but no other value. 1253 F13.0 ADDRESS AMS-0 DQ15-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 XX55 XX50XX55XXAA XX80 XXAA BAX OE# BEF# SIX-BYTE CODE FOR BLOCK-ERASE TBE TWP

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 13: WE# C ONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM 1253 F12.0 ADDRESS AMS-0 DQ15-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 XX55 XX30XX55XXAA XX80 XXAA SAX OE# BEF# SIX-BYTE CODE FOR SECTOR-ERASE TSE TWP Note: AMSF = Most Significant Flash Address AMSF = A19 for SST32HF16x2x and A20 for SST32HF32x2x This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14.) SA X = Sector Address WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence X can be VIL or VIH, but no other value.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 16: F LASH SEC ID ENTRY 1253 F26.0 ADDRESS AMSF-0 TIDA DQ15-0 WE# SW0 SW1 SW2 5555 2AAA 5555 OE# BEF# THREE-BYTE SEQUENCE FOR SEC ID ENTRY TWP TWPH TAA XX55XXAA XX88 Note: AMSF = Most Significant Flash Address AMSF = A19 for SST32HF16x2x and A20 for SST32HF32x2x WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 21: WORD-PROGRAM ALGORITHM 1253 F18.0 Start Write data: XXAAH Address: 5555H Write data: XX55H Address: 2AAAH Write data: XXA0H Address: 5555H Write Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed Note: X can be VIL or VIH, but no other value

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 22: W AIT OPTIONS 1253 F19.0 Wait TBP, TSCE, or TBE Program/Erase Initiated Internal Timer Toggle Bit Ye s Ye s No No Program/Erase Completed Does DQ6 match? Read same word Data# Polling Program/Erase Completed Program/Erase Completed Read word Is DQ7 = true data? Read DQ7 Program/Erase Initiated Program/Erase Initiated

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 23: S EC ID/SOFTWARE ID COMMAND FLOWCHARTS X can be VIL or VIH, but no other value 1253 F20.0 Load data: XXAAH Address: 5555H Software Product ID Entry Command Sequence Load data: XX55H Address: 2AAAH Load data: XX90H Address: 5555H Wait TIDA Read Software ID Load data: XXAAH Address: 5555H Sec ID Query Entry Command Sequence Load data: XX55H Address: 2AAAH Load data: XX88H Address: 5555H Wait TIDA Read Sec ID

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 24: S OFTWARE ID/SEC ID COMMAND FLOWCHARTS 1253 F25.0 Load data: XXAAH Address: 5555H Software ID Exit/Sec ID Exit Command Sequence Load data: XX55H Address: 2AAAH Load data: XXF0H Address: 5555H Load data: XXF0H Address: XXH Return to normal operation Wait TIDA Wait TIDA Return to normal operation X can be VIL or VIH, but no other value

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 25: E RASE COMMAND SEQUENCE 1253 F21.0 Load data: XXAAH Address: 5555H Chip-Erase Command Sequence Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XXAAH Address: 5555H Wait TSCE Chip erased to FFFFH Load data: XXAAH Address: 5555H Sector-Erase Command Sequence Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX30H Address: SAX Load data: XXAAH Address: 5555H Wait TSE Sector erased to FFFFH Load data: XXAAH Address: 5555H Block-Erase Command Sequence Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX50H Address: BAX Load data: XXAAH Address: 5555H Wait TBE Block erased to FFFFH Note: X can be VIL or VIH, but no other value.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 FIGURE 26: C ONCURRENT OPERATION FLOWCHART 1253 F22.0 Load SDP Command Sequence Concurrent Operation Flash Program/Erase Initiated Wait for End of Write Indication Flash Operation Completed End Concurrent Operation Read or Write SRAM End Wait

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST32HFxxxxC - XXX -X X -X XX X Environmental Attribute E1 = non-Pb Package Modifier FS = 63 ball positions S = 62 ball positions Package Type L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Device Blank = PseudoSRAM C = Standard SRAM Hardware Block Protection 2 = Top Boot Block SRAM Density 2 = 2 Mbit 4 = 4 Mbit 8 = 8 Mbit Flash Density 16 = 16 Mbit 32 = 32 Mbit Voltage H = 2.7-3.3V Product Series 32 = MPF+ + SRAM ComboMemory 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 Valid combinations for SST32HF1622C SST32HF1622C-70-4C-LS SST32HF1622C-70-4C-LFS SST32HF1622C-70-4C-LSE SST32HF1622C-70-4C-LFSE SST32HF1622C-70-4E-LS SST32HF1622C-70-4E-LFS SST32HF1622C-70-4E-LSE SST32HF1622C-70-4E-LFSE Valid combinations for SST32HF1642 SST32HF1642-70-4C-LS SST32HF1642-70-4C-LFS SST32HF1642-70-4C-LSE SST32HF1642-70-4C-LFSE SST32HF1642-70-4E-LS SST32HF1642-70-4E-LFS SST32HF1642-70-4E-LSE SST32HF1642-70-4E-LFSE Valid combinations for SST32HF1642C SST32HF1642C-70-4C-LS SST32HF1642C-70-4C-LFS SST32HF1642C-70-4C-LSE SST32HF1642C-70-4C-LFSE SST32HF1642C-70-4E-LS SST32HF1642C-70-4E-LFS SST32HF1642C-70-4E-LSE SST32HF1642C-70-4E-LFSE Valid combinations for SST32HF1682 SST32HF1682-70-4C-LS SST32HF1682-70-4C-LFS SST32HF1682-70-4C-LSE SST32HF1682-70-4C-LFSE SST32HF1682-70-4E-LS SST32HF1682-70-4E-LFS SST32HF1682-70-4E-LSE SST32HF1682-70-4E-LFSE Valid combinations for SST32HF3242 SST32HF3242-70-4C-LS SST32HF3242-70-4C-LFS SST32HF3242-70-4C-LSE SST32HF3242-70-4C-LFSE SST32HF3242-70-4E-LS SST32HF3242-70-4E-LFS SST32HF3242-70-4E-LSE SST32HF3242-70-4E-LFSE Valid combinations for SST32HF3242C SST32HF3242C-70-4C-LS SST32HF3242C-70-4C-LFS SST32HF3242C-70-4C-LSE SST32HF3242C-70-4C-LFSE SST32HF3242C-70-4E-LS SST32HF3242C-70-4E-LFS SST32HF3242C-70-4E-LSE SST32HF3242C-70-4E-LFSE Valid combinations for SST32HF3282 SST32HF3282-70-4C-LS SST32HF3282-70-4C-LFS SST32HF3282-70-4C-LSE SST32HF3282-70-4C-LFSE SST32HF3282-70-4E-LS SST32HF3282-70-4E-LFS SST32HF3282-70-4E-LSE SST32HF3282-70-4E-LFSE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 PACKAGING DIAGRAMS 62-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM SST PACKAGE CODE: LS 63-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM SST PACKAGE CODE: LFS A1 CORNER K J H G F E D C B AA B C D E F G H J K BOTTOM VIEWTOP VIEW 8.00 ± 0.20 0.40 ± 0.0 (62X) A1 CORNER 10.00 ± 0.20 0.80 5.60 0.80 7.20 62-lfbga-LS-8x10-400mic-4 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered . 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.32 mm (± 0.05 mm) 1mm SIDE VIEW SEATING PLANE 0.32 ± 0.05 1.30 ± 0.10 0.12 A1 CORNER K J H G F E D C B AA B C D E F G H J K BOTTOM VIEWTOP VIEW 8.0 ± 0.1 0.40 ± 0.0 (63X) A1 CORNER 10.0 ± 0.1 0.80 5.60 0.80 7.20 63-lfbga-LFS-8x10-400mic-1 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered . 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size: 0.32 mm (± 0.05 mm) 1mm SIDE VIEW SEATING PLANE 0.32 ± 0.05 1.3 ± 0.1 0.12

Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 TABLE 15: R EVISION HISTORY Number Description Date 00  Initial Release Feb 2004 01  Added SST32HF1622C device and associated MPNs  Removed SST32HF3282C and SST32HF6482C devices and associated MPNs Jun 2004 02  Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz See Table 7 on page 12  Added Table 2 on page 5 for the Boot Block address ranges  Updated L2S package outline drawing and pin assignments  Added RoHS compliance information on page 1 and in the “Product Ordering Information” on page 33  Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on page 11.  Removed all 90 ns information and associated MPNs beginning on page 34  Added all non-Pb MPNs beginning on page 34 Mar 2005 03  Removed SST32HF6482 commercial temperature devices and MPNs  Moved SST32HF6482 extended temperature MPNs to S71299 data sheet May 2005 Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  Telephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.sst.com