SST32HF162

SST32HF802 SST | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 28

Technical content

©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. MPF and ComboMemory are trademarks of Silicon Storage T echnology, Inc. These specifications are subject to change without notice. Data Sheet FEATURES:

• MPF + SRAM ComboMemory – SST32HF802: 512K x16 Flash + 128K x16 SRAM – SST32HF162: 1M x16 Flash + 128K x16 SRAM – SST32HF164: 1M x16 Flash + 256K x16 SRAM  Single 2.7-3.3V Read and Write Operations  Concurrent Operation – Read from or write to SRAM while Erase/Program Flash  Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention  Low Power Consumption: – Active Current: 15 mA (typical) for Flash or SRAM Read – Standby Current: 20 µA (typical)  Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks  Fast Read Access Times: – Flash: 70 ns and 90 ns – SRAM: 70 ns and 90 ns  Latched Address and Data for Flash  Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 µs (typical) – Chip Rewrite Time: SST32HF802: 8 seconds (typical) SST32HF162/164: 15 seconds (typical)  Flash Automatic Erase and Program Timing – Internal V PP Generation  Flash End-of-Write Detection – Toggle Bit – Data# Polling  CMOS I/O Compatibility  JEDEC Standard Command Set  Package Available – 48-lead TSOP (12mm x 20mm) – 48-ball TBGA (10mm x 12mm) PRODUCT DESCRIPTION The SST32HF802/162/164 ComboMemory devices inte- grate a 512K x16 or 1M x16 CMOS flash memory bank with a 128K x16 or 256K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 14 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 8 seconds for the SST32HF802 and 15 seconds for the SST32HF162/164, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST32HF802/ 162/164 devices contain on-chip hardware and software data protection schemes.The SST32HF802/162/164 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HF802/162/164 devices consist of two inde- pendent memory banks with respective bank enable sig- nals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable sig- nal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protec- tion (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HF802/162/164 provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automati- cally latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled erase or pro- gram cycle in the flash bank has commenced, the SRAM bank can be accessed for read or write. The SST32HF802/162/164 devices are suited for applica- tions that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF802/162/164 devices signif- icantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST32HF802/162/164 inherently use less energy during erase and program than alternative flash Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 SST32HF802 / 162 / 164MPF (x16) + 1Mb SRAM (x16) ComboMemories

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initi- ated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initi- ated, will be completed, within 20 µs. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program opera- tion, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector/Block-Erase Operation The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST32HF802/162/164 offer both Sector- Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A 19-A11, for SST32HF162/164, and A 18-A11, for SST32HF802, are used to determine the sector address. The Block-Erase operation is initiated by executing a six- byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines A 19-A15, for SST32HF162/164, and A18-A15, for SST32HF802, are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 12 and 13 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Flash Chip-Erase Operation The SST32HF802/162/164 provide a Chip-Erase opera- tion, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 21 for the flowchart. Any commands issued dur- ing the Chip-Erase operation are ignored. Write Operation Status Detection The SST32HF802/162/164 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time. The soft- ware detection includes two status bits: Data# Polling (DQ 7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which ini- tiates the internal program or erase operation. The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either DQ 7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. Flash Data# Polling (DQ7) When the SST32HF802/162/164 flash memory banks are in the internal Program operation, any attempt to read DQ will produce the complement of the true data. Once the Program operation is completed, DQ 7 will produce true data. Note that even though DQ 7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles. During internal Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once the inter- nal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 19 for a flowchart. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 Sector- or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 19 for a flowchart. Flash Memory Data Protection The SST32HF802/162/164 flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. Flash Software Data Protection (SDP) The SST32HF802/162/164 provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF802/162/164 devices are shipped with the soft- ware data protection permanently enabled. See Table 4 for the specific software command codes. During SDP com- mand sequence, invalid SDP commands will abort the device to the read mode, within Read Cycle Time (T RC). Concurrent Read and Write Operations The SST32HF802/162/164 provide the unique benefit of being able to read from or write to SRAM, while simulta- neously erasing or programming the Flash. This allows data alteration code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states. The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these com- mands will also be ignored while an Erase or Program operation is in progress. Product Identification The product identification mode identifies the devices as the SST32HFxxx and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A 9 may damage this device. Users may use the software product identification operation to identify the part (i.e., using the device ID) when using multi- ple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 14 for the software ID entry and read timing diagram and Figure 20 for the ID entry command sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software-reset command is ignored during an internal Program or Erase operation. See Table 4 for soft- ware command codes, Figure 15 for timing waveform and Figure 20 for a flowchart. Design Considerations SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between V DD and VSS, e.g., less than 1 cm away from the V DD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from V DD to VSS should be placed within 1 cm of the VDD pin. C ONCURRENT READ /W RITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write TABLE 1: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H 00BFH Device ID SST32HF802 0001H 2781H SST32HF162/164 0001H 2782H T1.1 520

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 1: P IN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM ) I/O Buffers 520 ILL B1.1 Address Buffers DQ15 - DQ8AMS(1)-A0 WE# SuperFlash Memory SRAM Control LogicBES# BEF# OE# Address Buffers & Latches LBS# UBS# DQ7 - DQ0 FUNCTIONAL BLOCK DIAGRAM A15 A14 A13 A12 A11 A10 A19 NC WE# VDDS BES# UBS# LBS# A18 A17 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDDF DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS BEF# 520 ILL F01b.1 Standard Pinout Top View Die Up SST32HF162/164SST32HF162/164

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 2: P IN ASSIGNMENTS FOR 48-BALL TBGA (10MM X 12MM ) TABLE 2: P IN DESCRIPTION Symbol Pin Name Functions AMS1-A0 1. A MS=Most significant address Address Inputs To provide flash addresses: A 19-A0 for 16M, and A18-A0 for 8M SRAM addresses: A16-A0 for 2M and A17-A0 for 4M DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V DDF Power Supply (Flash) 2.7-3.3V Power Supply to Flash only. VDDS Power Supply (SRAM) 2.7-3.3V Power Supply to SRAM only (For L3K package, VDDF and VDDS share one pin as VDD.) VSS Ground UBS# Upper Byte Control (SRAM) To enable DQ 15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0 NC No Connection Unconnected Pins T2.2 520 BES# A10 OE# A11 A13 WE# VSS DQ5 DQ7 A17 VDDS DQ1 DQ2 DQ4 UBS# A16 DQ0 DQ8 BEF# VSS DQ3 DQ10 DQ9 A18 DQ12 VDDF DQ11 NC NC NC A12 DQ6 DQ13 A14 A15 LBS# DQ15 DQ14 A B C D E F G H SST32HF802 TOP VIEW (balls facing down) 520 ILL F01a.0 BES# A10 OE# A11 A13 WE# VSS DQ5 DQ7 A17 VDDS DQ1 DQ2 DQ4 UBS# A16 DQ0 DQ8 BEF# VSS DQ3 DQ10 DQ9 A18 DQ12 VDDF DQ11 A19 NC NC A12 DQ6 DQ13 A14 A15 LBS# DQ15 DQ14 A B C D E F G H SST32HF162/SST32HF164 TOP VIEW (balls facing down) 520 ILL F01.0

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 TABLE 3: O PERATION MODES SELECTION Mode BES# 1 BEF# 1 OE# WE# UBS# LBS# DQ 15 to DQ8 DQ 7 to DQ0 Address Not Allowed V IL VIL X2 XX X X X X Flash Read V IH VIL VIL VIH XX D OUT DOUT AIN Program V IH VIL VIH VIL XX D IN DIN AIN Erase X V IL VIH VIL X X X X Sector or Block address, XXH for Chip-Erase SRAM Read V IL VIH VIL VIH VIL VIL DOUT DOUT AIN VIL VIH VIL VIH VIL VIH DOUT High Z A IN VIL VIH VIL VIH VIH VIL High Z D OUT AIN Write V IL VIH XV IL VIL VIL DIN DIN AIN VIL VIH XV IL VIL VIH DIN High Z A IN VIL VIH XV IL VIH VIL High Z D IN AIN Standby V IHC VIHC X X X X High Z High Z X Flash Write Inhibit X X V IL XX X H i g h Z / D OUT High Z / DOUT X XX X V IH XX H i g h Z / D OUT High Z / DOUT X XV IH XX X X H i g h Z / D OUT High Z / DOUT X Output Disable V IH VIL VIH VIH X X High Z High Z X VIL VIH XXV IH VIH High Z High Z X VIL VIH VIH VIH X X High Z High Z X Product Identification Software Mode V IH VIL VIL VIH X X Manufacturer’s ID (00BFH) Device ID3 A19-A1=VIL, A0=VIH (See Table 4) T3.2 520 1. Do not apply BES#=V IL and BEF#=VIL at the same time 2. X can be V IL or VIH, but no other value. 3. Device ID 2781H for SST32HF802, 2782H for SST32HF162/164

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 TABLE 4: S OFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA 3 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA X4 30H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA X4 50H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry 5,6 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit XXH F0H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H T4.2 520 1. Address format A 14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence. 2. DQ 15-DQ8 can be VIL or VIH, but no other value, for the Command sequence. 3. WA = Program word address 4. SA X for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses A19-A15 address lines AMS = Most significant address AMS = A18 for SST32HF802 and A19 for SST32HF162/164 5. The device does not remain in Software Product ID Mode if powered down. 6. With A MS-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A 0=0, SST32HF802 Device ID = 2781H, is read with A 0=1. SST32HF162/164 Device ID = 2782H, is read with A 0=1. Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) DD1+0.3V 1. V DD = VDDF and VDDS 2. Outputs shorted for no more than one second. No more than one output shorted at a time. O PERATING RANGE Range Ambient Temp V DD Commercial 0°C to +70°C 2.7-3.3V Extended -20°C to +85°C 2.7-3.3V AC C ONDITIONS OF TEST See Figures 16 and 17

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 TABLE 5: DC O PERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V) Symbol Parameter Limits Test ConditionsMin Max Units IDD Power Supply Current Address input = V IL/VIH, at f=1/TRC Min, VDD=VDD Max, all DQs open Read Flash 20 mA OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH SRAM 20 mA BEF#=V IH, BES#=VIL Concurrent Operation 45 mA BEF#=V IH, BES#=VIL Write Flash 25 mA WE#=VIL BEF#=VIL, BES#=VIH, OE#=VIH SRAM 20 mA BEF#=V IH, BES#=VIL ISB Standby VDD Current 3.0V 3.3V µA V DD = VDD Max, BEF#=BES#=VIHC ILI Input Leakage Current 1 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V V DD=VDD Min VIH Input High Voltage 0.7V DD VV DD=VDD Max VIHC Input High Voltage (CMOS) V DD-0.3 V V DD=VDD Max VOL Flash Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min VOH Flash Output High Voltage V DD-0.2 V I OH=-100 µA, VDD=VDD Min VOLS SRAM Output Low Voltage 0.4 V I OL=1 mA, VDD=VDD Min VOHS SRAM Output High Voltage 2.2 V I OH=-500 µA, VDD=VDD Min T5.5 520 TABLE 6: R ECOMMENDED SYSTEM POWER -UP TIMINGS Symbol Parameter Minimum Units T PU-READ1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. Power-up to Read Operation 100 µs TPU-WRITE1 Power-up to Program/Erase Operation 100 µs T6.0 520 TABLE 7: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. I/O Pin Capacitance V I/O = 0V 12 pF CIN1 Input Capacitance V IN = 0V 12 pF T7.0 520 TABLE 8: F LASH RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 + I DD mA JEDEC Standard 78 T8.1 520

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 AC CHARACTERISTICS TABLE 9: SRAM R EAD CYCLE TIMING PARAMETERS Symbol Parameter SST32HF802/162/164-70 SST32HF802/162/164-90 UnitsMin Max Min Max TRCS Read Cycle Time 70 90 ns TAAS Address Access Time 70 90 ns TBES Bank Enable Access Time 70 90 ns TOES Output Enable Access Time 35 45 ns TBYES UBS#, LBS# Access Time 70 90 ns TBLZS1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. BES# to Active Output 0 0 ns TOLZS1 Output Enable to Active Output 0 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 0 ns TBHZS1 BES# to High-Z Output 25 35 ns TOHZS1 Output Disable to High-Z Output 0 25 0 35 ns TBYHZS1 UBS#, LBS# to High-Z Output 35 45 ns TOHS Output Hold from Address Change 10 10 ns T9.1 520 TABLE 10: SRAM W RITE CYCLE TIMING PARAMETERS Symbol Parameter SST32HF802/162/164-70 SST32HF802/162/164-90 UnitsMin Max Min Max TWCS Write Cycle Time 70 90 ns TBWS Bank Enable to End-of-Write 60 80 ns TAWS Address Valid to End-of-Write 60 80 ns TASTS Address Set-up Time 0 0 ns TWPS Write Pulse Width 60 80 ns TWRS Write Recovery Time 0 0 ns TBYWS UBS#, LBS# to End-of-Write 60 80 ns TODWS Output Disable from WE# Low 30 40 ns TOEWS Output Enable from WE# High 0 0 ns TDSS Data Set-up Time 30 40 ns TDHS Data Hold from Write Time 0 0 ns T10.1 520

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 TABLE 11: FLASH READ CYCLE TIMING PARAMETERS Symbol Parameter SST32HF802/162/164-70 SST32HF802/162/164-90 UnitsMin Max Min Max TRC Read Cycle Time 70 90 ns TBE Bank Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TBLZ1 BEF# Low to Active Output 0 0 ns TOLZ1 OE# Low to Active Output 0 0 ns TBHZ1 BEF# High to High-Z Output 20 30 ns TOHZ1 OE# High to High-Z Output 20 30 ns TOH1 Output Hold from Address Change 0 0 ns T11.1 520 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. TABLE 12: FLASH PROGRAM /ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Word-Program Time 20 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TBS WE# and BEF# Setup Time 0 ns TBH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TBPW BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH WE# Pulse Width High 30 ns TBPH BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH Data Hold Time 0 ns TIDA Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 100 ms T12.0 520

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 5: SRAM W RITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED )1 ADDRESSES AMSS-0 WE# BES# TBWS TAWS TWCS TWPS TWRS TASTS TBYWS DQ15-8, DQ7-0 VALID DATA INNOTE 2 NOTE 2 TDSS TDHS UBS#, LBS# Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 520 ILL F29.0

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 18: W ORD -PROGRAM ALGORITHM 520 ILL F13.3 Start Write data: XXAAH Address: 5555H Write data: XX55H Address: 2AAAH Write data: XXA0H Address: 5555H Write Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed Note: X can be VIL or VIH, but no other value

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 19: W AIT OPTIONS 520 ILL F14.0 Wait TBP, TSCE, or TBE Program/Erase Initiated Internal Timer Toggle Bit Ye s Ye s No No Program/Erase Completed Does DQ6 match? Read same word Data# Polling Program/Erase Completed Program/Erase Completed Read word Is DQ7 = true data? Read DQ7 Program/Erase Initiated Program/Erase Initiated

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 20: SOFTWARE PRODUCT COMMAND FLOWCHARTS 520 ILL F15.2 Write data: XXAAH Address: 5555H Software Product ID Entry Command Sequence Write data: XX55H Address: 2AAAH Write data: XX90H Address: 5555H Wait TIDA Read Software ID Write data: XXAAH Address: 5555H Software Product ID Exit & Reset Command Sequence Write data: XX55H Address: 2AAAH Write data: XXF0H Address: 5555H Write data: XXF0H Address: XXXXH Return to normal operation Wait TIDA Wait TIDA Return to normal operation Note: X can be VIL or VIH, but no other value.

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 21: ERASE COMMAND SEQUENCE 520 ILL F26.2 Load data: XXAAH Address: 5555H Chip-Erase Command Sequence Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XXAAH Address: 5555H Wait TSCE Chip erased to FFFFH Load data: XXAAH Address: 5555H Sector-Erase Command Sequence Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX30H Address: SAX Load data: XXAAH Address: 5555H Wait TSE Sector erased to FFFFH Load data: XXAAH Address: 5555H Block-Erase Command Sequence Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX50H Address: BAX Load data: XXAAH Address: 5555H Wait TBE Block erased to FFFFH Note: X can be VIL or VIH, but no other value.

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 FIGURE 22: CONCURRENT OPERATION FLOWCHART 520 ILL F19.0 Load SDP Command Sequence Concurrent Operation Flash Program/Erase Initiated Wait for End of Write Indication Flash Operation Completed End Concurrent Operation Read or Write SRAM End Wait

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 PRODUCT ORDERING INFORMATION Valid combinations for SST32HF802 SST32HF802-70-4C-EK SST32HF802-70-4C-TBK SST32HF802-70-4E-EK SST32HF802-70-4E-TBK Valid combinations for SST32HF162 SST32HF162-70-4C-EK SST32HF162-70-4C-TBK SST32HF162-70-4E-EK SST32HF162-70-4E-TBK Valid combinations for SST32HF164 SST32HF164-70-4C-EK SST32HF164-70-4C-TBK SST32HF164-90-4C-EK SST32HF164-90-4C-TBK SST32HF164-70-4E-EK SST32HF164-70-4E-TBK SST32HF164-90-4E-EK SST32HF164-90-4E-TBK Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Device Speed Suffix1 Suffix2 SST32HFxxx -X X X -X X -X X Package Modifier K = 48 leads or balls Package Type E = TSOP (12mm x 20mm) TB = TBGA (10mm x 12mm x 1.2mm) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Density 802 = 8 Mbit Flash + 2 Mbit SRAM 162 = 16 Mbit Flash + 2 Mbit SRAM 164 = 16 Mbit Flash + 4 Mbit SRAM Function Voltage H = 2.7-3.3V Device Family 32 = MPF + SRAM ComboMemory

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 PACKAGING DIAGRAMS 48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE : EK 48-TSOP-EK-ILL.6 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. Pin # 1 Identifier 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 .270 .170 .50 BSC 1.05 0.95 0.15 0.05 Scale is 1:5 mm.

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 48-BALL THIN-PROFILE BALL GRID ARRAY (TBGA) 10MM X 12MM SST PACKAGE CODE : TBK A1 CORNER H G F E D C B AA B C D E F G H BOTTOM VIEW TOP VIEW SIDE VIEW SEATING PLANE 0.40 ± 0.05 1.10 ± 0.10 0.15 10.00 ± 0.20 0.50 ± 0.05 (48X) A1 CORNER 12.00 ± 0.20 1.0 5.0 1.0 7.0 48ba-TBGA-TBK-10x12-500mic-ILL.5 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 1mm

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  T elephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.ssti.com