SST31LF041 SST | Alldatasheet

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©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet FEATURES:

  • Monolithic Flash + SRAM ComboMemory – SST31LF041/041A: 512K x8 Flash + 128K x8 SRAM – SST31LF043/043A: 512K x8 Flash + 32K x8 SRAM  Single 3.0-3.6V Read and Write Operations  Concurrent Operation – Read from or write to SRAM while Erase/Program Flash  Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention  Low Power Consumption: – Active Current: 10 mA (typical) for Flash and 20 mA (typical) for SRAM Read – Standby Current: 10 µA (typical)  Flash Sector-Erase Capability – Uniform 4 KByte sectors  Latched Address and Data for Flash  Fast Read Access Times: – SST31LF041/043 Flash: 70 ns SRAM: 70 ns – SST31LF041A/043A Flash: 300 ns SRAM: 300 ns  Flash Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Bank-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Bank Rewrite Time: 8 seconds (typical)  Flash Automatic Erase and Program Timing – Internal VPP Generation  Flash End-of-Write Detection – Toggle Bit – Data# Polling  CMOS I/O Compatibility  JEDEC Standard Command Set  Packages Available – 32-lead TSOP (8 x 14 mm) SST31LF041A/043A – 40-lead TSOP (10 x 14 mm) SST31LF041/043 PRODUCT DESCRIPTION The SST31LF041/041A/043/043A devices are a 512K x8 CMOS flash memory bank combined with a 128K x8 or 32K x8 CMOS SRAM memory bank manufactured with SST ’s proprietary, high performance SuperFlash technol- ogy. The SST31LF041/041A/043/043A devices write (SRAM or flash) with a 3.0-3.6V power supply. The mono- lithic SST31LF041/041A/043/043A devices conform to Software Data Protect (SDP) commands for x8 EEPROMs. Featuring high performance Byte-Program, the flash mem- ory bank provides a maximum Byte-Program time of 20 µsec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 8 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LF041/041A/ 043/043A devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LF041/041A/043/043A devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST31LF041/041A/043/043A operate as two inde- pendent memory banks with respective bank enable sig- nals. The SRAM and Flash memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable sig- nal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protec- tion (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST31LF041/041A/043/043A provide the added func- tionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Byte-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Pro- gram cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST31LF041/041A/043/043A devices are suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all sys- tem applications, the SST31LF041/041A/043/043A

4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A SST31LF041 / 041A4Mb Flash (x8) + 1 Mb SRAM (x8) ComboMemories

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LF041/041A/043/043A inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program oper- ation is less than alternative flash technologies. The mono- lithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; there- fore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. The SST31LF041/041A/043/043A devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two sepa- rate devices. To meet high density, surface mount require- ments, the SST31LF041/043 device is offered in 40-lead TSOP package and the SST31LF041A/043A device is offered in 32-lead TSOP package. See Figures 1 and 2 for the pinouts. Device Operation The ComboMemory uses BES# and BEF# to control oper- ation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be exe- cuted in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared which minimizes power consumption and area. The device goes into standby when both bank enables are raised to V IHC. See Table 3 for SRAM operation mode selection. For SST31LF041A/043A only:BES# and OE# share pin 32. During SRAM operation, pin 32 will function as BES#. During flash operation, pin 32 will function as OE#. When pin 32 (OE#/BES#) is high, the data bus is in high impedance state. SRAM Operation With BES# low and BEF# high, the SST31LF041/041A operate as a 128K x8 CMOS SRAM and the SST31LF043/043A operate as 32K x8 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device for 041/041A or 32 KByte for 043/043A. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LF041/041A/ 043/043A are controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high imped- ance state when OE# is high. See Figure 3 for the Read cycle timing diagram. SRAM Write The SRAM Write operation of the SST31LF041/041A/043/ 043A is controlled by WE# and BES#; both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge to the first rising edge of BES# and WE#. OE# can be V IL or VIH, but no other value, for SRAM Write operations. See Figure 4 for the SRAM Write cycle timing diagram. Flash Operation With BEF# active, the SST31LF041/041A/043/043A oper- ate as a 512K x8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. See Table 3 for flash operation mode selection. Flash Read The Read operation of the SST31LF041/041A/043/043A devices are controlled by BEF# and OE#; both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are dese- lected and only standby power is consumed. OE# is the

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 5 for the Read cycle timing diagram. Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LF041/041A/ 043/043A. SDP commands are loaded to the flash mem- ory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the fall- ing edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Byte-Program Operation The flash memory bank of the SST31LF041/041A/043/ 043A devices are programmed on a byte-by-byte basis. Before the Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the ris- ing edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is ini- tiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initi- ated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program opera- tion, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector-Erase Operation The Sector-Erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KBytes. The Sector-Erase operation is initiated by executing a six- byte-command load sequence for Software Data Protec- tion with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A 18-A12 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Fig- ure 10 for timing waveforms. Any SDP commands loaded during the Sector-Erase operation will be ignored. Flash Bank-Erase Operation The SST31LF041/041A/043/043A flash memory bank pro- vides a Bank-Erase operation, which allows the user to erase the entire flash memory bank array to the “1s” state. This is useful when the entire bank must be quickly erased. The Bank-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Bank-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read operations are Toggle Bit and Data# Poll- ing. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 20 for the flowchart. Any SDP commands loaded during the Bank-Erase operation will be ignored. Flash Write Operation Status Detection The SST31LF041/041A/043/043A flash memory bank pro- vides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ 7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual comple- tion of the nonvolatile write is asynchronous with the sys- tem; therefore, either a Data# Polling or Toggle Bit Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an errone- ous result, i.e., valid data may appear to conflict with either DQ 7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Data# Polling (DQ7) When the SST31LF041/041A/043/043A flash memory bank is in the internal Program operation, any attempt to read DQ 7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will pro- duce true data. The flash memory bank is then ready for the next operation. During internal Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE#

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 (or BEF#) pulse for Program operation. For Sector or Bank- Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sec- tor or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 18 for a flowchart. Flash Memory Data Protection The SST31LF041/041A/043/043A flash memory bank pro- vides both hardware and software features to protect non- volatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. Flash Software Data Protection (SDP) The SST31LF041/041A/043/043A provide the JEDEC approved Software Data Protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, provid- ing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LF041/041A/043/043A devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP com- mands will abort the device to the Read mode, within T RC . Concurrent Read and Write Operations The SST31LF041/041A/043/043A provide the unique ben- efit of being able to read from or write to SRAM, while simultaneously erasing or programming the Flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alter- ation code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states. SST does not recommend that both bank enables, BEF# and BES#, be simultaneously asserted. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Product Identification The product identification mode identifies the devices as either SST31LF041/043 or SST31LF041A/043A and the manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware device ID Read operation is typically used by a programmer to iden- tify the correct algorithm for the SST31LF041/041A/043/ 043A flash memory banks. Users may wish to use the soft- ware product identification operation to identify the part (i.e., using the device ID) when using multiple manufactur- ers in the same socket. For details, see Table 3 for hard- ware operation or Table 4 for software operation, Figure 12 for the software ID entry and read timing diagram and Fig- ure 19 for the ID entry command sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, C ONCURRENT READ /W RITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write TABLE 1: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST31LF041 0001H 17H SST31LF041A 0001H 16H SST31LF043 0001H 65H SST31LF043A 0001H 66H T1.2 349

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 which returns the device to the Read operation. Please note that the software-reset command is ignored during an internal Program or Erase operation. See Table 4 for soft- ware command codes, Figure 13 for timing waveform and Figure 19 for a flowchart. Design Considerations SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between V DD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from V DD to VSS should be placed within 1 cm of the VDD pin. FIGURE 1: P IN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 14MM ) - SSTLF041/043 I/O Buffers 349 ILL B1.6 Address Buffers DQ 7 - DQ0OE# BEF# WE# SuperFlash Memory SRAM Control Logic BES# AMS - A0 AMS = Most Significant Address Address Buffers & Latches FUNCTIONAL BLOCK DIAGRAM A16 A15 A14 A13 A12 A11 WE# NC BES# NC A18 A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS BEF# 349 ILL F01.2 Standard Pinout Top View Die Up

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 2: P IN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM ) - SSTLF041A/043A TABLE 2: P IN DESCRIPTION Symbol Pin Name Functions AMS 1-A0 1. AMS = Most significant address Address Inputs To provide memory addresses. A 18-A0 to provide flash address A16-A0 to provide SRAM addresses for SST32LF041/041A A14-A0 to provide SRAM addresses for SST31LF043/043A During flash Sector-Erase, A18-A12 address lines will select the sector. DQ 7-DQ 0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. Note: For SST31LF041A/043A, BES# and OE# share pin 32. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. Note: For SST31LF041A/043A, BES# and OE# share pin 32. WE# Write Enable To control the Write operations. V DD Power Supply 3.0-3.6V Power Supply VSS Ground T2.11 349 A11 A13 A14 A17 WE# VDD A18 A16 A15 A12 OE#/BES# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 349 ILL F01A.1 Standard Pinout Top View Die Up

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 TABLE 3: O PERATION MODES SELECTION Mode BES# 1 BEF# 1 OE# WE# A 9 DQ Address Flash Read X 2 VIL VIL VIH AIN D OUT AIN Program X V IL VIH VIL AIN D IN AIN Erase X V IL VIH VIL X X Sector address, XXH for Bank-Erase SRAM Read V IL VIH VIL VIH AIN D OUT AIN Write V IL VIH XV IL AIN D IN AIN Standby V IHC VIHC XX X H i g h Z X Flash Write Inhibit X X V IL X X High Z / D OUT X XX X V IH XH i g h Z / DOUT X XV IH XX X H i g h Z / D OUT X Product Identification Hardware Mode X V IL VIL VIH VH Manufacturer’s ID (BFH) Device ID3 A18-A1=V IL, A0=VIL A18-A1=V IL, A0=VIH Software Mode X V IL VIL VIH AIN ID Code See Table 4 T3.9 349 1. BES# and BEF# cannot be asserted simultaneously. For SST31LF041A/043A BES# and OE# share pin 32. When flash is active, pin 32 becomes OE#. When flash is inactive, pin 32 becomes BES#. 2. X can be VIL or VIH, but no other value. 3. Device ID 17H for SST31LF041, 16H for SST31LF041A, 65H for SST31LF043 and 66H for SST31LF043A. TABLE 4: S OFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr1 1. Address format A14-A0 (Hex),Address A15-A18 can be VIL or VIH, but no other value, for the Command sequence. Data Addr 1 Data Addr 1 Data Addr 1 Data Addr 1 Data Addr 1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA 2 2. BA = Program Byte address Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA X3 3. SAX for Sector-Erase; uses A18-A12 address lines 30H Bank-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry 4,5 4. The device does not remain in Software Product ID Mode if powered down. 5. With A18-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0, SST31LF041 Device ID = 17H, is read with A0 = 1, SST31LF041A Device ID = 16H, is read with A0 = 1 SST31LF043 Device ID = 65H, is read with A0 = 1 SST31LF043A Device ID = 66H, is read with A0 = 1 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H T4.7 349

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) DD +0.5V 1. Outputs shorted for no more than one second. No more than one output shorted at a time. O PERATING RANGE Range Ambient Temp V DD Commercial 0 °C to +70°C 3.0-3.6V Extended -20 °C to +85°C 3.0-3.6V AC C ONDITIONS OF TEST See Figures 15 and 16

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 TABLE 5: DC O PERATING CHARACTERISTICS (VDD = 3.0-3.6V) Symbol Parameter Limits Test ConditionsMin Max Units IDD Power Supply Current Address input = V IL/VIH, at f=1/TRC Min, VDD =V DD Max, all DQs open Read Flash 12 mA OE#=V IL, WE#=VIH BEF#=V IL, BES#=VIH SRAM 40 mA BEF#=V IH, BES#=VIL Concurrent Operation 55 mA BEF#=V IH, BES#=VIL Write Flash (Program) 15 mA OE#=V IH, WE#=VIL BEF#=V IL, BES#=VIH SRAM 40 mA BEF#=V IH, BES#=VIL ISB 1 Standby VDD Current 30 µA BEF#=BES#=V IHC, VDD =V DD Max ILI Input Leakage Current 1 µA V IN=GND to VDD , VDD =VDD Max ILO Output Leakage Current 1 µA V OUT =GND to VDD , VDD =V DD Max VIL Input Low Voltage 0.4 V V DD = VDD Min VIH Input High Voltage 0.7V DD VV DD = VDD Max VIHC Input High Voltage (CMOS) V DD -0.3 V V DD = VDD Max VOL Output Low Voltage 0.2 V I OL = 100 µA, VDD = VDD Min VOH Output High Voltage V DD -0.2 V I OH = -100 µA, VDD = VDD Min VH Supervoltage for A9 pin 11.4 12.6 V BEF#=OE#=V IL, WE#=VIH IH Supervoltage Current for A9 pin 200 µA BEF#=OE#=V IL, WE#=VIH, A9=VH Max T5.14 349 1. Specification applies to commercial temperature devices only. This parameter may be higher for extended devices. TABLE 6: R ECOMMENDED SYSTEM POWER -UP TIMINGS Symbol Parameter Minimum Units T PU-READ 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Power-up to Read Operation 100 µs TPU-WRITE 1 Power-up to Write Operation 100 µs T6.2 349 TABLE 7: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum C I/O1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. I/O Pin Capacitance V I/O = 0V 12 pF C IN1 Input Capacitance V IN = 0V 6 pF T7.2 349 TABLE 8: R ELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N END 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Endurance 10,000 Cycles JEDEC Standard A117 TDR 1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 + I DD mA JEDEC Standard 78 T8.4 349

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 AC CHARACTERISTICS TABLE 9: SRAM M EMORY BANK CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF041/043-70 SST31LF041A/043A-300 UnitsMin Max Min Max TRCS Read Cycle Time 70 300 ns TBES Bank Enable Access Time 70 300 ns TAAS Address Access Time 70 300 ns TOES 1 1. No TOES value for SST31LF041A/043A Output Enable Access Time 35 150 ns TBLZS 2 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. BES# to Active Output 0 0 ns TOLZS 1 Output Enable to Active Output 0 0 ns TBHZS 1 BES# to High-Z Output 25 30 ns TOHZS 1 Output Disable to High-Z Output 25 30 ns TOHS Output Hold from Address Change 0 10 ns T9.8 349 TABLE 10: SRAM M EMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF041/043-70 SST31LF041A/043A-300 UnitMin Max Min Max TWCS Write Cycle Time 70 300 ns TBWS Bank Enable to End-of-Write 60 230 ns TAWS Address Valid to End-of-Write 60 230 ns TASTS Address Set-up Time 0 0 ns TWPS Write Pulse Width 60 200 ns TWRS Write Recovery Time 0 0 ns TDSS Data Set-up Time 30 150 ns TDHS Data Hold from Write Time 0 0 ns T10.5 349 TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF041/043-70 SST31LF041A/043A-300 UnitsMin Max Min Max TRC Read Cycle Time 70 300 ns TBE Bank Enable Access Time 70 300 ns TAA Address Access Time 70 300 ns TOE Output Enable Access Time 40 150 ns TBLZ 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. BEF# Low to Active Output 0 0 ns TOLZ 1 OE# Low to Active Output 0 0 ns TBHZ 1 BEF# High to High-Z Output 15 60 ns TOHZ 1 OE# High to High-Z Output 15 60 ns TOH 1 Output Hold from Address Change 0 0 ns T11.5 349

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 TABLE 12: FLASH PROGRAM /ERASE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF041/043-70 SST31LF041A/ 043A-300 UnitsMin Max Min Max TBP Byte-Program Time 20 20 µs TAS Address Setup Time 0 0 ns TAH Address Hold Time 30 50 ns TBS WE# and BEF# Setup Time 0 0 ns TBH WE# and BEF# Hold Time 0 0 ns TOES OE# High Setup Time 0 0 ns TOEH OE# High Hold Time 10 10 ns TBP BEF# Pulse Width 40 100 ns TWP WE# Pulse Width 40 100 ns TWPH WE# Pulse Width High 30 50 ns TBPH BEF# Pulse Width High 30 50 ns TDS Data Setup Time 40 50 ns TDH Data Hold Time 0 0 ns TIDA Software ID Access and Exit Time 150 150 ns TSE Sector-Erase 25 25 ms TSBE Bank-Erase 100 100 ms TBS Bank Enable Setup Time for Concurrent Operation 0 0 ns T12.4 349

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 3: SRAM R EAD CYCLE TIMING DIAGRAM FIGURE 4: SRAM W RITE CYCLE TIMING DIAGRAM 349 ILL F02.9 ADDRESS A 16-0 DQ 7-0 WE# OE# 1 BES# 1 TBES TRCS TAAS TOES TOLZSVIH HIGH-Z TBLZS TOHS TBHZS HIGH-Z DATA VALIDDATA VALID TOHZS BEF# Note 1: For SST31LF041A/043A. BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#. 349 ILL F03.10 ADDRESS A 16-0 ADDRESS DQ 7-0 OE# 1 WE# BES# 1 TBWS TWCS TAWS TASTS TWPS TWRS TDSS TDHS DATA VALID BEF# Note 1: For SST31LF041A/043A. BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#.

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 5: F LASH READ CYCLE TIMING DIAGRAM FIGURE 6: F LASH WE# C ONTROLLED PROGRAM CYCLE TIMING DIAGRAM 349 ILL F18.5 ADDRESS A 18-0 DQ 7-0 WE# OE# 1 BEF# BES# 1 TBE TRC TAA TOE TOLZ VIH HIGH-Z TBLZ TOH TBHZ HIGH-Z DATA VALIDDATA VALID TOHZ Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. 349 ILL F04.6 ADDRESS A 18-0 DQ 7-0 TDH TWPH TDS TWP TAH TAS TCH TCS BEF# BES# 1 SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# 1 WE# TBP Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 7: BEF# C ONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM FIGURE 8: F LASH DATA # POLLING TIMING DIAGRAM 349 ILL F05.6 ADDRESS A 18-0 DQ 7-0 TDH TCPH TDS TCP TAH TAS TCH TCS WE# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# 1 BEF# TBP BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. 349 ILL F06.6 ADDRESS A 18-0 DQ 7 DD # D # D WE# OE# 1 BEF# TOEH TOE TCE TOES BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 9: F LASH TOGGLE BIT TIMING DIAGRAM FIGURE 10: WE# C ONTROLLED FLASH SECTOR -ERASE TIMING DIAGRAM 349 ILL F07.6 ADDRESS A 18-0 DQ 6 WE# OE# 1 BEF# TOETOEH TBE TOES TWO READ CYCLES WITH SAME OUTPUTS BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. 349 ILL F08.8 ADDRESS A 18-0 DQ 7-0 WE# SW0 Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) SA X = Sector Address SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 3055AA 80 AA SA X BEF# SIX-BYTE CODE FOR SECTOR-ERASE TSE TWP OE# 1 BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 11: WE# C ONTROLLED FLASH BANK -ERASE TIMING DIAGRAM FIGURE 12: FLASH SOFTWARE ID ENTRY AND READ 349 ILL F17.8 ADDRESS A 18-0 DQ 7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 1055AA 80 AA 5555 BEF# SIX-BYTE CODE FOR BANK-ERASE TSBE TWP Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) OE# 1 BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. 349 ILL F09.7 ADDRESS A 14-0 TIDA DQ 7-0 WE# SW0 SW1 SW2 5555 2AAA 5555 0000 0001 BEF# THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY TWP TWPH TAA BF Device ID55AA 90 OE# 1 BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. Note: Device ID = 16H for SST31LF041A, 17H for SST31LF041, 65H for SST31LF043 and 66H for SST31LF043A.

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 13: FLASH SOFTWARE ID EXIT AND RESET FIGURE 14: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH /SRAM AND SRAM/F LASH 349 ILL F10.7 ADDRESS A 14-0 DQ 7-0 TIDA TWP T WHP WE# SW0 SW1 SW2 5555 2AAA 5555 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET BEF# AA 55 F0 OE# 1 BES# 1 Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. 349 ILL F22.0 ADDRESS A 18-0 TBS DQ 7-0 BEj# BEj1# WE# OE# Note: j = F or S j1 = S or F

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 15: AC INPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 16: A TEST LOAD EXAMPLE 349 ILL F11.1 REFERENCE POINTS OUTPUTINPUT VIT VIHT VILT VOT AC test inputs are driven at VIHT (0.9 VDD ) for a logic “1” and VILT (0.1 VDD ) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD ) and VOT (0.5 VDD ). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Tes t VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 349 ILL F12.2 TO TESTER TO DUT C L

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 17: BYTE -PROGRAM ALGORITHM 349 ILL F13.2 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP , Data# Polling bit, or Toggle bit operation) Program Completed

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 18: W AIT OPTIONS 349 ILL F14.0 Wait TBP , TSBE, or TSE Byte Program/Erase Initiated Internal Timer Toggle Bit Ye s Ye s No No Program/Erase Completed Does DQ 6 match? Read same byte Data# Polling Program/Erase Completed Program/Erase Completed Read byte Is DQ7 = true data? Read DQ 7 Byte Program/Erase Initiated Byte Program/Erase Initiated

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS 349 ILL F15.2 Load data: AAH Address: 5555H Software Product ID Entry Command Sequence Load data: 55H Address: 2AAAH Load data: 90H Address: 5555H Wait TIDA Read Software ID Load data: AAH Address: 5555H Software Product ID Exit & Reset Command Sequence Load data: 55H Address: 2AAAH Load data: F0H Address: 5555H Load data: F0H Address: XXH Return to normal operation Wait TIDA Wait TIDA Return to normal operation

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 FIGURE 20: ERASE COMMAND SEQUENCE 349 ILL F16.2 Load data: AAH Address: 5555H Chip-Erase Command Sequence Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: AAH Address: 5555H Wait TSBE Chip erased to FFH Load data: AAH Address: 5555H Sector-Erase Command Sequence Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 55H Address: 2AAAH Load data: 30H Address: SAX Load data: AAH Address: 5555H Wait TSE Sector erased to FFH

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 SST31LF041 Valid combinations SST31LF041-70-4C-WI SST31LF041-70-4E-WI SST31LF041A Valid combinations SST31LF041A-300-4C-WH SST31LF041A-300-4E-WH SST31LF043 Valid combinations SST31LF043-70-4C-WI SST31LF043-70-4E-WI SST31LF043A Valid combinations SST31LF043A-300-4C-WH SST31LF043A-300-4E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Device Speed Suffix1 Suffix2 SST31 LF04x x -X X X -X X -X X Package Modifier H = 32 leads I = 40 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm - 32-lead package) (10mm x 14mm - 40-lead package) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 300 = 300 ns Version A = 32-lead TSOP Package Density 041/041A = 4 Mbit Flash + 1 Mbit SRAM 043/043A = 4 Mbit Flash + 256 Kbit SRAM Voltage L = 3.0-3.6V Device Family 31 = Monolithic ComboMemory

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 PACKAGING DIAGRAMS 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 Pin # 1 Identifier 14.20 13.80 0.70 0.50

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 14MM SST PACKAGE CODE : WI 0.60 0.40 40.TSOP-WI-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 10.10 9.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 14.20 13.80 Pin # 1 Identifier

SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  T elephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.ssti.com