SST31LF021-70-4E-WH

SST31LF021 SST | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet FEATURES:

• Monolithic Flash + SRAM ComboMemory – SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM  Single 3.0-3.6V Read and Write Operations  Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash  Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention  Low Power Consumption: – Active Current: 10 mA (typical) for Flash and 20 mA (typical) for SRAM Read – Standby Current: 10 µA (typical)  Flash Sector-Erase Capability – Uniform 4 KByte sectors  Latched Address and Data for Flash  Fast Read Access Times: – SST31LF021 Flash: 70 ns SRAM: 70 ns – SST31LF021E Flash: 300 ns SRAM: 300 ns  Flash Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Bank-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Bank Rewrite Time: 4 seconds (typical)  Flash Automatic Erase and Program Timing – Internal V PP Generation  Flash End-of-Write Detection – Toggle Bit – Data# Polling  CMOS I/O Compatibility  JEDEC Standard Command Set  Package Available – 32-lead TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST31LF021/021E devices are a 256K x8 CMOS flash memory bank combined with a 128K x8 or 32K x8 CMOS SRAM memory bank manufactured with SST’s proprietary, high performance SuperFlash technology. Two pinout standards are available for these devices. The SST31LF021 conform to JEDEC standard flash pinouts and the SST31LF021E conforms to standard EPROM pinouts. The SST31LF021/021E devices write (SRAM or flash) with a 3.0-3.6V power supply. The monolithic SST31LF021/021E devices conform to Software Data Protect (SDP) commands for x8 EEPROMs. Featuring high performance Byte-Program, the flash memory bank provides a maximum Byte-Program time of 20 µsec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 4 seconds, when using interface features such as Toggle Bit or Data# Poll- ing to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LF021/ 021E devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LF021/ 021E devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST31LF021/021E operate as two independent mem- ory banks with respective bank enable signals. The SRAM and flash memory banks are superimposed in the same memory address space. Both memory banks share com- mon address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program opera- tions in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST31LF021/021E provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Byte-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus

2 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF021 / 021E2 Mb Flash (x8) + 1 Mb SRAM (x8) Monolithic ComboMemories

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 requirement. Once the internally controlled Erase or Pro- gram cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST31LF021/021E devices are suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LF021/021E devices significantly improve per- formance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LF021/021E inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy con- sumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed dur- ing any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory elimi- nates redundant functions when using two separate mem- ories of similar architecture; therefore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. The SST31LF021/021E devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LF021/021E devices are offered in 32-lead TSOP packages. See Figure 1 for the pinouts. Device Operation The ComboMemory uses BES# and BEF# to control oper- ation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be exe- cuted in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared; which minimizes power consumption and area. The device goes into standby when both bank enables are raised to V IHC. SRAM Operation With BES# low and BEF# high, the SST31LF021/021E operate as a 128K x8 or 32K x8 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LF021/021E are controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the out- put pins. The data bus is in high impedance state when OE# is high. See Figure 2 for the Read cycle timing dia- gram. SRAM Write The SRAM Write operation of the SST31LF021/021E are controlled by WE# and BES#, both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge to the first rising edge of BES# and WE#. See Figure 3 for the Write cycle timing diagram. Flash Operation With BEF# active, the SST31LF021/021E operate as a 256K x8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. Flash Read The Read operation of the SST31LF021/021E devices are controlled by BEF# and OE#, both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 4 for the Read cycle timing diagram.

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LF021/021E. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A com- mand is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Byte-Program Operation The flash memory bank of the SST31LF021/021E devices are programmed on a byte-by-byte basis. Before the Pro- gram operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, which- ever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be com- pleted, within 20 µs. See Figures 5 and 6 for WE# and BEF# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector-Erase Operation The Sector-Erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six- byte command load sequence for Software Data Protec- tion with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A 17-A12 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Fig- ure 9 for timing waveforms. Any SDP commands loaded during the Sector-Erase operation will be ignored. Flash Bank-Erase Operation The SST31LF021/021E flash memory bank provides a Bank-Erase operation, which allows the user to erase the entire flash memory bank array to the ‘1’s state. This is use- ful when the entire bank must be quickly erased. The Bank- Erase operation is initiated by executing a six-byte Software Data Protection command sequence with Bank-Erase com- mand (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read oper- ations are Toggle Bit and Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Fig- ure 19 for the flowchart. Any SDP commands loaded during the Bank-Erase operation will be ignored. Flash Write Operation Status Detection The SST31LF021/021E flash memory bank provides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ 7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvola- tile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ 7 or DQ 6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Data# Polling (DQ7) When the SST31LF021/021E flash memory bank is in the internal Program operation, any attempt to read DQ 7 will produce the complement of the true data. Once the Pro- gram operation is completed, DQ 7 will produce true data. Note that even though DQ7 may have valid data immedi- ately following the completion of an internal Write opera- tion, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent suc- cessive Read cycles after an interval of 1 µs. During inter- nal Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program opera- tion. For Sector or Bank-Erase, the Data# Polling is valid

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 17 for a flowchart. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sec- tor or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 17 for a flowchart. Flash Memory Data Protection The SST31LF021/021E flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. Flash Software Data Protection (SDP) The SST31LF021/021E provide the JEDEC approved Software Data Protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LF021/021E devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the Read mode, within T RC. Concurrent Read and Write Operations The SST31LF021/021E provide the unique benefit of being able to read from or write to SRAM, while simulta- neously erasing or programming the flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. SST does not rec- ommend that both bank enables, BEF# and BES#, be simultaneously asserted. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Product Identification The Product Identification mode identifies the devices as either SST31LF021 or SST31LF021E and the manufac- turer as SST. This mode may be accessed by hardware or software operations. The hardware device ID Read opera- tion is typically used by a programmer to identify the correct algorithm for the SST31LF021/021E flash memory banks. Users may wish to use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 18 for the ID entry com- mand sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an C ONCURRENT READ /W RITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write TABLE 1: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST31LF021 0001H 18H SST31LF021E 0001H 19H T1.4 392

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 internal Program or Erase operation. See Table 4 for soft- ware command codes, Figure 12 for timing waveform and Figure 18 for a flowchart. Design Considerations SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between V DD and VSS, e.g., less than 1 cm away from the V DD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from V DD to VSS should be placed within 1 cm of the VDD pin. FIGURE 1: P IN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM ) I/O Buffers 392 ILL B1.2 Address Buffers DQ7 - DQ0 SuperFlash Memory SRAM Control Logic Address Buffers & Latches OE# BEF# WE# BES# AMS - A0 Note: AMS = Most Significant Address FUNCTIONAL BLOCK DIAGRAM A11 A13 A14 A17 WE# VDD BES# A16 A15 A12 OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 392 ILL F01.3 Standard Pinout Top View Die Up A11 A13 A14 A17 BES# VDD WE# A16 A15 A12 SST31LF021E SST31LF021 SST31LF021 SST31LF021E

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 TABLE 2: P IN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During flash Sector-Erase, A17-A12 address lines will select the sector. A17-A0 to provide flash address A16-A0 to provide SST31LF021/021E SRAM addresses DQ7-DQ0 Data Input/Output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V DD Power Supply 3.0-3.6V Power Supply VSS Ground T2.3 392 1. A MS = Most significant address TABLE 3: O PERATION MODES SELECTION Mode BES# BEF# OE# WE# A 9 DQ Address Flash Read X 1 1. X can be V IL or VIH, but no other value. VIL VIL VIH AIN DOUT AIN Program X V IL VIH VIL AIN DIN AIN Erase X V IL VIH VIL X X Sector address, XXH for Bank-Erase SRAM Read V IL VIH VIL VIH AIN DOUT AIN Write V IL VIH XV IL AIN DIN AIN Standby V IHC VIHC XX X H i g h Z X Flash Write Inhibit X X V IL X X High Z / D OUT X XX X V IH XH i g h Z / DOUT X XV IH XX X H i g h Z / D OUT X Product Identification Hardware Mode X V IL VIL VIH VH Manufacturer’s ID (BFH) Device ID2 2. Device ID 18H for SST31LF021, 19H for SST31LF021E. A17-A1=VIL, A0=VIL A17-A1=VIL, A0=VIH Software Mode X V IL VIL VIH AIN ID Code See Table 4 T3.4 392

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 TABLE 4: S OFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr 1 Data Addr 1 Data Addr 1 Data Addr 1 Data Addr 1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA 2 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA X3 30H Bank-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H T4.4 392 1. Address format A 14-A0 (Hex),Address A15, A16, and A17 can be VIL or VIH, but no other value, for the Command sequence. 2. BA = Program Byte address 3. SA X for Sector-Erase; uses A17-A12 address lines 4. The device does not remain in Software Product ID mode if powered down. 5. With A 17-A1 = 0; SST Manufacturer’s ID = BFH, is read with A 0 = 0, SST31LF021 Device ID = 18H, is read with A 0 = 1, SST31LF021E Device ID = 19H, is read with A 0 = 1 Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) DD+0.5V 1. Outputs shorted for no more than one second. No more than one output shorted at a time. O PERATING RANGE : SST31LF021/021E Range Ambient Temp V DD Commercial 0°C to +70°C 3.0-3.6V Extended -20°C to +85°C 3.0-3.6V AC C ONDITIONS OF TEST L = 30 pF See Figures 14 and 15

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 TABLE 5: DC O PERATING CHARACTERISTICS (VDD = 3.0-3.6V) Symbol Parameter Limits Test ConditionsMin Max Units IDD Power Supply Current Address input V IL/VIH, at f=1/TRC Min, VDD=VDD Max, all DQs open Read Flash 12 mA OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH SRAM 40 mA BEF#=V IH, BES#=VIL Concurrent Operation 55 mA BEF#=V IH, BES#=VIL Write Flash (Program) 15 mA OE#=VIH, WE#=VIL BEF#=VIL, BES#=VIH SRAM 40 mA BEF#=V IH, BES#=VIL ISB1 Standby VDD Current 30 µA BEF#=BES#=V IHC, VDD=VDD Max ILI Input Leakage Current 1 µA V IN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA V OUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.4 V V DD=VDD Min VIH Input High Voltage 0.7V DD VV DD=VDD Max VIHC Input High Voltage (CMOS) V DD-0.3 V V DD=VDD Max VOL Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min VOH Output High Voltage V DD-0.2 V I OH=-100 µA, VDD=VDD Min VH Supervoltage for A9 pin 11.4 12.6 V BEF#=OE#=V IL, WE#=VIH IH Supervoltage Current for A9 pin 200 µA BEF#=OE#=V IL, WE#=VIH, A9=VH Max T5.3 392 1. Specification applies to commercial temperature device s only. This parameter may be higher for extended devices. TABLE 6: R ECOMMENDED SYSTEM POWER -UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. Power-up to Read Operation 100 µs TPU-WRITE1 Power-up to Write Operation 100 µs T6.1 392 TABLE 7: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. I/O Pin Capacitance V I/O = 0V 12 pF CIN1 Input Capacitance V IN = 0V 6 pF T7.0 392 TABLE 8: R ELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 + I DD mA JEDEC Standard 78 T8.1 392

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 AC CHARACTERISTICS TABLE 9: SRAM M EMORY BANK READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF021-70 SST31LF021E-300 UnitMin Max Min Max TRCS Read Cycle Time 70 300 ns TAAS Address Access Time 70 300 ns TBES Bank Enable Access Time 70 300 ns TOES Output Enable Access Time 35 150 ns TBLZS1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. BES# to Active Output 0 15 ns TOLZS1 Output Enable to Active Output 0 15 ns TBHZS1 BES# to High-Z Output 25 30 ns TOHZS1 Output Disable to High-Z Output 25 30 ns TOHS Output Hold from Address Change 0 10 ns T9.4 392 TABLE 10: SRAM M EMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF021-70 SST31LF021E-300 UnitMin Max Min Max TWCS Write Cycle Time 70 300 ns TBWS Bank Enable to End-of-Write 60 230 ns TAWS Address Valid to End-of-Write 60 230 ns TASTS Address Set-up Time 0 0 ns TWPS Write Pulse Width 60 200 ns TWRS Write recovery Time 0 0 ns TDSS Data Set-up Time 30 150 ns TDHS Data Hold from Write Time 0 0 ns T10.4 392 TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF021-70 SST31LF021E-300 UnitsMin Max Min Max TRC Read Cycle Time 70 300 ns TBE Bank Enable Access Time 70 300 ns TAA Address Access Time 70 300 ns TOE Output Enable Access Time 40 150 ns TBLZ1 1. This parameter is measured only for init ial qualification and after a design or proces s change that could affect this parameter. BEF# Low to Active Output 0 0 ns TOLZ1 OE# Low to Active Output 0 0 ns TBHZ1 BEF# High to High-Z Output 15 60 ns TOHZ1 OE# High to High-Z Output 15 60 ns TOH1 Output Hold from Address Change 0 0 ns T11.3 392

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 TABLE 12: FLASH PROGRAM /ERASE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) Symbol Parameter SST31LF021-70 SST31LF021E-300 UnitsMin Max Min Max TBP Byte-Program Time 20 20 µs TAS Address Setup Time 0 0 ns TAH Address Hold Time 30 50 ns TBS WE# and BEF# Setup Time 0 0 ns TBH WE# and BEF# Hold Time 0 0 ns TOES OE# High Setup Time 0 0 ns TOEH OE# High Hold Time 10 10 ns TBP BEF# Pulse Width 40 100 ns TWP WE# Pulse Width 40 100 ns TWPH WE# Pulse Width High 30 50 ns TBPH BEF# Pulse Width High 30 50 ns TDS Data Setup Time 40 50 ns TDH Data Hold Time 0 0 ns TIDA Software ID Access and Exit Time 150 150 ns TSE Sector-Erase 25 25 ms TSBE Bank-Erase 100 100 ms TBS Bank Enable Setup Time for Concurrent Operation 0 0 ns T12.3 392

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 2: SRAM R EAD CYCLE TIMING DIAGRAM FIGURE 3: SRAM W RITE CYCLE TIMING DIAGRAM 392 ILL F02.0 ADDRESS A16-0 DQ7-0 WE# OE# BES# BEF# TBES TRCS TAAS TOES TOLZSVIH HIGH-Z TBLZS TOHS TBHZS HIGH-Z DATA VALIDDATA VALID TOHZS 392 ILL F03.0 ADDRESS A16-0 ADDRESS DQ7-0 OE# WE# BES# TWCS TAWS TASTS TWPS TWRS TBWS TDSS TDHS DATA VALID BEF#

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 4: F LASH READ CYCLE TIMING DIAGRAM FIGURE 5: F LASH WE# C ONTROLLED PROGRAM CYCLE TIMING DIAGRAM 392 ILL F18.0 ADDRESS A17-0 DQ7-0 WE# OE# BEF# BES# TBE TRC TAA TOE TOLZVIH HIGH-Z TBLZ TOH TBHZ HIGH-Z DATA VALIDDATA VALID TOHZ 392 ILL F04.0 ADDRESS A17-0 DQ7-0 TDH TWPH TDS TWP TAH TAS TCH TCS BEF# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# WE# TBP BES#

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 6: BEF# C ONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM FIGURE 7: F LASH DATA # POLLING TIMING DIAGRAM 392 ILL F05.0 ADDRESS A17-0 DQ7-0 TDH TCPH TDS TCP TAH TAS TCH TCS WE# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# BEF# TBP BES# 392 ILL F06.0 ADDRESS A17-0 DQ7 DD # D # D WE# OE# BEF# TOEH TOE TCE TOES BES#

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 8: F LASH TOGGLE BIT TIMING DIAGRAM FIGURE 9: WE# C ONTROLLED FLASH SECTOR -ERASE TIMING DIAGRAM 392 ILL F07.0 ADDRESS A17-0 DQ6 WE# OE# BEF# TOETOEH TBE TOES TWO READ CYCLES WITH SAME OUTPUTS BES# 392 ILL F08.1 ADDRESS A17-0 DQ7-0 WE# SW0 Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) SAX = Sector Address SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 3055AA 80 AA SAX OE# BEF# SIX-BYTE CODE FOR SECTOR-ERASE TSE TWP BES#

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 10: WE# C ONTROLLED FLASH BANK -ERASE TIMING DIAGRAM FIGURE 11: FLASH SOFTWARE ID ENTRY AND READ 392 ILL F17.1 ADDRESS A17-0 DQ7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 1055AA 80 AA 5555 OE# BEF# SIX-BYTE CODE FOR BANK-ERASE TSBE TWP Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) BES# 392 ILL F09.5 ADDRESS A14-0 TIDA DQ7-0 WE# SW0 SW1 SW2 MFG ID DEVICE ID Device ID = 18H for SST31LF021 and 19H for SST31LF021E. 5555 2AAA 5555 0000 0001 OE# BEF# THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY TWP TWPH TAA BF55AA 90 BES#

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 12: FLASH SOFTWARE ID EXIT AND RESET FIGURE 13: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH /SRAM AND SRAM/F LASH 392 ILL F10.0 ADDRESS A14-0 DQ7-0 TIDA TWP T WHP WE# SW0 SW1 SW2 5555 2AAA 5555 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET OE# BEF# AA 55 F0 BES# 392 ILL F20.0 ADDRESS A17-0 TBS DQ7-0 BEj# BEj1# WE# OE# Note: j = F or S j1 = S or F

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 14: AC INPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 15: A TEST LOAD EXAMPLE 392 ILL F11.1 REFERENCE POINTS OUTPUTINPUT VIT VIHT VILT VOT AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Tes t VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 392 ILL F12.1 TO TESTER TO DUT CL

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 16: BYTE -PROGRAM ALGORITHM 392 ILL F13.1 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, DATA# Polling bit, or Toggle bit operation) Program Completed

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 17: W AIT OPTIONS 392 ILL F14.0 Wait TBP, TSBE, or TSE Byte Program/Erase Initiated Internal Timer Toggle Bit Ye s Ye s No No Program/Erase Completed Does DQ6 match? Read same byte Data# Polling Program/Erase Completed Program/Erase Completed Read byte Is DQ7 = true data? Read DQ7 Byte Program/Erase Initiated Byte Program/Erase Initiated

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS 392 ILL F15.1 Load data: AAH Address: 5555H Software Product ID Entry Command Sequence Load data: 55H Address: 2AAAH Load data: 90H Address: 5555H Wait TIDA Read Software ID Load data: AAH Address: 5555H Software Product ID Exit & Reset Command Sequence Load data: 55H Address: 2AAAH Load data: F0H Address: 5555H Load data: F0H Address: XXH Return to normal operation Wait TIDA Wait TIDA Return to normal operation

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 FIGURE 19: ERASE COMMAND SEQUENCE 392 ILL F16.1 Load data: AAH Address: 5555H Chip-Erase Command Sequence Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: AAH Address: 5555H Wait TSBE Chip erased to FFH Load data: AAH Address: 5555H Sector-Erase Command Sequence Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 55H Address: 2AAAH Load data: 30H Address: SAX Load data: AAH Address: 5555H Wait TSE Sector erased to FFH

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 PRODUCT ORDERING INFORMATION Valid combinations for SST31LF021 SST31LF021-70-4C-WH SST31LF021-70-4E-WH Valid combinations for SST31LF021E SST31LF021E-300-4C-WH SST31LF021E-300-4E-WH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Device Speed Suffix1 Suffix2 SST31LF021 x -X X X -X X -X X Package Modifier H = 32 leads Package Type W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 300 = 300 ns Version Blank = Flash Pinout E = EPROM Pinout Density 021 = 2 Mbit Flash + 1 Mbit SRAM Voltage L = 3.0-3.6V Device Family 31 = Monolithic ComboMemory

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 PACKAGING DIAGRAMS 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH 32-tsop-WH-ILL.6 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm Pin # 1 Identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0.50 BSC 1.05 0.95 0.15 0.05 0.70 0.50 0˚- 5˚ DETAIL

©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  T elephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.ssti.com