SST30VR043-70-C-WH

SST30VR041 SST | Alldatasheet

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©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Preliminary Specifications FEATURES:

• ROM + SRAM ROM/RAM Combo – SST30VR041: 512K x8 ROM + 128K x8 SRAM – SST30VR043: 512K x8 ROM + 32K x8 SRAM  ROM/RAM combo on a monolithic chip  Equivalent ComboMemory (Flash + SRAM): SST31LF041A for code development and pre-production  Wide Operating Voltage Range: 2.7-3.3V  Chip Access Time – SST30VR041 70 ns and 150 ns – SST30VR043 150 ns  Low Power Dissipation: – Standby: 1.0 µW (Typical) – Operating: 3.0 mW (Typical)  Fully Static Operation – No clock or refresh required  Three state Outputs  Packages Available – 32-pin TSOP (8mm x14mm)PRODUCT DESCRIPTION The SST30VR041/043 are ROM/RAM combo chips con- sisting of 4 Mbit Read Only Memory organized as 512 KBytes and a Static Random Access Memory organized as either 128 or 32 KBytes. Output Enable Input (OE#) is pin-shared with RAMCS# (RAM Enable Input) signal in order to maintain the standard 32-pin TSOP package. The device is fabricated using SST’s advanced CMOS low power process technology. The SST30VR041/043 have an output enable input for pre- cise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and for minimizing current drain during power-down mode. The SST30VR041/043 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications. RAMCS# OE#/RAMCS# ROMCS# WE# AMS -A0 Note: AMS = Most Significant Address DQ 7-DQ 0 ROMCS# RAM ROM WE# OE# OE# 381 ILL B1.2 Control CircuitAddress Buffer Data Buffer FUNCTIONAL BLOCK DIAGRAM

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041/0434 Mb Mask ROM (x8) + 1 Mb / 256 Kbit SRAM (x8) Combo

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 FIGURE 1: P IN ASSIGNMENTS FOR 32-PIN TSOP TABLE 1: P IN DESCRIPTION Symbol Pin Name AMS 1-A0 1. AMS = Most significant address Address Inputs, for ROM: AMS = A18, for RAM: AMS =A16 for SST30VR041 A14 for SST30VR043 WE# Write Enable Input OE#/RAMCS# Output Enable/RAM Enable Input ROMCS# ROM Enable Input DQ 7-DQ 0 Data Input/Output VDD Power Supply VSS Ground T1.2 381 A11 A13 A14 A17 WE# VDD A18 A16 A15 A12 OE#/RAMCS# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 381 ILL F01.0 Standard Pinout Top View Die Up

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Voltage on Any Pin Relative to V O PERATING RANGE Range Ambient Temp V DD Commercial 0 °C to +70°C 2.7-3.3V Extended -20°C to +85°C 2.7-3.3V AC C ONDITIONS OF TEST Input & Output Timing Reference Levels . . . VDD /2 TABLE 2: R ECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min Max Units VDD Supply Voltage 2.7 3.3 V VSS Ground 0 0 V VIH Input High Voltage 2.4 V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V T2.0 381 TABLE 3: DC O PERATING CHARACTERISTICS Symbol Parameter VDD = 3.0±0.3V Test ConditionsMin Max Units IDD1 ROM Operating Supply Current 4.0+1.1(f) 1 1. f = Frequency of operation (MHz) = 1/cycle time mA ROMCS# = V IL, RAMCS# = VIH, VIN = VIH or VIL, II/O = Opens IDD2 RAM Operating Supply Current 2.5+1(f) 1 mA ROMCS# = V IH, RAMCS# = VIL, II/O = Opens ISB Standby VDD Current 10 µA ROMCS# ≥ VDD -0.2V, RAMCS# ≥ VDD -0.2V VIN ≥ VDD -0.2V or VIN ≤ 0.2V ILI Input Leakage Current -1 1 µA V IN = VSS to VDD ILO Output Leakage Current -1 1 µA ROMCS# = RAMCS# = V IH or OE# = VIH or WE# = VIL, VI/O = VSS to VDD VOL Output Low Voltage 0.4 V I OL = 1.0 mA VOH Output High Voltage 2.2 V I OH = -0.5 mA T3.4 381

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 FIGURE 2: AC I NPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 3: A T EST LOAD EXAMPLE TABLE 4: C APACITANCE (Ta = 25°C, f=1 Mhz) Parameter Description Test Condition Maximum C I/O1 I/O Pin Capacitance V I/O = 0V 8 pF C IN1 Input Capacitance V IN = 0V 6 pF T4.1 381 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 381 ILL F07.0 REFERENCE POINTS OUTPUTINPUT VIT VIHT VILT VOT AC test inputs are driven at VIHT (0.9 VDD ) for a logic “1” and VILT (0.1 VDD ) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD ) and VOT (0.5 VDD ). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Tes t VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 381 ILL F08.0 TO TESTER TO DUT C L

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 AC CHARACTERISTICS I. ROM Operation FIGURE 4: ROM R EAD CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED ) (ROMCS# = OE# = VIL) TABLE 5: R EAD CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 Symbol Parameter SST30VR041-70 SST30VR041/043-150 UnitsMin Max Min Max TRC Read Cycle Time 70 150 ns TAA Address Access Time 70 150 ns TCO Chip Select to Output 70 150 ns TOE Output Enable to Valid Output 35 70 ns TLZ Chip Select to Low-Z Output 0 0 ns TOLZ Output Enable to Low-Z Output 0 0 ns THZ Chip Disable to High-Z Output 25 30 ns TOHZ Output Disable to High-Z Output 25 30 ns TOH Output Hold from Address Change 10 15 ns T5.2 381 TRC TAA Data Valid 381 ILL F02.0 Data Out Previous Data Valid Address TOH

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 FIGURE 5: ROM R EAD CYCLE TIMING DIAGRAM (ROMCS# & OE# C ONTROLLED ) II. SRAM Operation(ROMCS# = V IH) TRC TAA TCO TLZ(2) TOHZ(1) TOH THZ(1,2) Data Valid 381 ILL F03.0 Data Out OE# ROMCS# High-Z Address TOE TOLZ Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL . 2. At any given temperature and voltage condition THZ (max) is less than TLZ(min) both for a given device and from device to device. TABLE 6: R EAD CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 Symbol Parameter SST30VR041-70 SST30VR041/043-150 UnitsMin Max Min Max TRC Read Cycle Time 70 150 ns TAA Address Access Time 70 150 ns TCO Chip Select to Output 70 150 ns TLZ Chip Select to Low-Z Output 0 0 ns THZ Chip Disable to High-Z Output 25 30 ns TOH Output Hold from Address Change 10 15 ns T6.2 381 TABLE 7: W RITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 Symbol Parameter SST30VR041-70 SST30VR041/043-150 UnitsMin Max Min Max TWC Write Cycle Time 70 150 ns TCW Chip Select to End-of-Write 60 120 ns TAW Address Valid to End-of-Write 60 120 ns TAS Address Set-up Time 0 0 ns TWP Write Pulse Width 60 120 ns TWR Write Recovery Time 0 0 ns TWHZ Write to Output High-Z 30 60 ns TDW Data to Write Time Overlap 30 60 ns TDH Data Hold from Write Time 0 0 ns TOW End Write to Output Low-Z 0 10 ns T7.2 381

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 FIGURE 6: SRAM R EAD CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED ) (OE#/RAMCS# = VIL, WE# = VIH) FIGURE 7: SRAM R EAD CYCLE TIMING DIAGRAM (OE#/RAMCS# C ONTROLLED ) TRC TAA Data Valid 381 ILL F04.0 Data Out Previous Data Valid Address TOH TRC TAA TCO TLZ(2) TOH THZ(1,2) Data Valid 381 ILL F05.0 Data Out OE#/RAMCS# High-Z Address Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL . 2. At any given temperature and voltage condition THZ (max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle.

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 FIGURE 8: SRAM W RITE CYCLE TIMING DIAGRAM TABLE 8: F UNCTIONAL DESCRIPTION /TRUTH TABLE Address Inputs ROMCS# OE#/RAMCS# 1 (Pin 32) 1. OE# & RAMCS# are pin-shared WE# DQ 7-DQ 0 2. X means Don’t Care. H H X Z Standby AMS 3-A0 3. For ROM: AMS = A18 for SST30VR041 and SST30VR043 L OE# (H) X Z Output Floating AMS 3-A0 LO E # ( L ) X D OUT ROM Read Only AMS 4-A0 are valid 4. For RAM: AMS = A16 for SST30VR041, A18-A17 must be fixed to “L” or “H ” AMS = A14 for SST30VR043, A18-A15 must be fixed to “L” or “H ” HR A M C S # ( L ) H D OUT RAM Read Only AMS 4-A0 are valid H RAMCS# (L) L D IN RAM Write T8.3 381 TWC TAW TCW(2) TOH TDHTDW TOW TWR(4) Data Valid 381 ILL F06.0 Data In Data Out WE# OE#/RAMCS# High-Z High-Z (6) (7) (8) Address TWP(1)TAS(3) TWHZ(5) Notes: 1. A write occurs during the overlap (TWP ) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = V IH

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 SST30VR041 Valid combinations SST30VR041-70-C-WH SST30VR041-150-C-WH SST30VR041-70-C-U1 SST30VR041-150-C-U1 SST30VR041-70-E-WH SST30VR041-150-E-WH SST30VR043 Valid combinations SST30VR043-150-C-WH SST30VR043-150-C-U1 SST30VR043-150-E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. C-Spec Number Package Modifier H = 32 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm) U = Die only Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Read Access Speed 70 = 70 ns 150 = 150 ns Device Density 041 = 4 Mbit ROM + 1 Mbit SRAM 043 = 4 Mbit ROM + 256 Kbit SRAM Voltage Range V = 2.7-3.3V Device Family 30 = ROM/RAM Combo Device Speed Suffix1 Suffix2 SST30 V R0xx -X X X -X -X X - RXXXX

Preliminary Specifications ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 PACKAGING DIAGRAMS 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 Pin # 1 Identifier 14.20 13.80 0.70 0.50 Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  T elephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.ssti.com