SST30VR022-70-C-U1

SST30VR021 SST | Alldatasheet

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©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet FEATURES:

• ROM + SRAM ROM/RAM Combo – SST30VR021: 256K x8 ROM + 128K x8 SRAM – SST30VR022: 256K x8 ROM + 256K x8 SRAM – SST30VR023: 256K x8 ROM + 32K x8 SRAM  ROM/RAM combo on a monolithic chip  Equivalent ComboMemory (Flash + SRAM): SST31LF021E for code development and pre-production  Wide Operating Voltage Range: 2.7-3.3V  Chip Access Time – SST30VR022 70 ns – SST30VR021/023 500 ns  Low Power Dissipation: – Standby: 3 µW (Typical) – Operating: 10 mW (Typical)  Fully Static Operation – No clock or refresh required  Three state Outputs  Packages Available – 32-pin TSOP (8mm x14mm) PRODUCT DESCRIPTION The SST30VR021/022/023 are ROM/RAM combo chips consisting of 2 Mbit Read Only Memory organized as 256 KBytes and Static Random Access Memory organized as 128, 256, and 32 KBytes. The device is fabricated using SST’s advanced CMOS low power process technology. The SST30VR021/022/023 has an output enable input for precise control of the data outputs. It also has two (2) sepa- rate chip enable inputs for selection of either RAM or ROM and for minimizing current drain during power-down mode. The SST30VR021/022/023 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications. RAMCS# OE# ROMCS# WE# DQ 7-DQ 0 AMS -A0 Note: AMS = Most Significant Address ROMCS# RAM ROM WE# OE# OE# 380 ILL B1.1 Address Buffer Data Buffer RAMCS# Control Circuit FUNCTIONAL BLOCK DIAGRAM

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

SST30VR021 / SST30VR022 / SST30VR023 SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 FIGURE 1: P IN ASSIGNMENTS FOR 32-PIN TSOP TABLE 1: P IN DESCRIPTION Symbol Pin Name AMS 1-A0 1. AMS = Most significant address Address Inputs, for ROM: AMS = A17, for RAM: AMS =A16 for SST30VR021 A17 for SST30VR022 A14 for SST30VR023 WE# Write Enable Input OE# Output Enable RAMCS# RAM Enable Input ROMCS# ROM Enable Input DQ 7-DQ 0 Data Input/Output VDD Power Supply VSS Ground T1.2 380 A11 A13 A14 A17 RAMCS# VDD WE# A16 A15 A12 OE# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 380 ILL F01.0 Standard Pinout Top View Die Up

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Voltage on Any Pin Relative to V O PERATING RANGE Range Ambient Temp V DD Commercial 0 °C to +70°C 2.7-3.3V Extended -20°C to +85°C 2.7-3.3V AC C ONDITIONS OF TEST TABLE 2: R ECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min Max Units VDD Supply Voltage 2.7 3.3 V VSS Ground 0 0 V VIH Input High Voltage 2.4 V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V T2.0 380 TABLE 3: DC O PERATING CHARACTERISTICS Symbol Parameter VDD = 3.0 ± 0.3V Test ConditionsMin Max Units IDD1 ROM Operating Supply Current 4.0+1.1(f) 1 1. f = Frequency of operation (MHz) = 1/cycle time mA ROMCS#=V IL, RAMCS#=V IH, VIN=V IH or VIL, II/O=Opens IDD2 RAM Operating Supply Current 2.5+1(f) 1 mA ROMCS#=V IH, RAMCS#=V IL, II/O=Opens ISB Standby VDD Current 10 µA ROMCS# ≥VDD -0.2V, RAMCS#≥VDD -0.2V VIN≥VDD -0.2V or VIN ≤0.2V ILI Input Leakage Current -1 1 µA V IN=V SS to VDD ILO Output Leakage Current -1 1 µA ROMCS#=RAMCS#=V IH or OE#=VIH or WE#=V IL, VI/O=VSS to VDD VOL Output Low Voltage 0.4 V I OL = 1.0 mA VOH Output High Voltage 2.2 V I OH = -0.5 mA T3.3 380

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 FIGURE 2: AC I NPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 3: A T EST LOAD EXAMPLE TABLE 4: C APACITANCE (Ta = 25°C, f=1 Mhz) Parameter Description Test Condition Maximum C I/O1 I/O Pin Capacitance V I/O = 0V 8 pF C IN1 Input Capacitance V IN = 0V 6 pF T4.1 380 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 380 ILL F08.0 REFERENCE POINTS OUTPUTINPUT VIT VIHT VILT VOT AC test inputs are driven at VIHT (0.9 VDD ) for a logic “1” and VILT (0.1 VDD ) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD ) and VOT (0.5 VDD ). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Tes t VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 380 ILL F09.0 TO TESTER TO DUT C L

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 AC CHARACTERISTICS I. ROM Operation FIGURE 4: ROM R EAD CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED ) (ROMCS# = OE# = VIL) TABLE 5: R EAD CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 Symbol Parameter SST30VR022-70 SST30VR021/023-500 UnitsMin Max Min Max TRC Read Cycle Time 70 500 ns TAA Address Access Time 70 500 ns TCO Chip Select to Output 70 500 ns TOE Output Enable to Valid Output 35 250 ns TLZ Chip Select to Low-Z Output 0 25 ns TOLZ Output Enable to Low-Z Output 0 25 ns THZ Chip Disable to High-Z Output 25 30 ns TOHZ Output Disable to High-Z Output 25 30 ns TOH Output Hold from Address Change 10 15 ns T5.1 380 TRC TAA Data Valid 380 ILL F02.0 Data Out Previous Data Valid Address TOH

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 FIGURE 5: ROM R EAD CYCLE TIMING DIAGRAM (ROMCS# & OE# C ONTROLLED ) TRC TAA TCO TLZ(2) TOHZ(1) TOH THZ(1,2) Data Valid 380 ILL F03.0 Data Out OE# ROMCS# High-Z Address TOE TOLZ Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL . 2. At any given temperature and voltage condition THZ (max) is less than TLZ(min) both for a given device and from device to device.

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 II. SRAM Operation(ROMCS# = V IH) TABLE 6: R EAD CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 Symbol Parameter SST30VR022-70 SST30VR021/023-500 UnitsMin Max Min Max TRC Read Cycle Time 70 500 ns TAA Address Access Time 70 500 ns TCO Chip Select to Output 70 500 ns TOE Output Enable to Valid Output 35 250 ns TLZ Chip Select to Low-Z Output 0 25 ns THZ Chip Disable to High-Z Output 25 30 ns TOHZ Output Disable to High-Z Output 25 30 ns TOH Output Hold from Address Change 10 15 ns T6.2 380 TABLE 7: W RITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 Symbol Parameter SST30VR022-70 SST30VR021/023-500 UnitsMin Max Min Max TWC Write Cycle Time 70 500 ns TCW Chip Select to End-of-Write 60 365 ns TAW Address Valid to End-of-Write 60 375 ns TAS Address Set-up Time 0 0 ns TWP Write Pulse Width 60 375 ns TWR Write Recovery Time 0 0 ns TWHZ Write to Output High-Z 30 80 ns TDW Data to Write Time Overlap 30 200 ns TDH Data Hold from Write Time 0 0 ns TOW End Write to Output Low-Z 0 15 ns T7.1 380

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 FIGURE 6: SRAM R EAD CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED ) (OE# = RAMCS# = VIL, WE# = VIH) FIGURE 7: SRAM R EAD CYCLE TIMING DIAGRAM (OE# OR RAMCS# C ONTROLLED ) TRC TAA Data Valid 380 ILL F04.0 Data Out Previous Data Valid Address TOH TRC TAA TOE TCO TLZ(2) TOH TOHZ(1) THZ (1,2) Data Valid 380 ILL F05.0 Data Out RAMCS# High-Z Address OE# Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL . 2. At any given temperature and voltage condition THZ (max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle. 4. Address valid prior to coincidence with RAMCS# transition low.

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 FIGURE 8: SRAM W RITE CYCLE TIMING DIAGRAM TABLE 8: F UNCTIONAL DESCRIPTION /TRUTH TABLE Address Inputs ROMCS# 1 1. If is forbidden for ROMCS# pin and RAMCS# pin to be “0” at the same time RAMCS# 1 WE# OE# DQ 0-DQ 7 XH H X 2 2. X means Don’t Care. X2 Z Standby A17-A0 LH X 2 H Z Output Floating A17-A0 LH X 2 L Dout ROM Read Only AMS 3-A0 are valid4 3. AMS = A16 for SST30VR021, A17 for SST30VR022, and A14 for SST30VR023 4. For SST30VR021: A17 must be fixed to “L” or “H ” For SST30VR023: A15, A16, and A17 must be fixed to “L” or “H ” H L H H Z Output Floating Only AMS 3-A0 are valid4 H L H L Dout RAM Read Only AMS 3-A0 are valid4 HL L H D i n R A M W r i t e T8.4 380 Notes: 1. A write occurs during the overlap (TWP ) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = V IH TWC TAW TCW(2) TOH TDHTDW TOW TWR(4) Data Valid 380 ILL F07.0 Data In Data Out WE# High-Z High-Z (6) (7) (8) Address RAMCS# TWP(1)TAS(3) TWHZ(5)

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 SST30VR021 Valid combinations SST30VR021-500-C-WH SST30VR021-500-C-U1 SST30VR021-500-E-WH SST30VR022 Valid combinations SST30VR022-70-C-WH SST30VR022-70-C-U1 SST30VR022-70-E-WH SST30VR023 Valid combinations SST30VR023-500-C-WH SST30VR023-500-C-U1 SST30VR023-500-E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. C-Spec Number Package Modifier H = 32 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm) U = Die only Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Read Access Speed 70 = 70 ns 500 = 500 ns Device Density 021 = 2 Mbit ROM + 1 Mbit SRAM 022 = 2 Mbit ROM + 2 Mbit SRAM 023 = 2 Mbit ROM + 256 Kbit SRAM Voltage Range V = 2.7-3.3V Device Family 30 = ROM/RAM Combo Device Speed Suffix1 Suffix2 SST30 V R023 -X X X -X -X X - RXXXX

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 PACKAGING DIAGRAMS 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the packa ge ends, and 0.25mm between leads. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 Pin # 1 Identifier 14.20 13.80 0.70 0.50

SST30VR021 / SST30VR022 / SST30VR023 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  T elephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.ssti.com