SMP402 POWERINT | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Integrated Power Switch and CMOS Controller
- Output power > 1 W from 48 VDC input
- Adjustable output voltage
- Integrated solution minimizes overall size High-voltage, Low-capacitance MOSFET Output
- Designed for ISDN T1 telecommunications applications
- Low capacitance allows for high frequency operation High-voltage Buck Regulator
- Internal pre-regulator self-powers the IC on start-up
- Designed for low power consumption
- Minimum external parts required Built-In Self-protection Circuits
- Undervoltage lockout
- Thermal shutdown
- Input polarity/level sense
Description
The SMP402, intended for non-isolated ISDN telecommunications power supply applications, combines a high voltage power MOSFET switch with a switchmode power system controller in a monolithic integrated circuit. Few external components are required to implement a low cost power supply which meets stringent ISDN specifications. High frequency operation reduces total power supply size. The P-channel power MOSFET switch features include high voltage, low R DS(ON) , and low capacitance. Lower capacitance results in a reduction in gate drive power, and also facilitates higher frequency operation. The controller section of the SMP402 contains all the blocks required to drive and control the power stage: start-up pre- regulator circuit, oscillator, bandgap reference, error amplifier, gate driver and level shift. Protection features include undervoltage lockout, thermal shutdown, and input polarity and level sensing. The SMP402 is available in a 16-pin plastic SOIC package. Figure 1. Typical Application.
ORDERING INFORMATION
SMP402SC S16A 0 to 120 °C PI-555A-123091
48 VDC
5 VDC
Figure 2. Pin Configuration.
Figure 3. Functional Block Diagram.
D SMP402 Pin Functional Description Pin 1: V IN is the high-voltage input to the switching regulator. This is the Source connection of the P-Channel power MOSFET pass transistor. Pin 2: V LS is an internal supply for the level shift circuit that drives the P-Channel MOSFET. A capacitor should be placed between V LS and VIN for bypassing. VLS is normally 10 V below VIN. Pin 3: The power supply can be shut down by pulling ENABLE low. Pin 4: D GND is the common return point for the power and logic portions of the circuit. Pin 5: A GND is the common return point. R EXT and CEXT are directly connected to this point. Pin 6: The SENSE+ input monitors the polarity and level of the input voltage through an external resistor for ISDN emergency standby sensing. Pin 7: The SENSE- input monitors the polarity and level of the input voltage through an external resistor for ISDN emergency standby sensing. Pin 8: A 20.5 kΩ resistor connected between R EXT and A GND sets the internal bias currents including oscillator charge and discharge currents. Pin 9: The oscillator frequency can be programmed by selecting the value of the capacitor connected between C EXT and A GND. Pin 10: V BIAS can be connected to the output 5 V rail of the converter to reduce power dissipation. The internal 5 V regulator is cut off when the output is in regulation. Pin 11: EA OUT is the error amplifier output pin for connection to the external compensation network. Pin 12: EA IN is the error amplifier negative input for connection to the feedback and compensation networks. Pin 13: V S is the internal supply voltage. This pin is brought out for external bypassing. Pin 14: The LEVEL output indicates when the input voltage is in its normal operating range. Pin 15: The POLARITY output is used to notify a microprocessor of an emergency standby condition for ISDN applications. Pin 16: OUT is the Drain connection of the P- Channel pass transistor. Functional Description High Voltage Regulator The high-voltage regulator provides the bias current required by the controller and driver circuitry. The pre-regulator consists of a high voltage MOSFET, a gate bias current source, and an error amplifier. The error amplifier regulates V S to approximately 5 V by controlling the gate of the MOSFET. In 5 V output applications, the control circuitry may also be operated by connecting the V BIAS pin to the output 5 V rail of the converter to reduce power dissipation. The internal 5 V regulator is cut off automatically when the converter output is in regulation. Only the supply current for the level shift stage (≈50 µA) and the AC switching currents for the P- Channel output device are drawn from the V IN supply under this condition. If unused, VBIAS must be hardwired to A GND to disable the automatic switchover during power-up. V LS is the level-shift supply for driving the gate of the internal P-channel MOSFET. The voltage at V LS is approximately 10 V below VIN. VS is the supply voltage for the controller and driver circuitry. External bypass capacitors connected to V LS and VS are required for filtering and reducing noise. UV Lockout During power-up, the undervoltage lockout circuit keeps the P-channel output transistor in the off state until the internal V S supply is in regulation and the voltage sensed by the input monitor circuit is within the normal operation range (>12 V). Band Gap Reference V REF is the 1.3 V reference voltage generated by the temperature- compensated bandgap reference and buffer. This voltage is used for setting thresholds for the error amplifier and over temperature circuit.
by switched constant current sources. by hysteresis built into a comparator. slopes of the sawtooth waveform. a function of input voltage and load. power supply output voltage to go up. causes the output voltage to go down. the hysteresis temperature level.
5 V OUT
32 V 30 V
Figure 4. Turn-on and Turn-off Waveforms of the SMP402.
high (maximum duty cycle) state. when the input voltage reaches -32 V. the input voltage has reversed polarity. and turns off at approximately -10 V. Figure 5. LEVEL/POLARITY Truth Table. The LEVEL and POLARITY signals are only valid when the output voltage is in regulation.
Figure 6. Schematic Diagram of a Non-isolated 5 V, 1 W ISDN Regulator Circuit Utilizing the SMP402. actually the DC load current. the self-bias feature of the SMP402.
D SMP402 105 100 02 0 4 0 6 0 8 0 Input Voltage (VDC) Output Voltage (% of Nominal) LINE REGULATION 101 PI-939A-031393 ILOAD = 200 mA 102 103 104 Load Current (mA) Output Voltage (% of Nominal) LOAD REGULATION PI-938-022293 105 100 0 100 200 300 400 500 102 VIN = 48 VDC 101 103 104 012 Load Power (W)
5 V Output Efficiency (%)
EFFICIENCY vs. OUTPUT POWER PI-950-022593 VIN = 24 VDC VIN = 48 VDC VIN = 72 VDC 02 0 4 0 6 0 8 0 Input Voltage (VDC) Output Efficiency (%) EFFICIENCY vs. INPUT VOLTAGE PI-944-022293 ILOAD = 200 mA The line and load regulation graphs were measured on the circuit shown in Figure 6. The switching frequency of the power supply was measured at 230 kHz. The maximum output power curve shows General Circuit Operation (cont.) 2.0 02 0 4 0 6 0 8 0 Input Voltage (VDC) Output Power (W) MAXIMUM OUTPUT POWER PI-940-022293 0.5 1.0 TA = 25°C 1.5 0 100 200 300 500 Switching Frequency (kHz) Output Power (W) OUTPUT POWER vs. FREQUENCY PI-951-022593 TA = 25°C 400 VIN = 48 VDC Typical Performance Characteristics (Figure 6 Power Supply) the power output capability for a 470 µH output filter inductor (L1). The output power versus frequency curve was generated by characterization of the SMP402 at various frequencies. The curve demonstrates the trade-off between AC and DC power losses within the device. As AC losses rise with frequency, DC losses and output power must be reduced to maintain the same device maximum power dissipation.
D Conditions (Unless Otherwise Specified) Parameter Symbol V IN = 48 V, VBIAS = 5 V, GNDs = 0 V Min Typ Max Units R EXT = 20.5 kΩ , CEXT = 120 pF R S+ , RS- = 1.2 MΩ , Tj = 0 to 120°C ABSOLUTE MAXIMUM RATINGS 1 C EXT = 30 to 300 pF See Note 2 50 500 200 230 260 0-50 0-70 1.22 1.32 0.5 60 80 f OSC ΔfOSC DC VREF AVOL VEA IN ZOUT PULSE WIDTH MODULATOR ERROR AMPLIFIER Output Frequency Initial Accuracy Duty Cycle Threshold Voltage Gain-Bandwidth Product DC Gain Common-mode Range Output Impedance kHz kHz V MHz dB V kΩ Thermal Impedance (θ 1. Unless noted, all voltages referenced to A GND, TA =25˚C 2. Normally limited by internal circuitry. 3. 1/16" from case for 5 seconds. 4. Measured at pin 4/5. V S + 0.3 V OSCILLATOR
D SMP402 VIH = 3.0 V VIL = 0 V IOH = -0.5 mA IOL = 0.5 mA Tj = 25°C IOUT = -100 mA Tj = 100°C VDS = 5 V T j = 25°C See Note 1 T j = 100°C 120 140 10 50 -500 -100 3.0 1.0 3.5 0.4 1.7 2.2 21 24 27 200 500 100 350 I IH IIL VIH VIL V OH VOL V SENSE+/- ILEVEL IPOLARITY R DS(ON) ID(ON) µA µA V V V V V µA µA Ω mA CIRCUIT PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis Input Current High Input Current Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Threshold Voltage LEVEL Threshold Current POLARITY Threshold Current ON-State Resistance ON-State Current LOGIC SENSE INPUTS OUTPUT Conditions (Unless Otherwise Specified) Parameter Symbol VIN = 48 V, VBIAS = 5 V, GNDs = 0 V Min Typ Max Units R EXT = 20.5 kΩ , CEXT = 120 pF R S+ , RS- = 1.2 MΩ , Tj = 0 to 120°C
- At low output currents (< 20 mA), the part may operate in blocking oscillation mode, resulting in large output ripple.
- Applying >3.5 V to the EA IN pin activates an internal test circuit that turns on the output switch continuously.
Figure 7. Switching Time Test Circuit.
48 VDC 16
D SMP402 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 Junction Temperature (°C) Breakdown Voltage (V) (Normalized to 25°C) BREAKDOWN vs. TEMPERATURE PI-176B-051391 3.0 40 60 80 Drain Voltage (V) Drain Charge (nC) DRAIN CHARGE vs. DRAIN VOLTAGE PI-942-022293 2.0 1.5 1.0 2.5 0.5 100 Drain Voltage (V) Drain Capacitance (pF) C OSS vs. DRAIN VOLTAGE PI-1008-051093 500 300 100 100 200 400 5000 External Capacitance (pF) PWM Frequency (kHz) fPWM vs. EXTERNAL CAPACITANCE PI-1011-051793 200 400 300 40 60 80 Drain Voltage (V) Energy (nJ) DRAIN CAPACITANCE ENERGY PI-941-022293
D 10 10 10 10 1 10 100 1000-1-2-3 0.1 100 PI-1012-051793 Time (s) Thermal Impedance (°C/W) TRANSIENT THERMAL IMPEDANCE PI-1013-052093 0 25 50 75 100 125 Case Temperature (°C) Power Dissipation (W) PACKAGE POWER DERATING Tj = 120°C PI-1846-050196 A L C DIM inches mm B .050 BSC 1.27 BSC B E F J 0-8˚ TYP. M N Notes: 1. Package dimensions conform to JEDEC specification MS-013-AA for standard small outline (SO) package, 16 leads, 7.50 mm (.300 inch) body width (issue A, June 1985). 2. Controlling dimensions are in mm. 3. Dimensions are for the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .15 mm (.006 inch) on any side. 4. Pin 1 side identified by chamfer on top edge of the package body or indent on Pin 1 end. (3) (3) S16A Plastic SO-16 (W)
D SMP402 NOTES
D NOTES
D SMP402 NOTES
D JAPAN Power Integrations, K.K. Keihin-Tatemono 1st Bldg. 12-20 Shin-Yokohama 2-Chome, Kohoku-ku, Yokohama-shi, Kanagawa 222 Japan ASIA & OCEANIA For Your Nearest Sales/Rep Office Please Contact Customer Service Phone: 408•523•9265 Fax: 408•523•9365 WORLD HEADQUARTERS Power Integrations, Inc. 477 N. Mathilda Avenue Sunnyvale, CA 94086 USA Main: 408•523•9200 Customer Service: Phone: 408•523•9265 Fax: 408•523•9365 AMERICAS For Your Nearest Sales/Rep Office Please Contact Customer Service Phone: 408•523•9265 Fax: 408•523•9365 Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc. ©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086 APPLICATIONS HOTLINE World Wide 408•523•9260 APPLICATIONS FAX Americas 408•523•9361 Europe/Africa Japan 81•(0)•45•471•3717 Asia/Oceania 408•523•9364 EUROPE & AFRICA Power Integrations (Europe) Ltd. Mountbatten House Fairacres Windsor SL4 4LE United Kingdom