SMP212

SMP212 POWERINT | Alldatasheet

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Pw Pow | = ) 85-265 VAC Input P POWER Isolated, Regulated DC Output INTEGRATIONS, INC. Product Highlights Integrated Power Switch and CMOS Controller * Output power up to 10 W from rectified 220 VAC input, ° bs 5

5 W from rectified universal (85 to 265 VAC) input ac por] De

+ External transformer provides isolated output voltages IN K% gut + Integrated solution minimizes overall size ° 4 oy | & x High-voltage, Low-capacitance MOSFET Output ERROR * Designed for 120/220 V off-line applications Vin RAIN AMP * Can also be used with DC inputs from 36 V to 400 V FAULT Veias| + Low capacitance allows for high frequency operation cw Rexts back 3 ¢ | " Rext- High-speed Voltage-mode PWM Controller cext ‘+ Internal pre-regulator self-powers the IC on start-up Ve EARN + Wide V,,,, Voltage range i OM mal + Designed for use with optocoupler feedback Built-In Self-protection Circuits [| + Adjustable cycle-by-cycle current limit, P1447 042606 + Latching shutdown can be used for output overvoltage Figure I. Typical Application protection + Shutdown/auto-restart cycling * Input undervoltage lockout + Thermal shutdown ee vi T DRAIN Description " ‘The SMP212, intended for 220 V or universal off-line isolated R, 4 17] power supply applications, combines a high voltage power EXTs Hs 16 2 MOSFET switch witha switchmode power system controllerin Rext-Lil le 15) || |COM a monolithic integrated circuit. Few external components are FAULT Co)7 we required to implement a small, low-cost, isolated, off-line Cg : ul Vous, Ac power supply. ent 0 hibece week The high-speed power MOSFET switch features include high ussoncesone voltage, low R,..,.y9-10w capacitance, and low threshold voltage. - - Low capacitance and low threshold voltage reduce gate drive Figure 2. Pin Configuration and bias power, allowing higher frequency operation, The controller section of the SMP212 contains all the BIOS | ep required to drive and control the power stage: off-line | 4) OB RERINGINFORMATION _| pre-regulator, oscillator, bandgap reference, error amplifier, ‘ORE fe Susana base een anh enlace weal gate driver, and circuit protection. This voltage-mode Pulse E Width Modulation control circuit is optimized for flyback voor rae R ANGE topologies, but may be used with other topologies as well. a SMP212SRI $208 -40 to 125°C ‘The SMP212 is available in a 20-pin batwing SOIC package. A I 10P200 FAMILY RECOMMENDED FOR NEW DESIGNS. mM 7289229 0001425 419 a

Figure 3. Functional Block Diagram of the SMP212.

Pin Functional Description Pin 1: Pin 8: Pin 12: High voltage V,, for connection to the C, is used to set the shutdown/auto- FEEDBACK is the error amplifier high voltage pre-regulator used to self-__restart cycle time. output for connection to the external power the device during start-up. compensation network. Pin 9: Pin 4: Connection for a bypass capacitor for Pin 13: A resistor placed between Ryx;, and the internally generated V, supply. Varas is the bootstrap voltage used to Rage, Sets the internal bias currents. self-power the device once the supply is Pin 10: operating. Pin 5, 6: Cygr i8 used to set the oscillator Ryxz. is the return for the reference _ frequency. Adding externalcapacitance Pin 14, 18, 16, 17: current. lowers the PWM frequency. ‘COM connections. Ground or reference point for the circuit. Pin 7: Pin 11: The FAULT pinis used with anexternal EA IN is the error amplifier inverting Pin 20: resistor to provide protection of the input for connection to the external Open DRAIN of the output MOSFET. output during overcurrent and feedback and compensation networks. overvoltage conditions. SMP212 Functional Description Bias Regulator Bandgap Reference Error Amplifier The onboard supply voltage (V,) is Veep i8 a 1.25 V reference voltage ‘The error amplifier consists of a high suppliedfromeitheroftwohigh-voltage generated by the temperature performance operational amplifier with linear regulators. The V,,linearregulator compensated bandgap reference, This the non-inverting input connected to the draws current from the high-voltagebus _reference voltage is used for setting _internal bandgap reference voltage. The while the V,,,; regulator draws current. _ thresholds for comparators, amplifiers, output of the error amplifier directly from a voltage generated from a and the thermal shutdown circuit. The controls the duty cycle of the power transformer winding. The V,, regulator _ external resistor connected between _ switch dissipates significant power levels and Ry, and R,,, and the bandgap f 2 should becutoffduringnormaloperation _ reference set the proper internal bias Pulse Width Modulator for improved efficiency. The V, error current levels for the various internal The pulse width modulator implements amplifier has a built-in preference for _ circuits. a voltage-mode control loop by driving generating V, from the V,,,, regulator, the power MOSFET with a duty cycle which automatically cuts off the V, Oscillator proportional to the voltage on the regulator during normal operation. ‘The oscillator linearly charges and FEEDBACK pin as shown in Figure 4. During start-up and under power supply discharges the combined internal and ‘The duty cycle signal is generated by a fault conditions, the bias error amplifier external capacitance between two comparator which compares the generates V, from the V,, regulator. different voltage levels to create a FEEDBACK voltage with the sawtooth sawtooth waveform for the pulse width waveform generated on the C,._ pin. As V, isthe supply voltage forthecontrotler modulator. Two digital signals, D,,,, __ the input voltage increases the duty cycle and drivercircuitry. Anexternal bypass and CLOCK are also generated. D,,, decreases. A clock signal from the capacitor connected to V, isrequiredfor corresponds to the rising portion of the _ oscillator sets a latch which turns on the filtering and noise immunity. The value sawtooth waveform, and is usedto gate. power MOSFET. The pulse width of V, also determines when the internal the MOSFET driver. A short CLOCK modulator resets the latch, turning off undervoltage lockout is enabled pulse is used to reset the pulse width the power MOSFET. The D,,,, signal Undervoltage lockout disables the power modulator and current limit latch at the from the oscillator limits the maximum MOSFET until V, is within its normal —_ beginning of each cycle. duty cycle by gating the output driver. operating range. Ez 2B @™ 7289229 0001427 291

SMP212 Functional Description (cont.) Fault Protection For latching output overvoltage off, the charging current source is The FAULT pin is used to implement protection, an external optocoupler can switched off, causing the discharging bothcycle-by-cycle MOSFET transistor be used to drive the FAULT pin above current source to slowly discharge the current limiting and latching output the FAULT OV threshold as shown in C, capacitor. When the lower threshold shutdown protection. Figure 5. A latch is set that tums off the is reached, the power suppy is turned power MOSFET switch. Cycling the back on, and the cycle begins again as The FAULT pin tums off the power undervoltage lockout circuit by shown in Figure 5. When the excessive MOSFET switch when an overcurrent removing and restoring input power is _load condition is removed, the output condition causes the voltage on this pin necessary to reset the latch and resume voltage becomes regulated again, the to drop below the FAULT current limit normal power supply operation. erroramplifier output voltage isreduced threshold, The DRAIN current is back into the linear range (1.2 to 2.4 V), converted to a voltage by an external Shutdown/Autorestart and the C, capacitor is quickly reset to senseresistor. An internal current source The shutdown/autorestart feature turns zero volts by an internal MOSFET applied to an external offset resistor the power supply on and off ata duty switch. biases the FAULT signal to a positive cycle of 20% if an overcurrent fault voltage when no DRAIN current is condition persists. An overcurrent fault The thermal shutdown and UV lockout. flowing. During an overcurrent condition causes the output voltage to circuits also reset the C, capacitor prior condition, current flowing in the sense _fall out of regulation, which then causes —_to turn-on so that the power supply will resistor will cause the FAULT voltage the internal error amplifier output to always start from a known state to decrease. When the FAULT voltage saturate at maximum output voltage. regardless of the fault or operating falls below the fault current limit The saturated high output voltage is condition. threshold for a time period exceeding detected by acomparator which switches the current limit delay, the power switch a charging current source on to the C, Overtemperature Protection willbe latched off until the beginningof pin. ‘The 50 HA switched-charging Temperature protection is provided by a the next clock cycle as shown in Figure current source is greater than the 10 #A precision analog circuit that turns the 4. If this condition persists over many _fixed-discharging current source which power switch off and reduces supply switching cycles, the output voltage will creates a net C, capacitor charge current current when the switch junction gets fall out of regulation, the output of the of 40 WA. The net current charges the too hot (typically 140°C). When the error amplifier (FEEDBACK) will external C, capacitor while the power circuit has cooled past the hysterisis saturate ina high state, andthe external _ supply isstilloperatingintotheexcessive __ temperature, normal operation resumes. C, autorestart capacitor capacitor will load condition. When the upperthreshold begin to charge. is reached, the power supply is turned General Circuit Operation ‘The flyback power supply circuit shown. resistor divider. winding is rectified and filtered by D2, in Figure 6 is a dual 5/12 V, 5 W power C2,C14, and LS to create the 5 V output supply that operates from 85 to 265 AC power is rectified and filtered by _voltage. ‘The effective 12 V winding is V(rms) AC input voltage. The 5 V BR1 and Cl to create the high voltage _created by stacking a7 V winding on top output voltage is directly sensed and DC bus applied to the primary winding —_of the 5 V winding. D6, C24, C26, and accurately regulated by a secondary- of transformer TI, The other side ofthe 6 perform rectification and filtering referenced error amplifier. The error transformer primary is driven by the _ for the 12 V output voltage. R31 and amplifier drives an error signal through integrated high voltage MOSFET C27 damp the secondary leakage ‘an optocoupler to the SMP212 which transistor withintheSMP212. Theclamp inductance ringing voltage caused by directly controls the duty cycle of the circuitimplemented by R10, C9, and DS the stored charge in diode D6. R22 integrated high voltage MOSFET switch. clamps the leading-edge voltage spike provides a slight pre-load on the 12 V ‘Theeffective output voltagecanbefine- caused by transformer leakage output to improve load regulation at tuned by adjusting the resistor divider inductance to a safe value. Ringing light loads. The bias winding is rectified formed by R18 and R29. Other output caused by parasitic capacitance and and filtered by D3 and C5 tocreateabias voltages are possible by adjusting the leakage inductance is damped by C15 voltage to the SMP212, which effectively transformer turns ratios as well as the and R9. The 5 V power secondary | 4 M@@ 7249229 0001428 126

5 W Universal Off-line Power Supply with Optocoupler Feedback

400 V| VO : 16

2 C13 39ka % VW

Figure 6. Schematic Diagram of a dual output 5 W Universal Input Power Supply Utilizing the SMP212.

General Circuit Operation (cont.) cuts off the high-voltage internal linear RIL. The offset voltage level at the frequency gain setting resistorR 18. Bias regulator. FAULT pin is determined by R2 and the current of 2 mA for U2 is provided by internal FAULT current source. C13 R19. The LED current in optocoupler Common-mode emissioncurrents which determines the auto-restart time interval. U3 is limited by R15. The collector of flow between the primary windings of the optocoupler output transistor is the transformer and the secondary output, The secondary-referenced error connected to V, of the SMP212. RS and circuitry are attenuated by C7, C8, C17, amplifier is implemented with a TL431 the effective capacitance of the C20, L2, and L4. Differential-mode shunt regulator (U2). This device optocoupler filter high-frequency emission currents caused by pulsating _ consists of an accurate 2.5 V bandgap _switching noise. 6 sets the DC bias currents at the input of the power supply _reference , error amplifier, and driver. current through the optocoupler to a are attenuated by C6 and L2. Voltage Theoutputvoltageissensed,dividedby maximum value of 1.25 mA. During spikes on the line are clamped by VR1. R18 and R29, and applied to the inverting normal operation, the voltage across RO Thermistor R20 limits initial surge input of the error amplifier. R21 provides is constant and equal to the internal currents at turn on to a safe value. limited sensing of the 12 V output to bandgap reference voltage. R24 improve cross regulation. The non- determines the DC and low frequency Internal bias currents are accurately set inverting input of the error amplifier is AC gain of the SMP212 error amplifier by R3. Bypass capacitor C3 filters internally connected to the bandgap and optocoupler circuit. C4 and R4 currentspikes on the internally generated reference voltage. The frequency provide additional compensation for the voltage source V,. The oscillator response of the error amplifier is control loop as well as additional noise frequency is determined by C11. determined by the compensation network filtering. Transistor switch current is sensed by consisting of R30, C22, and the high ‘The overload shutdown/automaticrestart Typical Performance Characteristics (Figure 6 Power Supply) LINE REGULATION LOAD REGULATION MAXIMUM OUTPUT POWER. 108 tos a t =e (ELL TT] gS Vins feeupo] § =| 2B CEepeperepeped BS [SN evo sonna i at 3 2 6 | oo 71007 PRIMARY E io #& %o 02 04 06 08 +E. i As =

8 Boo Load Current (A) Lt =r

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yw ae seo oa 08 12 182 ow 900 300 800 Input Voltage (VDC) Load Current (A) Input Voltage (VDC) EFFICIENCY vs. INPUT VOLTAGE EFFICIENCY vs. OUTPUT POWER OUTPUT POWER vs. FREQUENCY ieee | Pees!” PNCERI : TTT H =z 9% = 90 pe \\ Pe Cobh Fw HCE bo | Ne be Cone Pecttaaceee] ] Z i TASS Fi A r t é CI] 2 _ | 2 I $ D g T= eVobr 600 ma, a or | ° © 6 t— 12VOUT = 50 mA o [7 TT a VON, J's Vouk ev Out may Lr 0 CLI 12 VOUT = 380 ma| 0 Lib--++12 Vout. VOUT « 100 ma) o © 100 20000400 o 2 4 6 8 0 er Input Voltage (VDC) Load Power (W) ‘Switching Frequency (kHz) Ez rq ..| mm 7289229 0001431 712 a

General Circuit Operation (cont.) timing function is activated when ever overvoltage exceeds the specified Thelineandload regulation graphs were the output voltage is out of regulation. voltage of Zener diode VR4, R28 limits measured when operated from a DC C, and current sources internal to the IC photodiode current to a safe value. source. The switching frequency of the set the time delays. The C, capacitor is power supply was measured at 125 kHz. normally heldlow. C,ischargedtoward —-Toreduce device power dissipation and the shutdown threshold whenever the temperature rise during normal Themaximumoutputpowercurveshows output of the intemal error amplifier is operation, the voltage applied to Vax. the power output capability for the saturated in the maximum duty cycle must be greater than the minimum —_normaltransformer, andthe performance state. The internal error amplifier is specified value to ensure complete cutoff with twice and half the normal number saturated whenever the circuit is in _ of the high-voltage linear regulator. _of primary turns. current limit, which occurs at turn-on Ensure that the maximum specified and overload conditions voltage on the V,,,,pin is notexceeded The outputpower versus frequency curve when adjusting the value of the output was generated by characterization of the During an overload, the auto-restart —_voltage. SMP212at various frequencies. Several feature tums the power supply on and different power transformers, optimized off at a typical duty cycle of 20% to The peak current limit circuit will turn foreach frequency, were used to generate reduce the effective power delivered to _offthe MOSFET switch whenthe voltage the maximum power at each point. The the output rectifier. acrossR11isapproximately equal tothe curves illustrate the trade-off between voltage across R2. AC and DC power losses within the Optocoupler U4 drives the FAULT pin device. As AC losses rise with frequency, high and latches the power supply offif Performance data is shown on the DC losses and output power must be ‘an output overvoltage condition exists, _ previous page for the circuit given in reduced to maintain the same device Optocoupler U4 willturnoniftheoutput Figure 6. maximum power dissipation, me 4 Mm 7289229 0001432 659

Drain Voltage ...romsnnnnnennnnemnnneneemaeee800V Thermal Impedance (8,,) senrnsnrnnnnnrnnen 30°C/W Voy Voltage nsnnnnnmnninnnneninnnnnnnnennnnee 500 V ‘Thermal Impedance (0,-)!.rssiinsntenenees OCIW Voias Voltage cccrnnninnnnsnmnnnnnnnannsnnanenn 3S Drain Current... 800 MA, 1. Unless noted, all voltages referenced to COM, T, = 25°C Input Voltage”) .niinnnnnnnennnnnO3VtOV,+03V 2. 300 ps, 2% duty cycle. Storage Temperature ...rnnnnnnnnnnnnnnn “6510 125°C 3, Does not apply to V,, or DRAIN. Lead Temperature’ .ionnsnnnnnnnnrimannnnnnnnnn 260°C 5, 1/16" from case for 5 seconds. Power Dissipation (T= 25°C) .orcnrmmnnnnnnnne3.33 W 6, Measured at pin 15/16. (Dy = 70°C) -srnntnnsernrrerne 183 W Conditions (Unless Otherwise Specified) Parameter Viy = 325 V, Veins = 8:5 V, COM = 0 V Typ R=20.5 kQ, C,=560 nF, C,,,=100 pF T, = -40 to 125°C (See Note 1) Output Ler mem Tm Duty oyce rs es Range es ee FAULT Offset Current HA FAULT OV FAULT Current v Vv Limit Threshold ‘unr n Current Limit i Delay Time See Figure 7 75 Thermal Shutdown’ « Temperature 125 c Thermal Shutdown °c Hysteresis. W@® 7289229 0001433 595 a

(Unless Otherwise Specified) Parameter Vyy = 325 V, Vays = 8.5 V, COM =0V Typ R12 20.5 kQ, C,=560 nF, C.,.=100 pF} T, = -40 to 125°C (See Note 1) Re Duty Auto-Restart | Hz Frequency | Upper Threshold Voltage Vi fF Pole) |e | Lower Threshold Voltage pm fo | Poel Reference Voltage pw | Reference Voltage Temperature ort fame | | [| | Gain-Bandwidth Dc Output [| wepezav Te [| Output tence | me | | foie] ON-State a ee ee Gurent= Hate] Lm M@ 7289229 OOOL434 42L

(Unless Otherwise Specified) Parameter Vyy = 325 V, Vous = 8.5 V, COM = 0 V Typ | Max Re,=20.5 k®, C,=560 nF, C,,.=100 pF T, = ~40 to 125°C (See Note 1) OFF-State Current Voran = 640 V, T, = 125°C HA Breakdown Voltage BV a5 \\nan = 250 HA, T, = 25°C 800 Vv Output Capacitance Coss Vena = 25 V, f= 1 MHz pF Output Stored Energy Foss Vonan = 400 V 700 | nJ Pre-regulator Voltage Viw 86 v i [Vaya notconnected fT as | Offline Supply ly Vag > 825V a i Thermal Shutdown ON [2 Vallage jx | [=| V,, Source | Voltage Vs | v NOTES: 1. Applying >3.5 V to the C,,,, pin activates an internal test circuit that turns on the output switch continuously. Destruction of the part can occur if the output of the SMP212 is connected to a high voltage power source when the test circuit is activated. z rf. Mm 7269229 0001435 366

BREAKDOWN vs. TEMPERATURE fpwm vs. EXTERNAL CAPACITANCE 800 " Fy T Th [TT TT TTT Eg pra | TT} Maape aces Ge M\\eaueuee geese Pe ACE] Ss A s \\ @ bzeoereeh gg PNCeep PERE SH oo LI oe Junction Temperature (°C) External Capacitance (pF) Coss vs. DRAIN VOLTAGE DRAIN CHARGE vs. DRAIN VOLTAGE 100, 8 Po} TT} gf Lt oe fhe g* TT 2 7 a sero e Loe

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<< | AF ecaaeenen ao oO 80 160, 240 320 400 oO 100 200 300 400 Drain Voltage (V) Drain Current (mA) MM 7289229 0001437 130

PACKAGE POWER DERATING TRANSIENT THERMAL IMPEDANCE "Tae ° SSS == : g Pl

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A 460-480 11.68-12.19 J c | 236-260 | 5.99-6.60 a is wire D | .240-REF. | 6.10-REF. 4 O iz | E | 520-560 | 19.21-14.22 A ¢ 4a 1 orackage dimension conform to F 028-038 71-97 1 One JEDEC sogclcation T0220 AB tor G | .045.055 | 1.14-1.40 | ieae package, 100 nch lend spacing Plate) leas (lve J, Maren 19 H | 090-110 | 229-279 4 S Conoting mension are inches J | 165-185 4.19-4,70 N cemustenteationgesne, K -045-.055 1.14-1.40 ' ‘iewad from the top. do motiestude L | 095-115 241-292 T Lh mold fash or thr protons, Mola ah or pretaaione shal nc ec 705-. 91-18. measured at postion 25,65 ° 146-156 3.71-3.96 ' E 4+ Tomine body “ " p | sos112 | 262287 il Aer ar sole ont FI Moelle G Pisece00000e psa SS Pinstie Dine Paes ee ea eg 8 5 395 MAX 10.03 MAX 090-110 2.29-2.79 015-021 0.38-0.53 caotye | 1.02 TYP 015-030 | 0.38-0.76 Notes 25MIN | 3.18 MIN o15MiN | 0.38 MIN 125-135 3.18-3.43 300-320 | 7.62-8.13 7 a 245-255 6.22-6.48 AG an | om [a Notes: | ® 5 1} Package dimensions conform to JEDEC fe TT yt pecteation MG-001-AB for standard Gua i 4 (Peasme) sags (saue BS) VE OO 2 Controlling dimensions: Inches. [LY 5. Dimensions are forthe molded body ano ‘otinclage mold tah or other protrusions. Noid aah or protrusions shal not exceed O10 F Inch (.25 mm) on any side. 6 {2 These dimensions measured with the leads ons" Constrained tobe perpendiouar fo package - , ee eee owl i 5. Pin 1 orientation identified by end noteh or c B ~ dt acjecentto Pi Pr 1ace oso108 E : oe 5-1 mm 7289229 0001810 61) a

a | zeomax | 19.01 max B | 090.110 | 2292.79 c | o1s021 | 38-53 pd | .osotyp | 1.02TYP e | 015030 | 38.76 F | a26min | stein | news @ | osmin | samin | J | 300-320 | 7.628:13 a J K | 245-255 | 6226.48 © @ L | 009-015 23-38 o a 1 pactage dimensions conform to JEDEC Speciation M&-001-a for standard dal tine Seniesa eee aan ARATE ia {lente (ve 8, 7198). Except for Joning of Pins Seandbine 1212 y 2° convoling dimension: ches. & Bimenclons me fore molded boty and do nt + ates ee ith ‘ “ erosions ea Oo inch (2 mn) on ~af ‘ ny sam Jee MA OY

1 Tins ienslons maaaured with th ede wllee s

‘onsained tobe perpendicular o package boton. Sint ortntaton enti by end notch or dot el lee alacant toPin neucznse 1844.0 A | 0199-0.197 | 4.80.00 B | oosotye | 1.27TvP ¢ | 00140019 | 035-049 D | oorztye | ost TvP 3 F | 00040010 | 0.10-0.28 7 7 (3) 5 | _—— : ots:

1 Package dimensions conform to JEDEC

tecticalon M012. for starcrd ema cS {itolncy body meth Oreos dune 905), | £ Conreing dimensions aren en. TSaeSasin « Bimensions are for healed body "1 ipemrceae Mon 6 4 Pvt ai Roh erpeaone L+H} . it Sra not exceed 1S mm (005 IneN) on any py gel J E ry i sic 8 1 Fin side dented edge by cameron . ign tae bart art ont c: F Al ake os’ TYP. Pise48080196 ne - 52 i @@ 72869229 0001811 554

saat et = 16 3 ooogggqq A | 398.413 | 10.10-10.50 RRAHAHHHE B | .o50BSC | 1.27BSC i c 014-018 0.36-0.46 J 394-418 10.01-10.62, L 009-012 0.23-0.32 M 020-040 0,51-1.02, Nn | 291-209 | 7.40-7.60 (8 HHAAAGE Notes: \\! (3) : 1 package mensions contrm to JEDEC pA Speciation Meats aktor sanded sal ouline (Eo) package, 1 lade, 130 mm (200 nc) body width (Issue A, June 1985). 4

2 Contraing dimensions are nm,

3 Dimenclons ne torte aided nod and o not —

include mold tas or protusions. Hold fash or _—_—_—a ee | Provusione thalipotonceed.ismmcooinayon freee | Ry, Piaomeneeme = UTA ty 4 the package ody orindant on Pi ona IL ry a | c 8 F il L 0-8 TYP, M Prsmteasoiee — = oa 20 W716 18 14 ” q — 496-512 12,60-13.00 i | A i 4 .050 BSC 1.27 BSC 394-419 | 10.00-10.65 291-299 7.40-7.60 a HEIEPEHEY H HES HHO 7 ase ° Notes: Fo) Souatietion WS O10-AC for sander sal inch) body width (issue A, June 1985), Except J torfining ot ine and Pine 19-18. 2" Eowating drecatans arin. ———

2 Serine afr tnlndonty andy —\\

Notinclide med fash or pratnsione: aid | Et re 1 fast or porusone shalt exceed 13 mm tana panns sat ess (IFA ao mi f.'Pin side dented by charter on top edge ‘ 4 ‘the package body ot aceon inten c ols t oo TYP, M so4ra80106 gE : Bee 5-3 MM 7269229 0001612 494 om

INTEGRATIONS, INC. Power Integrations, Inc. makes selected surface-mount parts SSE yee ta available in tape and reel form for use with automatic pick-and- PACKAGE Ld REL PEEL place equipment. Tape and reel specifications meet or exceed Soo }WADTH (W) | PrrcH (Pp) | DIA” Boule

Ordering Information

sore] sem | 2mm _[oeonn] 100 Parts available in tape and reel form can be ordered by placing Cat oer sus atte bas patente. Sune [9020 | 24mm | 12mm [asonen| 100 | orientations Pin | Left. The ordering suffix for this orientation (see Figure 1) is TL. For example: Table 1. Primary Tape & Reel Dimensions and Reel Quantities. Base Part # T&R Suffix INT100S TL Please contact the factory for other options. Minimum order size is 1 reel per line item, and all orders will be in multiples of fall reel quantities. The quantity per reel for each package type User Direction of Feed is shown in Table 1. Power Integrations normal terms and conditions apply. Electrical Specifications Parts are subjected to the Power Integrations standard test flow, after which the parts are loaded into the tape cavities and sealed Oo with acover tape using standard anti-static handling procedures. — The tape and cover are constructed of conductive modified polystyrene, providing a surface resistivity of $10° O/square. ‘The reel is made of polystyrene with a topical anti-static coating, providing a surface resistivity of $10" Q/square. SELLS | TL fe) Physical Specifications SUFFIX — Physical specifications of the tape, cover, and reel are governed | - by EIA-481. Physical dimensions of the tapes are given in Figure 2 and Table 2, and physical dimensions of the reels are — | given in Figure 3 and Table 3. 5 | Packaging for Shipment [e) Power Integrations supplies the following information on the side of each reel for ease of product identification: + Power Integrations part number (MPN), including —= orientation suffix Oo + Encapsulation date code (D/C) + Assembly lot identification (LOT) Prr7e4-0c0806 * Quantity (QTY) ce a « Tape and reel packing date code (R/D) Figure 1. Part Orientation and Ordering Suffix. z z= WM 7289229 0001813 320

1 P| F |

Figure 2. Tape Dimension Index. Table 2. Tape Dimensions (in mms)

Figure 3. Reel Dimension Indes. Table 3. Reel Dimensions (in mm).