Memory

SMJ44C251B-12SVM

Austin Semiconductor

256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM

Manufacturer: Austin Semiconductor

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Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

FEATURES

Class B High-Reliability Processing
DRAM: 262144 Words × 4 Bits SAM: 512 Words × 4 Bits
Single 5-V Power Supply (±10% Tolerance)
Dual Port Accessibility–Simultaneous and Asynchronous Access From the DRAM and SAM Ports
Bidirectional-Data-Transfer Function Between the DRAM and the Serial-Data Register
4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many as Four Memory Address Locations Written per Cycle From an On-Chip Color Register
Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design
Enhanced Page-Mode Operation for Faster Access
CAS-Before-RAS (CBR) and Hidden Refresh Modes
All Inputs/Outputs and Clocks Are TTL Compatible
Long Refresh Period: Every 8 ms (Max)
Up to 33-MHz Uninterrupted Serial-Data Streams
3-State Serial I/Os Allow Easy Multiplexing of Video-Data Streams
512 Selectable Serial-Register Starting
Split Serial-Data Register for Simplified Real-Time Register Reload OPTIONS MARKING
Timing 100ns, 30ns/27ns -10 120ns, 35ns/35ns -12
Package(s) MT Prefix SMJ Prefix Ceramic SOJ DCJ --- Ceramic DIP (400 mil) C JDM Ceramic LCC EC HMM Ceramic Flat Pack F --- Ceramic ZIP CZ SVM Ceramic LCC --- HJM PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
SMD 5962-89497
MIL-STD-883 28-Pin DIP (C) (400 MIL) 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM For more products and information please visit our web site at www.austinsemiconductor.com 28-Pin SOJ (DCJ) 28-Pin LCC (EC) 28-Pin ZIP (CZ) DSF DQ3 SDQ2 Vss SDQ0 TRG\\ DQ1 GND Vcc QSF DQ2 SE\\ SDQ3 SC SDQ1 DQ0 RAS\\ CAS\\ SC SDQ1 SDQ2 TR\\/OE\\ DQ1 DQ2 ME\\/WE\\ NC RAS\\ Vcc Vss SDQ4 SDQ3 SE\\ DQ4 DQ3 DSF CAS\\ QSF SC SDQ1 SDQ2 TR\\/OE\\ DQ1 DQ2 ME\\/WE\\ NC RAS\\ Vcc Vss SDQ4 SDQ3 SE\\ DQ4 DQ3 DSF CAS\\ QSF 28-Pin FP (F) SC SDQ1 SDQ2 TR\\/OE\\ DQ1 DQ2 ME\\/WE\\ NC RAS\\ Vcc Vss SDQ4 SDQ3 SE\\ DQ4 DQ3 DSF CAS\\ QSF PIN NAME (SMJ) PIN NAME (MT) DESCRIPTION A0 - A8 A0 - A8 Address Inputs CAS\\ CAS\\ Column Enable DQ0 - DQ3 DQ1 - DQ4 DRAM Data In-Out/Write-Mask Bit SE\\ SE\\ Serial Enable RAS\\ RAS\\ Row Enable SC SC Serial Data Clock SDQ0 - SDQ3 SDQ1 - SDQ4 Serial Data In-Out TRG\\ TR\\ /OE\\ Transfer Register/Q Output Enable W\\ ME\\ /WE\\ Write-Mask Select/Write Enable DSF DSF Special Function Select QSF QSF Split-Register Activity Status Vcc Vcc 5V Supply Vss Vss Ground GND NC Ground (Important: Not Connected to internal Vss, Pin should be left open or tied to ground.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

DESCRIPTION

The SMJ44C251B/MT42C4256 multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic random-access memory (DRAM) organized as 262144 words of 4 bits each interfaced to a serial-data register or serial- access memory (SAM) organized as 512 words of 4 bits each. The SMJ44C251B/MT42C4256 supports three types of operation: random access to and from the DRAM, serial access to and from the serial register, and bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer operations, the SMJ44C251B/MT42C4256 can be accessed simultaneously and asynchronously from the DRAM and SAM ports. During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial data register. The 512 × 4-bit serial-data register can be loaded from the memory row (transfer read), or the contents of the 512 × 4-bit serial-data register can be written to the memory row (transfer write). The SMJ44C251B/MT42C4256 is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can be achieved by the device’s 4 × 4 block-write mode. The block- write mode allows four bits of data (present in an on-chip color- data register) to be written to any combination of four adjacent column-address locations. As many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a write mask or a write-per-bit feature allows mask- ing any combination of the four input/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles. The mask register eliminates having to provide mask data on every mask-write cycle. The SMJ44C251B/MT42C4256 offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port). This feature enables real-time register reload implementation for truly continuous serial data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register reload (for example, reloads done during CRT retrace periods), the single-register mode of operation is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an external device. Once the serial register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any row in memory in a single memory cycle. The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the split-register mode. All inputs, outputs, and clock signals on the SMJ44C251B/ MT42C4256 are compatible with Series 54 TTL devices. All ad- dress lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility. Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup, row-address hold, and address multiplex is eliminated, and a memory cycle time reduction of up to 3× can be achieved, compared to minimum RAS cycle times. The maximum number of columns that can be accessed is determined by the maximum RAS low time and page-mode cycle time used. The SMJ44C251B/MT42C4256 allows a full page (512 cycles) of information to be accessed in read, write, or read-modify-write mode during a single RAS-low period using relatively conser- vative page-mode cycle times. The SMJ44C251B/MT42C4256 employs state-of-the-art technology for very high performance combined with improved reliability.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FUNCTIONAL BLOCK DIAGRAM

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FUNCTION TABLE CAS\\ FALL CAS\\ TRG\\ W\\1 DSF SE\\ DSF RAS\\ CAS\\ RAS\\ CAS\\2 CBR Refresh L XXXXX X X XXR Register-to-memory transfer (transfer write) HLLXLX Row Addr Tap Point XXT Alternate transfer write (independent of SE\\) HLLHXX Row Addr Tap Point XXT Serial-write-mode enable (pseudo-transfer write) HLLLH X Refresh Addr Tap Point XXT Memory-to-register transfer (transfer read) HLHLXX Row Addr Tap Point XXT Split-register-transfer read (must reload tap) HLHHXX Row Addr Tap Point XXT Load and use write mask, Write data to DRAM HLLLXL Row Addr Col Addr DQ Mask Valid Data R Load and use write mask, Block write to DRAM HHL LXH Row Addr Blk Addr A2-A8 DQ Mask Col Mask R Persistent write-per-bit, Write data to DRAM HHLHXL Row Addr Col Addr X Valid Data R Persistent write-per-bit, Block write to DRAM HHLHXH Row Addr Blk Addr A2-A8 X Col Mask R Normal DRAM read/write (nonmasked) HHHLXL Row Addr Col Addr X Valid Data R Block write to DRAM (nonmasked) HHHLXH Row Addr Blk Addr A2-A8 X Col Mask R Load write mask HHHHXL Refresh Addr XX DQ Mask R Load color register HHHHXH Refresh Addr XX Color Data R RAS\\ FALL FUNCTION ADDRESS TYPE3 DQ0 - DQ3 NOTES: 1. In persistent write-per-bit function, W\\ must be high during the refresh cycle. 2. DQ0 - DQ3 are latched on the later of W\\ or CAS\\ falling edge. Col Mask = H: Write to address/column location enabled. DQ Mask = H: Write to I/O enabled. 3. R = random access operation, T = transfer operation. LEGEND H = HIGH L = LOW X = Don’t Care

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. DETAILED SIGNAL DESCRIPTION VS. OPERATIONAL MODE PIN DRAM TRANSFER SAM A0 - A8 Row, column address Row, tap address CAS\\ Column enable, output enable Tap-address strobe DQi DRAM data I/O, write mask bits DSF Block-write enable Persistent write-per-bit enable Color-register load enable Split-register enable Alternative write-transfer enable RAS\\ Row enable Row enable SE\\ Serial-in mode enable Serial enable SC Serial clock SDQ Serial-data I/O TRG\\ Q output enable Transfer enable W\\ Write enable, write-per-bit select Transfer-write enable QSF Split register Active status NC/GND Make no external connection or tie to system Vss Vcc 5V supply (typical) Vss Device ground OPERATION Depending on the type of operation chosen, the signals of the SMJ44C251B/MT42C4256 perform different functions. The “Detailed Signal Description vs. Operational Mode” table summarizes the signal descriptions and the operational modes they control. The SMJ44C251B/MT42C4256 has three kinds of operations: random-access operations typical of a DRAM, transfer operations from memory arrays to the SAM, and serial- access operations through the SAM port. The signals used to control these operations are described here, followed by discussions of the operations themselves. ADDRESS (A0–A8) For DRAM operation, 18 address bits are required to decode one of the 262144 storage cell locations. Nine row- address bits are set up on A0–A8 and latched onto the chip on the falling edge of RAS\\. Nine column-address bits are set up on A0–A8 and latched onto the chip on the falling edge of CAS\\. All addresses must be stable on or before the falling edges of RAS\\ and CAS\\. During the transfer operation, the states of A0–A8 are latched on the falling edge of RAS\\ to select one of the 512 rows where the transfer occurs. To select one of 512 tap points (starting positions) for the serial-data input or output, the appropriate 9-bit column address (A0–A8) must be valid when CAS\\ falls. ROW-ADDRESS STROBE (RAS\\) RAS\\ is similar to a chip enable because all DRAM cycles and transfer cycles are initiated by the falling edge of RAS\\. RAS\\ is a control input that latches the states of row address, W\\, TRG\\, SE\\, CAS\\, and DSF onto the chip to invoke DRAM and transfer functions. COLUMN-ADDRESS STROBE (CAS\\) CAS\\ is a control input that latches the states of column address and DSF to control DRAM and transfer functions. When CAS\\ is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output. CAS\\ also acts as an output enable for the DRAM outputs DQ0–DQ3. OUTPUT ENABLE/TRANSFER SELECT (TRG\\) TRG\\ selects either DRAM or transfer operation as RAS\\ falls. For DRAM operation, TRG\\ must be held high as RAS\\ falls. During DRAM operation, TRG\\ functions as an output enable for the DRAM outputs DQ0–DQ3. For transfer operation, TRG\\ must be brought low before RAS\\ falls. WRITE-MASK SELECT, WRITE ENABLE (W\\) In DRAM operation, W\\ enables data to be written to the DRAM. W\\ is also used to select the DRAM write-per-bit mode. Holding W\\ low on the falling edge of RAS\\ invokes the write- per-bit operation. The SMJ44C251B/MT42C4256 supports both the normal write-per-bit mode and the persistent write-per-bit mode. CONTINUED

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. WRITE-MASK SELECT, WRITE ENABLE (W\\) (continued) For transfer operation, W\\ selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation (SAM to DRAM). During a transfer cycle, if W is high when RAS\\ falls, a read transfer occurs; if W is low, a write transfer occurs. SPECIAL FUNCTION SELECT (DSF) DSF is latched on the falling edge of RAS\\ or CAS\\, similar to an address. DSF determines which of the following functions are invoked on a particular cycle:

Persistent write-per-bit
Block write
Split-register transfer read
Mask-register load for the persistent write-per-bit mode
Color-register load for the block-write mode DRAM DATA I/O, WRITE-MASK DATA (DQ0–DQ3) DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W\\ is brought low prior to CAS\\ and the data is strobed in by CAS\\ with data setup and hold times referenced to this signal. In a delayed- write or read-modify-write cycle, W\\ is brought low after CAS\\ and the data is strobed in by W\\ with data setup and hold times referenced to this signal. The 3-state DQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state as long as CAS\\ and TRG\\ are held high. Data does not appear at the outputs until both CAS\\ and TRG\\ are brought low. Once the outputs are valid, they remain valid while CAS\\ and TRG\\ are low. CAS\\ or TRG\\ going high returns the outputs to the high-impedance state. In a register-transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. The write-per-bit mask is latched into the device via the random DQ terminals by the falling edge of RAS\\. This mask selects which of the four random I/Os are written. SERIAL DATA I/O (SDQ0–SDQ3) Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in serial-output mode. While in serial-output mode, data in SAM is accessed from the least significant bit to the most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be accessed are 00, 01, 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the data register is in serial-input mode and signal data can be input to the register. SERIAL CLOCK (SC) Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B/MT42C4256 is designed to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency. SERIAL ENABLE (SE\\) During serial-access operations SE\\ is used as an enable/ disable for SDQ in both the input and output modes. If SE\\ is held as RAS\\ falls during a write-transfer cycle, a pseudo- transfer write occurs. There is no actual transfer, but the data register switches from the output mode to the input mode. NO CONNECT/GROUND (NC/GND) NC/GND is reserved for the manufacturer’s test operation. It is an input and should be tied to system ground or left floating for proper device operation. SPECIAL FUNCTION OUTPUT (QSF) During split-register operation the QSF output indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of SAM. When QSF is high, the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. QSF changes state upon crossing the boundary between the two SAM halves in the split-register mode. During normal transfer operations QSF changes state upon completing a transfer cycle. This state is determined by the tap point being loaded during the transfer cycle. POWER UP To achieve proper device operation, an initial pause of 200ms is required after power-up, followed by a minimum of eight RAS\\ cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. RANDOM-ACCESS-OPERATION FUNCTIONS CAS\\ FALL CAS\\ TRG\\ W\\1 DSF SE\\ DSF RAS\\ CAS\\ RAS\\ CAS\\2 CBR Refresh L XXXXX X X XX Load and use write mask, Write data to DRAM HHL LXL Row Addr Col Addr DQ Mask Valid Data Load and use write mask, Block write to DRAM HHL LXH Row Addr Blk Addr A2-A8 DQ Mask Col Mask Persistent write-per-bit, Write data to DRAM HHLHXL Row Addr Col Addr X Valid Data Persistent write-per-bit, Block write to DRAM HHLHXH Row Addr Blk Addr A2-A8 X Col Mask Normal DRAM read/write (nonmasked) HHHLXL Row Addr Col Addr X Valid Data Block write to DRAM (nonmasked) HHHLXH Row Addr Blk Addr A2-A8 X Col Mask Load write mask HHHHXL Refresh Addr XX DQ Mask Load color register HHHHXH Refresh Addr XX Color Data RAS\\ FALL FUNCTION ADDRESS DQ0 - DQ3 NOTES: 1. In persistent write-per-bit function, W must be high during the refresh cycle. 2. DQ0–DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled. DQ Mask = H: Write to I/O enabled LEGEND: H = High L = Low X = Don’t care RANDOM-ACCESS OPERATION The random-access operation functions are summarized in the “Random-Access-Operation Function” table and described in the following sections. ENHANCED PAGE-MODE Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row address setup-and-hold and address multiplex. The maximum RAS\\ low time and the CAS\\ page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B/MT42C4256 to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS\\ transitions low. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in ad- vance of the falling edge of CAS\\. In this case, data can be obtained after t a(C) max (access time from CAS low), if ta(CA) max (access time from column address) has been satisfied. REFRESH There are three types of refresh available on the SMJ44C251B/MT42C4256: RAS\\-only refresh, CBR refresh, and hidden refresh. RAS\\-ONLY REFRESH A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS\\ is applied, the output buffers are in the high-impedance state, so the RAS\\- only refresh sequence avoids any output during refresh. Exter- nally generated addresses must be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes (continued)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. RAS\\-ONLY REFRESH (continued) all bits in each row to be refreshed. CAS\\ can remain high (inactive) for this refresh sequence to conserve power. CAS\\-BEFORE-RAS\\ (CBR) REFRESH CBR refresh is accomplished by bringing CAS\\ low earlier than RAS\\. The external row address is ignored and the refresh row address is generated internally when using CBR refresh. Other cycles can be performed in between CBR cycles without disturbing the internal address generation. HIDDEN REFRESH A hidden refresh is accomplished by holding CAS\\ low in the DRAM-read cycle and cycling RAS\\. The output data of the DRAM-read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh. WRITE-PER-BIT The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1). The write-per-bit operation is invoked only when W\\ is held low on the falling edge of RAS\\. If W\\ is held high on the falling edge of RAS\\, write-per-bit is not enabled and the write operation is performed to all four DQs. The SMJ44C251B/ MT42C4256 offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent write-per-bit mode. NONPERSISTENT WRITE-PER-BIT When DSF is low on the falling edge of RAS\\, the write mask is reloaded. A 4-bit code (the write-per-bit mask) is input to the device via the random DQ terminals and latched on the falling edge of RAS\\. The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS\\ has latched the on-chip write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS\\ or W\\. When a data low is strobed into a particular I/O on the falling edge of RAS\\, data is not written to that I/O. When a data high is strobed into a particular I/O on the falling edge of RAS\\, data is written to that I/O. PERSISTENT WRITE-PER-BIT When DSF is high on the falling edge of RAS\\, the write- per-bit mask is not reloaded: it retains the value stored during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because the write-per-bit mask is persistent over an arbitrary number of write cycles. The write- per-bit mask reload can be done during the nonpersistent write- per-bit cycle or by the mask-register-load cycle. BLOCK WRITE The block-write mode allows data (present in an on-chip color register) to be written into four consecutive column-address locations. The 4-bit color register is loaded by the color-register-load cycle. Both write-per-bit modes can be applied in the block-write cycle. The block-write mode also offers the 4 × 4 column-mask capability. LOAD COLOR REGISTER The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high on the falling edges of RAS\\ and CAS\\. A 4-bit code is input to the color register via the random I/O terminals and latched on the later of the falling edge of CAS\\ or W\\. After the color register is loaded, it retains data until power is lost or until another load- color-register cycle is executed. BLOCK WRITE CYCLE After the color register is loaded, the block-write cycle can begin as a normal DRAM write cycle with DSF held high on the falling edge of CAS\\ (see Figures 2, 3, and 4). When the block- write cycle is invoked, each data bit in the 4-bit color register is written to selected bits of the four adjacent columns of the corresponding random I/O. During block-write cycles, only the seven most significant column addresses (A2–A8) are latched on the falling edge of CAS\\. The two least significant addresses (A0–A1) are replaced by four DQ bits (DQ0–DQ3), which are also latched on the later of the falling edge of CAS\\ or W\\. These four bits are used as a column mask, and they indicate which of the four column-address locations addressed by A2–A8 are written with the contents of the color register during the block-write cycle. DQ0 enables a write to column-address A1 = 0 (low), A0 = 0 (low); DQ1 enables a write to column-address A1 = 0 (low), A0 = 1 (high); DQ2 enables a write to column-address A1 = 1 (high), A0 = 0 (low); DQ3 enables a write to column-address A1 = 1 (high), A0 = 1 (high). A high logic level enables a write, and a low logic level disables the write. A maximum of 16 bits (4 × 4) can be written to memory during each CAS\\ cycle in the block- write mode.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. TRANSFER OPERATION Transfer operations between the memory arrays (DRAM) and the data registers (SAM) are invoked by bringing TRG\\ low before RAS\\ falls. The states of W\\, SE\\, and DSF, which are also latched on the falling edge of RAS\\, determine which transfer operation is invoked. Figure 5 shows an overview of data flow between the random and the serial interfaces. As shown in the “Transfer-Operation Functions” table, the SMJ44C251B/MT42C4256 supports five basic modes of transfer operation:

Register-to-memory transfer (normal write transfer, SAM to DRAM)
Alternate-write transfer (independent of the state of SE\\) FIGURE 5: BLOCK DIAGRAM SHOWING ONE RANDOM AND ONE SERIAL-I/O INTERFACE
Memory-to-register transfer (pseudo-transfer write). Switches serial port from serial-out mode to serial-in mode. No actual data transfer takes place between the DRAM and the SAM.
Memory-to-register transfer (normal-read transfer, transfer entire contents of DRAM row to SAM)
Split-register-read transfer (divides the SAM into a low and a high half. Only one half is transferred to the SAM while the other half is read from the serial I/O port.)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. TRANSFER-OPERATION FUNCTIONS CAS\\ FALL CAS\\ TRG\\ W\\ DSF SE\\ DSF RAS\\ CAS\\ RAS\\ CAS\\ Register-to-memory transfer (normal write transfer) HLLXLX Row Addr Tap Point XX Alternate-write transfer (independent of SE\\) HLLHXX Row Addr Tap Point XX Serial-write-mode enable (pseudo-transfer write) HLLLHX Refresh Addr Tap Point XX Memory-to-register transfer (normal read transfer) HLHLXX Row Addr Tap Point XX Split-register-read transfer (must reload tap) HLHHXX Row Addr Tap Point XX FUNCTION RAS\\ FALL ADDRESS DQ0 - DQ3 LEGEND: H = High L = Low X = Don’t Care WRITE TRANSFER All write-transfer cycles (except the pseudo write transfer) transfer the entire content of SAM to the selected row in the DRAM. To invoke a write-transfer cycle, W\\ must be low when RAS\\ falls. There are three possible write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer. All write-transfer cycles switch the serial port to the serial-in mode. NORMAL-WRITE TRANSFER (SAM-to-DRAM transfer) A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array. TRG\\, W\\, and SE\\ are brought low and latched at the falling edge of RAS\\. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS\\ to select one of the 512 rows available as the destination of the data transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS\\ to select one of the 512 tap points in SAM that are available for the next serial input. During a write-transfer operation before RAS\\ falls, the serial-input operation must be suspended after a minimum delay of t d(SCRL) but can be resumed after a minimum delay of td(RHSC) after RAS goes high (see Figure 6). ALTERNATE-WRITE TRANSFER (refer to Figure 30) When DSF is brought high and latched at the falling edge of RAS\\ in the normal-write-transfer cycle, the alternate-write transfer occurs. PSEUDO-WRITE TRANSFER (write-mode control) (refer to Figure 28) To invoke the pseudo-write transfer (write-mode control cycle), SE\\ is brought high and latched at the falling edge of RAS\\. The pseudo-write transfer does not actually invoke any data transfer but switches the mode of the serial port from the serial-out (read) mode to the serial-in (write) mode. Before serial data can be clocked into the serial port via the SDQ terminals and the SC input, the SDQ terminals must be switched into input mode. Because the transfer does not occur during the pseudo-transfer write, the row address (A0–A8) is in the don’t care state and the column address (A0–A8), which is latched on the falling edge of CAS\\, selects one of the 512 tap points in the SAM that are available for the next serial input. READ TRANSFER (DRAM-to-SAM transfer) (refer to Figure 7) During a read-transfer cycle, data from the selected row in DRAM is transferred to SAM. There are two read-transfer operations: normal-read transfer and split-register-read transfer. NORMAL-READ TRANSFER (refer to Figure 7) The normal-read-transfer operation loads data from a selected row in DRAM into SAM. TRG\\ is brought low and latched at the falling edge of RAS\\. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS\\ to select one of the 512 rows available for transfer. The nine column- (continued)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SPLIT-REGISTER-READ TRANSFER In split-register-read-transfer operation, the serial-data register is split into halves. The low half contains bits 0–255, and the high half contains 256–511. While one half is being read out of the SAM port, the other half can be loaded from the memory array. To invoke a split-register read-transfer cycle, DSF is brought high, TRG\\ is brought low, and both are latched at the falling edge of RAS\\. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS\\ to select one of the 512 rows available for the transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS\\, where address bits A0 –A7 select one of the 255 tap points in the specified half of SAM and address bit A8 selects which half is to be transferred. If A8 is a logic low, the low half is transferred. If A8 is a logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points. A normal-read transfer must precede the split-register-read transfer to ensure proper operation. After the normal-read- transfer cycle, the first split-register read transfer can follow immediately without any minimum SC requirement. However, there is a minimum requirement of a rising edge of SC between split-register read-transfer cycles. QSF indicates which half of the SAM is being accessed during serial-access operation. When QSF is low, the serial- address pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF. In split-register read-transfer mode, QSF changes state when a boundary between the two register halves is reached (see Figure 8 and Figure 9). FIGURE 8: EXAMPLE OF A SPLIT-REGISTER READ-TRANSFER CYCLE AFTER A NORMAL READ-TRANSFER CYCLE

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ABSOLUTE MAXIMUM RATINGS* Supply voltage range, VCC Operating free-air temperature range, T NOTE: 1. All voltage values are with respect to Vss. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS SYM PARAMETER MIN NOM MAX UNIT VCC Supply Voltage 4.5 5 5.5 V VSS Supply Voltage 0 V VIH High-level input voltage 2.9 6.5 V VIL Low-level input voltage -1 0.6 V TA Operating free-air temperature -55 125 °C TC Operating case temperature 125 °C NOTE: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED) PARAMETER SYM CONDITIONS MIN MA X UNIT High-level output voltage VOH IOH = -5mA 2.4 V Low-level output voltage1 VOL IOL = 4.2mA 0.4 V Input leakage current II VCC = 5V, VI = 0V to 5.8V, All others open ±10 µA Output leakage current2 IO VCC = 5.5V, VO = 0V to VCC ±10 µA PARAMETER3 SYM CONDITIONS SAM PORT MIN MAX MIN MAX UNITS Operating current I CC1 tc(rd) and tc(W) = MIN Standby 100 90 mA Operating current I CC1A tc(SC) = MIN Active 110 100 mA Standby current I CC2 All clocks = V CC Standby 15 15 mA Standby current I CC2A tc(SC) = MIN Active 35 35 mA RAS\\-only refresh current I CC3 tc(rd) and tc(W) = MIN Standby 100 90 mA RAS\\-only refresh current I CC3A tc(SC) = MIN Active 110 100 mA Page-mode current I CC4 tc(P) = MIN Standby 65 60 mA Page-mode current I CC4A tc(SC) = MIN Active 70 65 mA CAS\\-before-RAS\\ current I CC5 tc(rd) and tc(W) = MIN Standby 90 80 mA CAS\\-before-RAS\\ current I CC5A tc(SC) = MIN Active 110 100 mA Data-transfer current I CC6 tc(rd) and tc(W) = MIN Standby 100 90 mA Data-transfer current I CC6A tc(SC) = MIN Active 110 100 mA -10 -12 NOTES: 1. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic Designer’ s Handbook . This phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ terminals when the DQ termi nals are switched. This may cause V OL and V OH to exceed the data-book limit for a short period of time, depending upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the device to minimize simultaneous switching effects. 2. SE\\ is disabled for SDQ output leakage tests. 3. I CC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for I CC2). ICCA (active) denotes that the SAM port is active and the DRAM port is active (except for I CC2). ICC is measured with no load on DQ or SDQ. 4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE, f = 1MHz PARAMETER SYM MIN MAX UNIT Input capacitance, A0 - A8 C i(A) 7p F Input capacitance, CAS\\ and RAS\\ C i(RC) 7p F Output capacitance, SDQs and DQs C o(O) 9p F Output capacitance, SQSF C o(QSF) 9p F SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERA- TURE PARAMETER SYM/ALT. SYM CONDITIONS4 MIN MAX MIN MAX UNIT Access time from CAS\\ t a(C)/tCAC td(RLCL) = MAX 25 30 ns Access time from column address t a(CA)/tCAA td(RLCL) = MAX 50 60 ns Access time from CAS\\ high t a(CP)/tCPA td(RLCL) = MAX 55 65 ns Access time from RAS\\ t a(R)/tRAC td(RLCL) = MAX 100 120 ns Access time of DQ0 - DQ3 from TRG\\ low t a(G)/tOEA 25 30 ns Access time of SDQ0 - SDQ3 from SC high t a(SQ)/tSCA CL = 30pF 30 35 ns Access time of SDQ0 - SDQ3 from SE\\ low t a(SE)/tSEA CL = 30pF 20 25 ns Disable time, random output from CAS\\ high3 tdis(CH)/tOFF CL = 100pF 0 20 0 20 ns Disable time, random output from TRG\\ high3 tdis(G)/tOEZ CL = 100pF 0 20 0 20 ns Disable time, random output from SE\\ high3 tdis(SE)/tSEZ CL = 30pF 0 20 0 20 ns -10 -12 NOTES: 1. Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz si gnal applied to the terminal under test. All other terminals are open. 2. Switching times assume C L = 100 pF unless otherwise noted (see Figure 12). 3. t dis(CH), t dis(G), and t dis(SE) are specified when the output is no longer driven. 4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE PARAMETER SYM/ALT. SYM MIN MAX MIN MAX UNIT Cycle time, read2 tc(rd)/tRC 190 220 ns Cycle time, write2 tc(W)/tWC 190 220 ns Cycle time, read-modify-write2 tc(rdW)/tRMW 250 290 ns Cycle time, page-mode read or write2 tc(P)/tPC 60 70 ns Cycle time, page-mode read-modify-write2 tc(rdWP)/tPRMW 105 125 ns Cycle time, read transfer2 tc(TRD)/tRC 190 220 ns Cycle time, write transfer2 tc(TW)/tWC 190 220 ns Cycle time, serial clock 2 tc(SC)/tSCC 30 35 ns Pulse duration, CAS\\ high t w(CH)/tCPN 20 30 ns Pulse duration, CAS\\ low4 tw(CL) /tCAS 25 75000 30 75000 ns Pulse duration, RAS\\ high t w(RH)/tRP 80 90 ns Pulse duration, RAS\\ low5 tw(RL) /tRAS 100 75000 120 75000 ns Pulse duration,W\\ low t w(WL) /tWP 25 25 ns Pulse duration, TRG\\ low t w(TRG) 25 30 ns Pulse duration, SC high t w(SCH)/tSC 10 12 ns Pulse duration, SC low t w(SCL)/tSCP 10 12 ns Pulse duration, SE\\ low t w(SEL)/tSE 35 40 ns Pulse duration, SE\\ high t w(SEH)/tSEP 35 40 ns Pulse duration, TRG\\ high t w(GH)/tTP 30 20 ns Pulse duration, RAS\\ low (page mode) t w(RL)P 100 75000 120 75000 ns Setup time, column address t su(CA)/tASC 00 n s Setup time, DSF before CAS\\ low t su(SFC)/tFSC 00 n s Setup time, row address t su(RA)/tASR 00 n s Setup time, W\\ before RAS\\ low t su(WMR)/tWSR 00 n s Setup time, DQ before RAS\\ low t su(DQR)/tMS 00 n s Setup time, TRG\\ before RAS\\ low t su(TRG)/tTHS 00 n s Setup time, SE\\ before RAS\\ low 6 tsu(SE)/tESR 00 n s Setup time, serial write disable t su(SESC)/tSWIS 10 15 ns Setup time, DSF before RAS\\ low t su(SFR)/tFSR 00 n s Setup time, data before CAS\\ low t su(DCL)/tDSC 00 n s Setup time, data before W\\ low t su(DWL)/tDSW 00 n s Setup time, read command t su(rd)/tRCS 00 n s Setup time, early write command before CAS\\ low t su(WCL)/tWCS 00 n s Setup time, write before CAS\\ high t su(WCH)/tCWL 25 30 ns Setup time, write before RAS\\ high with TRG\\ = W\\ = low tsu(WRH)/tRWL 25 30 ns -10 -12

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. TIMING REQUIREMENTS (continued)1 PARAMETER SYM/ALT. SYM MIN MAX MIN MAX UNIT Setup time, SDQ before SC high t su(SDS)/tSDS 00 n s Hold time, column address after CAS\\ low t h(CLCA)/tCAH 20 20 ns Hold time, DSF after CAS\\ low t h(SFC)/tCFH 20 20 ns Hold time, row address after RAS\\ low t h(RA)/tRAH 15 15 ns Hold time, TRG\\ after RAS\\ low t h(TRG)/tTLH 15 15 ns Hold time, SE\\ after RAS\\ low with TRG\\ = W\\ = low 6 th(SE)/tREH 15 15 ns Hold time, write mask, transfer enable after RAS\\ low th(RWM)/tRWH 15 15 ns Hold time, DQ after RAS\\ low (write-mask operation) th(RDQ)/tMH 15 15 ns Hold time, DSF after RAS\\ low t h(SFR)/tRFH 15 15 ns Hold time, column address after RAS\\ low7 th(RLCA)/tAR 45 45 ns Hold time, data after CAS\\ low t h(CLD)/tDH 20 25 ns Hold time, data after RAS\\ low7 th(RLD)/tDHR 45 50 ns Hold time, data after W\\ low t h(WLD)/tDH 20 25 ns Hold time, read after CAS\\ high8 th(CHrd)/tRCH 00 n s Hold time, read after RAS\\ high8 th(RHrd)/tRRH 10 10 ns Hold time, write after CAS\\ low t h(CLW)/tWCH 30 35 ns Hold time, write after RAS\\ low7 th(RLW)/tWCR 50 55 ns Hold time, TRG\\ after W\\ low9 th(WLG)/tOEH 25 30 ns Hold time, SDQ after SC high t h(SDS)/tSDH 55 n s Hold time, SDQ after SC high t h(SHSQ)/tSOH 55 n s Hold time, DSF after RAS\\ low t h(RSF)/tFHR 45 45 ns Hold time, serial-write disable t h(SCSE)/tSWIH 20 20 ns Delay time, RAS\\ low to CAS\\ high t d(RLCH)/tCSH 100 120 ns Delay time, CAS\\ high to RAS\\ low t d(CHRL)/tCRP 00 n s Delay time, CAS\\ low to RAS\\ high t d(CLRH)/tRSH 25 30 ns Delay time, CAS\\ low to W\\ low 10,11 td(CLWL)/tCWD 55 65 ns Delay time, RAS\\ low to CAS\\ low 12 td(RLCL)/tRCD 25 75 25 90 ns Delay time, column address to RAS\\ high t d(CARH)/tRAL 50 60 ns Delay time, RAS\\ low to W\\ low 10 td(RLWL)/tRWD 130 155 ns Delay time, column address to W\\ low 10 td(CAWL)/tAWD 85 100 ns Delay time, RAS\\ low to CAS\\ high 13 td(RLCH)RF/tCHR 25 25 ns Delay time, CAS\\ low to RAS\\ low 13 td(CLRL)RF/tCSR 10 10 ns Delay time, RAS\\ high to CAS\\ low 13 td(RHCL)RF/tRPC 10 10 ns Delay time, CAS\\ low to TRG\\ high for DRAM read cycles td(CLGH) 25 30 ns -10 -12

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. TIMING REQUIREMENTS (continued)1 PARAMETER SYM/ALT. SYM MIN MAX MIN MAX UNIT Delay time, TRG\\ high before data applied at DQ t d(GHD)/tOED 25 30 ns Delay time, RAS\\ low to TRG\\ high (real-time-reload read-transfer cycle only) td(RLTH)/tRTH 90 95 ns Delay time, RAS\\ low to first SC high after TRG\\ high14 td(RLSH)/tRSD 130 140 ns Delay time, CAS\\ low to first SC high after TRG\\ high14 td(CLSH)/tCSD 40 45 ns Delay time, SC high to TRG\\ high14,15,16 td(SCTR)/tTSL 15 20 ns Delay time, TRG\\ high to RAS\\ high15,16 td(THRH)/tTRD -10 -10 ns Delay time, SC high to RAS\\ low with TRG\\ = W\\ = low 6, 17, 18 td(SCRL)/tSRS 10 20 ns Delay time, SC high to SE\\ high in serial-input mode td(SCSE) 20 20 ns Delay time, RAS\\ high to SC high 6 td(RHSC)/tSRD 25 30 ns Delay time, TRG\\ high to RAS\\ low19 td(THRL)/tTRP tw(RH) tw(RH) ns Delay time, TRG\\ high to SC high15, 16 td(THSC)/tTSD 35 40 ns Delay time, SE\\ low to SC high 20 td(SESC)/tSWS 10 15 ns Delay time, RAS\\ high to last (most significant) rising edge of SC before boundary switch during split-register read-transfer cycles t d(RHMS) 15 20 ns Delay time, CAS\\ low to TRG\\ high in real-time read-transfer cycles td(CLGH)/tCTH 55 n s Delay time, column address to first SC in early- load read-transfer cycles td(CASH)/tASD 45 50 ns Delay time, column address to TRG\\ high in real- time read-transfer cycles td(CAGH)/tATH 10 10 ns Delay time, RAS\\ low to column address 12 td(RLCA)/tRAD 15 50 15 60 ns Delay time, data to CAS\\ low t d(DCL)/tDZC 00 n s Delay time, data to TRG\\ low t d(DGL)/tDZO 00 n s Delay time, RAS\\ low to serial-input data t d(RLSD)/tSDD 50 50 ns Delay time, TRG\\ low to RAS\\ high t d(GLRH)/tROH 25 30 ns Delay time, last (most significant) rising edge of SC to RAS\\ low before boundary switch during split-register read-transfer cycles t d(MSRL) 25 25 ns Delay time, last (255 or 511) rising edge of SC to QSF switching a the boundary during split-register read transfer cycles21 td(SCQSF)/tSQD 40 40 ns Delay time, CAS\\ low to QSF switching in read- transfer or write-transfer cycles21 td(CLQSF)/tCQD 35 35 ns Delay time, TRG\\ high to QSF switching in read- transfer or write-transfer cycles21 td(GHQSF)/tTQD 30 30 ns Delay time, RAS\\ low to QSF switching in read- transfer or write-transfer cycles21 td(RLQSF)/tRQD 75 75 ns Refresh time interval, memory t rf/tREF 88 m s Transition time t t/tT 35 035 0 n s -10 -12

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. NOTES: 1. Timing measurements are referenced to V IL max and V IH min. 2. All cycle times assume t t = 5 ns. 3. When the odd tap is used (tap address can be 0–511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first seri al data out cycle needs to be 70 ns minimum. 4. In a read-modify-write cycle, t d(CLWL) and t su(WCH) must be observed. Depending on the user’s transition times, this may require additional CAS\\ low time [t w(CL) ]. 5. In a read-modify-write cycle, t d(RLWL) and t su(WRH) must be observed. Depending on the user’s transition times, this may require additional RAS\\ low time [t w(RL) ]. 6. Register-to-memory (write) transfer cycles only 7. The minimum value is measured when t d(RLCL) is set to t d(RLCL) min as a reference. 8. Either t h(RHrd) or t (CHrd) must be satisfied for a read cycle. 9. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 10. Read-modify-write operation only 11. TRG\\ must disable the output buffers prior to applying data to the DQ terminals. 12. The maximum value is specified only to assure RAS\\ access time. 13. CAS\\-before-RAS\\ refresh operation only 14. Early-load read-transfer cycle only 15. Real-time-reload read-transfer cycle only 16. Late-load read-transfer cycle only 17. In a read-transfer cycle, the state of SC when RAS\\ falls is a don’t care condition. However, to assure proper sequencing o f the internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS\\ goes low. 18. In a memory-to-register (read) transfer cycle, t d(SCRL) applies only when the SAM was previously in serial-input mode. 19. Memory-to-register (read) and register-to-memory (write) transfer cycles only 20. Serial data-in cycles only 21. Switching times assume C L = 100 pF unless otherwise noted (see Figure 12). FIGURE 12: LOAD CIRCUIT

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 13: Read-Cycle Timing

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 14: Early-Write-Cycle Timing WRITE-CYCLE STATE TABLE 123 4 5 Write Operation L L H Don't Care Valid Data Write-mask load/use, Write DQs to I/Os L L L W rite Mask Valid Data Use previous write mask, Write DQs to I/Os H L L Don't Care Valid Data Load write mask on later of W\\ fall and CAS\\ fall H L H Don't Care W rite Mask STATECYCLE

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 15: Delayed-Write-Cycle Timing (Output-Enable-Controlled Write) WRITE-CYCLE STATE TABLE 123 4 5 Write Operation L L H Don't Care Valid Data Write-mask load/use, Write DQs to I/Os L L L W rite Mask Valid Data Use previous write mask, Write DQs to I/Os H L L Don't Care Valid Data Load write mask on later of W\\ fall and CAS\\ fall H L H Don't Care W rite Mask STATECYCLE

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. WRITE-CYCLE STATE TABLE FIGURE 16: Read-Write/Read-Modify-Write-Cycle Timing 123 4 5 Write Operation L L H Don't Care Valid Data Write-mask load/use, Write DQs to I/Os L L L Write Mask Valid Data Use previous write mask, Write DQs to I/Os H L L Don't Care Valid Data Load write mask on later of W\\ fall and CAS\\ fall H L H Don't Care Write Mask STATECYCLE

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 17: Enhanced-Page-Mode Read-Cycle Timing NOTES: 1. Access time is t a(CP) or t a(CA) dependent. 2. Output can go from the high-impedance state to an invalid data state prior to the specified access time. NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS\\ and CAS\\ to select the desired write m ode (normal, block write, etc.)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 18: Enhanced-Page-Mode Write-Cycle Timing NOTES: 1. Referenced to CAS or W, whichever occurs last NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write tim ing specifications. TRG\\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write feature is use d. If the early-write- cycle timing is used, the state of TRG\\ is a don’t care after the minimum period t h(TRG) from the falling edge of RAS\\. WRITE-CYCLE STATE TABLE 123 4 5 Write Operation L L H Don't Care Valid Data Write-mask load/use, Write DQs to I/Os L L L Write Mask Valid Data Use previous write mask, Write DQs to I/Os H L L Don't Care Valid Data Load write mask on later of W\\ fall and CAS\\ fall H L H Don't Care Write Mask STATECYCLE

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 19: Enhanced-Page-Mode Read-Modify-Write-Cycle Timing NOTES: 1. Output can go from the high-impedance state to an invalid data state prior to the specified access time. NOTE C: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specificat ions are not violated. WRITE-CYCLE STATE TABLE 123 4 5 Write Operation L L H D on't Care Valid Data Write-mask load/use, Write DQs to I/Os L L L Write Mask Valid Data Use previous write mask, Write DQs to I/Os H L L D on't Care Valid Data Load write mask on later of W\\ fall and CAS\\ fall H L H D on't Care Write Mask STATECYCLE

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 20: Load-Color-Register-Cycle Timing (Early-Write Load)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 21: Load-Color-Register-Cycle Timing (Delayed-Write Load)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 22: Block-Write-Cycle Timing (Early Write) BLOCK-WRITE-CYCLE STATE TABLE 12 3 4 Write-mask load/use, Block write L L Write Mask Column Mask Use previous write mask, Block write H L Don't Care Column Mask Write mask disable, Block write to all I/Os L H Don't Care Column Mask CYCLE STATE Write mask data 0: I/O write disable 1: I/O write enable Column mask data DQn = 0 column write disable (n = 0, 1, 2, 3) 1 column write enable DQ0 — column 0 (address A1 = 0, A0 = 0) DQ1 — column 1 (address A1 = 0, A0 = 1) DQ2 — column 2 (address A1 = 1, A0 = 0) DQ3 — column 3 (address A1 = 1, A0 = 1)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 23: Block-Write-Cycle Timing (Delayed-Write) BLOCK-WRITE-CYCLE STATE TABLE 12 3 4 Write-mask load/use, Block write L L Write Mask Col umn Mask Use previous write mask, Block write H L Don't Care Col umn Mask Write mask disable, Block write to all I/Os L H Don't Care Col umn Mask CYCLE STATE Write mask data 0: I/O write disable 1: I/O write enable Column mask data DQn = 0 column write disable (n = 0, 1, 2, 3) 1 column write enable DQ0 — column 0 (address A1 = 0, A0 = 0) DQ1 — column 1 (address A1 = 0, A0 = 1) DQ2 — column 2 (address A1 = 1, A0 = 0) DQ3 — column 3 (address A1 = 1, A0 = 1)

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 24: Enhanced-Page-Mode Block-Write-Cycle Timing ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE 12 3 4 Write-mask load/use, Block write L L Write Mask Column Mask Use previous write mask, Block write H L Don't Care Column Mask Write mask disable, Block write to all I/Os L H Don't Care Column Mask CYCLE STATE Write mask data 0: I/O write disable 1: I/O write enable Column mask data DQn = 0 column write disable (n = 0, 1, 2, 3) 1 column write enable DQ0 — column 0 (address A1 = 0, A0 = 0) DQ1 — column 1 (address A1 = 0, A0 = 1) DQ2 — column 2 (address A1 = 1, A0 = 0) DQ3 — column 3 (address A1 = 1, A0 = 1) NOTES: 1. Referenced to CAS\\ or W\\, whichever occurs last NOTE D: TRG\\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write featur e is used. If the early-write-cycle timing is used, the state of TRG\\ is a don’t care after the minimum period t h(TRG) from the falling edge of RAS\\.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 25: RAS\\-Only Refresh-Cycle Timing NOTES: NOTE E: In persistent write-per-bit function, W\\ must be high at the falling edge of RAS\\ during the refresh cycle.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 26: CBR-Refresh-Cycle Timing NOTES: NOTE F: In persistent write-per-bit operation, W\\ must be high at the falling edge of RAS\\ during the refresh cycle.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 27: Hidden-Refresh-Cycle Timing

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 28: Write-Mode-Control Pseudo-Transfer Timing NOTES: NOTE G: The write-mode-control cycle is used to change the SDQs from the output mode to the input mode. This allows serial dat a to be written into the data register. This figure assumes that the device was originally in the serial-read mode.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 29: Data-Register-to-Memory Transfer Timing, Serial Input Enable

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 30: Alternate Data-Register-to-Memory Transfer-Cycle Timing

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 31: Memory-to-Data-Register Transfer-Cycle Timing, Early-Load Operation NOTES: NOTE H: Early-load operation is defined as t h(TRG) min < t h(TRG) < t d(RLTH) min. NOTE I: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data -register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register ar e written from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted out or tr ansferred back into another row. NOTE J: Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., SQ is enabled), allowing da ta to be shifted out of the registers. Also, the first bit to be read from the data register after TRG\\ has gone high must be activated by a positive trans ition of SC.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 32: Memory-to-Data-Register Transfer-Cycle Timing, Real-Time-Reload Operation/Late-Load Operation NOTES: NOTE K: Late-load operation is defined as t d(THRH) < 0 ns. NOTE L: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data -register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register ar e written from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted out or tr ansferred back into another row. NOTE M: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing da ta to be shifted out of the registers. Also, the first bit to be read from the data register after TRG\\ has gone high must be activated by a positive t ransition of SC.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 33: Memory-to-Data-Register Transfer-Cycle Timing, SDQ Ports Previously in Serial-Input Mode NOTES: NOTE N: Late-load operation is defined as t d(THRH) < 0 ns. NOTE O: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data -register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register ar e written from the 512 corresponding columns of the selected row. The data that is transferred into the data registers may be either shifted out or tr ansferred back into another row. NOTE P: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing da ta to be shifted out of the registers. Also, the first bit to be read from the data register after TRG\\ has gone high must be activated by a positive t ransition of SC.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 34: Split-Register-Mode Read-Transfer-Cycle Timing

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 35: Split-Register-Transfer Operating Sequence NOTES: NOTE Q: In order to achieve proper split-register operation, a normal read transfer should be performed before the first split- register transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then begin either afte r the normal read-transfer cycle (CASE I), during the first split-register cycle (CASE II), or even after the first split-register transfer cycle (CASE II I). There is no minimum requirement of SC clock between the normal read-transfer cycle and the first split-register cycle. NOTE R: A split register transfer into the inactive half is not allowed until t d(MSRL) is met. t d(MSRL) is the minimum delay time between the rising edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\\ of the split-register transfer cycle into the inactive half. After t d(MSRL) is met, the split-register transfer into the inactive half must also satisfy the t d(RHMS) requirement. t d(RHMS) is the minimum delay time between the rising edge of RAS\\ of the split-register transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). There is a minimum requirement of one rising edge of SC clock between two split-register transfer cycles.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 36: Serial-Write-Cycle Timing (SE\\ = VIL) NOTES: NOTE S: The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the SDQ terminals, the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other w rite-transfer cycle. A read-transfer cycle is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the read mode, disabling the input data. Data is written starting at the location specified by the input address loaded on the previous transfer cycle. NOTE T: While accessing data in the serial-data registers, the state of TRG\\ is a don’t care as long as TRG\\ is held high when RAS\\ goes low to prevent data transfers between memory and data registers.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 37: Serial-Write-Cycle Timing (SE\\-Controlled Write) NOTES: NOTE U: The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the SDQ terminals, the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other w rite-transfer cycle. A read-transfer cycle is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the read mode, disabling the input data. Data is written starting at the location specified by the input address loaded on the previous transfer cycle. NOTE V: While accessing data in the serial-data registers, the state of TRG\\ is a don’t care as long as TRG\\ is held high when RAS\\ goes low to prevent data transfers between memory and data registers.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 38: Serial-Read-Cycle Timing (SE\\ = VIL) NOTES: NOTE W: While reading data through the serial-data register, the state of TRG\\ is a don’t care as long as TRG\\ is held high whe n RAS\\ goes low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation. NOTE X: The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device m ust be put into the read mode by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the subsequen t shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 39: Serial-Read-Cycle Timing (SE\\-Controlled Read) NOTES: NOTE Y: While reading data through the serial-data register, the state of TRG\\ is a don’t care as long as TRG\\ is held high whe n RAS\\ goes low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation. NOTE Z: The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device m ust be put into the read mode by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the subs equent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data.

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. MECHANICAL DEFINITIONS* ASI Case #302 (Package Designator F) SMD 5962-89497, Case Outline U *All measurements are in inches. MIN MAX A 0.090 0.130 b 0.015 0.022 c 0.004 0.009 D --- 0.740 E 0.380 0.420 E1 --- 0.440 E2 0.180 --- E3 0.030 --- e L 0.250 0.370 Q 0.026 0.045 S1 0.000 ---

0.050 BSC

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

ORDERING INFORMATION

*OPERATING TEMPERATURE XT = Military Temperature Range -55 oC to +125oC IT = Industrial Temperature Range -40°C to +85°C 883C = MIL-STD-883C process -55 oC to +125oC NOTE: SMJ prefix denotes MIL-STD-883C process, temperature range -55oC to +125oC. EXAMPLE: MT42C4256DCJ-10/XT EXAMPLE: MT42C4256C-12/IT Device Number Package Type Speed ns Pro cess Device Number Package Type Speed ns Process MT42C4256 DCJ -10 /* MT42C4256 C -10 /* MT42C4256 DCJ -12 /* MT42C4256 C -12 /* EXAMPLE: MT42C4256EC-10/883C EX AMPLE: MT42C4256F-12/XT Device Number Package Type Speed ns Pro cess Device Number Package Type Speed ns Process MT42C4256 EC -10 /* MT42C4256 F -10 /* MT42C4256 EC -12 /* MT42C4256 F -12 /* EXAMPLE: MT42C4256CZ-12/883C Device Number Package Type Speed ns Pro cess MT42C4256 CZ -10 /* MT42C4256 CZ -12 /* EXAMPLE: SMJ44C251B 10HJM EXAMPLE: SMJ44C251B 12JDM Device Number Speed ns Package Type Process Device Number Speed ns Package Type Process SMJ44C251B 10 HJM See Note SM J44C251B 10 JDM See Note SMJ44C251B 12 HJM See Note SM J44C251B 12 JDM See Note EXAMPLE: SMJ44C251B 12HMM EXAMPLE: SMJ44C251B 10SVM Device Number Speed ns Package Type Process Device Number Speed ns Package Type Process SMJ44C251B 10 HMM See Note SM J44C251B 10 SVM See Note SMJ44C251B 12 HMM See Note SM J44C251B 12 SVM See Note

Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ASI TO DSCC PART NUMBER CROSS REFERENCE* * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999. ASI Part Number SMD Part Number ASI Part Number SMD Part Number MT42C4256C-10/883C 5962-8949704MXA MT42C4256CZ-10/883C 5962-8949704MMA MT42C4256C-12/883C 5962-8949703MXA MT42C4256CZ-12/883C 5962-8949703MMA SMJ44C251B-10JDM 5962-8949704MXA SMJ44C251B-10SVM 5962-8949704MMA SMJ44C251B-12JDM 5962-8949703MXA SMJ44C251B-12SVM 5962-8949703MMA ASI Part Number SMD Part Number ASI Part Number SMD Part Number MT42C4256EC-10/883C 5 962-8949704MZA MT42C4256DCJ-10/883C 5962-8949704MTA MT42C4256EC-12/883C 5 962-8949703MZA MT42C4256DCJ-12/883C 5962-8949703MTA SMJ44C251B-10HMM 5 962-8949704MZA SMJ44C251B-12HMM 5 962-8949703MZA ASI Part Number SMD Part Number ASI Part Number SMD Part Number MT42C4256F-10/883C 5962-8949704MUA SMJ44C251B-10HJM 5962-8949704MYA MT42C4256F-12/883C 5962-8949703MUA SMJ44C251B-12HJM** 5962-8949703MYA Package Designator F Package Designator HJM Package Designator C or JDM Package Designator CZ or SVM Package Designator EC or HMM Package Designator DCJ

Product Information

SMJ44C251B-12SVM specifications and overview.

Summary

256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM

Description

256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM

Source title SMJ44C251B-12SVM Datasheet(PDF) - Austin Semiconductor

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