SMJ27C256 AUSTIN | Alldatasheet

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Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

FEATURES

  • Organized 32,768 x 8
  • Single +5V ±10% power supply
  • Pin-compatible with existing 256K ROM’s and EPROM’s
  • All inputs/outputs fully TTL compatible
  • Power-saving CMOS technology
  • Very high-speed SNAP! Pulse Programming
  • 3-state output buffers
  • 400-mV DC assured noise immunity with standarad TTL loads
  • Latchup immunity of 250 mA on all input and output pins
  • Low power dissipation (CMOS Input Levels) PActive - 165mW Worst Case PStandby - 1.7mW Worst Case (CMOS-input levels) OPTIONS MARKING
  • Timing 150ns access -15 170ns access -17 200ns access -20 250ns access -25 300ns access -30
  • Package(s) Ceramic DIP (600mils) J No. 110
  • Operating Temperature Ranges Military (-55 oC to +125oC) M PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
  • SMD 5962-86063
  • MIL-STD-883 32-Pin DIP (J) (600 MIL) 256K UVEPROM UV Erasable Programmable Read-Only Memory For more products and information please visit our web site at www.austinsemiconductor.com GENERAL DESCRIPTION The SMJ27C256 series is a set of 262,144 bit, ultraviolet- light erasable, electrically programmable read-only memories. These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits without the use of external pullup resistors. Each output can drive one Series 54 TTL circuit without external resistors. The data outputs are 3-state for connecting multiple devices to a common bus. The SMJ27C256 is pin-compatible with 28-pin 256K ROMs and EPROMs. It is offered in a 600mil dual-in-line ceramic pagackage (J suffix) rated for operation from -55°C to 125°C. Because this EPROM operates from a single 5V supply (in the read mode), it is ideal for use in microprocessor-based systems. One other supply (13V) is needed for programming. All programming signals are TTL level. This device is programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a V PP of 13V and a VCC of 6.5V for a nominal programming time of four seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be programmed singly, in blocks, or at random. Pin Name Function A0 - A14 Address Inputs DA0-DQ7 Inputs (programming)/Outputs E\\ Chip Enable/Power Down G\\ Output Enable GND Ground VCC 5V Supply VPP 13V Programming Power Supply V PP A12 DQ0 DQ1 DQ2 GND Vcc A14 A13 A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and (12V) on A9 for signature mode. TABLE 1. OPERATION MODES

  • This symbol is in accordance with ANSI/IEEE std 91-1984 and IEC Publication 617-12.

Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. READ/OUTPUT DISABLE When the outputs of two or more SMJ27C256s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of the selected SMJ27C256, a low-level signal is applied to E\\ and G\\. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7. LATCHUP IMMUNITY Latchup immunity on the SMJ27C256 is a minimum of 250mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the printed circuit board level when the EPROM is interfaced to industry standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density. POWER DOWN Active ICC supply current can be reduced from 25mA (SMJ27C256-15 through SMJ27C256-25) to 500µA (TTL- level inputs) or 300µA (CMOS-level inputs) by applying a high TTL/CMOS signal to the E\\ pin. In this mode all outputs are in the high-impedance state. ERASURE Before programming, the SMJ27C256 is erased by exposing the chip through the transparent lid to a high-intensity ultra- violet light (wavelength 2537 Å). EPROM erasure before programming is necessary to ensure that all bits are in the logic-high state. Logic-lows are programmed into the desired locations. A programmed logic-low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity x exposure time) is 15W•s/cm 2. A typical 12mW/cm 2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5cm above the chip during erasure. After erasure, all bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure; therefore, when using the SMJ27C256, the window should be covered with an opaque label. SNAP! PULSE PROGRAMMING The SMJ27C256 EPROM is programmed by using the SNAP! Pulse programming algorithm as illustrated by the flowchart in Figure 1. This algorithm programs the device in a nominal time of 4 seconds. Actual programming time varies as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E\\ is pulsed. The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte-verification step to determine when the addressed byte has been successfully programmed. Up to ten 100µs pulses per byte are provided before a failure is recognized. The programming mode is achieved when V PP = 13V , V CC = 6.5V , G\\ = VIH, and E\\ = VIL. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is completed, all bits are verified with V CC = VPP = 5V . PROGRAM INHIBIT Programming can be inhibited by maintaining a high-level input on E\\. PROGRAM VERIFY Programmed bits can be verified with VPP = 13V when G\\ = VIL, and E\\ = VIH. SIGNATURE MODE The signature mode provides access to a binary code identifying the manufacturer and device type. This mode is activated when A9 is forced to 12V ±0.5V . Two identifier bytes are accessed by A0 (terminal 10); i.e., A0=V IL accesses the manufacturer code, which is output on DQ0-DQ7; A0=VIH accesses the device code, which is also output on DQ0-DQ7. All other addresses must be held at VIL. Each byte contains odd parity on bit DQ7. The manufacturer code for these devices is 97h and the device code is 04h.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART

Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** All voltage values are with respect to GND. ABSOLUTE MAXIMUM RATINGS* Supply V oltage Range, V Input V oltage Range, All inputs except A9**..-0.6V to +6.5V RECOMMENDED OPERATING CONDITIONS NOTES: 1. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The deivce must not be inserted into or removed from the board when VPP or VCC is applied. 2. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC2 + IPP1. ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE NOTES: 1. Typical values are at TA =25°C and nominal voltages. 2. This parameter has been characterized at 25°C and is not tested. MIN TYP MAX UNIT 4.5 5 5.5 V 6.25 6.5 6.75 V VCC -0.6 V 12.75 13 13.25 V TTL inputs 2 VCC +1 V CMOS inputs VCC -0.2 V CC +1 V TTL inputs -0.5 0.8 V CMOS inputs -0.5 0.2 V VID 11.5 13 V TA -55 °C TC +125 °C VCC Read Mode1 SNAP! Pulse programming algorithm Supply Voltage Read Mode2 SNAP! Pulse programming algorithm VPP High-level input voltageVIH Supply Voltage VIL Low-level input voltage Operating free-air temperature Operating case temperature Voltage level on A9 for signature mode TEST CONDITIONS MIN TYP 1 MAX UNIT VOH IOH = -400µA 2.4 V VOL IOL = 2.1mA 0.4 V II VI = 0V to 5.5V ±1 µA IO VO = 0V to VCC ±1 µA IPP1 VPP = VCC = 5.5V 10 µA IPP2 VPP = 13V 35 50 mA TTL-Input Level VCC = 5.5V, E\\=VIH 500 µA CMOS-Input Level VCC = 5.5V, E\\=VCC 300 µA ICC2 VCC supply current (active) '27C256-15 '27C256-17 '27C256-20 '27C256-25 E\\=V IL, VCC =5.5V tcycle = minimum, outputs open 15 25 mA IOS 100 mAOutput current (leakage) PARAMETER ICC1 VCC supply current (standby) High-level output voltage Low-level output voltage Input current (leakage) V PP supply current Output current (leakage) VPP supply current (during program pulse)2

Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, f = 1MHz Capacitance measurements are made on a sample basis only. Typical values are at TA = 25°C and nominal voltages. SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 1,2 NOTES: 1.Timing measurements are made at 2V for logic high and 0.8V for logic low (see figure 2). 2. Common test conditions apply for tdis except during programming. 3. Value calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested. TEST CONDITIONS TYP** MAX UNIT C i Input capacitance VI = 0V 61 0 p F C o Output capacitance VO = 0V 10 14 pF PARAMETER MIN MAX MIN MAX ta(A) Access time from address 150 170 ns ta(E) Access time from E\\ 150 170 ns ten(G)R Output enable time from G\\ 70 70 ns tdis Disable time of output from G\\ or E\\, whichever occurs first3 05 505 5 n s tv(A) Output data valid time after change of address, E\\, or G\\, whichever occurs first3 00 n s PARAMETER -15 see Figure 2 -17 UNIT TEST CONDITIONS 1, 2 MIN MAX MIN MAX MIN MAX ta(A) Access time from address 200 250 300 ns ta(E) Access time from E\\ 200 250 300 ns ten(G)R Output enable time from G\\ 75 100 120 ns tdis Disable time of output from G\\ or E\\, whichever occurs first3 0 60 0 60 0 105 ns tv(A) Output data valid time after change of address, E\\, or G\\, whichever occurs first3 000 n s PARAMETER -20 -25 see Figure 2 -30 UNIT TEST CONDITIONS 1, 2 SWITCHING CHARACTERISTICS FOR PROGRAMMING: V CC = 6.5V and VPP = 13V (SNAP! Pulse), TA = 25°C MIN MAX UNIT tdis(G) Output disable time from G\\ 0 130 ns ten(G)W Output enable time from G\\ 150 ns PARAMETER

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

  1. CL includes probe and fixture capacitance.

FIGURE 2. LOAD CIRCUIT AND VOLTAGE WAVEFORMS made at 2V for logic high and 0.8V for logic low for both inputs and outputs.

Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. MECHANICAL DEFINITION* NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ , but they will be within the SMD limits. *All measurements are in inches. ASI Case #110 (Package Designator CW) SMD 5962-86063, Case Outline X A Q L e bb2S1 MIN MAX A --- 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 D --- 1.490 E 0.500 0.610 eA e L 0.125 0.200 Q 0.015 0.060 S1 0.005 --- S2 0.005 --- SYMBOL

0.100 BSC

0.600 BSC

c D E

Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. *AVAILABLE PROCESSES M = Extended Temperature Range -55 oC to +125oC

ORDERING INFORMATION

Temp. SMJ27C256 -15 J * SMJ27C256 -17 J * SMJ27C256 -20 J * SMJ27C256 -25 J * SMJ27C256 -30 J * EXAMPLE: SMJ27C256-30JM

Austin Semiconductor, Inc. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ASI TO DSCC PART NUMBER CROSS REFERENCE* TI Part #** SMD P art # SMJ27C256-15JM 5962-8606305XA SMJ27C256-17JM 5962-8606304XA SMJ27C256-20JM 5962-8606301XA SMJ27C256-25JM 5962-8606302XA SMJ27C256-30JM 5962-8606303XA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999.