SM55161A

SM55161A AUSTIN | Alldatasheet

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Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05

FEATURES

• Organization: – DRAM: 262 144 by 16 Bits – SAM: 512 by 16 Bits  Dual-Port Accessibility – Simultaneous and Asynchronous Access From the DRAM and SAM Ports  Bidirectional Data-Transfer Function From the DRAM to the Serial-Data Register, and from Serial Data Register to DRAM  (8 x 8) x 2 Block Write feature for fast area fill  Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design  Byte-Write Control (CASL, CASU) Provides Flexibility  Extended Data Output for Faster System Cycle Time  Enhanced Page-Mode Operation for Faster Access  CAS-Before-RAS (CBR) and Hidden-Refresh Modes  Long Refresh Period: Every 8 ms (Maximum)  Up to 50-MHz Uninterrupted Serial-Data Streams  512 Selectable Serial-Register Starting Locations  SE-Controlled Register-Status QSF  Split-Register-Transfer Read for Simplified Real-Time Register Load  Programmable Split-Register Stop Point  3-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams  Pin-out Compatible upgrade from SM55161  Compatible With JEDEC Standards 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM PIN ASSIGNMENT (Top View) 64-Pin Ceramic Flatpack (HKC) OPTIONS MARKING  Timing 70ns access -70 75ns access -75 80ns access -80  Package 68 pin PGA GB 64 pin Flatpack HKC  Operating Temperature Ranges - Military (-55 oC to +125 oC) M suffix - Industrial (-40oC to +85oC) I suffix For more products and information please visit our web site at www.austinsemiconductor.com AVAILABLE AS MILITARY SPECIFICATIONS  Military Processing Flow(SM Level)  -55C to 125C temperature PIN DESCRIPTIONS PIN DESCRIPTION A0-A8 Address inputs CASL\\, CASU\\ Column-Address Strobe/Byte Selects DQ0-DQ15 DRAM Data I/O, Write Mask Data Special Function Select DSF Special-Function Select NC/GND No Connect/Ground (NOTE: Not connected internally to VSS) QSF Special-Function Output RAS\\ Row-Address Strobe SC Serial Clock SE\\ Serial Enable SQ0-SQ15 Serial-Data Output TRG\\ Output Enable, Transfer Select V CC 5V Supply (TYP) VSS Ground WE\\ DRAM Write-Enable Select

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 PERFORMANCE RANGES DESCRIPTION SYM MIN MAX MIN MAX MIN MAX UNITS Access Time Row Enable t a(R) 70 75 80 ns Access Time Serial Data ta(SQ) 20 23 25 ns DRAM Cycle Time tc(W) 130 140 150 ns DRAM Page Mode tc(P) 45 48 50 ns Serial Cycle Time tc(SC) 22 24 30 ns Operating Current, Serial Port Stand-by ICC1 165 165 210 mA Operating Current, Serial Port Active ICC1A 210 210 195 mA -70 -75 -80 GB PACKAGE (Bottom View) & PIN ASSIGNMENTS PIN No. NAME PIN No. NAME J1 DQ1 E8 VSS1 J2 SQ3 E9 A4 J3 DQ3 D1 SE\\ J4 DQ4 D2 VSS1 J5 DQ5 D3 VDD1 J6 DQ6 D7 VSS1 J7 SQ7 D8 A3 J8 CASL\\ D9 A2 J9 A8 C1 SQ15 H1 DQ0 C2 V SS1 H2 SQ2 C3 VDD2 H3 DQ2 C4 VSS2 H4 SQ4 C6 VDD2 H5 SQ5 C7 VSS2 H6 SQ6 C8 CASU\\ H7 DQ7 C9 A1 H8 WE\\ B1 DQ15 H9 A7 B2 DQ14 G1 SQ0 B3 DQ13 G2 SQ1 B4 DQ12 G3 V DD2 B5 DQ11 G4 VSS2 B6 DQ10 G6 VDD2 B7 SQ8 G7 VSS2 B8 DSF G8 RAS\\ B9 A0 G9 A6 A1 SQ14 F1 TRG A2 SQ13 F2 VSS1 A3 SQ12 F3 VDD1 A4 SQ11 F7 VDD1 A5 SQ10 F8 VDD1 A6 SQ9 F9 A5 A7 DQ9 E1 SC A8 DQ8 E2 VDD1 A9 QSF

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 GENERAL DESCRIPTION The SMJ55161A, a multiport-video random-access memory (RAM), is a high-speed, dual-port memory device. It consists of a dynamic RAM (DRAM) module organized as 262 144 words of 16 bits each interfaced to a serial-data register (serial-access memory [SAM]) organized as 512 words of 16 bits each. The SMJ55161A supports three basic types of operation: random access to and from the DRAM, serial access to/from the serial register, and transfer of data from any row in the DRAM to the serial register and vice versa. Except during transfer operations, the SMJ55161A can be accessed simultaneously and asynchronously from the DRAM and SAM ports. The SMJ55161A is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel-draw rates are achieved by the device’s (8 × 8) × 2 block-write feature. The block-write mode allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of eight adjacent column-address locations. As many as 128 bits of data can be written to memory during each CAS\\ cycle time. Also, on the DRAM port and SAM port, a write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. The SMJ55161A also offers byte control which can be applied in read cycles, write cycles, block- write cycles, load-write-mask-register cycles, and load-color- register cycles. The SMJ55161A also offers extended-data- output (EDO) mode. The EDO mode is effective in both the page-mode and standard DRAM cycles. The SMJ55161A offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port) that enables real-time-register-load implementation for continuous serial-data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register load (for example, loads done during CRT-retrace periods), the full-register mode of operation is retained to simplify system design. The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up to 50 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active. All inputs, outputs, and clock signals on the SMJ55161 are compatible with Series 54/74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data- out lines are unlatched to allow greater system flexibility. The SMJ55161A is offered in a 68-pin ceramic pin-grid- array package (GB suffix) and a 64-pin ceramic flatpack (HKC suffix). The SMJ55161A is supported by a broad line of graphic processors and control devices from Texas Instruments. See Table 2 and Table 4 for additional information. Additional features of the 55161A include MASKED FLASH WRITE which allows for data in color register to be written into all the memory locations of a selected row.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FUNCTIONAL BLOCK DIAGRAM

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TABLE 1: DRAM & SAM FUNCTIONS CASx\\ FALL CASx\\2 TRG\\ WE\\ DSF DSF RAS\\ CASX\\3 RAS\\ CASL\\ CASU\\ WE\\ Reserved (do not use) L L L L X X X X X --- CBR refresh (no reset) and stop- point set4 LXL H X Stop point5 X X X CBRS CBR refresh (option reset)6 L X H L X X X X X CBR CBR refresh (no reset)7 L X H H X X X X X CBRN Full-register-transfer read H L H L X Row Address Tap Point XX R T Split-register-transfer read H L H H X Row Address Tap Point X X SRT DRAM write (nonpersistent write-per-bit) HHLLL Row Address Column Address Write Mask Valid Data RWM DRAM block write (nonpersistent write-per-bit) HHLLH Row Address Block Address A3-A8 Write Mask Column Mask BWM DRAM write (persistent write-per-bit) HHLLL Row Address Column Address X Valid Data RWM DRAM block write (persistent write-per-bit) HHLLH Row Address Block Address A3-A8 X Column Mask BWM DRAM write (nonmasked) H H H L L Row Address Column Address X Valid Data RW DRAM block write (nonmasked) H H H L H Row Address Block Address A3-A8 X Column Mask BW Load write-mask register8 HHHHL Refresh Address XX Write Mask LMR Load color register H HHHH Refresh Address XX Color Data LCR Masked Write Transfer9 HLLLX Row Address Tap Point Write Mask X MWT Masked Split Write Transfer9 HLLH X Row Address Tap Point Write Mask X MSWT Masked Flash Write Transfer9 HHLHX Row Address X Write Mask --- FWM MNE CODEFUNCTION RAS\\ FALL ADDRESS DQ0-DQ151 LEGEND: Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don’t Care NOTES: 1. DQ0–DQ15 are latched on either the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later. 2. Logic L is selected when either or both CASL\\ and CASU\\ are low. 3. The column address and block address are latched on the first falling edge of CASx\\. 4. CBRS cycle should be performed immediately after the power-up initialization cycle. 5. A0–A3, A8: don’t care; A4–A7: stop-point code 6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. 7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. 8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by th e CBR (option reset) cycle. 9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TABLE 2: PIN DESCRIPTIONS VS. OPERATIONAL MODE PIN DRAM TRANSFER SAM A0-A8 Row, column address Row address, Tap point CASL\\, CASU\\ Column-address strobe, DQ output enable Tap-address strobe DQ DRAM data I/O, write mask Block-write enable Write-mask-register load enable Color-register load enable CBR (option reset) RAS\\ Row-address strobe Row-address strobe SC Serial clock SQ Serial-data output TRG\\ DQ output enable Transfer enable WE\\ Write enable, write-pre-bit enable QSF Special-function output Serial-register status NC/GND Either make no external connection or tie to system GND (V SS) VCC 1 5V supply VSS

1 Ground

SQ output enable, QSF output enable DSF Split-register-transfer enable SE\\ NOTES: 1. For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground. address (A0–A8) Eighteen address bits are required to decode each one of the 262 144 storage cell locations. Nine row-address bits are set up on pins A0–A8 and latched onto the chip on the falling edge of RAS\\. Nine column-address bits are set up on pins A0–A8 and latched onto the chip on the first falling edge of CASx\\. All addresses must be stable on or before the falling edge of RAS\\ and the first falling edge of CASx\\. During the full-register-transfer read operation, the states of A0–A8 are latched on the falling edge of RAS\\ to select one of the 512 rows where the transfer occurs. At the first falling edge of CASx\\, the column-address bits A0–A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred to the SAM. The appropriate 8-bit column address (A0–A8) selects one of 512 tap points (starting positions) for the serial-data output. During the split-register-transfer read operation, an internal counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (A8) selects the DRAM half row. The remaining eight address bits (A0–A7) are used to select one of 256 possible starting locations within the SAM. row-address strobe (RAS\\) RAS\\ is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of RAS\\. RAS\\ is a control input that latches the states of the row address, WE\\, TRG\\, CASL\\, CASU\\, and DSF onto the chip to invoke DRAM and transfer-read/write functions of the SMJ55161A. column-address strobe (CASL, CASU) CASL\\ and CASU\\ are control inputs that latch the states of the column address and DSF to control DRAM and transfer functions of the SMJ55161A. CASx\\ also acts as output enable for the DRAM output pins DQ0–DQ15. In DRAM operation, CASL\\ enables data to be written to or read from the lower byte (DQ0–DQ7), and CASU\\ enables data to be written to or from the upper byte (DQ8–DQ15). In transfer operations, address bits A0–A8 are latched at the first falling edge of CASx\\ as the start position (tap) for the serial-data output (SQ0–SQ15).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 output enable/transfer select (TRG\\) TRG\\ selects either DRAM or transfer operation as RAS\\ falls. For DRAM operation, TRG\\ must be held high as RAS\\ falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0–DQ15. For transfer operation, TRG\\ must be brought low before RAS\\ falls. write-mask select, write enable (WE) In DRAM operation, WE\\ enables data to be written to the DRAM. WE\\ is also used to select the DRAM write-per-bit mode. Holding WE\\ low on the falling edge of RAS\\ invokes the write-per-bit operation. The SMJ55161A supports both the nonpersistent write-per-bit mode and the persistent write-per- bit mode. special-function select (DSF) The DSF input is latched on the falling edge of RAS\\ or the first falling edge of CASx\\, similar to an address. DSF deter- mines which of the following functions are invoked on a par- ticular cycle:  CBR refresh with reset (CBR)  CBR refresh with no reset (CBRN)  CBR refresh with no reset and stop-point set (CBRS)  Block write  Loading write-mask register for the persistent write-per-bit mode (LMR)  Loading color register for the block-write mode  Split-register-transfer read DRAM data I/O, write mask data (DQ0–DQ15) DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG\\ is brought low. Data appears at the outputs until TRG\\ returns high, CASx\\ returns high following RAS\\ returning high, or RAS\\ returns high following CASx\\ returning high. The write mask is latched into the device through the random DQ pins by the falling edge of RAS\\ and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. serial-data outputs (SQ0 –SQ15) Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long as the serial-enable pin, SE\\, is high. The serial outputs are enabled when SE\\ is brought low. serial clock (SC) Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161A is designed to work with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC- clock operating frequency. serial enable (SE) During serial-access operations, SE\\ is used as an enable/ disable for the SQ outputs. SE\\ low enables the serial-data out- put while SE\\ high disables the serial-data output. SE\\ is also used as an enable/disable for output pin QSF. IMPORTANT: While SE\\ is held high, the serial clock is not disabled. External SC pulses increment the internal serial- address counter regardless of the state of SE\\. This ungated serial-clock scheme minimizes access time of serial output from SE\\ low because the serial-clock input buffer and the serial- address counter are not disabled by SE\\. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of the serial register (SAM). When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. During full-register-transfer operations, QSF can change state upon completing the cycle. This state is determined by the tap point loaded during the transfer cycle. QSF is enabled by SE\\; therefore, if SE\\ is high, the QSF output is in the high- impedance state. no connect / ground (NC/GND) NC/GND must be tied to system ground or left floating for proper device operation.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 LEGEND: Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don’t Care NOTES: 1. DQ0–DQ15 are latched on either the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later. 2. Logic L is selected when either or both CASL\\ and CASU\\ are low. 3. The column address and block address are latched on the first falling edge of CASx\\. 4. CBRS cycle should be performed immediately after the powerup initialization cycle. 5. A0–A3, A8: don’t care; A4–A7: stop-point code 6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. 7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. 8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by th e CBR (option reset) cycle. 9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write. TABLE 3: DRAM FUNCTIONS CASx\\ FALL CASx\\2 TRG\\ WE\\ DSF DSF RAS\\ CASX\\3 RAS\\ CASL\\ CASU\\ WE\\ Reserved (do not use) L L L L X X X X X --- CBR refresh (no reset) and stop- point set4 LXL H X Stop point5 X X X CBRS CBR refresh (option reset)6 L X H L X X X X X CBR CBR refresh (no reset)7 L X H H X X X X X CBRN DRAM write (nonpersistent write-per-bit) HHLLL Row Address Column Address Write Mask Valid Data RWM DRAM block write (nonpersistent write-per-bit) HHLLH Row Address Block Address A3-A8 Write Mask Column Mask BWM DRAM write (persistent write-per-bit) HHLLL Row Address Column Address X Valid Data RWM DRAM block write (persistent write-per-bit) HHLLH Row Address Block Address A3-A8 X Column Mask BWM DRAM write (nonmasked) H H H L L Row Address Column Address X Valid Data RW DRAM block write (nonmasked) H H H L H Row Address Block Address A3-A8 X Column Mask BW Load write-mask register8 HHHHL Refresh Address XX Write Mask LMR Load color register H HHHH Refresh Address XX Color Data LCR MNE CODEFUNCTION RAS\\ FALL ADDRESS DQ0-DQ151

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 4: Example of a Byte-Read Cycle byte operation Byte operation can be applied in DRAM-read cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. In byte operation, the column address (A0–A8) is latched at the first falling edge of CASx\\. In read cycles, CASL\\ enables the lower byte (DQ0–DQ7) and CASU\\ enables the upper byte (DQ8–DQ15) (see Figure 4). In byte-write operation, CASL enables data to be written to the lower byte (DQ0–DQ7), and CASU\\ enables data to be written to the upper byte (DQ8–DQ15). In an early write cycle, WE is brought low prior to both CASx\\ signals, and data setup and hold times for DQ0 –DQ15 are referenced to the first falling edge of CASx\\ (see Figure 5). For late-write or read-modify-write cycles, WE\\ is brought low after either or both CASL\\ and CASU\\ fall. The data is strobed in with data setup and hold times for DQ0 –DQ15 referenced to WE\\ (see Figure 6).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 write-per-bit The write-per-bit feature allows masking any combination of the 16 DQs on any write cycle. The write-per-bit operation is invoked when WE\\ is held low on the falling edge of RAS\\. If WE\\ is held high on the falling edge of RAS\\, the write opera- tion is performed without any masking. The SMJ55161A offers two write-per-bit modes: nonpersistent write-per-bit and per- sistent write-per-bit. nonpersistent write-per-bit When WE\\ is low on the falling edge of RAS\\, the write mask is reloaded. A 16-bit binary code (the write-per-bit mask) is input to the device through the DQ pins and latched on the falling edge of RAS\\. The write-per-bit mask selects which of the 16 I/Os are to be written and which are not. After RAS\\ has latched the on-chip write-per-bit mask, input data is driven onto the DQ pins and is latched on either the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later. CASL\\ enables the lower byte (DQ0–DQ7) to be written through the mask and CASU\\ enables the upper byte (DQ8–DQ15) to be written through the mask. If a data low (write mask = 0) is strobed into a particular I/O pin on the falling edge of RAS\\, data is not written to that I/O. If a data high (write mask = 1) is strobed into a particular I/O pin on the falling edge of RAS\\, data is written to that I/O (see Figure 7). FIGURE 7: Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 persistent write-per-bit The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the persistent write-per-bit mode, the write-per-bit mask is overwritten but remains valid over an arbitrary number of write cycles until another LMR cycle is performed or power is removed. The LMR cycle is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS\\ and held low on the first falling edge of CASx\\. A binary code is input to the write-mask register via the random I/O pins and latched on either the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later. Byte write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling edge of RAS\\ is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and is reset only by a CBR refresh (option-reset) cycle (see Figure 8). FIGURE 8: Example of a Persistent Write-Per-Bit Operation

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 9: Block-Write Operation block write The block-write feature allows up to 128 bits of data to be written simultaneously to one row of the memory array. This function is implemented as eight columns by eight DQs and repeated in two halves. In this manner, each of the two 2M-bit halves can have up to eight consecutive columns written at a time with up to eight DQs per column (see Figure 9). Each 2M-bit half has a 8-bit column mask to mask off and prevent any or all of the eight columns from being written with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to provide write-masking options. The DQ data is provided by 8 bits from the on-chip color register. Bits 0–7 from the 16-bit write-mask register, bits 0 –7 from the 16-bit column-mask register, and bits 0 –7 from the 16-bit color-data register configure the block write for the first half, while bits 8 - 15 of the corresponding register control the other half in a similar fashion (see Figure 10).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 10: Block-Write With Masks

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 DRAM-to-SAM transfer operation During the DRAM-to-SAM transfer operation, one row (512 columns) in the DRAM array is selected to be transferred to the 512-bit serial-data register. The transfer operation is invoked by TRG\\ being brought low and WE\\ being held high on the falling edge of RAS\\. The state of DSF, which is latched on the falling edge of RAS\\, determines whether the full- register-transfer read operation or the split-register-transfer read operation is performed (see Table 4). full-register-transfer read A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TRG\\ is brought low and latched at the falling edge of RAS\\. Nine row- address bits (A0–A8) are also latched at the falling edge of RAS\\ to select one of the 512 rows available for the transfer. The nine column-address bits (A0– A8) are latched at the first falling edge of CASx\\. Address bits A0–A8 select one of the SAM’s 512 available tap points from which the serial data is read out. A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late load. Each of these offers the flexibility of controlling the TRG\\ trailing edge in the full-register-transfer read cycle (see Figure 15). TABLE 4: SAM Fuction Table CASx\\ FALL CASx\\1 TRG\\ WE\\ DSF DSF RAS\\ CASX\\ RAS\\ CASx\\ WE\\ Full-register-transfer Read H L H L X Row Address Tap Point XX R T Split-register-transfer Read H L H H X Row Address Tap Point X X SRT MNE CODEFUNCTION RAS\\ FALL ADDRESS DQ0-DQ15 LEGEND: X = Don’t Care NOTES: 1. Logic L is selected when either CASL\\ or CASU\\ are low. FIGURE 15: Example of Full-Register-Transfer Read Operations

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 split-register-transfer read The SMJ55161A features two types of bidirectional data transfer capability between DRAM and SAM. 1) Conventional (non split) transfer: 512 words by 16 bits of data can be loaded from DRAM to SAM (Read transfer), or from SAM to DRAM (write transfer). 2) Split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the DRAM to the lower/uppper half of the SAM (Split read transfer), or from the lower/upper half to SAM to the lower/upper half of DRAM (Split write transfer). The conventional transfer and split transfer modes are controlled by the DSF input signal. Data transfer is invoked by holding the TRG\\ signal “low” at the falling edge of RAS\\. The SMJ55161A supports 4 types of transfer operations: Read transfer, Split read transfer, Write transfer and Split write transfer as shown in the truth table. The type of transfer operation is determined by the state of CAS\\, WE\\, and DSF latched at the falling edge of RAS\\. During conventional transfer operations, the SAM port is switched from input to output mode (Read transfer), or output to input mode (Write transfer). It remains unchanged during split transfer operation (Split read transfer or Split write transfer). Both DRAM and SAM are divided by the most significant row address (AX8), as shown in Figure 16. Therefore, no data transfer between AX8=0 side DRAM and AX8=1 side DRAM can be provided through the SAM. Care must be taken if the split read transfer on AX8=1 side (or AX8=0 side) is provided after the read transfer or the split read transfer, is provided on AX8=0 side (or AX8=1 side). QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low, the serial- address pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a full-register-transfer-read cycle. The tap point loaded during the current transfer cycle determines the state of QSF. QSF also changes state when a boundary between two register halves is reached. FIGURE 16: DRAM and SAM Configuration

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 serial-read operation The serial-read operation can be performed through the SAM port simultaneously and asynchronously with DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 19. For split-register-transfer-read operation, serial data can be read out from the active half of the SAM by clocking SC starting at the tap point loaded by the preceding split- register-transfer cycle. The serial pointer then proceeds sequentially to the most significant bit of the half, bit 255 or bit 511. If there is a split-register-transfer read to the inactive half during this period, the serial pointer points next to the tap point location loaded by that split-register transfer (see Figure 20). If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to bit 256 or bit 0, respectively (see Figure 21). split-register programmable stop point The SMJ55161A offers a programmable stop-point mode for split-register-transfer read operations. This mode can be used to improve two-dimensional drawing performance in a nonscanline data format. For a split-register-transfer-read operation, the stop point is defined as a register location at which the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode, the SAM is divided into partitions whose length is programmed via row addresses A4–A7 in a CBR set (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 22).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 split-register programmable stop point (continued) Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is enabled by holding CASx\\ and WE\\ low and DSF high on the falling edge of RAS\\. The falling edge of RAS\\ also latches row addresses A4–A7 which are used to define the SAM’s partition length. The other row- address inputs are don’t cares. Stop-point mode should be initiated after the initialization cycles are performed (see Table 5). In stop-point mode, the tap point loaded during the split- register-transfer read cycle determines the SAM partition in which the serial output begins and at which stop point the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM (see Figure 23). The stop-point mode of the previous revision 55161 is designed to be compatible with both 256-bit SAM and 512-bit SAM devices like the 55161A. IMPORTANT: For proper device operation, a stop-point- mode (CBRS) cycle should be initiated immediately after the power-up initialization cycles are performed. TABLE 5: Programming Code for Stop-Point Mode A8 A7 A6 A5 A4 A0 - A3 1 6 XLLLL X 1 6 31, 63, 95, 127, 159, 191, 223, 255, 287, 319, 351, 383, 415, 447, 479, 511

32 X L L L H X 8 63, 127, 191, 255, 319, 383, 447, 511

64 X L L H H X 4 127, 255, 383, 511

128 X L H H H X 2 255, 511

ADDRESS AT RAS\\ IN CBRS CYCLEMAX PARTITION LENGTH NUMBER OF PARTITIONS STOP-POINT LOCATIONS FIGURE 23: Example of Split-Register Operation With Programmable Stop Points

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 power up To achieve proper device operation, an initial pause of 200 ms is required after power up followed by a minimum of eight RAS\\ cycles or eight CBR cycles to initialize the DRAM port. A full- register-transfer-read cycle and two SC cycles are required to initialize the SAM port. After initialization, the internal state of the SMJ55161A is as shown in Table 6. TABLE 6: Internal State of SMJ55161A STATE STATE AFTER INITIALIZATION QSF Defined by the transfer cycle during initialization Write Mode Nonpersistent Mode Write-mask Register Undefined Color Register Undefined Serial-Register Tap Point Defined by the transfer cycle during initialization SAM Port Output Mode *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **All voltage values are with respect to V SS. ABSOLUTE MAXIMUM RATINGS* Operating free-air temperature range, T RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN NOM MAX UNIT Supply Voltage VCC 4.5 5 5.5 V Supply Voltage VSS 0V High-level input voltage VIH 2.4 VCC +0.5 V Low-level input voltage1 VIL -0.5 0.8 V Operating free-air temperature TA -55 125 °C NOTES: 1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED) MIN MAX MIN MAX MIN MAX High-level output voltage VOH VOH = -1 mA 2.4 2.4 2.4 V Low-level output voltage VOL VOL = 2 mA 0.4 0.4 0.4 V Input current (leakage) I I VCC = 5.5V, VI = 0V to 5.8V, All other pins at 0V to VCC ±10 ±10 ±10 µA Output current (leakage)3 IO VCC = 5.5V, VO = 0V to VCC ±10 ±10 ±10 µA Operating current2 ICC1 See note 4 Standby 140 130 120 mA Operating current2 ICC1A tc(SC) = MIN Active 180 170 160 mA Standby current I CC2 All clocks = VCC Standby 12 12 12 mA Standby current ICC2A tc(SC) = MIN Active 60 55 50 mA RAS\\-only refresh current I CC3 See note 4 Standby 130 120 115 mA RAS\\-only refresh current ICC3A tc(SC) = MIN5 Active 175 165 155 mA Page-mode current2 ICC4 tc(P) = MIN5 Standby 140 130 120 mA Page-mode current2 ICC4A tc(SC) = MIN5 Active 190 180 170 mA CBR current I CC5 See note 4 Standby 110 100 95 mA CBR current ICC5A tc(SC) = MIN5 Active 150 140 130 mA Data-transfer current I CC6 See note 4 Standby 120 120 110 mA Data-transfer current ICC6A tc(SC) = MIN Active 170 160 150 mA UNIT SAM PORT -70 -75 -80 PARAMETER SYMBOL CONDITIONS NOTES: 1. For conditions shown as MAX/MIN, use the appropriate value specified in the timing requirements. 2. Measured with outputs open. 3. SE\\ is disabled for SQ output leakage tests. 4. Measured with one address change while RAS\\ = V IL; t c(rd), t c(W), t c(TRD) = MIN. 5. Measured with one address change while CASx\\ = V IH.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE* PARAMETER SYMBOL MIN TYP MAX UNIT Input capacitance, address inputs Ci(A) 51 0 p F Input capacitance, address-strobe inputs Ci(RC) 81 0 p F Input capacitance, write-enable input Ci(W) 71 0 p F Input capacitance, serial clock Ci(SC) 61 0 p F Input capacitance, serial enable Ci(SE) 71 0 p F Input capacitance, special function Ci(DSF) 71 0 p F Input capacitance, transfer-register input Ci(TRG) 71 0 p F Output capacitance, SQ and DQ CO(O) 12 15 pF Output capacitance, QSF CO(QSF) 10 12 pF NOTES: *VCC = 5V ±0.5V , and the bias on pins under test is 0V . SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 1 MIN MAX MIN MAX MIN MAX Access time from CASx\\ ta(C) 17 20 20 ns Access time from column address ta(CA) 35 38 40 ns Access time from CASx\\ high ta(CP) 40 43 45 ns Access time from RAS\\ ta(R) 70 75 80 ns Access time of DQ from TRG\\ low ta(G) 17 20 20 ns Access time of SQ from SC high ta(SQ) CL = 30 pF 20 23 25 ns Access time of SQ from SE\\ low ta(SE) CL = 30 pF 17 18 20 ns Disable time, random output from CASx\\ high3 tdis(CH) CL = 50 pF 01 702 002 0n s Disable time, random output from RAS\\ high3 tdis(RH) CL = 50 pF 01 702 002 0n s Disable time, random output from TRG\\ high3 tdis(G) CL = 50 pF 01 702 002 0n s Disable time, random output from WE\\ low tdis(WL) CL = 50 pF 01 702 502 5n s Disable time, serial output from SE\\ high tdis(SE) CL = 30 pF 01 501 802 0n s UNIT td(RLCL) = MAX -70 -75 -80 PARAMETER SYMBOL CONDITIONS 2 NOTES: 1. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50pF. Data-out reference level: VOH/VOL = 2V/0.8V . Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30pF. Serial-data out reference le vel: V OH/VOL = 2V/0.8V . 2. For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. 3. t dis(CH), t dis(RH), t dis(G), t dis(WL), and t dis(SE) are specified when the output is no longer driven.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 1 MIN MAX MIN MAX MIN MAX Cycle time, read tc(rd) 124 140 150 ns Cycle time, write tc(W) 124 140 150 ns Cycle time, read-modify-write tc(rdW) 170 188 200 ns Cycle time, page-mode read, write tc(P) 35 48 50 ns Cycle time, page-mode read-modify-write tc(RDWP) 74 88 90 ns Cycle time, transfer read tc(TRD) 130 140 150 ns Cycle time, serial clock2 tc(SC) 20 24 30 ns Pulse duration, CASx\\ high tw(CH) 10 10 10 ns Pulse duration, CASx\\ low3 tw(CL) 15 10,000 20 10,000 20 10,000 ns Pulse duration, RAS\\ high tw(RH) 50 55 60 ns Pulse duration, RAS\\ low4 tw(RL) 70 10,000 75 10,000 80 10,000 ns Pulse duration, WE\\ low tw(WL) 10 13 15 ns Pulse duration, TRG\\ low tw(TRG) 17 20 20 ns Pulse duration, SC high tw(SCH) 79 1 0 n s Pulse duration, SC low tw(SCL) 79 1 0 n s Pulse duration, TRG\\ high tw(GH) 20 20 20 ns Pulse duration, RAS\\ low (page mode) tw(RL)P 70 100,000 75 100,000 80 100,000 ns Setup time, column address before CASx\\ low tsu(CA) 000n s Setup time, DSF before CASx\\ low tsu(SFC) 000n s Setup time, row address before RAS\\ low tsu(RA) 000n s Setup time, WE\\ before RAS\\ low tsu(WMR) 000n s Setup time, DQ before RAS\\ low tsu(DQR) 000n s Setup time, TRG\\ high before RAS\\ low tsu(TRG) 000n s Setup time, DSF low before RAS\\ low tsu(SFR) 000n s Setup time, data valid before CASx\\ low tsu(DCL) 000n s Setup time, data valid before WE\\ low tsu(DWL) 000n s Setup time, read command, WE\\ high before CASx\\ low t su(rd) 000n s Setup time, early-write command, WE\\ low before CASx\\ low t su(WCL) 000n s Setup time, WE\\ low before CASx\\ high, write tsu(WCH) 15 18 20 ns Setup time, WE\\ low before RAS\\ high, write tsu(WRH) 17 20 20 ns Hold time, column address after CASx\\ low th(CLCA) 10 13 15 ns Hold time, DSF after CASx\\ low th(SFC) 12 15 15 ns Hold time, row address after RAS\\ low th(RA) 10 10 10 ns Hold time, TRG\\ after RAS\\ low th(TRG) 12 15 15 ns Hold time, write mask after RAS\\ low th(RWM) 12 15 15 ns Hold time, DQ after RAS\\ low (write-mask operation) th(RDQ) 12 15 15 ns UNIT -70 -75 -80 PARAMETER SY MBOL

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued) 1 MIN MAX MIN MAX MIN MAX Hold time, DSF after RAS\\ low th(SFR) 10 10 10 ns Hold time, column address valid after RAS\\ low5 th(RLCA) 30 33 35 ns Hold time, data valid after CASx\\ low th(CLD) 12 15 15 ns Hold time, data valid after RAS\\ low5 th(RLD) 30 35 35 ns Hold time, data valid after WE\\ low th(WLD) 12 15 15 ns Hold time, read, WE\\ high after CASx\\ high6 th(CHrd) 00 0 n s Hold time, read, WE\\ high after RAS\\ high6 th(RHrd) 00 0 n s Hold time, write, WE\\ low after CASx\\low th(CLW) 12 15 15 ns Hold time, write, WE\\ low after RAS\\ low5 th(RLW) 30 35 35 ns Hold time, TRG\\ high after WE\\ low7 th(WLG) 10 10 10 ns Hold time, SQ valid after SC high th(SHSQ) 22 2 n s Hold time, DSF after RAS\\ low th(RSF) 30 35 35 ns Hold time, output valid after CASx\\ low th(CLQ) 00 0 n s td(RLCH) 70 75 80 td(RLCH) 10 13 15 Delay time, CASx\\ high to RAS\\ low td(CHRL) 75 5 n s Delay time, CASx\\ low to RAS\\ high td(CLRH) 17 20 20 ns Delay time, CASx\\ low to WE\\ low9,10 td(CLWL) 40 48 50 ns Delay time, RAS\\ low to CASx\\ low11 td(RLCL) 15 50 20 50 20 60 ns Delay time, column address valid to RAS\\ high td(CARH) 35 38 40 ns Delay time, column address valid to CASx\\ high td(CACH) 35 38 40 ns Delay time, RAS\\ low to WE\\ low9 td(RLWL) 90 100 105 ns Delay time, column address valid to WE\\ low9 td(CAWL) 55 63 65 ns Delay time, CASx\\ low to RAS\\ low8 td(CLRL) 55 5 n s Delay time, RAS\\ high to CASx\\ low8 td(RHCL) 00 0 n s Delay time, CASx\\ low to TRG\\ high for DRAM read cycles td(CLGH) 20 20 20 ns Delay time, TRG\\ high before data applied at DQ td(GHD) 15 15 15 ns Delay time, RAS\\ low to TRG\\ high12 td(RLTH) 55 58 ns Delay time, RAS\\ low to first SC high after TRG\\ high13 td(RLSH) 70 75 ns Delay time, RAS\\ low to column address valid td(RLCA) 12 35 15 35 15 40 ns Delay time, TRG\\ low to RAS\\ high td(GLRH) 15 20 20 ns Delay time, CASx\\ low to first SC high after TRG\\ high13 td(CLSH) 20 23 25 ns Delay time, SC high to TRG\\ high12, 13 td(SCTR) 55 5 n s Delay time, TRG\\ high to RAS\\ high12 td(THRH) -10 -10 -10 ns Delay time, TRG\\ high to RAS\\ low14 td(THRL) 50 55 60 ns Delay time, TRG\\ high to SC high12 td(THSC) 15 18 20 ns UNIT Delay time, RAS\\ low to CASx\\ high ns -70 -75 -80 PARAMETER SYMBOL See Note 8

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued) 1 NOTE: 1. Timing measurements are referenced to V IL MAX and V IH MIN. 2. Cycle time assumes tt = 3 ns. 3. In a read-modify-write cycle, t d(CLWL) and t su(WCH) must be observed. Depending on the transition times, this can require additional CASx\\ low time [t w(CL)]. 4. In a read-modify-write cycle, t d(RLWL) and t su(WRH) must be observed. Depending on the transition times, this can require additional RAS\\ low time [t w(RL)]. 5. The minimum value is measured when t d(RLCL) is set to t d(RLCL) MIN as a reference. 6. Either t h(RHrd) or t d(CHrd) must be satisfied for a read cycle. 7. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 8. CBR refresh operation only. 9. Read-modify-write operation only. 10. TRG\\ must disable the output buffers prior to applying data to the DQ pins. 11. The maximum value is specified only to assure RAS\\ access time. 12. Real-time-load transfer read or late-load-transfer read cycle only. 13. Early-load-transfer read cycle only. 14. Full-register-(read) transfer cycles only. 15. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference leve l is V OH / VOL = 2 V/0.8 V . MIN MAX MIN MAX MIN MAX Delay time, RAS\\ high to last (most significant) rising edge of SC before boundary switch during split-register-transfer read cycles td(RHMS) 20 20 20 ns Delay time, CASx\\ low to TRG\\ high in read-time-transfer read cycles td(CLTH) 17 15 15 ns Delay time, column address to first SC in early-load-transfer read cycles td(CASH) 25 28 30 ns Delay time, column address to TRG\\ high in real-time-transfer read cycles td(CAGH) 20 20 20 ns Delay time, data to CASx\\ low td(DCL) 000n s Delay time, data to TRG\\ low td(DGL) 000n s Delay time, last (most significant) rising edge of SC to RAS\\ low before boundary switch during split-register-transfer read cycles td(MSRL) 20 20 20 ns Delay time, last (127 or 255) rising edge of SC to QSF switching at the boundary during split-register-transfer read cycles15 td(SCQSF) 25 28 30 ns Delay time, CASx\\ low to QSF switching in transfer-read cycles15 td(CLQSF) 30 33 35 ns Delay time, TRG\\ high to QSF switching in transfer-read cycles15 td(GHQSF) 25 28 30 ns Delay time, RAS\\ lwo to QSF switching in transfer-read cycles15 td(RLQSF) 70 73 75 ns Refresh time interval, memory trf(MA) 888 m s Transition time tt 32 532 532 5n s UNIT -70 -75 -80 PARAMETER SYMBOL

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 PARAMETER SYMBOL -70 -75 -80 UNITS Last SC to RAS\\ set-up time (serial input) tSRS 25 25 25 ns RAS\\ to serial input delay time tSDD 35 40 45 ns Serial input set-up time tSDS 000 n s Serial input hold time tSDH 000 n s Serial input to SE\\ delay time tSZE 000 n s Serial input to first SC delay time tSZS 000 n s Serial write enable to set-up time tSWS 000 n s Serial write enable to hold time tSWH 10 12 12 ns Serial write disable to set-up time tSWiS 000 n s Serial write disable to hold time tSWiH 10 12 12 ns SAM TO DRAM WRITE TRANSFER & SERIAL IN TIMINGS

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 24: READ-CYCLE TIMING WITH CASx\\-CONTROLLED OUTPUT

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 25: READ-CYCLE TIMING WITH RAS\\-CONTROLLED OUTPUT

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TABLE 7: EARLY-WRITE-CYCLE STATE TABLE FIGURE 26: EARLY-WRITE-CYCLE TIMING 12 3 Write operation (nonmasked) H Don't Care Valid Data Write operation with nonpersistent write-per-bit L Write Mask Valid Data Write operation with persistent write-per-bit L Don't Care Valid Data CYCLE STATE

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 27: LATE-WRITE-CYCLE TIMING (OUTPUT-ENABLE-CONTROLLED WRITE) TABLE 8: LATE-WRITE-CYCLE STATE TABLE 12 3 Write operation (nonmasked) H Don't Care Valid Data Write operation with nonpersistent write-per-bit L Write Mask Valid Data Write operation with persistent write-per-bit L Don't Care Valid Data CYCLE STATE

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 28: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD) NOTES: 1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 29: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (LATE-WRITE LOAD) NOTES: 1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 30: READ-WRITE/READ-MODIFY-WRITE-CYCLE TIMING TABLE 9: READ-WRITE/READ-MODIFY-WRITE-CYCLE STATE TABLE 12 3 Write operation (nonmasked) H Don't Care Valid Data Write operation with nonpersistent write-per-bit L Write Mask Valid Data Write operation with persistent write-per-bit L Don't Care Valid Data CYCLE STATE

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 31: ENHANCED-PAGE-MODE READ-CYCLE TIMING NOTES: A. Access time is t a(CP) or t a(CA) dependent. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timi ng specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\\ and CASx\\ to select the desired write mode (normal, block write, etc.).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 32: ENHANCED-PAGE-MODE WRITE-CYCLE TIMING TABLE 10: ENHANCED-PAGE-MODE WRITE-CYCLE STATE TABLE NOTES: A. Referenced to the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications. To ensure page-mode cycle time, TRG\\ must remain high throughout the entire page-mode operation if the late wri te feature is used. If the early write-cycle timing is used, the state of TRG\\ is a don’t care after the minimum period t h(TRG) from the falling edge of RAS\\.. 12 3 45 Write operation (nonmasked) L L H Don't Care Valid Data Write operation with nonpersistent write-per-bit L L L Write M ask Valid Data Write operation with persistent write-per-bit L L L Don't Care Valid Data Load-write mask on either the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later.1 H L H Don't Care Write Mask CYCLE STATE NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\\ is a don’t care during this cycle.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 33: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE TIMING TABLE 11: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE STATE TABLE NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated. NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\\ is a don’t care during this cycle. 12 3 45 Write operation (nonmasked) L L H Don't Care Valid Data Write operation with nonpersistent write-per-bit L L L Write Mask Valid Data Write operation with persistent write-per-bit L L L Don't Care Valid Data Load-write mask on either the first falling edge of CASx\\ or the falling edge of WE\\, whichever occurs later.1 H L H Don't Care Write Mask CYCLE STATE

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 34: ENHANCED-PAGE-MODE READ-/WRITE-CYCLE TIMING NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timi ng specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\\ and CASx\\ to select the desired write mode (normal, block write, etc.).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 35: LOAD-COLOR-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD)

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 36: LOAD-COLOR-REGISTER-CYCLE TIMING (LATE-WRITE LOAD)

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 37: BLOCK-WRITE-CYCLE TIMING (EARLY WRITE)

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 COLUMN MASK DATA DQ0-15 COLUMN MASK DATA DQ0 Column 0 (A0 = 0, A1 = 0, A2 = 0) DQ1 Column 1 (A0 = 1, A1 = 0, A2 = 0) DQ2 Column 2 (A0 = 0, A1 = 1, A2 = 0) DQ3 Column 3 (A0 = 1, A1 = 1, A2 = 0) DQ4 Column 4 (A0 = 0, A1 = 0, A2 = 1) DQ5 Column 5 (A0 = 1, A1 = 0, A2 = 1) DQ6 Column 6 (A0 = 0, A1 = 1, A2 = 1) DQ7 Column 7 (A0 = 1, A1 = 1, A2 = 1) DQ8 Column 0 (A0 = 0, A1 = 0, A2 = 0) DQ9 Column 1 (A0 = 1, A1 = 0, A2 = 0) DQ10 Column 2 (A0 = 0, A1 = 1, A2 = 0) DQ11 Column 3 (A0 = 1, A1 = 1, A2 = 0) DQ12 Column 4 (A0 = 0, A1 = 0, A2 = 1) DQ13 Column 5 (A0 = 1, A1 = 0, A2 = 1) DQ14 Column 6 (A0 = 0, A1 = 1, A2 = 1) DQ15 Column 7 (A0 = 1, A1 = 1, A2 = 1) Lower Byte Upper Byte Low: Mask High: No Mask Low: Mask High: No Mask TABLE 12: BLOCK-WRITE-CYCLE STATE TABLE 12 3 Block-write operation (nonmasked) H Don't Care Valid Data Block-write operation with nonpersistent write-per-bit L Write Mask Valid Data Block-write operation with persistent write-per-bit L Don't Care Valid Data CYCLE STATE Write-mask data 0: I/O write disable 1: I/O write enable DQ Column-mask data DQi – DQi + 7 0: column-write disable (i = 0,8) 1: column-write enable

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 38: BLOCK-WRITE-CYCLE TIMING (LATE WRITE)

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 COLUMN MASK DATA TABLE 13: BLOCK-WRITE-CYCLE STATE TABLE Write-mask data 0: I/O write disable 1: I/O write enable DQ Column-mask data DQi – DQi + 7 0: column-write disable (i = 0,8) 1: column-write enable 12 3 Block-write operation (nonmasked) H Don't Care Valid Data Block-write operation with nonpersistent write-per-bit L Write Mask Valid Data Block-write operation with persistent write-per-bit L Don't Care Valid Data CYCLE STATE DQ0-15 COLUMN MASK DATA DQ0 Column 0 (A0 = 0, A1 = 0, A2 = 0) DQ1 Column 1 (A0 = 1, A1 = 0, A2 = 0) DQ2 Column 2 (A0 = 0, A1 = 1, A2 = 0) DQ3 Column 3 (A0 = 1, A1 = 1, A2 = 0) DQ4 Column 4 (A0 = 0, A1 = 0, A2 = 1) DQ5 Column 5 (A0 = 1, A1 = 0, A2 = 1) DQ6 Column 6 (A0 = 0, A1 = 1, A2 = 1) DQ7 Column 7 (A0 = 1, A1 = 1, A2 = 1) DQ8 Column 0 (A0 = 0, A1 = 0, A2 = 0) DQ9 Column 1 (A0 = 1, A1 = 0, A2 = 0) DQ10 Column 2 (A0 = 0, A1 = 1, A2 = 0) DQ11 Column 3 (A0 = 1, A1 = 1, A2 = 0) DQ12 Column 4 (A0 = 0, A1 = 0, A2 = 1) DQ13 Column 5 (A0 = 1, A1 = 0, A2 = 1) DQ14 Column 6 (A0 = 0, A1 = 1, A2 = 1) DQ15 Column 7 (A0 = 1, A1 = 1, A2 = 1) Lower Byte Upper Byte Low: Mask High: No Mask Low: Mask High: No Mask

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 39: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE TIMING

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 COLUMN MASK DATA TABLE 14: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE Write-mask data 0: I/O write disable 1: I/O write enable DQ Column-mask data DQi – DQi + 7 0: column-write disable (i = 0,8) 1: column-write enable 12 3 Block-write operation (nonmasked) H Don't Care Valid Data Block-write operation with nonpersistent write-per-bit L Write Mask Valid Data Block-write operation with persistent write-per-bit L Don't Care Valid Data CYCLE STATE DQ0-15 COLUMN MASK DATA DQ0 Column 0 (A0 = 0, A1 = 0, A2 = 0) DQ1 Column 1 (A0 = 1, A1 = 0, A2 = 0) DQ2 Column 2 (A0 = 0, A1 = 1, A2 = 0) DQ3 Column 3 (A0 = 1, A1 = 1, A2 = 0) DQ4 Column 4 (A0 = 0, A1 = 0, A2 = 1) DQ5 Column 5 (A0 = 1, A1 = 0, A2 = 1) DQ6 Column 6 (A0 = 0, A1 = 1, A2 = 1) DQ7 Column 7 (A0 = 1, A1 = 1, A2 = 1) DQ8 Column 0 (A0 = 0, A1 = 0, A2 = 0) DQ9 Column 1 (A0 = 1, A1 = 0, A2 = 0) DQ10 Column 2 (A0 = 0, A1 = 1, A2 = 0) DQ11 Column 3 (A0 = 1, A1 = 1, A2 = 0) DQ12 Column 4 (A0 = 0, A1 = 0, A2 = 1) DQ13 Column 5 (A0 = 1, A1 = 0, A2 = 1) DQ14 Column 6 (A0 = 0, A1 = 1, A2 = 1) DQ15 Column 7 (A0 = 1, A1 = 1, A2 = 1) Lower Byte Upper Byte Low: Mask High: No Mask Low: Mask High: No Mask

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 40: RAS\\-ONLY REFRESH-CYCLE TIMING

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TABLE 15: CBR-CYCLE STATE TABLE FIGURE 41: CBR-REFRESH-CYCLE TIMING 12 3 CBR refresh with option reset Don't Care L H CBR refresh with no reset Don't Care H H CBR refresh with stop-point set and no reset Stop Address H L CYCLE STATE

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 TABLE 16: HIDDEN-REFRESH-CYCLE STATE TABLE FIGURE 42: HIDDEN-REFRESH-CYCLE TIMING 12 3 CBR refresh with option reset Don't Care L H CBR refresh with no reset Don't Care H H CBR refresh with stop-point set and no reset Stop Address H L CYCLE STATE

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 43: FULL-REGISTER TRANSFER-READ TIMING, EARLY-LOAD OPERATIONS NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-regi ster transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register ar e written to from the 512 corresponding columns of the selected row. B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing d ata to be shifted out of the registers. Also, the first bit to read from the data register after TRG\\ has gone high must be activated by a positive transition of SC. C. A0 – A8. D. Early-load operation is defined as t h(TRG) MIN < t h(TRG) < t d(RLTH) MIN. E. There must be no rising transitions.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 44: FULL-REGISTER TRANSFER READ-TIMING, REAL-TIME LOAD OPERATION/LATE-LOAD OPERATION NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-regi ster transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register ar e written to from the 512 corresponding columns of the selected row. B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing d ata to be shifted out of the registers. Also, the first bit to read from the data register after TRG\\ has gone high must be activated by a positive transition of SC. C. A0–A8. D. Late load operation is defined as t d(THRH) < 0 ns.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 45: SPLIT-REGISTER-TRANSFER-READ TIMING NOTES: A. A0–A7: tap point of the given half; A8: identifies the DRAM row half

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 48: SERIAL-READ TIMING (SE\\-CONTROLLED READ) NOTES: A. While the data is being read through the serial-data register, TRG\\ is a don’t care; however, TRG\\ must be held high when RA S\\ goes low. This is to avoid the initiation of a register-data transfer operation. B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 49: SPLIT-REGISTER OPERATING SEQUENCE NOTES: A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register- transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-re gister-transfer-read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle. B. A split-register transfer into the inactive half is not allowed until t d(MSRL) is met. t d(MSRL) is the minimum delay time between the rising edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\\ of the split-register-transfer cycle into the in active half. After the td(MSRL) requirement is met, the split-register transfer into the inactive half must also satisfy the minimum t d(RHMS) requirement. t d(RHMS) is the minimum delay time between the rising edge of RAS\\ of the split-register-transfer cycle into the inactive half and the rising e dge of the serial clock of the last bit (bit 255 or 511).

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 50: MASKED WRITE TRANSFER NOTES: 1. SE\\ = “L” 2. There must be no rising transitions. 3. QSF = “L” - Lower SAM (0-255) is active. QSF = “H” - Upper SAM (256-511) is active.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 FIGURE 51: MASKED SPLIT WRITE TRANSFER NOTES: 1. SE\\ = “L” 2. QSF = “L” - Lower SAM (0-255) is active. QSF = “H” - Upper SAM (256-511) is active. 3. Si is the SAM start address in before SWT. 4. STOP i and STOP j are programmable stop addresses.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 MECHANICAL DEFINITIONS* Package Designator GB SMD 5962-94549, Case Outline X NOTES: 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Index mark may appear on top or bottom depending on package vendor. 4. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38) radius relative to the center of the ceramic. 5. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. 6. The pins can be gold plated or solder dipped. 7. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 MECHANICAL DEFINITIONS* Package Designator HKC SMD 5962-94549, Case Outline Y NOTES: 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. This package can be hermetically sealed with a metal lid. 4. The terminals are gold plated. 5. All leads not shown for clarity purposes.

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05

ORDERING INFORMATION

Prefix* Part Number Speed Package Temp SM 55161A -70 GB M or I SMX 55161A -70 GB M or I SM 55161A -75 GB M or I SMX 55161A -75 GB M or I SM 55161A -80 GB M or I SMX 55161A -80 GB M or I Prefix* Part Number Speed Package Temp SM 55161A -70 HKC M or I SMX 55161A -70 HKC M or I SM 55161A -75 HKC M or I SMX 55161A -75 HKC M or I SM 55161A -80 HKC M or I SMX 55161A -80 HKC M or I SM Prefix: Standard Military Processing using MIL-STD-883C flow & methods but non-complaint to para 1.2.1 SMX Prefix: strictly commercial flow samples I suffix: -40C to +85C M suffix: -55C to 125C EXAMPLE: SM55161A-75GBI EXAMPLE: SM55161A-80HKCM

Austin Semiconductor, Inc. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6 03/05 ASI TO DSCC PART NUMBER CROSS REFERENCE Package Designator GB ASI Part # SMD Part # Package Designator HKC ASI Part # SMD Part # TO BE COMPLETED WHEN SMD LISTING IS RELEASED TO BE COMPLETED WHEN SMD LISTING IS RELEASED