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  • 5A, 500V, RDS(on) typ. = 1.12Ω@VGS = 10 V N50Sadvanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction based on half bridge topology. () y p - Low gate charge ( typical 22 nC) - High ruggedness - Fast switching - 100% avalanche tested - Improved dv/dt capability G S D-PAK D G D S I-PAK Absolute Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameter SLD5N50S SLU5N50S Units VDSS Drain-Source Voltage 500 V ID Drain Current - Continuous (T C = 25℃)5 . 0 A - Continuous (TC = 100℃)3 . 2 A IDM Drain Current - Pulsed (Note 1) 18 A VGSS Gate-Source Voltage ±30 VGSS g ± EAS Single Pulsed Avalanche Energy (Note 2) 300 mJ IAR Avalanche Current (Note 1) 5.0 A EAR Repetitive Avalanche Energy (Note 1) 6.5 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns PD Power Dissipation (TC = 25℃)4 6 W - Derate above 25℃ 0.37 W/ ℃ TJ, TSTG Operating and Storage Temperature Range -55 to +150 ℃ Mi ld t t f l d i TL Maximum lead temperature for soldering purposes, 300 ℃1/8" from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance Junction-to-Case -- 27 ℃/W * Drain current limited by maximum junction temperature. RθJC Thermal Resistance, Junction to Case 2.7 ℃/W RθJS Thermal Resistance, Case-to-Sink Typ. -- -- ℃/W RθJA Thermal Resistance, Junction-to-Ambient -- 62.5 ℃/W

Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Ch t i ti N50S / SLU5N Off Characteristics BVDSS Drain-Source Breakdown Voltage V GS = 0 V, ID = 250 uA 500 -- -- V △BVDSS / △TJ Breakdown Voltage Temperature Coefficient ID = 250 uA, Referenced to 25℃ -- 0.5 -- V/ ℃ IDSS Zero Gate Voltage Drain Current VDS = 500 V, VGS = 0 V -- -- 25 uA VDS = 400 V, TC = 125℃ -- -- 250 uA IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0V -- -- 100 nA N50S IGSSF Gate Body Leakage Current, Forward VGS 30 V, VDS 0 V 100 nA IGSSR Gate-Body Leakage Current, Reverse V GS = -30 V, VDS = 0 V -- -- -100 nA On Characteristics VGS(th) Gate Threshold Voltage V DS = VGS, ID = 250 uA 2.0 -- 4.0 V RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 2.5 A -- 1.12 1.5 Ω gFS Forward Transconductance V DS = 40 V, ID = 2.5 A (Note 4) -- 4.2 -- S Dynamic Characteristics Ciss Input Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz -- 600 -- pF Coss Output Capacitance -- 100 -- pF Crss Reverse Transfer Capacitance -- 20 -- pF Switching Characteristics td(on) Turn-On Delay Time -- 10 -- ns() y VDD = 250 V, ID = 5A, RG = 25 Ω (Note 4, 5) tr Turn-On Rise Time -- 15 -- ns td(off) Turn-Off Delay Time -- 33 -- ns tf Turn-Off Fall Time -- 16 -- ns Qg Total Gate Charge VDS = 400 V, ID = 5A, VGS = 10 V (Note 4, 5) -- 22 -- nC Qgs Gate-Source Charge -- 3.5 -- nC Qgd Gate-Drain Charge -- 11 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 5 A ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 18 A VSD Drain-Source Diode Forward Voltage V GS = 0 V, IS = 5A -- -- 1.6 V trr Reverse Recovery Time V GS = 0 V, IS = 5A, -- 350 -- ns Qrr Reverse Recovery Charge dI F / dt = 100 A/us (Note 4) -- 2.2 -- uC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. IAS =5A,L=24mH, VDD = 50V, RG = 25Ω, Starting TJ = 25°C 3. ISD  5A, di/dt  200A/us, VDD  BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width  300us, Duty cycle  2% 5. Essentially independent of operating temperature

Figure 1. On-Region Characteristics Figure 2. Transfer Character istics Figure 3. On-Resistance Variation vs Figure 4. Body Diode Forward Voltage

800 Ciss

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

2 I = 250 uA

1 V = 10 V

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain C urrent Figure 11. Transient Thermal Response Curve

Gate Charge Test Circuit & Waveform N50S / SLU5N VGS 10V Qg Qgs QgdVGS VDS 300nF 50KΩ 200nF12V Same Type as DUT Current Regulator N50S Charge 3mA Current Sampling (IG) Resistor Current Sampling (ID) Resistor DUT R1 R2 Resistive Switching Test Circuit & Waveforms Vout 90%VDD Vout Vin RL Vin 10% td(on) tr t on t off td(off) tf ( 0.5 rated VDS ) 10V Vin DUT RG Unclamped Inductive Switching Test Circuit & Waveforms EAS =L L IAS---- BV -- V BVDSS LL V 2 BVDSS -- VDD Vary tp to obtain required peak ID 10V VDDC VDS ID RG DUT BVDSS VDD IAS VDS (t) ID (t) t p t p Time

Peak Diode Recovery dv/dt Test Circuit & Waveforms N50S / SLU5N DUT VDS I S N50SL S DriverVGS RG Same Type as DUT V • dv/dt controlled by밨 VDD

  • dv/dt controlled by RGVGS • dv/dt controlled by 밨G
  • I S controlled by Duty Factor 밆? 10V VGS (D r i v e r) D = Gate Pulse Width Gate Pulse Period dv/dt controlled by RG
  • ISD controlled by pulse period ( Driver ) I S ( DUT ) IFM , Body Diode Forward Current IRM di/dt VDS ( DUT ) VDDVf Body Diode Reverse Current Body Diode Recovery dv/dt Body Diode Forward Voltage Drop