SLP20N50C MAPLESMI | Alldatasheet
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Technical content
SLP20N50C/ SLF20N50CSLP20N50C/ SLF20N50C500VN-Channel MOSFETGeneral DescriptionThis Power MOSFET is produced using Maple semi‘s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction based on half bridge topology. Features-20A, 500V, RDS(on)typ.= 220mΩ@VGS= 10 V-Low gate charge ( typical 74.5nC)-High ruggedness-Fast switching-100% avalanche tested-Improved dv/dtcapability * Drain current limited by maximum junction temperature. GS D G D SG D STO-220 TO-220F
Gate Charge Test Circuit & Waveform Resistive Switching Test Circuit & Waveforms Vin Vout 10%90% td(on)trton tofftd(off)tf Charge VGS10VQg QgsQgd Vary tpto obtainrequired peak ID 10V VDDC LLVDSIDRG tp DUT BVDSS t pVDD IAS VDS (t)ID (t)Time VDD( 0.5 rated VDS )10V VoutVin RL DUTRG 3mAVGS Current Sampling (IG)ResistorCurrent Sampling (ID)Resistor DUTVDS300nF50KΩ200nF12V Same Typeas DUTCurrent Regulator R1 R2
Peak Diode Recovery dv/dtTest Circuit & WaveformsDUTVDS+ --LIS DriverVGSRG Same Type as DUTVGS •dv/dt controlled by 밨G•IScontrolled by Duty Factor 밆? VDD 10VVGS( Driver )IS( DUT ) VDS( DUT ) VDD Body DiodeForward Voltage DropVf IFM, Body Diode Forward Current Body Diode Reverse CurrentIRM Body Diode Recovery dv/dt di/dt
- dv/dtcontrolled by RG•ISDcontrolled by pulse period