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Technical content

Features

  • Low Power Consumption
  • Pb-Free / RoHS Compliant
  • Halogen-Free
  • STQFN-20 Package Output Summary
  • 8 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 STQFN-20 TOP VIEW VDD SLG7NT4805 GND SLP_S4_N SLP_S3_N H_SKTOCC_N V3.3A_PWRGD V5DSW V3.3DSW_PWRGD V1.8A_PWRGD SLP_SUS_N V3.3A V3A_FET_CTRL V5A_FET_CTRL RSMRST_N DPWROK V1.05A_PWRGD VCCST_VCCSFT_EN RSMRST_N_2 XDP_PRST_N PS_ON_N Silego SLG7NT4805 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.

DPWROK and RSMRST_N Logic SLG7NT4805_DS_r101 SLG7NT4805 Pin Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 SLP_S4_N Digital Input Digital Input without Schmitt trigger

3 SLP_S3_N Digital Input Digital Input without Schmitt trigger

4 H_SKTOCC_N Digital Input Digital Input without Schmitt trigger

5 V3.3A_PWRGD Digital Output Open Drain NMOS 1X

6 V5DSW Analog Input/Output Analog Input/Output

7 V3.3DSW_PWRGD Digital Input Digital Input without Schmitt trigger 8 V1.8A_PWRGD Digital Input Digital Input without Schmitt trigger

9 SLP_SUS_N Digital Input Digital Input without Schmitt trigger

10 V3.3A Analog Input/Output Analog Input/Output

11 GND GND Ground

12 V3A_FET_CTRL Digital Output Open Drain NMOS 1X

13 V5A_FET_CTRL Digital Output Open Drain NMOS 1X

14 RSMRST_N Digital Output Open Drain NMOS 1X

15 DPWROK Digital Output Open Drain NMOS 1X

16 XDP_PRST_N Digital Input Digital Input without Schmitt trigger

17 PS_ON_N Digital Output Open Drain NMOS 1X

18 V1.05A_PWRGD Digital Input Digital Input without Schmitt trigger

19 VCCST_VCCSFT_EN Digital Output Open Drain NMOS 1X

20 RSMRST_N_2 Digital Output Open Drain NMOS 1X

Ordering Information

SLG7NT4805V V=STQFN-20 SLG7NT4805VTR VTR=STQFN-20 – Tape and Reel (3k units)

DPWROK and RSMRST_N Logic SLG7NT4805_DS_r101 SLG7NT4805 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5 5.5 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static inputs and outputs -- 85 -- µA VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IO Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2-PIN10, PIN12-PIN20) -- -- 90 mA VIH HIGH-Level Input Voltage Logic Input, at VDD=5.0V 2.64 -- VDD V VIL LOW-Level Input Voltage Logic Input, at VDD=5.0V -- -- 1.84 V IIH HIGH-Level Input Current Logic Input PINs; VIN = VDD -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input PINs; VIN = 0V -1.0 -- 1.0 µA VOL LOW-Level Output Voltage Open Drain, IOL = 5mA, 1X Driver, at VDD=5.0 V -- 0.102 0.180 V IOL LOW-Level Output Current Open Drain, VOL =0.4V, 1X Driver, at VDD=5.0 V 10.82 17.38 -- mA VACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 936 -- 964 mV ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature -40°C +85°C (note 1) 895 -- 985 VACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 936 -- 964 mV ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature -40°C +85°C (note 1) 895 -- 985

DPWROK and RSMRST_N Logic SLG7NT4805_DS_r101 SLG7NT4805 TDLY0 Delay0 Time At temperature 25°C 9.44 10 10.68 ms At temperature -40°C +85°C (note 1) 8.43 10 15.07 TDLY1 Delay1 Time At temperature 25°C 9.44 10 10.68 ms At temperature -40°C +85°C (note 1) 8.43 10 15.07 TSU Start up Time From VDD rising past 1.35V -- 0.31 -- ms 1. Guaranteed by Design.

DPWROK and RSMRST_N Logic SLG7NT4805_DS_r101 SLG7NT4805 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.01 006 L 4805V AA 03/08/2016 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking.

DPWROK and RSMRST_N Logic SLG7NT4805_DS_r101 SLG7NT4805 Package Drawing and Dimensions

20 Lead STQFN Package

JEDEC MO-220, Variation WECE IC Net Weight: 0.015 g

DPWROK and RSMRST_N Logic SLG7NT4805_DS_r101 SLG7NT4805 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 20L 2x3mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3mm 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.3 mm3 (nominal). More information can be found at www.jedec.org.

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