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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
Features
- Low Power Consumption
- 3.3V Supply Voltage
- RoHS Compliant / Halogen-Free
- Pb-Free TDFN-12 Package Pin Configuration VDD DLY_PWRGD_IN M_RAIL_PWRGD V1.05S_PWRGD ALL_SYS_PWRGD SYS_PWROK SYS_RAIL_PWRGD VCCST_PWRGD TDFN-12 TOP VIEW Thermal Pad connected to GND SLG7NT4083 SLP_M_N MPWROK SLP_S3_N GND Output Summary
- 1 Output – Open Drain
- 3 Outputs – Push Pull Block Diagram
SLG7NT4083_DB_r102 Page 2 Typical Application Circuit SLG7NT4083 VDD data I data I/O data I/O data I/O data I/O data I/O GND 7data I/O 8data I/O 9data I/O 10data I/O +V3.3A IN IN IN IN IN IN OUT OUT OUT OUT 100nF 10k +V1.05S_VCCST SLP_M _N V1.05S_PWRGD M _RAIL_PWRGD DLY_PWRGD_IN SLP_S3_N MP W ROK SYS_RAIL_PWRGD SYS_PWROK ALL_SYS_PWRGD VCCST_PWRGD
SLG7NT4083_DB_r102 Page 3 Pin Configuration Pin # Pin Name Type Pin Description
1 VDD Power Supply Voltage
2 DLY_PWRGD_IN Input Digital Input
3 M_RAIL_PWRGD Input Digital Input
4 V1.05S_PWRGD Input Digital Input
5 SLP_M_N Input Digital Input
6 MPWROK Output Push Pull
7 GND GND Ground
8 SLP_S3_N Input Digital Input
9 VCCST_PWRGD Output Open Drain
10 SYS_RAIL_PWRGD I nput Digital Input
11 ALL_SYS_PWRGD Output Push Pull
12 SYS_PWROK Output Push Pull
Exposed Bottom Pad GND Ground
Ordering Information
SLG7NT4083V V = TDFN-12 SLG7NT4083VTR VTR = TDFN-12 - Tape and Reel (3k units)
SLG7NT4083_DB_r102 Page 4 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C
Electrical Characteristics
(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static inputs and outputs -- 1 -- μA TA Operating Temperature -40 25 85 °C IL Input Leakage Current Leakage Current for Analog/Digital Inputs or outputs in High impedance state -100 -- 100 nA VIH HIGH-Level Input Voltage Logic I nput at VDD=3.3V 1.8 -- -- V VIL LOW-Level Input Voltage Logic Input at VDD=3.3V -- -- 1.1 V VOH Output Voltage High Push Pull Logic Level Output at VDD=3.3V, IOH=3mA 2.1 -- -- V VOL Output Voltage Low Push Pull Logic Level Output at VDD=3.3V, IOL=3mA -- -- 0.81 V VOL Output Voltage Low Open Drain Logic Level Output at VDD=3.3V, IOL=10mA -- -- 0.605 V VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IOL LOW-Level Output Current Push Pull Current at, V OL=0.4V -- 1 -- mA IOL LOW-Level Output Current Open Drain Current at V OL=0.4V -- 7 -- mA TDELAY1 Time Delay1 Delay1 5 -- 8.5 ms TSU Start up Time After VDD reaches 1.6V -- 7 -- ms
SLG7NT4083_DB_r102 Page 5 Timing Diagrams
SLG7NT4083_DB_r102 Page 6 Package Top Marking Datasheet Revision Programming Code Number Part Code Revision Date 1.02 05 4083V AD 12/11/2012
SLG7NT4083_DB_r102 Page 7 Package Drawing and Dimensions
12 Lead TDFN Package
JEDEC MO-229, Variation WDDE
SLG7NT4083_DB_r102 Page 8 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TDFN 12L 2.5x2.5mm 0.4P Green 12 2.5x2.5x0.75 3000 3000 178/60 42 168 42 168 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W TDFN 12L 2.5x2.5mm 0.4P Green Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.6875 mm3 (nominal). More information can be found at www.jedec.org.
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