SLG7NT4192 DIALOG | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
Features
- Low Power Consumption
- Pb-Free / RoHS Compliant
- Halogen-Free
- TQFN-20 Package Output Summary
- 9 Outputs – Open Drain Pin Configuration VDD BC_ACOK_DSW DPWROK BC_ACOK_EC_IN SUS_VR_PWRGD
7 PWRBTN_N 11 8 9 10
PCH_PWROK VCCST_PWRGD PWRBTN_DSW_N DDR_VCCIO_PWRGD ALL_SYS_PWRGD TQFN-20 TOP VIEW GND SYS_PWROK PWRBTN_EC_IN VBAT_MON RSMRST_PWRGD_N V3.3A_DSW_PWRGD SLG7NT4192
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 2 Block Diagram
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 3 Pin Configuration Pin # Pin Name Type Pin Description
1 VDD PWR Supply Voltage
2 BC_ACOK_DSW Input Digital in without Schmitt trigger
3 DPWROK Output Open Drain
4 BC_ACOK_EC_IN Output Open Drain
5 SUS_VR_PWRGD Input Digital in without Schmitt trigger
6 V1 Input Analog Input
7 PWRBTN_N Input Digital in without Schmitt trigger
8 VCCST_PWRGD Output Open Drain
9 PWRBTN_DSW_N Output Open Drain
10 V2 Input Analog Input
11 GND GND Ground
12 SYS_PWROK Output Open Drain
13 V3 Input Analog input
14 PWRBTN_EC_IN Output Open Drain
15 VBAT_MON Input Analog input
16 RSMRST_PWRGD_N Output Open Drain
17 V3.3A_DSW_PWRGD Input Digital in without Schmitt trigger
18 ALL_SYS_PWRGD Output Open Drain
19 DDR_VCCIO_PWRGD Input Digital in without Schmitt trigger
20 PCH_PWROK Output Open Drain
Ordering Information
SLG7NT4192V V=TQFN-20 SLG7NT4192VTR TQFN-20 – Tape and Reel (3k units)
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 4 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C
Electrical Characteristics
(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.135 3.3 3.465 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static inputs and outputs -- 85 -- μA VIH HIGH-Level Input Voltage Logic Input 1.8 -- -- -- VIL LOW-Level Input Voltage Logic Input -- -- 1.3 V IIH HIGH-Level Input Current Logic Input Pins; VIN =3.3V -1.0 -- 1.0 μA IIL LOW-Level Input Current Logic Input Pins; VIN =0V -1.0 -- 1.0 μA VOL LOW-Level Output Voltage Open Drain, IOL = 3 mA, 1X Driver -- 0.080 0.15 V IOL LOW-Level Output Current Open Drain, VOL = 0.4 V, 1X Driver 7.3 12 -- mA VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V VACMP0 Analog Comparator Reference VACMP1 Analog Comparator Reference VACMP2 Analog Comparator Reference VACMP3 Analog Comparator Reference VHYST Analog Comparator Hysteresis VOFFSET Analog Comparator Offset Voltage ACMP0, ACMP1, ACMP2, ACMP3 -- ±5 -- mV
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 5 TSU Start up Time -- T.B.D. -- ms
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 6 SLG7NT4192 Functionality Waveforms Inputs: D0 – Pin #15 (VBAT_MON) D1 – Pin #17 (V3.3A_DSW_PWRGD) D2 – Pin #7 (PWRBTN_N) D3 – Pin #6 (V1) D4 – Pin #10 (V2) D5 – Pin #13 (V3) D6 – Pin #2 (BC_ACOK_DSW) Outputs: D7 – Pin #3 (DPWROK) with external 5kΩ pull-up resistor D8 – Pin #16 (RSMRST_PWRGD_N) with external 5kΩ pull-up resistor D9 – Pin #14 (PWRBTN_EC_IN) with external 5kΩ pull-up resistor D10 – Pin #9 (PWRBTN_DSW_N) with external 5kΩ pull-up resistor D11 – Pin #8 (VCCST_PWRGD) with external 5kΩ pull-up resistor D12 – Pin #18 (ALL_SYS_PWRGD) with external 5kΩ pull-up resistor D13 – Pin #12 (SYS_PWROK) with external 5kΩ pull-up resistor D14 – Pin #20 (PCH_PWROK) with external 5kΩ pull-up resistor D15 – Pin #4 (BC_ACOK_EC_IN) with external 5kΩ pull-up resistor 1. Chip functionality (Pin5 (SUS_VR_PWRGD), Pin19 (DDR_VCCIO_PWRGD) are always HIGH)
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 7 Package Top Marking Datasheet Revision Programming Code Number Part Code Revision Date 0.11 02 05/27/2013
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 8 Package Drawing and Dimensions
20 Lead TQFN Package
JEDEC MO-220, Variation WCEE
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 9 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TQFN 20L 2x3mm 0.4P Green 20 2x3x0.75 3000 3000 178/60 42 168 42 168 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W TQFN 20L 2x3mm 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.50 mm3 (nominal). More information can be found at www.jedec.org.
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 10 Datasheet Revision History Date Version Change 05/20/2013 0.1 New design 05/27/2013 0.11 Updated design
Power Good Generator Logic SLG7NT4192_DS_r011 Preliminary Page 11 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customer s. For more information regarding Silego Green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ Products are also available for purchase directly from Silego at the Sileg o Online Store at http://store.silego.com/. Silego Technical Support Datasheets and errata, application notes and example designs, user guides, and hardware support docu ments and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send email requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for suppo rt. Local sales offices are also available to help customers. More information regarding your local representative is availa ble at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of worldwide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USE S OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.