SL23EP05 SPECTRALINEAR | Alldatasheet

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Rev 1.0, May 21, 2007 Page 1 of 11 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL23EP05 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features x 10 to 220 MHz operating frequency range x Low output clock jitter:  20 ps-typ cycle-to-cycle jitter  15 ps-typ period jitter x Low output-to-output skew: 30 ps-typ x Low product-to-product skew: 60 ps-typ x Wide 2.5 V to 3.3 V power supply range x Low power dissipation:  16 mA-max at 66 MHz and VDD=3.3 V  14 mA-max at 66 MHz and VDD=2.5V x One input drives 5 outputs organized as 4+1 x SpreadThru™ PLL that allows use of SSCG x Standard and High-Drive options x Available in 150 mil 8-pin SOIC package x Available in Commercial and Industrial grades

Applications

x Routers, Switchers and Servers x Digital Embeded Systems

Description

The SL23EP05 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP05 is available with two (2) drive strength versions called -1 and -1H. The -1 is the standard-drive version and -1H is the high-drive version. The SL23EP05 high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. The standard drive version -1 operates up to 167MHz and 133MHz at 3.3V and 2.5V respectively. The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is less then 2.0MHz or there is no rising edge. In this state all five (5) outputs are tri-stated and the PLL is turned off leading to less than 10 ȝA of power supply current draw. Benefits x Up to five (5) distribution of input clock x Standard and High-Dirive levels to control impedance level, frequency range and EMI x Low power dissipation, jitter and skew x Low cost Block Diagram

Rev 1.0, May 21, 2007 Page 2 of 11 SL23EP05 Pin Configuration 8-Pin (150 mil) SOIC Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (150k ȍ). 2 CLK2 Output Buffered Clock Output Weak pull-down (150k ȍ). 3 CLK1 Output Buffered Clock Output. Weak pull-down (150k ȍ). 4 GND Power Power Ground. 5 CLK3 Output Buffered Clock Output. Weak pull-down (150k ȍ). 6 VDD Power 3.3V or 2.5V Power Supply. 7 CLK4 Output Buffered Clock Output. Weak pull-down (150k ȍ). 8 CLKOUT Output Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pull-down (150kȍ).

systems requiring clock distribution. number of total available output clocks to five (5).

3.3 HIGH 10 220

3.3 STD 10 167

2.5 HIGH 10 200

2.5 STD 10 133

Table 1. Input/Output Frequency Range the AC electrical tables for the details.

Rev 1.0, May 21, 2007 Page 4 of 11 SL23EP05 Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 85 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C Soldering Temperature – 260 °C ESD Rating (Human Body Model) MIL-STD-883, Method 3015 2000 – V Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades Symbol Description Condition Min Max Unit VDD3.3 3.3V Supply Voltage 3.0 3.6 V VDD2.5 2.5V Supply Voltage 2.3 2.7 V Commercial 0 85 °C TA Operating Temperature(Ambient) Industrial –40 85 °C <100 MHz, 3.3V – 30 pF <100 MHz, 2.5V with High drive – 30 pF <133.3 MHz, 3.3V – 22 pF <133.3 MHz, 2.5V with High drive – 22 pF <133.3 MHz, 2.5V with Standard drive – 15 pF >133.3 MHz, 3.3V – 15 pF CLOAD Load Capacitance >133.3 MHz, 2.5V with High drive – 15 pF CIN Input Capacitance CLKIN pin – 5 pF 3.3V, (typical) 1-1.5 MHz CLBW Closed-loop bandwidth 2.5V, (typical) 0.8 MHz 3.3V, (typical), High drive 29 Ÿ 3.3V, (typical), Standard drive 41 Ÿ 2.5V, (typical), High drive 37 Ÿ ZOUT Output Impedance 2.5V, (typical), Standard drive 41 Ÿ

Rev 1.0, May 21, 2007 Page 5 of 11 SL23EP05 Symbol Description Condition Min Max Unit VDD Supply Voltage 3.0 3.6 V VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 VDD+0.3 V IIL Input Leakage Current 0 < VIN < 0.8V – ±10 µA IIH Input HIGH Current – 100 µA VIN = VDD IOL = 8 mA (standard drive) – 0.4 VVOL Output LOW Voltage IOL = 12 mA (high drive) – 0.4 V IOH = –8 mA (standard drive) 2.4 – VVOH Output HIGH Voltage 2.4 – VIOH = –12 mA (high drive) CLKIN = 0 MHz (Commercial) – 10 µA IDDPD Power Down Supply Current CLKIN = 0 MHz (Industrial) – 25 µA IDD Power Supply Current 16 mA All Outputs CL=0, 66-MHz CLKIN – Symbol Description Condition Min Max Unit VDD Supply Voltage 2.3 2.7 V VIL Input LOW Voltage – 0.7 V VIH Input HIGH Voltage 1.7 VDD+ 0.3 V IIL Input Leakage Current 0<VIN < 0.8V – +/-10 µA IIH Input HIGH Current – 100 µA VIN = VDD IOL = 8 mA (Standard drive) – 0.5 VVOL Output LOW Voltage – 0.5 VIOL = 12 mA (High drive) IOH = –8 mA (Standard drive) VDD – 0.6 –VVOH Output HIGH Voltage VDD – 0.6 – VIOH = –12 mA (High drive) CLKIN = 0 MHz (Commercial) – 10 µA IDDPD Power Down Supply Current CLKIN = 0 MHz (Industrial) – 25 µA IDD Power Supply Current All Outputs CL=0, 66-MHz CLKIN – 14 mA

Rev 1.0, May 21, 2007 Page 6 of 11 SL23EP05 Symbol Description Condition Min Typ Max Unit 3.3V High Drive 10 – 220 MHz 3.3V Standard Drive 10 – 167 MHz 2.5V High Drive 10 – 200 MHz FMAX Maximum Frequency [1] (Input=Output ) 2.5V Standard Drive 10 – 133 MHz <135 MHz, VDD=3.3V 25 – 75 %INDC Input Duty Cycle <135 MHz, VDD=2.5V 40 – 60 % <135 MHz, VDD=3.3V 47 – 53 %OUTDC Output Duty Cycle [2] <135 MHz, VDD=2.5V 45 55 % Std drive, CL = 30 pF, <100 MHz – – 1.6 ns Std drive, CL = 22 pF, <135 MHz – – 1.6 ns Std drive, CL = 15 pF, <170 MHz – – 0.6 ns High drive, CL = 30 pF, <100 MHz – – 1.2 ns High drive, CL = 22 pF, <135 MHz – – 1.2 ns tr/f3.3 Rise, Fall Time (3.3V) [2] Measured at: 0.8 to 2.0V High drive, CL = 15 pF, >135 MHz – – 0.5 ns Std drive, CL = 15 pF, <135 MHz – – 1.5 ns High drive, CL = 30 pF, <100 MHz – – 2.1 ns High drive, CL = 22 pF, <135 MHz – – 1.3 ns tr/f2.5 Rise, Fall Time (2.5) [2] Measured at: 0.6 to 1.8V High drive, CL = 15 pF, >135 MHz – – 1.2 ns All outputs CL=0, 3.3V supply, 2.5 power supply, standard drive – 30 90 pst1 Output-to-Output Skew [9] All outputs CL=0, 2.5V power supply, high drive – 40 100 ps PLL Bypass mode 1.5 – 4.4 ns PLL enabled @ 3.3V -100 – 100 ps t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge [2] PLL enabled @2.5V -200 – 200 ps Measured at VDD/2. Any output to any output, 3.3V supply -150 – 150 pst3 Part-to-Part Skew [2] Measured at VDD/2. Any output to any output, 2.5V supply -300 – 300 Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. ps

Rev 1.0, May 21, 2007 Page 7 of 11 SL23EP05 Symbol Description Condition Min Typ Max Unit tPLLOCK PLL Lock Time[9] From 90% of VDD to valid clocks presented on all output clock pins –– 1.0 ms 3.3V supply, >66 MHz, <15 pF –2 0 5 0 ps 3.3V supply, >66 MHz, <30 pF, standard drive – 40 100 ps 3.3V supply, >66 MHz, <30 pF, high drive – 40 100 ps 2.5V supply, >66 MHz, <15 pF, standard drive – 35 90 ps 2.5V supply, >66 MHz, <15 pF, high drive – 30 60 ps CCJ [2,3] Cycle-to-cycle Jitter 2.5V supply, >66 MHz, <30 pF, high drive – 50 125 ps 3.3V supply, 66–100 MHz, <15 pF – 18 50 ps 3.3V supply, >100 MHz, <15 pF – 15 35 ps 3.3V supply, >66 MHz, <30 pF, standard drive – 30 75 ps 3.3V supply, >66 MHz, <30 pF, high drive – 25 60 ps 2.5V supply, >66 MHz, <15 pF, standard drive – 25 60 ps 2.5V supply, 66–100 MHz, <15 pF, high drive – 20 60 ps PPJ [2,3] Peak Period Jitter 2.5V supply, >100 MHz, <15 pF, high drive 20–4 5 p s Notes: 3. Typical jitter is measured at 3.3V or 2.5V, 30 qC with all outputs driven into the maximum specified load.

Rev 1.0, May 21, 2007 Page 8 of 11 SL23EP05 External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1ȝF must be used between VDD and VSS on the pins 6 and 4. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output (SSCLK) and the load is over 1 ½ inch. The nominal impedance of the SSCLK output is about 30 Ÿ. Use 20 Ÿ resistor in series with the output to terminate 50Ÿ trace impedance and place 20 Ÿ resistor as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal feedback to PLL, and sees an additional 2 pF load with respect to the clock pins. For applications requiring zero input/output delay, the load a t the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between clocks and CLKIN. For minimum pin-to-pin skew, the external load at the clocks must be the same.

Rev 1.0, May 21, 2007 Page 10 of 11 SL23EP05 Package Drawing and Dimensions 8-Lead SOIC (150 Mil) Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit ș JA Still air - 150 - °C/W ș JA 1m/s air flow - 140 - °C/W Thermal Resistance Junction to Ambient ș JA 3m/s air flow - 120 - °C/W Thermal Resistance Junction to Case ș JC Independent of air flow - 40 - °C/W

Rev 1.0, May 21, 2007 Page 11 of 11 SL23EP05 Ordering Information [4] Ordering Number Marking Shipping Package Package Temperature SL23EP05SC-1 SL23EP05SC-1 Tube 8-pin SOIC 0 to 70°C SL23EP05SC-1T SL23EP05SC-1 Tape and Reel 8-pin SOIC 0 to 70°C SL23EP05SI-1 SL23EP05SI-1 Tube 8-pin SOIC -40 to 85°C SL23EP05SI-1T SL23EP05SI-1 Tape and Reel 8-pin SOIC -40 to 85°C SL23EP05SC-1H SL23EP05SC-1H Tube 8-pin SOIC 0 to 70°C SL23EP05SC-1HT SL23EP05SC-1H Tape and Reel 8-pin SOIC 0 to 70°C SL23EP05SI-1H SL23EP05SI-1H Tube 8-pin SOIC -40 to 85°C SL23EP05SI-1HT SL23EP05SI-1H Tape and Reel 8-pin SOIC -40 to 85°C Notes: 4. The SL23EP05 products are RoHS compliant. While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This produ ct is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. re serves the right to change any circuitry or specification without notice.