SL2305

SL2305 SPECTRALINEAR | Alldatasheet

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Technical content

Rev 1.4, May 25, 2007 Page 1 of 11 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL2305 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features x 10 to 140 MHz operating frequency range x Low output clock jitter:  45 ps-typ cycle-to-cycle jitter x Low output-to-output skew: 50 ps-typ x Low product-to-product skew: 125 ps-typ x 3.3 V power supply range x Low power dissipation:  26 mA-max at 66 MHz  42 mA-max at 140 MHz x One input drives 5 outputs organized as 4+1 x SpreadThru™ PLL that allows use of SSCG x Standard and High-Drive options x Available in 8-pin SOIC and TSSOP packages x Available in Commercial and Industrial grades

Applications

x Routers, Switchers and Servers x Digital Embeded Systems

Description

The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2305 is available with two (2) drive strength versions. The -1 is the standard-drive version and -1H is the high- drive version. The SL2305 high-drive version operates up to 140MHz and the standard drive version -1 operates up to 100. The SL2305 enter into Power-Down (PD) mode if the input at CLKIN is DC (0 to VDD). In this power-down state all five (5) outputs are tri-stated and the PLL is turned off leading to less than 12ȝA-max of power supply current draw. Benefits x Up to five (5) distribution of input clock x Standard and High-Dirive levels to control impedance level, frequency range and EMI x Low jitter and skew x Low power dissipation x Low cost Block Diagram

Rev 1.4, May 25, 2007 Page 2 of 11 SL2305 Pin Configuration 8-Pin SOIC or TSSOP Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (250k ȍ). 2 CLK2 Output Buffered Clock Output Weak pull-down (250k ȍ). 3 CLK1 Output Buffered Clock Output. Weak pull-down (250k ȍ). 4 GND Power Power Ground. 5 CLK3 Output Buffered Clock Output. Weak pull-down (250k ȍ). 6 VDD Power 3.3V Power Supply. 7 CLK4 Output Buffered Clock Output. Weak pull-down (250k ȍ). 8 CLKOUT Output Buffered Clock Output, Used f or Internal Feedback to PLL Input. Weak pull- down (250kȍ).

systems requiring clock distribution. capacitance (CL) as given in the below Table 1. Table 1. Input/Output Frequency Range spread profile and modulation frequency. to the AC electrical tables for the details. clock outputs since CLKOUT is the feedback to the PLL. (Max), complying with VDD=3.3V+/-10% requirement. power supply operation requirements. temperature range of -40 to +85°C (I-Grade).

Rev 1.4, May 25, 2007 Page 4 of 11 SL2305 Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 85 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C Soldering Temperature – 260 °C ESD Rating (Human Body Model) MIL-STD-883, Method 3015 2000 – V Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit VDD 3.3V Supply Voltage 3.3V+/-10% 3.0 3.6 V Commercial 08 5 ° C TA Operating Temperature(Ambient) Industrial –40 85 °C 10 to 140 MHz, -1H high drive –1 5 p F 10 to 100 MHz, -1H high drive –3 0 p F 10 to 100MHz, -1 standard drive –1 5 p F CLOAD Load Capacitance 10 to 66MHz, -1 standard drive –3 0 p F CIN Input Capacitance CLKIN pin – 7 pF tpu Power-up Time Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). 0.05 100 ms CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz 3.3V (typical), -1H high drive 22 ŸZOUT Output Impedance 3.3V (typical), -1 standard drive 32 Ÿ

Rev 1.4, May 25, 2007 Page 5 of 11 SL2305 Symbol Description Condition Min Max Unit VDD Supply Voltage 3.0 3.6 V VIL Input LOW Voltage CLKIN (Pin-1) – 0.8 V VIH Input HIGH Voltage CLKIN (Pin-1) 2.0 V DD+0.3 V IIL Input LOW Current CLKIN, 0 < VIN < 0.8V – 25 µA IIH Input HIGH Current CLKIN, VIN = VDD – 50 µA IOL = 8 mA (standard drive) – 0.4 VVOL Output LOW Voltage (All outputs) IOL = 12 mA (high drive) – 0.4 V IOH = –8 mA (standard drive) 2.4 – VVOH Output HIGH Voltage (All outputs) IOH = –12 mA (high drive) 2.4 – V C-Grade, Power-down if CLKIN=0 to VDD or input is floating –1 2 µ A IDDPD Power Down Supply Current CLKIN=0 to VDD I-Grade, Power-down if CLKIN=0 to VDD or input is floating –2 5 µ A IDD1 Power Supply Current All Outputs CL=0, 33-MHz CLKIN – 18 mA IDD2 Power Supply Current All Outputs CL=0, 66-MHz CLKIN – 26 mA IDD3 Power Supply Current All Outputs CL=0, 100-MHz CLKIN – 34 mA IDD4 Power Supply Current All Outputs CL=0, 140-MHz CLKIN – 42 mA RPD Pull-down Resistors Pins-1/2/3/5/7/8, 250kŸ-typ 175 325 k Ÿ

Rev 1.4, May 25, 2007 Page 6 of 11 SL2305 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit High drive (-1H). All outputs CL=15pF 10 140 MHz High drive (-1H), All outputs CL=30pF 10 100 MHz Standard drive, (-1), All outputs CL=15pf 10 100 MHz FMAX1 Maximum Frequency [1] (Input=Output ) All Active PLL Modes Standard drive, (-1), All outputs CL=30pf 10 66 MHz INDC Input Duty Cycle Measured at 1.4V, Fout=66MHz, CL=15pF 30 70 % OUTDC Output Duty Cycle [2] Measured at 14V, Fout=66MHz, CL=15pF 40 60 % High drive (-1H), CL=10pF – 1.5 ns High drive (-1H), CL=30pF – 1.8 ns Standard drive (-1), CL=10pF – 2.2 ns tr/f Rise, Fall Time (3.3V) [2] (Measured at: 0.8 to 2.0V) Standard drive (-1), CL=30pF – 2.5 ns t1 Output-to-Output Skew [2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 120 ps t2 Device-to-Device Skew [2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 400 ps t3 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge [2] Measured at VDD/2 –150 150 ps tPLOCK PLL Lock Time [2] Time from 90% of VDD to valid clocks on all the output clocks – 1.0 ms Fin=Fout=66 MHz, <CL=15pF, -1H drive – 90 ps Fin=Fout=66 MHz, <CL=15pF, -1 drive – 100 ps Fin=Fout=66 MHz, <CL=30pF, -1H drive – 120 ps CCJ Cycle-to-cycle Jitter [2] Fin=Fout=66 MHz, <CL=30pF, -1 drive – 140 ps Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Rev 1.4, May 25, 2007 Page 7 of 11 SL2305 External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 ȝF must be used between VDD and VSS on the pins 6 and 4. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor : A series termination resistor is recommended if the distance between the outputs and the load is over 1 ½ inch. The nominal impedance of the Clock outputs are about 30 Ÿ. Use 20 Ÿ resistor in series with the output to terminate 50Ÿ trace impedance and place 20 Ÿ resistor as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal feedback to PLL, and sees an additional 2 pF load with respect to the clock pins. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between clocks and CLKIN. For minimum pin-to-pin skew, the external load at the clock outputs must be the same.

Rev 1.4, May 25, 2007 Page 9 of 11 SL2305 Package Outline and Package Dimensions 8-Pin SOIC Package (150 mil) Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit ș JA Still air - 150 - °C/W ș JA 1m/s air flow - 140 - °C/W Thermal Resistance Junction to Ambient ș JA 3m/s air flow - 120 - °C/W Thermal Resistance Junction to Case ș JC Independent of air flow - 40 - °C/W

Rev 1.4, May 25, 2007 Page 10 of 11 SL2305 Package Outline and Package Dimensions 8-Pin TSSOP Package (173 mil) Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit Still air - 110 - °C/W 1m/s air flow - 100 - °C/W Thermal Resistance Junction to Ambient 3m/s air flow - 80 - °C/W Thermal Resistance Junction to Case Independent of air flow - 35 - °C/W

Rev 1.4, May 25, 2007 Page 11 of 11 SL2305 Ordering Information [3] Ordering Number Marking Shipping Package Package Temperature SL2305SC-1 SL2305SC-1 Tube 8-pin SOIC 0 to 70°C SL2305SC-1T SL2305SC-1 Tape and Reel 8-pin SOIC 0 to 70°C SL2305SI-1 SL2305SI-1 Tube 8-pin SOIC -40 to 85°C SL2305SI-1T SL2305SI-1 Tape and Reel 8-pin SOIC -40 to 85°C SL2305SC-1H SL2305SC-1H Tube 8-pin SOIC 0 to 70°C SL2305SC-1HT SL2305SC-1H Tape and Reel 8-pin SOIC 0 to 70°C SL2305SI-1H SL2305SI-1H Tube 8-pin SOIC -40 to 85°C SL2305SI-1HT SL2305SI-1H Tape and Reel 8-pin SOIC -40 to 85°C SL2305ZC-1 SL2305ZC-1 Tube 8-pin TSSOP 0 to 70°C SL2305ZC-1T SL2305ZC-1 Tape and Reel 8-pin TSSOP 0 to 70°C SL2305ZI-1 SL2305ZI-1 Tube 8-pin TSSOP -40 to 85°C SL2305ZI-1T SL2305ZI-1 Tape and Reel 8-pin TSSOP -40 to 85°C SL2305ZC-1H SL2305ZC-1H Tube 8-pin TSSOP 0 to 70°C SL2305ZC-1HT SL2305ZC-1H Tape and Reel 8-pin TSSOP 0 to 70°C SL2305ZI-1H SL2305ZI-1H Tube 8-pin TSSOP -40 to 85°C SL2305ZI-1HT SL2305ZI-1H Tape and Reel 8-pin TSSOP -40 to 85°C Notes: 3. The SL2305 products are RoHS compliant. While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This produ ct is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. re serves the right to change any circuitry or specification without notice.