SHARP_LH7A404 SHARP | Alldatasheet
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Advance Data Sheet 32-Bit System-on-Chip
FEATURES
- ARM922T™ Core: – 32-bit ARM9TDMI™ RISC Core (200 MHz) – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) 80KB On-Chip Memory Vectored Interrupt Controller External Bus Interface – 100 MHz – Asynchronous SRAM/ROM/Flash – Synchronous DRAM/Flash – PCMCIA – Compact Flash Clock and Power Management – 32.768 kHz and 14.7456 MHz Oscillators – Programmable PLL Low Power Modes – Run (200 mA), Halt, Standby (35 µA) Programmable LCD Controller – Up to 1,024 × 768 Resolution – Supports STN, Color STN, HR-TFT, TFT – Up to 64 k-Colors and 15 Gray Shades 10 Channel, 10-bit A/D Converter – Touch Screen Controller – Brownout Detector DMA (12 Channels) – External DMA Channels – AAC (AC97) –M M C –U S B USB Host and Device Interface (USB1.1) Synchronous Serial Port (SSP) – Motorola SPI™ – Texas Instruments SSI – National MICROWIRE™ PS/2 Keyboard/Mouse Interface (KMI) Three Programmable Timers Three UARTs – Classic IrDA (115 kbit/s) Smart Card Interface (ISO7816) Four Pulse Width Modulators (PWMs) MultiMediaCard Interface with Secure Digital (MMC 2.11/SD 1.0) AAC (AC97) Codec Interface Smart Battery Monitor Interface Real Time Clock (RTC) Up to 64 General Purpose I/O Channels Programmable Interrupt Controller Watchdog Timer JTAG Debug Interface and Boundary Scan Operating Voltage – 1.8 V Core – 3.3 V Input/Output (1.8 V I/O Optional*) Temperature – 0°C to +70°C Commercial – -40°C to +85°C Industrial (With Clock Frequency Reduction*) 324-Ball PBGA Package
DESCRIPTION
The advent of 3G technology opens the door for a wide range of Multimedia applications in mobile infor- mation appliances. These appliances require high pro- cessing performance and low power consumption. The LH7A404 is designed from the ground up to provide high processing performance, low power consumption, and a high level of integration. The LH7A404 contains a high performance 32-bit ARM922T Core. Power consumption is reduced by the high level of integration, 80KB on-chip SRAM, fully static design, power management unit, low voltage operation (1.8 V Core, 1.8 V or 3.3 V I/O) and on-chip PLL. Motorola SPI is a trademark of Motorola, Inc. National Semiconductor MICROWIRE is a trademark of National Semiconductor Corporation. ARM922T and ARM 9TDMI are trademarks of Advanced RISC Machines (ARM) Ltd. Windows CE is a trademark of Microsoft Corporation. NOTE: *Under development. Results pending further characterization.
2 Advance Data Sheet
Figure 1. LH7A404 Block Diagram
Table 1. Functional Pin List
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Table 1. Functional Pin List (Cont’d)
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GPIO Port F and Smart Card Interface. Can be used for external interrupts.
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- Signals beginning with ‘n’ are Active LOW.
- The SCLK pin can source up to 16 mA and sink up to 24 mA.
- The Intensity bit is identically generated for all three colors.
Table 2. LCD Pin Muxing
Table 3. Detailed Pin List
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Table 3. Detailed Pin List (Cont’d)
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prior to entering the Standby state.
Manual’, available on ARM’s website at www.arm.com. power-down operations and real time clock peripheral. depends on the power saving mode selected. counter using a ripple divider to save power. erates the following clocks: FCLK, HCLK, and PCLK. FCLK is the clock that drives the ARM922T core. ated by dividing HCLK by either 2, 4, or 8. Figure 2. Application Diagram
20 Advance Data Sheet
halted while it waits for an event such as a key press. then take appropriate actions. AHB (AMBA AHB) is a high speed 32-bit-wide data bus. buffers and bus holders and simplifies bus arbitration. Figure 3. Clock and State Controller Block Diagram
14.7456 MHz
wide, high speed gateway to external memory devices. given to the Synchronous Memory Controller interface. ded memory and the synchronous memory controller. In both cases the LCD bus is given priority. APB. The rest of the memory space is not used. system for the two boot modes. set the interrupt vector table. Table 4. Boot Modes
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Figure 4. Memory Mapping for Each Boot Mode
6000.0000 PCMCIA (SLOT1)
with a simple interrupt controller. existing access has been completed. See Figure 5. Figure 5. External Bus Interface Block Diagram
LH7A404 32-Bit System-on-Chip
24 Advance Data Sheet
The LH7A404 incorporates 80KB of embedded SRAM. This embedded memory is used for storing code, data, or LCD frame data and is contiguous with external SDRAM. The 80KB is large enough to store a QVGA panel (320 × 240) at 8 bits per pixel, equivalent to 70KB of information. Locating the frame buffer on chip reduces the overall power consumed by any application that uses the LH7A404. Normally, the system performs external accesses to acquire this data. The LCD controller auto- matically uses an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any 4KB page boundary in SDRAM, allowing software to set the MMU (in the LCD control- ler) page tables such that the two memory areas appear contiguous. Byte, half-word and word accesses are permissible. Static Memory Controller (SMC) The asynchronous Static Memory Controller (SMC) provides an interface between the AMBA AHB system bus and external (off-chip) memory devices. The SMC simultaneously supports up to eight inde- pendently configurable memory banks. Each memory bank can support: S R A M R O M Flash EPROM Burst ROM memory. Each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. The memory controller can be configured to support either little- endian or big-endian operation. The memory banks can be configured to support: Non-burst read and write accesses only to high- speed CMOS static RAM Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. The SMC has six main functions: Memory bank select Access sequencing Wait state generation Byte lane write control External bus interface Compact Flash or PCMCIA interfacing. SDRAM (Synchronous) Memory Controller The SDRAM (Synchronous) Memory Controller pro- vides a high speed memory interface to a wide variety of synchronous memory devices, including Synchro- nous DRAM, Synchronous Flash and Synchronous ROMs. The key features of the controller are: LCD DMA port for high bandwidth Up to four Synchronous Memory banks can be inde- pendently set up Includes special configuration bits for Synchronous ROM operation Includes ability to program Synchronous Flash devices using write and erase commands On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset Data is transferred between the controller and the Synchronous DRAM in four-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst Programmable for 16- or 32-bit data bus size Two reset domains enable Synchronous DRAM con- tents to be preserved over a ‘soft’ reset Power saving Synchronous Memory SCKE and external clock modes provided. Secure Digital/MultiMediaCard (MMC) The SD Memory Card (Secure Digital Memory Card) is a flash-based memory card that meets the security, capacity, performance, and environment requirements inherent in electronic devices. The SD Memory Card host supports MultiMediaCard (MMC) operation as well and is forward compatible. The main difference between SD Card and MMC is the initialization process. The Secure Digital and MMC adapter can be used as an MMC card or as an SD card and supports the full MMC/SD bus protocol as defined in the MMC system specification 2.11 provided by the MMC Definition Group and the SD Memory Card Spec v1.0 from the SD group. The controller can also implement the SPI inter- face to the cards. SD/MMC INTERFACE DESCRIPTION The SD/MMC controller uses the three-wire serial data bus (clock, command, and data) to input and out- put data to and from the MMC card, and to configure and acquire status information from the card’s regis- ters. The SD differs only in that it has four data lines.
32-Bit System-on-Chip LH7A404 Advance Data Sheet 25 The SD/MMC bus lines can be divided into three groups: Power supply: VSS1, VSS2 and VDD Data transfer: MMCCMD, MMCDAT0, MMCDAT1, MMCDAT2, MMCDAT3 (for MMC, do not use MMCDAT1, MMCDAT2, MMCDAT3) Clock: MMCCLK MMC bus lines can be divided into three groups: Power supply: VDD and VSS Data Transfer: MMCCMD, MMCDATA Clock: MMCLK. MMC ADAPTER The MMC Adapter implements MMC specific func- tions, serves as the bus master for the MMC Bus and implements the standard interface to the MMC Cards (card initialization, CRC generation and validation, command/response transactions, etc.). Smart Card Interface (SCI) The SCI (ISO7816) connects to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES Supports asynchronous T0 and T1 transmission pro- tocols Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported Eight-character-deep buffered Tx and Rx paths Direct interrupts for Tx and Rx FIFO level monitoring Interrupt status register Hardware-initiated card deactivation sequence on detection of card removal Software-initiated card deactivation sequence on transaction complete Limited support for synchronous smart cards via reg- istered input/output. PROGRAMMABLE PARAMETERS Smart card clock frequency Communication baud rate Protocol convention Card activation/deactivation time Check for maximum time for first character of Answer to Reset (ATR) reception Check for maximum duration of ATR character stream Check for maximum time of receipt of first character of data stream Check for maximum time allowed between characters Character guard time Block guard time Transmit/receive character retry. Direct Memory Access Controller (DMA) The DMA Controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels which consist of five M2P (transmit) channels and five P2M (receive) channels. The following peripherals may be allocated to the 10 channels: USB Device USB Host SD/MMC AAC U A R T 1 U A R T 2 U A R T 3 Each of the above peripherals contain one Tx and one Rx channel, except the AAC, which contains three Tx and Rx channels. These peripherals also have their own bi-directional DMA bus, capable of simultaneously transferring data in both directions. All memory trans- fers take place via the main system AHB bus. The DMA Controller can also be used to interface streams from memory-to-memory (M2M) or memory- to-external peripheral (M2P) using two dedicated M2M channels. External handshake signals are available to suport memory-to-/from-external peripheral (M2P/ P2M) transfers. A software trigger is available for M2M transfers only.
LH7A404 32-Bit System-on-Chip
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The DMA features: Two dedicated channels for M2M and external M2P/ P2M Ten fully independent, programmable DMA control- ler internal M2P/P2M channels (5 Tx and 5 Rx) Channels assignable to one of a number of different peripherals Independent source and destination address regis- ters. Source and destination can be programmed to auto-increment or not auto-increment for M2M chan- nels Two buffer descriptors per M2P and M2M channel to avoid potential data under/over-flow due to software introduced latency. A buffer refers to the area in sys- tem memory that is characterized by a buffer descriptor, ie., a start address and the length of the buffer in bytes No AMBA wrapping bursts for DMA channels; only incrementing bursts are supported Buffer size independent of the peripheral’s packet size for the internal M2P channels. Transfers can automatically switch between buffers Maskable interrupt generation Internal arbitration between DMA channels, plus support for an AHB bus arbiter DMA data transfer sizes, byte, word and quad-word data transfers are supported using a 16-byte data bay. Maximum data transfer size per M2M channel is programmable Per-channel clock gating reducing power in chan- nels that have not been enabled by software. See the ‘Clock and State Controller’ section. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. System interrupts are gen- erated when any/all of the DMA channels wish to inform the processor to update the buffer descriptor. The DMA controller can service 10 out of 20 possible peripherals using the ten DMA channels, each with its own peripheral DMA bus capable of simultaneously transferring data in both directions. The SD/MMC, UART1/2/3, USB Device, and USB Host peripherals can each use two DMA channels, one for transmit and one for receive. The AAC peripheral can use six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. The DMA controller includes an M2M transfer fea- ture allowing block moves of data from one memory address space to another with minimum of program effort and time. An M2M software trigger capability is provided. The DMA controller can also fill a block of memory with data from a single location. The DMA controller’s M2M channels can also be used in M2P/P2M mode. A set of external handshake signals, DREQ, DACK and TC/DEOT are provided for each of two M2M channels. DREQ (input) can be programmed edge or level active, and active HIGH or LOW. The peripheral may hold DREQ active for the duration of the block transfers or may assert/deassert on each transfer. DACK (output) can be programmed active HIGH or LOW. DACK will assert and return to de-asserted with each Read or Write, the timing coinciding with nOE or nWE from the EBI. TC/DEOT is a bidirectional signal with programma- ble direction and active polarity. When configured as an Output, the DMA will assert Terminal Count (TC) on the final transfer to coincide with the DACK, typically when the byte count has expired. When configured as an Input, the peripheral must assert DEOT concurrent with DREQ for the final transfer in the block. Transfer is terminated when DEOT is asserted by the external peripheral or when the byte count expires, whichever occurs first. Status bits indicate if the actual byte count is equal to the programmed limit, and if the count was terminated by peripheral asserting DEOT. Terminating the transfer causes a DMA interrupt on that channel and rollover to the ‘other’ buffer if so con- figured. For byte- or word-wide peripherals, the DMA is pro- grammed to request byte- or word-wide AHB transfers respectively. The DMA does not issue an AHB HREQ for a transfer until it has DREQ asserted after a DACK for the previous transfer; and the previous transfer has been asserted for the duration of the programmed wait states in the SMC (and possibly DREQ is sampled in the cycle DACK is deasserted). USB Device The features of the USB are: Fully compliant to USB 1.1 specification Provides a high-level interface that shields the firm- ware from USB protocol details Compatible with both OpenHCI and Intel UHCI standards Supports full-speed (12 Mbps) functions Supports Suspend and Resume signalling.
32-Bit System-on-Chip LH7A404 Advance Data Sheet 27 USB Host Controller The features of the USB Host Controller are: Open Host Controller Interface Specification (Open- HCI) Rev. 1.0 compatible Universal Serial Bus Specification Rev. 1.1 compatible Support for both Low Speed and High Speed USB devices Root Hub has two Downstream Ports DMA functionality. Color LCD Controller The LH7A404’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A404’s LCD Controller incorporates the timing conversion logic from TFT to HR-TFT, allowing a direct interface to HR- TFT and minimizing external chip count. The Color LCD Controller features support for: Up to 1,024 × 768 Resolution 16-bit Video Bus STN, Color STN, HR-TFT, TFT panels Single and Dual Scan STN panels Up to 15 Gray Shades Up to 64 k-Colors Advanced Audio Codec (AAC) The Advanced Audio Codec controller (AC97) includes a 5-pin serial interface to an external audio codec. The AAC link is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AAC controller contains logic that controls the AAC link to the audio codec and an interface to the AMBA APB. Its main features include: Serial-to-parallel conversion for data received from the external codec Parallel-to-serial conversion for data transmitted to the external codec Reception/transmission of control and status infor- mation via the AMBA APB interface Support for up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored indepen- dently in both transmit and receive modes. The out- going data for the FIFOs can be written via either the APB interface or with DMA channels 1-3. Audio Codec Interface (ACI) The ACI provides: A digital serial interface to an off-chip 8-bit codec All the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the codec device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchroniza- tion output signal that is coincident with the bit clock. Pulse Width Modulator (PWM) The Pulse Width Modulator features: Configurable dual output Separate input clocks for each PWM output 16-bit resolution Programmable synchronous mode support – Allows external input to start PWM Programmable pulse width (duty cycle), interval (fre- quency), and polarity – Static programming: when the PWM is stopped – Dynamic programming: when the PWM is running – Updates duty cycle, frequency, and polarity at end of a PWM cycle The PWM is a configurable dual-output, dual-clock- input AMBA slave module, and connects to the APB.
LH7A404 32-Bit System-on-Chip
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Synchronous Serial Port (SSP) The SSP is a master-only interface for synchro- nous serial communication with peripheral devices that have either Motorola SPI, National Semicon- ductor MICROWIRE, or Texas Instruments Synchronous Serial Interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO mem- ories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A404 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usu- ally be determined by peripheral device’s capability. UART/IrDA The LH7A404 contains three UARTs; UART1, UART2, and UART3. The UART performs: Serial-to-Parallel conversion on data received from the peripheral device Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths can both be routed through the DMA separately or simultaneously, and are buffered with internal FIFO memories. This allows up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: Four individually maskable interrupts from the receive, transmit and modem status logic blocks A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is pre- vented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Timers The LH7A404 includes three programmable timers. Each of the timers can operate in two modes: free run- ning and pre-scale. The timers are programmed using four registers; Load, Value, Control, and Clear. Two identical timers, Timer 1 (TC1) and Timer 2 (TC2), use clock sources of either 508 kHz or 2 kHz. The clock source and mode is selectable by writing to the appropriate bits in the system control register. Each timer has a 16-bit read/write data register and a control register. The timer is loaded with the value written to the data register immediately. This value is then decre- mented on the next active clock edge to arrive after the write. When the timer underflows, it immediately asserts its appropriate interrupt. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. Once the timer has been enabled and written to, it decrements on the next rising edge of the 7.3728 MHz clock after the data register has been updated. FREE-RUNNING MODE In free-running mode, the timer wraps around to 0xFFFF when it underflows and continues counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a pro- grammable frequency to drive the buzzer or generate a periodic interrupt. Real Time Clock (RTC) The RTC provides a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed num- ber of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC.
32-Bit System-on-Chip LH7A404 Advance Data Sheet 29 Keyboard and Mouse Interface (KMI) The Keyboard and Mouse Interface has the follow- ing features: IBM PS2 or AT-compatible keyboard or mouse inter- face Half-duplex bidirectional synchronous serial inter- face using open-drain outputs for clock and data. Programmable 4-bit reference clock divider Polled or interrupt-driven mode Separately maskable transmit and receive interrupts Single combined interrupt output Odd parity generation and checking Register bits for override of keyboard clock and data lines. Additional test registers and modes are implemented for functional verification and manufacturing test. Touch Screen Controller (TSC) The Touch Screen Controller is a complete interface to a touch screen as used in portable personal devices. It combines the front-end biasing and control circuitry with analog-to-digital conversion, reference genera- tion, and digital control and interface functions to com- pletely replace external ICs used to implement this interface. The features are: 10-bit A/D converter with integrated sample-and- hold, fully differential, high impedance signal and ref- erence inputs. Input active matrix for bias and control circuits nec- essary for connection to external 4- and 5-wire touch sensitive panels. Auxiliary functions such as temperature sense, pen pressure sense, battery voltage sense, in addition to normal direct voltage inputs. A 10-channel multiplexer for routing user-selected inputs to A/D 16 × 16 FIFO for 10-bit digital output of A/D Pen down sensor to generate interrupts to the host Low power circuitry and power control modes to min- imize in-system power dissapation. Conversion automation to maximize flexibility while minimizing CPU management and interrupt overhead Supply voltage 3.0 V - 3.6 V Configurable input pads so that when an Analog input is not being used, the pad can be used as a GPIO. Battery Monitor Interface (BMI) The BMI is a serial communication interface speci- fied for two types of battery monitors/gas gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. SINGLE WIRE INTERFACE The Single Wire Interface performs: Serial-to-parallel conversion on data received from the peripheral device Parallel-to-serial conversion on data transmitted to the peripheral device Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol in which the host initiates a data transfer by sending a WriteData/Command word to the battery monitor. This word always contains the command sec- tion, which tells the Single Wire Interface device the location for the current transaction. The most signifi- cant bit of the command determines if the transaction is Read or Write. In the case of a Write transaction the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The Smart Battery Interface performs: Serial-to-parallel conversion on data received from the peripheral device Parallel-to-serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multi- master bus (the SMBus), allowing multiple bus masters to be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism by relying on the wired-AND connection of all SMBus interfaces to the SMBus.
LH7A404 32-Bit System-on-Chip
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The features of the DC-DC Converter interface are: Dual drive PWM outputs with independent closed loop feedback Software programmable configuration of one of 8 output frequencies (each being a fixed division of the input clock). Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. Hardware-configured output polarity (for positive or negative voltage generation) during power-on reset via the polarity select inputs Dynamically switched PWM outputs to one of a pair of preprogrammed frequency/duty cycle combina- tions via external pins. Watchdog Timer (WDT) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause an FIQ interrupt. Failure to service the FIQ interrupt generates a system reset. Features of the WDT: Timing derived from the system clock 16 programmable time-out periods: 2 16 through 231 clock cycles Generates a system reset (resets LH7A404) or a FIQ interrupt whenever a time-out period is reached Software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes Protection mechanism guards against interrupt-ser- vice-failure: – The first WDT time-out triggers FIQ and asserts nWDFIQ status flag – If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a system reset. General Purpose I/O (GPIO) The GPIO has eight ports, each with a data register and a data direction register. It also has added regis- ters including Keyboard Scan, PINMUX, GPIO Inter- rupt Enable, INTYPE1/2, GPIOFEOI and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and the GPIOFEOI registers control edge-triggered Interrupts on Port F. The PINMUX register controls which signals are from Port D and Port E when they are set as out- puts, while the PGHCON controls the operations of Port G and Port H.
32-Bit System-on-Chip LH7A404 Advance Data Sheet 31 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings NOTE: These stress ratings are only for transient conditions. Oper- ation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operat ing Conditions NOTES: 1. Core Voltage should never exceed I/O Voltage. 2. Using 14.756 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal. 3. Commercial Temperature Range. 4. VDDC = 1.62 V to 1.98 V. 5. VDD = 3.0 V to 3.6 V. 6. With Clock Frequency Reduction. The LH7A404 has not yet been characterized for the Industrial Temperature Range. 7. Using the LH7A404 below VDD = 3.0 V will affect the AC timing and the USB will not function. AC timing for VDD less than 3.0 V has not yet been characterized. PARAMETER MINIMUM MAXIMUM DC Core Supply Voltage (VDDC) - 0.3 V 2.4 V DC I/O Supply Voltage (VDD) - 0.3 V 4.6 V DC Analog Supply Voltage (VDDA1, VDDA2) - 0.3 V 2.4 V DC Analog Supply Voltage (VDDA3) - 0.3 V 4.6 V Storage Temperature -55°C 125°C PARAMETER MINIMUM TYPICAL MAXIMUM NOTES DC Core Supply Voltage (VDDC) 1.62 V 1.8 V 1.98 V 1 DC I/O Supply Voltage (VDD) 1.62 V 3.3 V 3.6 V 7 DC Analog Supply Voltage (VDDA1, VDDA2) 1.62 V 1.8 V 1.98 V DC Analog Supply Voltage (VDDA3) 3.0 V 3.3 V 3.6 V Clock Frequency 10 MHz 200 MHz 2, 3, 4, 5 Commercial Operating Temperature 0°C 25°C +70°C Industrial Operating Temperature -40°C 25°C +85°C 6
LH7A404 32-Bit System-on-Chip
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DC/AC SPECIFICAT IONS (COMMERCIAL) Unless otherwise noted, all data provided under commercial DC/AC specifications are based on 0°C to +70°C, VDDC = 1.62 V to 1.98 V, VDD = 3.3 V to 3.6 V, VDDA1 and VDDA2 = 1.62 V to 1.98 V; VDDA3 = 3.0 to 3.6 V. DC Specifications NOTES: 1. Output Drive 5 can sink 24 mA of current, but sources 16 mA of current. 2. Both oscillators running, LCD Active; all other peripherals stopped. 3. 32 kHz oscillator running; all other peripherals stopped. 4. Current consumption until oscillators are stabilized. AC Test Conditions SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS NOTES VIH CMOS and Schmitt Trigger Input HIGH Voltage 2.0 V VIL CMOS and Schmitt Trigger Input LOW Voltage 0.8 V VHST Schmitt Trigger Hyst eresis 0.35 V VIL to VIH VOH CMOS Output HIGH Voltage, Output Drive 1 2.6 3.6 V IOH = 2 mA Output Drive 2 2.6 3.6 V IOH = 4 mA Output Drive 3 2.6 3.6 V IOH = 8 mA Output Drive 4 and 5 2.6 3.6 V IOH = 16 mA 1 VOL CMOS Output LOW Voltage, Output Drive 1 0.0 0.4 V IOL = 2 mA Output Drive 2 0.0 0.4 V IOL = 4 mA Output Drive 3 0.0 0.4 V IOL = 8 mA Output Drive 4 0.0 0.4 V IOL = 16 mA Output Drive 5 0.0 0.4 V IOL = 24 mA 1 IIN Input Leakage Current -10 10 µA VIN = VDD or GND IOZ Output Tri-state Leakage Current -10 10 µA VOUT = VDD or GND IACTIVE Active Current (Operating Current) 180 mA IHALT Halt Current 6.0 mA 2 ISTANDBY Standby Current 20 µA3 ISTARTUP Startup Current 50 µA4 CIN Input Capacitance 4 pF COUT Output Capacitance 4 pF PARAMETER RATING UNIT DC I/O Supply Voltage (VDD) 3.0 to 3.6 V DC Core Supply Voltage (VDDC) 1.62 to 1.98 V Input Pulse Levels VSS to 3 V Input Rise and Fall Times 2 ns Input and Output Timing Reference Levels VDD/2 V
SCLK, the Synchronous Memory clock. point of the clock to the 50% point of the signal. valid from the rising edge of the reference clock signal. requirements for tOHXXX are listed in Table 5. for tISXXX are shown in Table 5. requirements are shown in Table 5. Figure 6. LH7A404 Signal Timing Table 5. AC Signal Characteristics
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- TBD = To Be Determined, awaiting characterization.
- For Output Drive strength specifications, refer to ‘DC Specifications’.
Table 5. AC Signal Characteristics (Cont’d)
memory Read, with two wait states. Figure 7. External Asynchronous Memory Write Figure 8. External Asynchronous Memory Read, One Wait State
- All signal transitions are measured from the
50% point of the clock to the 50% point of the signal.
1 WAIT STATE
50% point of the clock to the 50% point of the signal.
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Figure 9. External Asynchronous Memory Read, Two Wait States
2 WAIT STATES
50% point of the clock to the 50% point of the signal.
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length, depending upon the programmed data size. device on the falling edge. See Figure 12 and Figure 13. Figure 12. Texas Instruments Synchronous Serial Frame Format (Single Transfer) Figure 13. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer)
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Figure 17. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 Figure 18. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 Figure 19. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0
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13 to 25 bits. See Figure 22 and Figure 23. Figure 22. MICROWIRE Frame Format (Single Transfer) Figure 23. MICROWIRE Frame Format (Continuous Transfers)
44 Advance Data Sheet
Figure 25. PCMCIA Attribute Memory Write Transfer
Figure 26. PCMCIA Common Memory Read Transfer
46 Advance Data Sheet
Figure 27. PCMCIA Common Memory Write Transfer
48 Advance Data Sheet
Table 6. Reset AC Timing Figure 31. PLL Start-up Figure 32. External Reset
32-Bit System-on-Chip LH7A404 Advance Data Sheet 49 DC/AC SPECIFICAT IONS (INDUSTRIAL) To be determined.
50 Advance Data Sheet
Figure 33. 324-Ball PBGA Package Specification
3 PLACES
4 PLACES
LH7A404 32-Bit System-on-Chip ©2002 by SHARP Corporation Reference Code SMA02004 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3
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