SCH-V

LH28F008SC-V SHARP | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 40

Technical content

DESCRIPTION

The LH28F008SC-V/SCH-V flash memories with Smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SC-V/SCH-V offer three levels of protection : absolute protection with V PP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs.

FEATURES

• Smart 5 technology –5 V VCC – 5 V or 12 V VPP
• High performance read access time LH28F008SC-V85/SCH-V85 LH28F008SC-V12/SCH-V12
• Enhanced automated suspend options – Byte write suspend to read – Block erase suspend to byte write – Block erase suspend to read
• Enhanced data protection features – Absolute protection with V PP = GND – Flexible block locking – Block erase/byte write lockout during power transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture – Sixteen 64 k-byte erasable blocks
• Enhanced cycling capability – 100 000 block erase cycles – 1.6 million block erase cycles/chip
• Low power management – Deep power-down mode – Automatic power saving mode decreases ICC in static mode
• Automated byte write and block erase – Command user interface – Status register
• ETOXTM * V nonvolatile flash technology
• Packages – 40-pin TSOP Type I (TSOP040-P-1020) Normal bend/Reverse bend – 44-pin SOP (SOP044-P-0600) – 48-ball CSP (FBGA048-P-0608) * ETOX is a trademark of Intel Corporation. - 1 - In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. LH28F008SC-V/SCH-V

8 M-bit (1 MB x 8) Smart 5

DC CHARACTERISTICSVERSIONS OPERATING TEMPERATURE VCC deep power-down current (MAX.) LH28F008SC-V 0 to +70 ˚C 10 µA LH28F008SCH-V –25 to +85 ˚C 20 µA COMPARISON TABLE

• 2 - 44-PIN SOP (SOP044-P-0600) VPP RP# A11 A10 NC NC A DQ 0 DQ 1 DQ 2 DQ 3 GND GND VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE# OE# RY/BY# DQ DQ 6 DQ 5 DQ 4 VCC 40-PIN TSOP (Type I) (TSOP040-P-1020) A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 NC NC WE# OE# RY/BY# DQ DQ 6 DQ 5 DQ 4 VCC GND GND DQ DQ 2 DQ 1 DQ 0 A A6B A4C A3D A1E DQ 1 DQ 0 A11 VPP VCC A10 DQ 2 GND DQ 3 NC NC NC GND NC NC NC NC V CC A12 CE# A13 DQ 6 DQ 4 DQ 5 A15 A14 A16 RY/BY# DQ 7 NC A18 A17 A19 NC OE# WE#F NC RP# (FBGA048-P-0608) 48-BALL CSP NOTE : Reverse bend available on request. TOP VIEW PIN CONNECTIONS

• 3 - BLOCK DIAGRAM Y GATINGY DECODERINPUT BUFFER OUTPUT BUFFER DQ 0-DQ 7 VCC CE# WE# OE# RP# ADDRESS LATCH DATA COMPARATOR PROGRAM/ERASE VOLTAGE SWITCH STATUS REGISTER COMMAND USER INTERFACE WRITE STATE MACHINE DATA REGISTER OUTPUT MULTIPLEXER IDENTIFIER REGISTER ADDRESS COUNTER A0-A19 X DECODER 64 k-BYTE BLOCKS RY/BY# VCC GND VPP INPUT BUFFER I/O LOGIC

• 4 - SYMBOL TYPE NAME AND FUNCTION A0-A19 INPUT ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. INPUT/ DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provide data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at V HH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIH ≤ RP# ≤ VHH produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE : Gates the device's outputs during a read cycle. WE# INPUT WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, byte write, or lock-bit configuration). RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes, or configuring lock-bits. With V PP ≤ VPPLK , memory contents cannot be altered. Block erase, byte write, and lock-bit configuration with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation. Do not float any power pins. With VCC ≤ VLKO , all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS" ) produce spurious results and should not be attempted. GND SUPPLY GROUND : Do not float any ground pins. NC NO CONNECT : Lead is not internal connected; recommend to be floated. OUTPUTDQ 0-DQ7 PIN DESCRIPTION RP# INPUT RY/BY# OUTPUT VPP SUPPLY VCC SUPPLY

5 V 5 V, 12 V

1 INTRODUCTION

This datasheet contains LH28F008SC-V/SCH-V specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SC-V/ SCH-V flash memories documentation also includes ordering information which is referenced in Section 7.

1.1 New Features

LH28F008SC-V/SCH-V Smart 5 flash memories maintain backwards-compatibility with the LH28F008SA. Key enhancements over the LH28F008SA include :

• Smart 5 Technology
• Enhanced Suspend Capabilities
• In-System Block Locking Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the LH28F008SA to LH28F008SC-V/SCH-V. When upgrading, it is important to note the following differences :
• Because of new feature support, the two devices have different device codes. This allows for software optimization.
• V PPLK has been lowered from 6.5 V to 1.5 V to support 5 V block erase, byte write, and lock-bit configuration operations. Designs that switch V PP off during read operations should make sure that the VPP voltage transitions to GND.
• To take advantage of Smart 5 technology, allow VPP connection to 5 V.

1.2 Product Overview

The LH28F008SC-V/SCH-V are high-performance

8 M-bit Smart 5 flash memories organized as 1 M-

byte of 8 bits. The 1 M-byte of data is arranged in sixteen 64 k-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Fig.1. Smart 5 technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. VPP at 5 V eliminates the need for a separate 12 V converter, while V PP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK . Table 1 VCC and VPP Voltage Combinations Offered by Smart 5 Technology Internal VCC and V PP detection circuitry auto- matically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the device’s 64 k-byte blocks typically within 1 second (5 V VCC , 12 V VPP ) independent of other blocks. Each block can be independently erased 100 000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. Writing memory data is performed in byte increments typically within 6 µs (5 V V CC , 12 V VPP ). Byte write suspend mode enables the system - 5 -

to read data from, or write data to any other flash memory array location. Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM’s block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. The access time is 85 ns (t AVQV ) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70˚C (LH28F008SC-V)/ –25 to +85˚C (LH28F008SCH-V). At 4.5 to 5.5 V V CC , the access time is 90 ns or 120 ns. The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I CCR current is 1 mA at 5 V VCC . When CE# and RP# pins are at V CC , the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (t PHQV ) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL ) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. Fig. 1 Memory Map 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block FFFFF F0000 EFFFF E0000 DFFFF CFFFF D0000 C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 - 6 -

2 PRINCIPLES OF OPERATION

The LH28F008SC-V/SCH-V Smart 5 flash memories include an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the V PP voltage. High voltage on VPP enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contents—block erase, byte write, lock-bit configuration, status, and identifier codes—are accessed via the CUI and verified through the status register. Commands are written using standard micro- processor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer may choose to make the V PP power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to V PPH1/2. The device accommodates either design practice and encourages optimization of the processor-memory interface. When V PP ≤ VPPLK , memory contents cannot be altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP . All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH . The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read - 7 -

array mode. Four control pins dictate the data flow in and out of the component : CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ 0-DQ 7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH . Fig. 12 illustrates a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ 7 are placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ 7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes.

3.4 Deep Power-Down

RP# at VILinitiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time t PHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP ’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. - 8 -

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When V PP = VPPH1/2, the CUI additionally controls block erasure, byte write, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 13 and Fig. 14 illustrate WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK , read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2 on V PP enables successful block erase, byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. FFFFF F0004 F0003 F0002 F0001 F0000 1FFFF 10004 10003 10002 10001 10000 0FFFF 00004 00003 00002 00001 00000 Reserved for Future Implementation Block 15 Lock Configuration Code Block 15 Block 1 Block 0 (Blocks 2 through 14) Reserved for Future Implementation Reserved for Future Implementation Block 1 Lock Configuration Code Reserved for Future Implementation Reserved for Future Implementation Master Lock Configuration Code Block 0 Lock Configuration Code Device Code Manufacture Code - 9 -

• 10 - MODE NOTE RP# CE# OE# WE# ADDRESS VPP DQ 0-7 RY/BY# Read 1, 2, 3, 8 VIH or VHH VIL VIL VIH XX D OUT X Output Disable 3 VIH or VHH VIL VIH VIH X X High Z X Standby 3 VIH or VHH VIH XXXX High Z X Deep Power-Down 4 V IL XXXXX High Z V OH Read Identifier Codes 8 VIH or VHH VIL VIL VIH See Fig. 2 X( NOTE 5) VOH Write 3, 6, 7, 8 VIH or VHH VIL VIH VIL XX D IN X Table 2 Bus Operations NOTES : 1. Refer to Section 6.2.3 "DC CHARACTERISTICS" . When V PP ≤ VPPLK , memory contents can be read, but not altered. 2. X can be VILor VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP . See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2 voltages. 3. RY/BY# is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is V OH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. 4. RP# at GND±0.2 V ensures the lowest deep power- down current. 5. See Section 4.2for read identifier code data. 6. Command writes involving block erase, byte write, or lock-bit configuration are reliably executed when V PP = VPPH1/2 and VCC = VCC1/2. Block erase, byte write, or lock-bit configuration with VIH < RP# < V HH produce spurious results and should not be attempted. 7. Refer to Table 3for valid DIN during a write operation. 8. Don ’t use the timing both OE# and WE# are VIL.

• 11 - NOTES : 1. Bus operations are defined in Table 2. 2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. BA = Address within the block being erased or locked. WA = Address of memory location to be written. 3. SRD = Data read from status register. See Table 6for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and master lock codes. See Section 4.2for read identifier code data. 5. If the block is locked, RP# must be at V HH to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is V IH. 6. Either 40H or 10H is recognized by the WSM as the byte write setup. 7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. 8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V IH. 9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. COMMAND BUS CYCLES NOTE FIRST BUS CYCLE SECOND BUS CYCLE REQ ’D. Oper (NOTE 1) Addr (NOTE 2) Data(NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data(NOTE 3) Read Array/Reset 1 Write X FFH Read Identifier Codes ‡ 2 4 Write X 90H Read IA ID Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase 2 5 Write BA 20H Write BA D0H Byte Write 2 5, 6 Write WA 40H or 10H Write WA WD Block Erase and 1 5 Write X B0HByte Write Suspend Block Erase and 1 5 Write X D0HByte Write Resume Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H Set Master Lock-Bit 2 7 Write X 60H Write X F1H Clear Block Lock-Bits 2 8 Write X 60H Write X D0H Table 3 Command Definitions(NOTE 9)

• 12 -

4.1 Read Array Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the V PP voltage and RP# can be VIH or VHH .

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2retrieve the manufacture, device, block lock configuration and master lock configuration codes (see Table 4for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the V PP voltage and RP# can be VIH or VHH . Following the Read Identifier Codes command, the following information can be read : Table 4 Identifier Codes NOTE : 1. X selects the specific block lock configuration code to be read. See Fig. 2for the device identifier code memory map.

4.3 Read Status Register Command

The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to V IH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH .

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V PP voltage. RP# can be VIH or VHH . This command is not functional during block erase or byte write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, CODE ADDRESS DATA Manufacture Code 00000H 89 Device Code 00001H A6 Block Lock ConfigurationX0002H (NOTE 1)

• Block is Unlocked DQ 0 = 0
• Block is Locked DQ 0 = 1
• Reserved for Future Use DQ 1-7 Master Lock Configuration 00003H
• Device is Unlocked DQ 0 = 0
• Device is Locked DQ 0 = 1
• Reserved for Future Use DQ 1-7

the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP ≤ VPPLK , SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH . If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to "1". Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.6 Byte Write Command

Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the byte write and write verify algorithms internally. After the byte write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the completion of the byte write event by analyzing the RY/BY# pin or status register bit SR.7. When byte write is complete, status register bit SR.4 should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable byte writes can only occur when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, memory contents are protected against byte writes. If byte write is attempted while V PP ≤ VPPLK , status register bits SR.3 and SR.4 will be set to "1". Successful byte write requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH . If byte write is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1". Byte write operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block erase interruption to read or byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to V OH . Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte - 13 -

Write Suspend command (see Section 4.8), a byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to V OL . However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V OL . After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 5). V PP must remain at VPPH1/2 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until byte write operations initiated during block erase suspend have completed.

4.8 Byte Write Suspend Command

The Byte Write Suspend command allows byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to V OH . Specification tWHRH1 defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V OL . After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Fig. 6). VPP must remain at VPPH1/2 (the same VPP level used for byte write) while in byte write suspend mode. RP# must also remain at V IH or VHH (the same RP# level used for byte write).

4.9 Set Block and Master Lock-Bit

A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = V HH , sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. See Table 5for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are executed by a two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Fig. 7). The CPU can detect the completion of the set lock- bit event by analyzing the RY/BY# pin output or status register bit SR.7. - 14 -

When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP# = VHH . If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP# = VHH . If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.10 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and V HH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock- bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Fig. 8). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock- Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when V CC = VCC1/2 and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP ≤ VPPLK , SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are protected against alteration. A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = V HH . If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with V IH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transition out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. - 15 -

• 16 - MASTER BLOCK OPERATION RP# EFFECTLOCK-BIT LOCK-BIT Block Erase 0V IH or VHH Block Erase and Byte Write Enabled or Byte Write X 1 VIH Block is Locked. Block Erase and Byte Write Disabled VHH Block Lock-Bit Override. Block Erase and Byte Write Enabled Set Block 0X V IH or VHH Set Block Lock-Bit Enabled Lock-Bit 1 X VIH Master Lock-Bit is Set. Set Block Lock-Bit Disabled VHH Master Lock-Bit Override. Set Block Lock-Bit Enabled Set Master XX VIH Set Master Lock-Bit Disabled Lock-Bit V HH Set Master Lock-Bit Enabled Clear Block 0X V IH or VHH Clear Block Lock-Bits Enabled Lock-Bits 1 X VIH Master Lock-Bit is Set. Clear Block Lock-Bits Disabled VHH Master Lock-Bit Override. Clear Block Lock-Bits Enabled Table 5 Write Protection Alternatives Table 6 Status Register Definition WSMS ESS ECLBS BWSLBS VPPS BWSS DPS R 76543210 SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) 1 = Error in Block Erase or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS (BWSLBS) 1 = Error in Byte Write or Set Master/Block Lock-Bit 0= Successful Byte Write or Set Master/Block Lock-Bit SR.3 = VPP STATUS (VPPS) 1=V PP Low Detect, Operation Abort 0=V PP OK SR.2 = BYTE WRITE SUSPEND STATUS (BWSS) 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTES : Check RY/BY# or SR.7 to determine block erase, byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of V PP level. The WSM interrogates and indicates the VPP level only after Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when V PP „ VPPH1/2. SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock- bit, block lock-bit, and RP# only after Block Erase, Byte Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not V HH . Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register.

• 17 - Block Erase Complete Start Write 20H, Block Address Write D0H, Block Address Read Status Register SR.7 = Full Status Check if Desired Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last block erase operation to place device in read array mode. BUS OPERATION Write Write Read Standby COMMAND Erase Setup COMMENTS Data = 20H Addr = Within Block to be Erased Data = D0H Addr = Within Block to be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy SR.3 = FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) VPP Range Error SR.1 = Device Protect Error1 BUS OPERATION COMMAND COMMENTS Standby Standby Check SR.1 1 = Device Protect Detect RP# = V IH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.5 1 = Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. No Suspend Block Erase Yes Suspend Block Erase Loop Erase Confirm Block Erase Successful SR.4, 5 = Command Sequence Error SR.5 = Block Erase Error Standby Check SR.3 1 = VPP Error Detect Standby Check SR.4, 5 Both 1 = Command Sequence Error Fig. 3 Automated Block Erase Flowchart

• 18 - Byte Write Complete Start Write 40H, Address Write Byte Data and Address Read Status Register SR.7 = Full Status Check if Desired Repeat for subsequent byte writes. SR full status check can be done after each byte write or after a sequence of byte writes. Write FFH after the last byte write operation to place device in read array mode. BUS OPERATION Write Write Read Standby COMMAND Setup Byte Write COMMENTS Data = 40H Addr = Location to be Written Data = Data to be Written Addr = Location to be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy SR.3 = FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) VPP Range Error SR.1 = Device Protect Error1 BUS OPERATION COMMAND COMMENTS Standby Check SR.1 1 = Device Protect Detect RP# = V IH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. No Suspend Byte WriteYes Suspend Byte Write Loop Byte Write Byte Write Successful SR.4 = Byte Write Error Standby Check SR.3 1 = VPP Error Detect Standby Check SR.4 1 = Data Write Error Fig. 4 Automated Byte Write Flowchart

• 19 - Block Erase Resumed Start Write B0H Read Status Register SR.7 = Byte Write BUS OPERATION Write Read Standby Standby COMMAND Erase Suspend COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Erase Resume SR.6 = Done? Write D0H Block Erase Completed Write FFH Read Array Data No Yes Write Data = D0H Addr = X Read or Byte Write? Read Read Array Data Byte Write Loop Fig. 5 Block Erase Suspend/Resume Flowchart

• 20 - Byte Write Resumed Start Write B0H Read Status Register SR.7 = Write FFH BUS OPERATION Write Read Standby Standby COMMAND Byte Write Suspend COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Byte Write Suspended 0 = Byte Write Completed Read Array SR.2 = Read Array Data Done Reading Write D0H Byte Write Completed Write FFH Read Array Data No Yes Write Read Write Byte Write Resume Data = FFH Addr = X Read array locations other than that being written. Data = D0H Addr = X Fig. 6 Byte Write Suspend/Resume Flowchart

• 21 - Set Lock-Bit Complete Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register SR.7 = Full Status Check if Desired Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode. BUS OPERATION Write Write Read Standby COMMAND Set Block/Master Lock-Bit Setup COMMENTS Data = 60H Addr = Block Address (Block), Device Address (Master) Data = 01H (Block), F1H (Master) Addr = Block Address (Block), Device Address (Master) Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy SR.3 = FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) VPP Range Error SR.1 = Device Protect Error BUS OPERATION COMMAND COMMENTS Standby Standby Check SR.1 1 = Device Protect Detect RP# = V IH (Set Master Lock-Bit Operation) RP# = VIH, Master Lock-Bit is Set (Set Block Lock-Bit Operation) Check SR.4 1 = Set Lock-Bit Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. Set Block or Master Lock-Bit Confirm Set Lock-Bit Successful SR.4, 5 = Command Sequence Error SR.4 = Set Lock-Bit Error Standby Check SR.3 1 = VPP Error Detect Standby Check SR.4, 5 Both 1 = Command Sequence Error Fig. 7 Set Block and Master Lock-Bit Flowchart

• 22 - Clear Block Lock-Bits Complete Start Write 60H Write D0H Read Status Register 0SR.7 = Full Status Check if Desired Write FFH after the last clear block lock-bits operation to place device in read array mode. BUS OPERATION Write Write Read Standby COMMAND Clear Block Lock-Bits Setup COMMENTS Data = 60H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy SR.3 = FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) VPP Range Error SR.1 = Device Protect Error BUS OPERATION COMMAND COMMENTS Standby Standby Check SR.1 1 = Device Protect Detect RP# = V IH, Master Lock-Bit is Set Check SR.5 1 = Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the status register before attempting retry or other error recovery. Clear Block Lock-Bits Confirm Clear Block Lock-Bits Successful SR.4, 5 = Command Sequence Error SR.5 = Clear Block Lock-Bits Error Standby Check SR.3 1 = VPP Error Detect Standby Check SR.4, 5 Both 1 = Command Sequence Error Fig. 8 Clear Block Lock-Bits Flowchart

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three- line control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.

5.2 RY/BY# and Block Erase, Byte Write,

and Lock-Bit Configuration Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. It transitions low after block erase, byte write, or lock- bit configuration commands and returns to V OH when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also V OH when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its V CC and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.

5.4 V PP Trace on Printed Circuit Boards

Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V PP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.

5.5 V CC , VPP , RP# Transitions

Block erase, byte write and lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2 range, VCC falls outside of a valid VCC1/2 range, or RP# ≠ VIH or VHH . If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, byte write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal - 23 -

operation is restored. Device power-off or RP# transitions to VILclear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power- down or after VCC transitions below VLKO . After block erase, byte write, or lock-bit configuration, even after VPP transitions down to VPPLK , the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon power- up, the device is indifferent as to which power supply (VPP or VCC ) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI’s two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = VIL regardless of its control inputs state.

5.7 Power Consumption

When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid- state storage can consume negligible power by lowering RP# to V IL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP# is first raised to VIH. See Section 6.2.4 through 6.2.6 "AC CHARACTERISTICS - READ-ONLY and WRITE OPERATIONS" and Fig. 12, Fig. 13and Fig. 14 for more information. - 24 -

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings*

• LH28F008SC-V During Read, Block Erase, Byte Write and Lock-Bit Configuration
• LH28F008SCH-V During Read, Block Erase, Byte Write and Lock-Bit Configuration...–25 to +85°C(NOTE 2) Voltage On Any Pin VPP Update Voltage during Block Erase, Byte Write and Lock-Bit Configuration..–2.0 to +14.0 V(NOTE 3, 4) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations..–2.0 to +14.0 V(NOTE 3, 4) *WARNING : Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES : 1. Operating temperature is for commercial product defined by this specification. 2. Operating temperature is for extended temperature product defined by this specification. 3. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and – 0.2 V on V CC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and V CC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns. 4. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods < 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. - 25 - SYMBOL PARAMETER NOTE MIN. MAX. UNIT VERSIONS TA Operating Temperature 1 0 +70 ˚C LH28F008SC-V –25 +85 ˚C LH28F008SCH-V VCC1 VCC Supply Voltage (5.0±0.25 V) 4.75 5.25 V LH28F008SC-V85/SCH-V85 VCC2 VCC Supply Voltage (5.0±0.5 V) 4.50 5.50 V

6.2 Operating Conditions

NOTE : 1. Test condition : Ambient temperature

• 26 - NOTE : 1. Sampled, not 100% tested.

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

Fig. 9 Transient Input/Output Reference Waveform for VCC = 5.0±0.25 V (High Speed Testing Configuration) Fig. 10 Transient Input/Output Reference Waveform for VCC = 5.0±0.5 V (Standard Testing Configuration) AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL(0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. SYMBOL PARAMETER TYP. MAX. UNIT CONDITION C IN Input Capacitance 6 8 pF V IN = 0.0 V C OUT Output Capacitance 8 12 pF V OUT = 0.0 V

6.2.1 CAPACITANCE (NOTE 1)

TA = +25˚C, f = 1 MHz 1.5 1.5 3.0 0.0 TEST POINTSINPUT OUTPUT 2.0 0.8 2.0 0.8 2.4 0.45 TEST POINTSINPUT OUTPUT DEVICE UNDER TEST C L Includes Jig Capacitance R L = 3.3 kΩ C L OUT 1.3 V 1N914 Fig. 11 Transient Equivalent Testing Load Circuit NOTE : 1. Applied to high-speed products, LH28F008SC-V85 and LH28F008SCH-V85. TEST CONFIGURATION C L (pF) VCC = 5.0±0.25 V(NOTE 1) 30 VCC = 5.0±0.5 V 100 Test Configuration Capacitance Loading Value

• 27 - LH28F008SC-V/SCH-V SYMBOL PARAMETER NOTE VCC = 5.0±0.5 V UNIT TEST TYP. MAX. CONDITIONS ILI Input Load Current 1 ±1 µA VCC = VCC Max. VIN = VCC or GND ILO Output Leakage Current 1 ±10 µA VCC = VCC Max. VOUT = VCC or GND CMOS Inputs 25 100 µA V CC = VCC Max. ICCS VCC Standby Current 1, 3, 6 CE# = RP# = VCC ±0.2 V TTL Inputs 0.4 2 mA V CC = VCC Max. CE# = RP# = VIH ICCD VCC Deep Power- LH28F008SC-V 1 10 µA RP# = GND±0.2 V Down Current LH28F008SCH-V 20 I OUT (RY/BY#) = 0 mA CMOS Inputs VCC = VCC Max. 17 35 mA CE# = GND f = 8 MHz ICCR VCC Read Current 1, 5, 6 IOUT = 0 mA TTL Inputs VCC = VCC Max. 20 50 mA CE# = GND f = 8 MHz IOUT = 0 mA ICCW VCC Byte Write or Set Lock-Bit Current1, 7 35 mA V PP = 5.0±0.5 V 30 mA V PP = 12.0±0.6 V ICCE VCC Block Erase or 1, 7 30 mA V PP = 5.0±0.5 V Clear Block Lock-Bits Current 25 mA V PP = 12.0±0.6 V ICCWS VCC Byte Write or 1, 2 1 10 mA CE# = V IH ICCES Block Erase Suspend Current IPPS VPP Standby or Read Current 1 ±2 ±15 µA V PP ≤ VCC IPPR 10 200 µA V PP > VCC IPPD VPP Deep Power-Down Current 1 0.1 5 µA RP# = GND±0.2 V IPPW VPP Byte Write or Set Lock-Bit Current1, 7 40 mA V PP = 5.0±0.5 V 15 mA V PP = 12.0±0.6 V IPPE VPP Block Erase or 1, 7 20 mA V PP = 5.0±0.5 V Clear Block Lock-Bits Current 15 mA V PP = 12.0±0.6 V IPPWS VPP Byte Write or 1 10 200 µA V PP = VPPH1/2 IPPES Block Erase Suspend Current

6.2.3 DC CHARACTERISTICS

• 28 - LH28F008SC-V/SCH-V 6.2.3 DC CHARACTERISTICS (contd.) NOTES : 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25˚C. These currents are valid for all product versions (packages and speeds). 2. ICCWS and ICCES are specified with the device de- selected. If reading or byte writing in erase suspend mode, the device’s current draw is the sum of I CCWS or ICCES and ICCR or ICCW , respectively. 3. Includes RY/BY#. 4. Block erases, byte writes, and lock-bit configurations are inhibited when VPP ≤ VPPLK , and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.), and above VPPH2 (max.). 5. Automatic Power Saving (APS) reduces typical ICCR to 1 mA at 5 V VCC in static operation. 6. CMOS inputs are either VCC ±0.2 V or GND±0.2 V. TTL inputs are either VILor VIH. 7. Sampled, not 100% tested. 8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and byte writes are inhibited when the corresponding block lock-bit is set and RP# = V IH. Block erase, byte write, and lock-bit configuration operations are not guaranteed with V IH < RP# < VHH and should not be attempted. 9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. SYMBOL PARAMETER NOTE VCC = 5.0±0.5 V UNIT TEST MIN. MAX. CONDITIONS VIL Input Low Voltage 7 –0.5 0.8 V VIH Input High Voltage 7 2.0 VCC V+0.5 VOL Output Low Voltage 3, 7 0.45 V VCC = VCC Min. IOL = 5.8 mA VOH1 Output High Voltage 3, 7 2.4 V VCC = VCC Min. (TTL) IOH = –2.5 mA 0.85 V VCC = VCC Min. VOH2 Output High Voltage 3, 7 VCC IOH = –2.5 mA (CMOS) VCC V VCC = VCC Min. –0.4 I OH = –100 µA VPPLK VPP Lockout Voltage during 4, 7 1.5 VNormal Operations VPPH1 VPP Voltage during Byte Write, 4.5 5.5 VBlock Erase or Lock-Bit Operations VPPH2 VPP Voltage during Byte Write, 11.4 12.6 VBlock Erase or Lock-Bit Operations VLKO VCC Lockout Voltage 2.0 V Set master lock-bit VHH RP# Unlock Voltage 8, 9 11.4 12.6 V Override master and block lock-bit

• 29 - tAVAV Read Cycle Time 85 90 120 ns tAVQV Address to Output Delay 85 90 120 ns tELQV CE# to Output Delay 2 85 90 120 ns tPHQV RP# High to Output Delay 400 400 400 ns tGLQV OE# to Output Delay 2 40 45 50 ns tELQX CE# to Output in Low Z 3 0 0 0 ns tEHQZ CE# High to Output in High Z 3 55 55 55 ns tGLQX OE# to Output in Low Z 3 0 0 0 ns tGHQZ OE# High to Output in High Z 3 10 10 15 ns Output Hold from Address, tOH CE# or OE# Change, 3 0 0 0 ns Whichever Occurs First LH28F008SC-V/SCH-V VERSIONS NOTES : 1. See AC Input/Output Reference Waveform (Fig. 9 and Fig. 10) for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV -tGLQV after the falling edge of CE# without impact on tELQV . 3. Sampled, not 100% tested. 4. See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit"(High Speed Configuration) for testing characteristics. 5. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)

VCC ±0.25 V VCC ±0.5 V (NOTE 4) LH28F008SC-V85/ LH28F008SCH-V85 (NOTE 5) LH28F008SC-V12/ LH28F008SCH-V12 (NOTE 5) LH28F008SC-V85/ LH28F008SCH-V85 UNIT

• 30 - VOL VOH Standby Device Address Selection Data Valid ADDRESSES (A) VIL VIL VIL VIH VIH VIH VIH VIL VIL CE# (E) OE# (G) WE# (W) DATA (D/Q) (DQ 0 - DQ7) RP# (P) VCC High Z High Z tAVAV tEHQZ tGHQZ tOH tGLQV tELQV tGLQX tELQX tAVQV tPHQV Valid Output VIH Address Stable Fig. 12 AC Waveform for Read Operations

• 31 -

6.2.5 AC CHARACTERISTICS - WRITE OPERATION (NOTE 1)

NOTES : 1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 3for valid A IN and DIN for block erase, byte write, or lock-bit configuration. 4. V PP should be held at VPPH1/2 (and if necessary RP# should be held at VHH ) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit"(High Seed Configuration) for testing characteristics. 6. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. tAVAV Write Cycle Time 85 90 120 ns tPHWL RP# High Recovery to WE# 2 111 µ sGoing Low tELWL CE# Setup to WE# Going Low 10 10 10 ns tWLWH WE# Pulse Width 40 40 40 ns tPHHWH RP# VHH Setup to WE# Going High 2 100 100 100 ns tVPWH VPP Setup to WE# Going High 2 100 100 100 ns tAVWH Address Setup to WE# Going High 3 4 04 04 0 n s tDVWH Data Setup to WE# Going High 3 40 40 40 ns tWHDX Data Hold from WE# High 5 5 5 ns tWHAX Address Hold from WE# High 5 5 5 ns tWHEH CE# Hold from WE# High 10 10 10 ns tWHWL WE# Pulse Width High 30 30 30 ns tWHRL WE# High to RY/BY# Going Low 90 90 90 ns tWHGL Write Recovery before Read 0 0 0 ns tQVVL VPP Hold from Valid SRD, 2, 4 0 0 0 nsRY/BY# High tQVPH RP# VHH Hold from Valid SRD, 2, 4 0 0 0 nsRY/BY# High VERSIONS VCC ±0.25 V VCC ±0.5 V (NOTE 5) LH28F008SC-V85/ LH28F008SCH-V85 (NOTE 6) LH28F008SC-V12/ LH28F008SCH-V12 (NOTE 6) LH28F008SC-V85/ LH28F008SCH-V85 UNIT

• 32 - VPP (V) VIH VIH VIH VIH VIH VOH VOL VIH VIL VIL VIL VIL VIL VIL VPPH1/2 VPPLK RP# (P) RY/BY# (R) DATA (D/Q) WE# (W) OE# (G) CE# (E) ADDRESSES (A) tAVAV tAVWH tELWL tWHGL tWHQV1/2/3/4tWHWL tWHDX D IN D IN AIN AIN High Z tPHWL tWHRL Valid SRD D IN tVPWH tWHEH VIL VHH tQVPHtPHHWH (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) tDVWH tWLWH tWHAX tQVVL NOTES : 1. V CC power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Fig. 13 AC Waveform for WE#-Controlled Write Operations

• 33 - NOTES : 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3for valid A IN and DIN for block erase, byte write, or lock-bit configuration. 4. V PP should be held at VPPH1/2 (and if necessary RP# should be held at VHH ) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit"(High Seed Configuration) for testing characteristics. 6. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. tAVAV Write Cycle Time 85 90 120 ns tPHEL RP# High Recovery to CE# 2 111 µ sGoing Low tWLEL WE# Setup to CE# Going Low 0 0 0 ns tELEH CE# Pulse Width 50 50 50 ns tPHHEH RP# VHH Setup to CE# Going High 2 100 100 100 ns tVPEH VPP Setup to CE# Going High 2 100 100 100 ns tAVEH Address Setup to CE# Going High 3 4 04 04 0 n s tDVEH Data Setup to CE# Going High 3 40 40 40 ns tEHDX Data Hold from CE# High 5 5 5 ns tEHAX Address Hold from CE# High 5 5 5 ns tEHWH WE# Hold from CE# High 0 0 0 ns tEHEL CE# Pulse Width High 25 25 25 ns tEHRL CE# High to RY/BY# Going Low 90 90 90 ns tEHGL Write Recovery before Read 0 0 0 ns tQVVL VPP Hold from Valid SRD, 2, 4 0 0 0 nsRY/BY# High tQVPH RP# VHH Hold from Valid SRD,2, 4 0 0 0 nsRY/BY# High

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1)

VCC ±0.25 V VCC ±0.5 V (NOTE 5) LH28F008SC-V85/ LH28F008SCH-V85 (NOTE 6) LH28F008SC-V12/ LH28F008SCH-V12 (NOTE 6) LH28F008SC-V85/ LH28F008SCH-V85 UNIT

• 34 - VPP (V) VIH VIH VIH VIH VIH VOH VOL VIH VIL VIL VIL VIL VIL VIL VPPH1/2 VPPLK RP# (P) RY/BY# (R) DATA (D/Q) CE# (E) OE# (G) WE# (W) ADDRESSES (A) tAVAV tAVEH tWLEL tEHGL tEHQV1/2/3/4tEHEL tEHDX D IND IN AIN AIN High Z tPHEL tEHRL Valid SRD D IN tVPEH tEHWH VIL VHH tQVPHtPHHEH (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) tDVEH tELEH tEHAX tQVVL NOTES : 1. V CC power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Fig. 14 AC Waveform for CE#-Controlled Write Operations

• 35 - VIH VOH VOL VIL RY/BY# (R) (A) Reset During Read Array Mode (B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration (C) RP# Rising Timing tPLPH RP# (P) VIH VOH VOL VIL RY/BY# (R) tPLRH tPLPH RP# (P) VIH 5 V VIL VIL VCC t5VPH RP# (P) Fig. 15 AC Waveform for Reset Operation Reset AC Specifications(NOTE 1) NOTES : 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. A reset time, tPHQV , is required from the latter of RY/BY# or RP# going high until outputs are valid. 4. When the device power-up, holding RP#-low minimum 100 ns is required after VCC has been in predefined range and also has been in stable there. VCC = 5.0±0.5 V SYMBOL PARAMETER NOTE MIN. MAX. UNIT tPLPH RP# Pulse Low Time (If RP# is tied to VCC , 100 nsthis specification is not applicable) tPLRH RP# Low to Reset during Block Erase, 2, 3 12 µsByte Write or Lock-Bit Configuration t5VPH VCC 4.5 V to RP# High 4 100 ns

6.2.7 RESET OPERATIONS

• 36 - tWHQV1 Byte Write Time 2 6.5 8 TBD 4.8 6 TBD µstEHQV1 Block Write Time 2 0.4 0.5 TBD 0.3 0.4 TBD s tWHQV2 Block Erase Time 2 0.9 1.1 TBD 0.3 1.0 TBD stEHQV2 tWHQV3 Set Lock-Bit Time 2 9.5 12 TBD 7.8 10 TBD µstEHQV3 tWHQV4 Clear Block Lock-Bits Time 2 0.9 1.1 TBD 0.3 1.0 TBD stEHQV4 tWHRH1 Byte Write Suspend Latency Time to Read 5.6 7 5.2 7.5 µstEHRH1 tWHRH2 Erase Suspend Latency Time to Read 9.4 13.1 9.8 12.6 µstEHRH2 NOTES : 1. Typical values measured at TA = +25˚C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested. 6.2.8BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4)

• 37 - LH28F008S C (H) T-V 85 Device Density 008 = 8 M-bit Access Speed (ns) Limited Voltage Option V = 5 V VCC only Package T = 40-pin TSOP (I) (TSOP040-P-1020) Normal bend R = 40-pin TSOP (I) (TSOP040-P-1020) Reverse bend N = 44-pin SOP (SOP044-P-0600) B = 48-ball CSP (FBGA048-P-0608) Architecture S = Symmetrical Block Power Supply Type C = Smart 5 Technology Operating Temperature Blank = 0 to +70°C H = –25 to +85°C Product line designator for all SHARP Flash products VALID OPERATIONAL COMBINATIONS VCC = 5.0±0.5 V V CC = 5.0±0.25 VOPTION ORDER CODE 100 pF load, 30 pF load, TTL I/O Levels 1.5 V I/O Levels

1 LH28F008SCXX-V85 90 ns 85 ns

2 LH28F008SCXX-V12 120 ns

7 ORDERING INFORMATION

–0.2 –0.05 –0.1 MAX. –0.2 TYP. Package base plane 20.0–0.3 19.0–0.3 0.125 0.125 0.435 2120 10.0 18.4 P _0.5 1.20 0.115 40_0.2–0.08 0.10 0.08 M 0.995–0.1

40 TSOP (TSOP040-P-1020)

13.2 16.0 1.2744_0.4 0.15 (14.4) –0.1 TYP. –0.4 –0.2 –0.05 0.15 M 0.15 28.2 2.7 1.275 –0.2 –0.1 –0.2 0.15 0.1 Package base plane

44 SOP (SOP044-P-0600)

A B 6.00 +0.2 S 8.0 +0.2 D 0.45–0.03 C0.8TYP. 0.4TYP. 1.0TYP. 0.8TYP. 0.4TYP. 0.1 S ∗0.4TYP. 1.2TYP. F A SM0.30 ∗Land hole diameter for ball mounting AB SC DM0.15 / /

48 CSP (FBGA048-P-0608)