SAK-TC1782F-320F180HR

TC1782 INFINEON | Alldatasheet

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V 1.4.1 2014-05 Microcontrollers 32-Bit Microcontroller TC1782 32-Bit Single-Chip Microcontroller

81726 Munich, Germany

© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V 1.4.1 2014-05 Microcontrollers 32-Bit Microcontroller TC1782 32-Bit Single-Chip Microcontroller

Data Sheet I-1 V 1.4.1, 2014-05 TC1782 Table of Contents

Data Sheet I-2 V 1.4.1, 2014-05 TC1782

Data Sheet 3 V 1.4.1, 2014-05

Data Sheet 4 V 1.4.1, 2014-05

Data Sheet 1 V 1.4.1, 2014-05

1 Summary of Features

The SAK-TC1782F-320F180HR / SAK-TC1782F-320F180HL has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 180 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) – 180 MHz operation at full temperature range
• Multiple on-chip memories – 2.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 128 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 16 Kbyte (ICACHE, configurable) – 40 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) – One FlexRay TM module with 2 channels (E-Ray).

Data Sheet 2 V 1.4.1, 2014-05 – One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

• 32 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 3 V 1.4.1, 2014-05 The SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 180 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) – 180 MHz operation at full temperature range
• Multiple on-chip memories – 2.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 128 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 16 Kbyte (ICACHE, configurable) – 40 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality)

Data Sheet 4 V 1.4.1, 2014-05 – One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

• 32 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 5 V 1.4.1, 2014-05 The SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) – 133 MHz operation at full temperature range
• Multiple on-chip memories – 2 Mbyte Program Flash Memory (PFLASH) with ECC – 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 128 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 16 Kbyte (ICACHE, configurable) – 40 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality)

Data Sheet 6 V 1.4.1, 2014-05 – One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

• 32 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 7 V 1.4.1, 2014-05 The SAK-TC1782F-320F160HR / SAK-TC1782F-320F160HL has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 160 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) – 160 MHz operation at full temperature range
• Multiple on-chip memories – 2.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 128 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 16 Kbyte (ICACHE, configurable) – 40 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) – One FlexRay TM module with 2 channels (E-Ray).

Data Sheet 8 V 1.4.1, 2014-05 – One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

• 32 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 9 V 1.4.1, 2014-05 The SAK-TC1782N-320F160HR / SAK-TC1782N-320F160HL has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 160 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) – 160 MHz operation at full temperature range
• Multiple on-chip memories – 2.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 128 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 16 Kbyte (ICACHE, configurable) – 40 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality)

Data Sheet 10 V 1.4.1, 2014-05 – One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

• 32 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 11 V 1.4.1, 2014-05

Ordering Information

The ordering code for Infineon microcontro llers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• The package and the type of delivery. For the available ordering codes for the TC1782 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the de rivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 TC1782 Derivative Synopsis Derivative Ambient Temperature Range Package SAK-TC1782F-320F180HR T A = -40oC to +125oC PG-LQFP-176-20 SAK-TC1782F-320F180HL T A = -40oC to +125oC PG-LQFP-176-10 SAK-TC1782N-320F180HR T A = -40oC to +125oC PG-LQFP-176-20 SAK-TC1782N-320F180HL T A = -40oC to +125oC PG-LQFP-176-10 SAK-TC1782N-256F133HR T A = -40oC to +125oC PG-LQFP-176-20 SAK-TC1782N-256F133HL T A = -40oC to +125oC PG-LQFP-176-10 SAK-TC1782F-320F160HR T A = -40oC to +125oC PG-LQFP-176-20 SAK-TC1782F-320F160HL T A = -40oC to +125oC PG-LQFP-176-10 SAK-TC1782N-320F160HR T A = -40oC to +125oC PG-LQFP-176-20 SAK-TC1782N-320F160HL T A = -40oC to +125oC PG-LQFP-176-10

System Overview of the TC1782 Data Sheet 12 V 1.4.1, 2014-05

2 System Overview of the TC1782

The TC1782 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications:

• Reduced Instruction Set Computing (RISC) processor architecture
• Digital Signal Processing (DSP) operations and addressing modes
• On-chip memories and peripherals DSP operations and addressing modes prov ide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features of the TC1782 include:
• Efficient memory organization: instru ction and data scratch memories, caches
• Serial communication interfaces – flexible synchronous and asynchronous modes
• Peripheral Control Processor – standalon e data operations and interrupt servicing
• DMA Controller – DMA operations and interrupt servicing
• General-purpose timers
• High-performance on-chip buses
• On-chip debugging and emulation facilities
• Flexible interconnections to external components
• Flexible power-management The TC1782 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor and a DMA controller and several on-chip peripherals. The TC1782 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. The TC1782 offers several versatile on-chip per ipheral units such as serial controllers, timer units, and Analog-to-Digital converte rs. Within the TC1782, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1782 ports are reserved for these peripheral units to communicate with the external world.

System Overview of the TC1782Block Diagrams Data Sheet 13 V 1.4.1, 2014-05

2.1 Block Diagrams

Figure 1 shows the block diagram of the SAK-TC1782-320F180HR / SAK-TC1782- 320F180HL / SAK-TC1782-320F160HR / SAK-TC1782-320F160HL. Figure 1 SAK-TC1782-320F180HR / SAK- TC1782-320F180HL / SAK-TC1782- 320F160HR / SAK-TC1782-320F160HL Block Diagram E-Ray (2 Channels) OCDS L1 Debug Interface/ JTAG MLI0 MemCheck FADC TriCore CPU PMI Interrupt System FPI-Bus Interface

16 KB PRAM

32 KB CMEM

(SPB) SSC0 SBCU Bridge SM IF DMI LDRAM DCACHE CPS BCU PMU GPTA0 Multi CAN (3 Nodes,

128 MO)

(LVDS ) SSC1 STM SCU Ports Ext. Request Unit LTCA2 2,5 MB PFlash

128 KB DFlash

8 KB OVRAM

16 KB BROM

M M/S 3.3V Ext. FADC Supply

24 KB SPRAM

16 KB ICACHE

(Configurable)

124 KB LDRAM

4 KB DCACHE

(Configurable) FPU PLL E-RAY PLL fE-Ray fCPU Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM : Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM : Parameter RAM in PCP PCODE: Code RAM in PCP DMA 16 channels (3.3V max) (5V max) SSC2 5V (3.3V supported as well) Ext. ADC Supply Local Memory Bus (LMB)

System Overview of the TC1782Block Diagrams Data Sheet 14 V 1.4.1, 2014-05 Figure 2 shows the block diagram of the SAK-TC1782N-320F180HR / SAK-TC1782N- 320F180HL / SAK-TC1782N-320F160HR / SAK-TC1782N-320F160HL. Figure 2 SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK- TC1782N-320F160HR / SAK-TC1782N-320F160HL / Block Diagram OCDS L1 Debug Interface / JTAG MLI0 MemCheck FADC TriCore CPU PMI Interrupt System FPI-Bus Interface (SPB) SSC0 SBCU Bridge SM IF DMI LDRAM DCACHE CPS BCU PMU GPTA0 Multi CAN (3 Nodes, (LVDS ) SSC1 STM SCU Ports Ext. Request Unit LTCA2 2,5 MB PFlash M M/S 3.3V Ext. FADC Supply (Configurable) (Configurable) FPU PLL E-RAY PLL fE-Ray fCP U Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM : Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM : Parameter RAM in PCP PCODE: Code RAM in PCP DMA 16 channels (3.3V max) (5V max) SSC2 5V (3.3V supported as well) Ext. ADC Supply Local Memory Bus (LMB)

System Overview of the TC1782Block Diagrams Data Sheet 15 V 1.4.1, 2014-05 Figure 3 shows the block diagram of the SAK-TC1782N-256F133HR / SAK-TC1782N- 256F133HL. Figure 3 SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL Block Diagram OCDS L1 Debug Interface/ JTAG MLI0 MemCheck FADC TriCore CPU PMI Interrupt System FPI-Bus Interface (SPB) SSC0 SBCU Bridge SM IF DMI LDRAM DCACHE CPS BCU PMU GPTA0 Multi CAN (3 Nodes, (LVDS ) SSC1 STM SCU Ports Ext. Request Unit LTCA2

2 MB PFlash

64 KB DFlash

M M/S 3.3V Ext. FADC Supply (Configurable) (Configurable) FPU PLL E-RAY PLL fE-Ray fCP U Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM : Scratch-Pad RAM LDRAM: Local Data RAM OVRAM : Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM : Parameter RAM in PCP PCODE: Code RAM in PCP DMA 16 channels (3.3V max) (5V max) SSC2 5V (3.3V supported as well) Ext. ADC Supply Local Memory Bus (LMB)

Data Sheet 16 V 1.4.1, 2014-05

3 Pinning

Figure 4 is showing the TC1782 Logic Symbol. Figure 4 TC1782 Logic Symbol TESTMODE ESR 0 PORST Digital Circuitry Power Supply General Control AN[35:0]Analog Inputs VDDM VSSM VDDMF VSSMF VDDAF VAREF0 VAGND0 VFAREF VFAGND VDDFL 3 Analog Power Supply TC1782_LQFP-176 VDDOSC 3 Alternate Functions Oscillator GPTA, SCU, E-RAY, MSC0 GPTA, SSC 0/1, MLI 0, MSC0 GPTA, ASC 0/1, SSC 0/1, SCU, CAN, MSC0 GPTA, SCU , CAN VDDOSC GPTA, MLI0, E-RAY, SSC2 VSSOSC TC1782 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 GPTA, MSC0 XTAL2 XTAL1 VSS VDDP VDD ESR 1 TRST TCK / DAP0 TDI / BRKIN TDO / DAP2 / BRKOUT TMS / DAP1 OCDS / JTAG Control GPTA, SSC 1, ADC0, OCDS 1) Only available for SAK -TC1782 F-320 F180HR, SAK -TC1782 F-320 F180HL, SAK -TC1782 F-320 F160HR, SAK -TC1782 F-320F160HL, SAK -TC1782 F-320 F133HR and SAK -TC1782 F-320 F133HL

PinningTC1782 Pin Configuration Data Sheet 17 V 1.4.1, 2014-05

3.1 TC1782 Pin Configuration

This chapter shows the pin configuration of the TC1782 package PG-LQFP-176-10 / PG- LQFP-176-20. Figure 5 SAK-TC1782F-320F180HR / SAK-TC1782F-320F180HL / SAK-TC1782F-320F160HR / SAK-TC1782F-320F160HL Pinning 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 13213 3 13 4 13 5 13 6 137 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 147 14 8 14 9 15 0 15 1 15 2 153 154 155 156 15 7 158 159 160 161 162 16 3 16 4 16 5 16 6 16 7 16 8 16 9 17 0 17 1 17 2 17 3 17 4 17 5 17 6 P 0.0 /IN0 /HW CF G0/O UT0 /OUT 56 P 0.1 /IN1 /HW CF G1/O UT1 /OUT 57 /S DI1 P 0.2 /IN2 /HW CF G2/O UT2 /OUT 58 P 0.3 /IN3 /HW CF G3/O UT3 /OUT 59 P 0.4 /IN4 /HW CF G4/O UT4 /OUT 60 P 0.5 /IN5 /HW CF G5/O UT5 /OUT 61 P 0.6 /IN6 /HW CF G6/RE Q 2/O UT6 /OUT 62 P 0.7 /IN7 /HW CF G7/RE Q 3/O UT7 /OUT 63 P0.8 /IN8 /RXDA0/OU T 8/ OUT64 P0.9 /IN9 /RXDB0/OU T 9/ OUT65 P 0.1 0/IN 10/O UT1 0/T X DA 0 P 0.1 1/IN 11/O UT1 1/T X DB 0 P 0.1 2/IN 12/O UT1 2/T X E NA P 0.1 3/IN 13/O UT1 3/T X E NB P 0.1 4/IN 14/R EQ 4/O UT1 4/F CLP 0C P 0.1 5/IN 15/R EQ 5/O UT1 5/S OP 0 C P1 .0/IN 16/ OUT 16/OUT 72 /BRKIN/ BRKOUT P1.1 5/BRKIN/BRKOUT P1 . 2 /I N 1 8/ O U T1 8/ O U T7 4 P1 . 3 /I N 1 9/ O U T1 9/ O U T7 5 P1 . 4 /I N2 0/ EMG STO P / O UT2 0/ O UT7 6 P1 . 5 /I N 2 1/ O U T2 1/ O U T7 7 P1 . 6 /I N 2 2/ O U T2 2/ O U T7 8 P1 . 7 /I N 2 3/ O U T2 3/ O U T7 9 P1.8/ IN24 /IN48 /M T SR 1 B / OUT 24/OUT 48 P1.9/ IN25 /IN49 /M RST1 B / OUT 25/OUT 49 P1.10 /IN26 /IN50 /OUT 26 /OUT 50 /SLSO 17 P1.11 /IN27 /IN51 /SCLK 1B/OUT 27 /OUT 51 A D0E M UX 0/OU T1 6/IN1 6/P 1 .12 A D0E M UX 1/OU T1 7/IN1 7/P 1 .13 A D0E M UX 2/OU T1 8/IN1 8/P 1 .14 T CLK 0/ OUT 28/ OUT 32/I N32/ P 2.0 S LS O 13/ SL S O03 /OUT 33 /TRE A DY 0A /I N33/ P 2.1 T V A LID0 A/ OUT 29/ OUT 34/I N34/ P 2.2 T DA TA 0/ OUT 30/ OUT 35/I N35/ P 2.3 OUT 31 /OUT 36 /RCLK 0A /I N36/ P 2.4 RRE A DY 0A /O UT3 7/OU T1 10/I N37/ P 2.5 O UT 38 / O UT 11 1 /RVA LI D0 A/ IN3 8 /P2 . 6 OUT 39/ RDA TA 0A /I N39/ P 2.7 P 2.8 /S LS O0 4/S LS O 14/ EN0 0 P 2.9 /S LS O0 5/S LS O 15/ EN0 1 P 2.1 0/IN 10/O UT0 /M RST 1A P 2.1 1/IN 11/O UT1 /S CLK 1 A/ FCL P0 B P 2.1 2/IN 12/O UT2 /M TS R1A / SO P 0B P 2.1 3/IN 13/O UT3 /S LS I1 1/S DI0 P 3.0 /OUT 84 /RX D0A P 3.1 /OUT 85 //T XD 0 P3.2 / OUT8 6 / SCLK0 P3.3 / OUT8 7 / MRST 0 P3.4 / OUT8 8 / MTSR 0 P3.5 / SL SO0 0/SLSO1 0/SL SO 0 0&SL SO 1 0 P3.6 / SL SO0 1/SLSO1 1/SL SO 0 1&SL SO 1 1 P3.7 / SL SI0 1/OUT8 9/SLSO0 2/SL SO1 2 P3.8/ SLSO06 /OUT 90 /T XD 1 P 3.9 /OUT 91 /RX D1A P3 . 10 / O UT 92 / REQ0 P3 . 11 / O UT 93 / REQ1 P3.1 2 /O UT 9 4/RXDCAN0 /RXD0B P3 . 13 / O UT 95 / TXDCAN0 / TXD0 P3 . 14 / O UT 96 / RXDCAN1/ RXD1 B/ SDI 2 P3 . 15 / O UT 97 / TXDCAN1 / TXD1 OUT 52 /OUT 28 /IN52 /IN2 8/RX DCA N2/ P 4.0 O UT5 3/O UT2 9/IN5 3/I N29/ TX DCA N2/ P 4.1 E X T CLK 1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2 P4.3/ IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0 S LS CO 20 /OUT 40/ OUT 8/IN 40/IN 26/ P5 .0 S LS CO 21 /OUT 41/ OUT 9/IN 41/IN 27/ P5 .1 SLSCO22 /OUT 42 /OUT 10 /IN 42/IN 28/ P5 .2 SLSCO2 4/OUT4 4/OUT12/SL SI2 AIN 4 4/IN 2 9 / P 5.4 S LS CO 23/ OUT 43/ OUT 11/IN 43/ P5 .3 M RST2A/OUT 45 /OUT 13 /IN 45/IN 30/ P5 .5 M T SR 2A/OUT 46 /OUT 14 /IN 46/IN 31/ P5 .6 S CLK 2/ OUT 47/ OUT 15/IN 47/ P5 .7 RX DB1 /T CLK 0/OUT 95/P 5 .15 T XDB 1 /RVALID0 B/OUT 90/ P5 .9 TXENA /RREADY0 B/OUT9 1/P5. 1 0 TXENB / RCL K0 B/OUT9 2/P5. 1 1 TDATA 0/ SL SO 0 7/ O UT9 3/ P5 .1 2 TVAL ID0 B/SL SO1 6/P5. 1 3 RXDA1 / TREADY 0 B/OUT9 4/P5. 1 4 T X DA 1/RDA T A 0B /OUT 89 /P 5. 8 P 6.1 /IN1 5/OUT 5/ OUT 81/ FCL P0 A P 6.0 /IN1 4/OUT 4/ OUT 80/ FCL N0 P 6.3 /IN2 5/OUT 7/ OUT 83/ SO P 0A P 6.2 /IN2 4/OUT 6/ OUT 82/ SO N0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN8 AN7 AN9 AN1 0 AN1 1 AN1 2 AN1 3 AN1 4 AN1 5 AN1 6 AN1 7 AN1 8 AN1 9 AN2 0 AN2 1 AN2 2 AN2 3 AN2 4 AN2 5 AN2 6 AN2 7 AN2 8 AN2 9 AN3 0 AN3 1 AN3 2 AN3 3 AN3 4 AN3 5 TRST P1 .1/IN 17/ OUT 17/ OUT 73 T DI/BRKIN/BRKOUT T DO/DAP2/BRKIN/BRKOUT TMS / DAP1 TCK / DAP0 ESR 1 PORST VSS TESTMO DE XTAL1 XTAL2 VDD VDDP VSS VDD VDD(SB) TC1782 VDD VDDP VSS VDDM F VSSM F VDDAF VSS VFAR EF VFAG N D V DDM VSSM V AREF0 V AGND0 VDD V DDP V SS VDD V DDP V SS V SS VDD VDDP VSS VDDOSC VDDOSC3 VSSO SC V DDFL3 V DDP V SS V DD V DDP V SS V DD(SB) V DDP V SS SAK_TC1782-320F180HR SAK_TC1782-320F180HL SAK_TC1782-320F160HR SAK_TC1782-320F160HL SAK_TC1782-320F133HR SAK_TC1782-320F133HL VDDP VDDP ESR0

PinningTC1782 Pin Configuration Data Sheet 18 V 1.4.1, 2014-05 Figure 6 SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK-TC1782N-320F160HR / SAK-TC1782N-320F160HL / SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / Pinning 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 13213 3 13 4 13 5 13 6 137 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 147 14 8 14 9 15 0 15 1 15 2 153 154 155 156 15 7 158 159 160 161 162 16 3 16 4 16 5 16 6 16 7 16 8 16 9 17 0 17 1 17 2 17 3 17 4 17 5 17 6 P 0.0 /IN0 /HW CF G0/O UT0 /OUT 56 P 0.1 /IN1 /HW CF G1/O UT1 /OUT 57 /S DI1 P 0.2 /IN2 /HW CF G2/O UT2 /OUT 58 P 0.3 /IN3 /HW CF G3/O UT3 /OUT 59 P 0.4 /IN4 /HW CF G4/O UT4 /OUT 60 P 0.5 /IN5 /HW CF G5/O UT5 /OUT 61 P 0.6 /IN6 /HW CF G6/RE Q 2/O UT6 /OUT 62 P 0.7 /IN7 /HW CF G7/RE Q 3/O UT7 /OUT 63 P 0.8 /IN8 /OUT 8/O UT6 4 P 0.9 /IN9 /OUT 9/O UT6 5 P 0.1 0/IN 10/O UT1 0 P 0.1 1/IN 11/O UT1 1 P 0.1 2/IN 12/O UT1 2 P 0.1 3/IN 13/O UT1 3 P 0.1 4/IN 14/R EQ 4/O UT1 4/F CLP 0C P 0.1 5/IN 15/R EQ 5/O UT1 5/S OP 0 C P 1.0 /IN1 6/OUT1 6 / OUT7 2 /BRKIN/BRKOUT P 1.1 5/BRKIN/BRKOUT P1 . 2/ I N1 8/ O UT1 8/ O UT7 4 P1 . 3/ I N1 9/ O UT1 9/ O UT7 5 P1 . 4/ I N2 0/ EMG STO P /O UT2 0 / O UT7 6 P1 . 5/ I N2 1/ O UT2 1/ O UT7 7 P1 . 6/ I N2 2/ O UT2 2/ O UT7 8 P1 . 7/ I N2 3/ O UT2 3/ O UT7 9 P1.8 /IN24 /IN48 /M T SR 1 B/OUT 24/ OUT 48 P1.9 /IN25 /IN49 /M RST1 B/OUT 25/ OUT 49 P1.10 /IN26 /IN 50/ OUT 26/ OUT 50/SLSO 17 P1.11 /IN27 /IN 51/ SCLK1B/OUT 27 /OUT 51 A D0E M UX 0/OU T1 6/IN1 6/P 1 .12 A D0E M UX 1/OU T1 7/IN1 7/P 1 .13 A D0E M UX 2/OU T1 8/IN1 8/P 1 .14 T CLK 0/ OUT 28/ OUT 32/I N32/ P 2.0 SL SO 1 3 /S LSO0 3/ OUT3 3/ T READY0 A/ IN3 3 /P2 . 1 T V A LID0 A/ OUT 29/ OUT 34/I N34/ P 2.2 T DA TA 0/ OUT 30/ OUT 35/I N35/ P 2.3 OUT 31 /OUT 36 /RCLK 0A /I N36/ P 2.4 RRE A DY 0A /O UT3 7/OU T1 10/I N37/ P 2.5 O UT3 8/O UT1 11/ RV AL ID0A /I N38/ P 2.6 OUT 39/ RDA TA 0A /I N39/ P 2.7 P 2.8 /S LS O0 4/S LS O 14/ EN0 0 P 2.9 /S LS O0 5/S LS O 15/ EN0 1 P 2.1 0/IN 10/O UT0 /M RST 1A P 2.1 1/IN 11/O UT1 /S CLK 1 A/ FCL P0 B P 2.1 2/IN 12/O UT2 /M TS R1A / SO P 0B P 2.1 3/IN 13/O UT3 /S LS I1 1/S DI0 P 3.0 /OUT 84 /RX D0A P 3.1 /OUT 85 /TX D0 P3.2 /OUT 86 /SCLK0 P3.3 /OUT 87 /M RST0 P3.4 /OUT 88 /M T SR 0 P3 .5/SL SO0 0/SL SO 1 0 /SL SO0 0& SL SO 1 0 P3 .6/SL SO0 1/SL SO 1 1 /SL SO0 1& SL SO 1 1 P3 .7/SL SI0 1/OUT8 9/SL SO0 2/SL SO 1 2 P3.8 /SLSO06 /OUT 90 /T XD1 P 3.9 /OUT 91 /RX D1A P 3.1 0/O UT9 2/RE Q0 P 3.1 1/O UT9 3/RE Q1 P 3.1 2/O UT9 4/RX DCA N0 /RX D0B P 3.1 3/O UT9 5/T X DCA N0/T X D0 P 3.1 4/O UT9 6/RX DCA N1 /RX D1B /S DI2 P 3.1 5/O UT9 7/T X DCA N1/T X D1 OUT52 /OUT28 /IN52 /IN2 8/RXDCAN2/ P4.0 O UT5 3/O UT2 9/IN5 3/I N29/ TX DCA N2/ P 4.1 E X T CLK 1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2 P4.3 /IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0 SL SCO2 0/OUT4 0/OUT8 /IN 4 0 /IN2 6/P5 .0 SL SCO2 1/OUT4 1/OUT9 /IN 4 1 /IN2 7/P5 .1 SLSCO 2 2/ OUT42 /OUT10/IN 4 2/ IN2 8/P5 .2 SL SC O 2 4/ O U T4 4/ O U T1 2/ SL SI 2 A/ I N4 4 /I N 2 9/ P5 . 4 SL SCO 2 3/OUT4 3/OUT1 1 /IN4 3/P5 .3 M RST2 A/ OUT 45/OUT 13 /IN 45/ IN30 /P 5.5 M T SR 2 A/ OUT 46/OUT 14 /IN 46/ IN31 /P 5.6 SCLK2 /OUT 47 /OUT 15/ IN47 /P5.7 T CLK 0/ OUT 95/ P5 .15 RVALID0 B/OUT 90 /P5.9 RREADY0 B/OUT9 1 /P5.1 0 RCLK 0B / OUT 92/P 5 .11 TDATA 0 / SL SO0 7 /O UT9 3 / P5. 1 2 T VALID0B/SLSO 16/P5 .13 TREADY 0B/ OUT94/P5 .14 RDATA 0B/OUT89 /P5 .8 P 6.1 /IN1 5/OUT 5/ OUT 81/ FCL P0 A P 6.0 /IN1 4/OUT 4/ OUT 80/ FCL N0 P 6.3 /IN2 5/OUT 7/ OUT 83/ SO P 0A P 6.2 /IN2 4/OUT 6/ OUT 82/ SO N0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN8 AN7 AN9 AN1 0 AN1 1 AN1 2 AN1 3 AN1 4 AN1 5 AN1 6 AN1 7 AN1 8 AN1 9 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 TRSTP1 . 1 /I N1 7/ O UT1 7/ O UT7 3 T DI/BRKIN/BRKOUT T DO/DAP2/BRKIN/ BRKOUT TMS / DAP1 T C K/ D A P0 ESR1 PORST VSS TESTMO DE XTAL 1 XTAL 2 VDD VDDP VSS VDD VDD(SB) TC1782 VDD VDDP VSS VDDMF VSSM F VDDAF VSS VFAREF VFAG ND V DDM VSSM V AREF0 V AGND0 VDD V DDP V SS VDD V DDP V SS V SS VDD VDDP VSS VDDOSC VDDOSC3 VSSOSC V DDFL3 V DDP V SS V DD V DDP V SS V DD(SB) V DDP V SS VDDP VDDP ESR0 SAK_TC1782N-320F180HR SAK_TC1782N-320F180HL SAK_TC1782N-320F160HR SAK_TC1782N-320F160HL SAK_TC1782N-320F133HR SAK_TC1782N-320F133HL

PinningTC1782 Pin Configuration Data Sheet 19 V 1.4.1, 2014-05 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) Pin Symbol Ctrl. Type Function Port 0 145 P0.0 I/O0 A1/ PU Port 0 General Purpose I/O Line 0 IN0 I GPTA0 Input 0 IN0 I LTCA2 Input 0 HWCFG0 I Hardware Configuration Input 0 OUT0 O1 GPTA0 Output 0 OUT56 O2 GPTA0 Output 56 OUT0 O3 LTCA2 Output 0 146 P0.1 I/O0 A1/ PU Port 0 General Purpose I/O Line 1 IN1 I GPTA0 Input 1 IN1 I LTCA2 Input 1 SDI1 I MSC0 Serial Data Input 1 HWCFG1 I Hardware Configuration Input 1 OUT1 O1 GPTA0 Output 1 OUT57 O2 GPTA0 Output 57 OUT1 O3 LTCA2 Output 1 147 P0.2 I/O0 A1/ PU Port 0 General Purpose I/O Line 2 IN2 I GPTA0 Input 2 IN2 I LTCA2 Input 2 HWCFG2 I Hardware Configuration Input 2 OUT2 O1 GPTA0 Output 2 OUT58 O2 GPTA0 Output 58 OUT2 O3 LTCA2 Output 2

PinningTC1782 Pin Configuration Data Sheet 20 V 1.4.1, 2014-05 148 P0.3 I/O0 A1+/ PU Port 0 General Purpose I/O Line 3 IN3 I GPTA0 Input 3 IN3 I LTCA2 Input 3 HWCFG3 I Hardware Configuration Input 3 OUT3 O1 GPTA0 Output 3 OUT59 O2 GPTA0 Output 59 OUT3 O3 LTCA2 Output 3 166 P0.4 I/O0 A1/ PU Port 0 General Purpose I/O Line 4 IN4 I GPTA0 Input 4 IN4 I LTCA2 Input 4 HWCFG4 I Hardware Configuration Input 4 OUT4 O1 GPTA0 Output 4 OUT60 O2 GPTA0 Output 60 OUT4 O3 LTCA2 Output 4 167 P0.5 I/O0 A1/ PU Port 0 General Purpose I/O Line 5 IN5 I GPTA0 Input 5 IN5 I LTCA2 Input 5 HWCFG5 I Hardware Configuration Input 5 OUT5 O1 GPTA0 Output 5 OUT61 O2 GPTA0 Output 61 OUT5 O3 LTCA2 Output 5 173 P0.6 I/O0 A1/ PU Port 0 General Purpose I/O Line 6 IN6 I GPTA0 Input 6 IN6 I LTCA2 Input 6 HWCFG6 I Hardware Configuration Input 6 REQ2 I External Request Input 2 OUT6 O1 GPTA0 Output 6 OUT62 O2 GPTA0 Output 62 OUT6 O3 LTCA2 Output 6 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 21 V 1.4.1, 2014-05 174 P0.7 I/O0 A1/ PU Port 0 General Purpose I/O Line 7 IN7 I GPTA0 Input 7 IN7 I LTCA2 Input 7 HWCFG7 I Hardware Configuration Input 7 REQ3 I External Request Input 3 OUT7 O1 GPTA0 Output 7 OUT63 O2 GPTA0 Output 63 OUT7 O3 LTCA2 Output 7 149 P0.8 I/O0 A1/ PU Port 0 General Purpose I/O Line 8 IN8 I GPTA0 Input 8 IN8 I LTCA2 Input 8 RXDA0 I E-Ray Channel A Receive Data Input 0 1) OUT8 O1 GPTA0 Output 8 OUT64 O2 GPTA0 Output 64 OUT8 O3 LTCA2 Output 8 150 P0.9 I/O0 A1/ PU Port 0 General Purpose I/O Line 9 IN9 I GPTA0 Input 9 IN9 I LTCA2 Input 9 RXDB0 I E-Ray Channel B Receive Data Input 0 1) OUT9 O1 GPTA0 Output 9 OUT65 O2 GPTA0 Output 65 OUT9 O3 LTCA2 Output 9 151 P0.10 I/O0 A2/ PU Port 0 General Purpose I/O Line 10 IN10 I GPTA0 Input 10 OUT10 O1 GPTA0 Output 10 TXDA0 O2 E-Ray Channel A transmit Data Output 1) OUT10 O3 LTCA2 Output 10 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 22 V 1.4.1, 2014-05 152 P0.11 I/O0 A2/ PU Port 0 General Purpose I/O Line 11 IN11 I GPTA0 Input 11 OUT11 O1 GPTA0 Output 11 TXDB0 O2 E-Ray Channel B transmit Data Output 1) OUT11 O3 LTCA2 Output 11 168 P0.12 I/O0 A2/ PU Port 0 General Purpose I/O Line 12 IN12 I GPTA0 Input 12 OUT12 O1 GPTA0 Output 12 TXENA O2 E-Ray Channel A transmit Data Output enable OUT12 O3 LTCA2 Output 12 169 P0.13 I/O0 A2/ PU Port 0 General Purpose I/O Line 13 IN13 I GPTA0 Input 13 OUT13 O1 GPTA0 Output 13 TXENB O2 E-Ray Channel B transmit Data Output enable OUT13 O3 LTCA2 Output 13 175 P0.14 I/O0 A1+/ PU Port 0 General Purpose I/O Line 14 IN14 I GPTA0 Input 14 REQ4 I External Request Input 4 OUT14 O1 GPTA0 Output 14 FCLP0C O2 MSC0 Clock Output Positive C OUT14 O3 LTCA2 Output 14 176 P0.15 I/O0 A1+/ PU Port 0 General Purpose I/O Line 15 IN15 I GPTA0 Input 15 REQ5 I External Request Input 5 OUT15 O1 GPTA0 Output 15 SOP0C O2 MSC0 Serial Data Output Positive C OUT15 O3 LTCA2 Output 15 Port 1 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 23 V 1.4.1, 2014-05 116 P1.0 I/O0 A2/ PU Port 1 General Purpose I/O Line 0 IN16 I GPTA0 Input 16 BRKIN I Break Input OUT16 O1 GPTA0 Output 16 OUT72 O2 GPTA0 Output 72 OUT16 O3 LTCA2 Output 16 BRKOUT O Break Output (controlled by OCDS module) 119 P1.1 I/O0 A1/ PU Port 1 General Purpose I/O Line 1 IN17 I GPTA0 Input 17 OUT17 O1 GPTA0 Output 17 OUT73 O2 GPTA0 Output 73 OUT17 O3 LTCA2 Output 17 93 P1.2 I/O0 A1/ PU Port 1 General Purpose I/O Line 2 IN18 I GPTA0 Input 18 OUT18 O1 GPTA0 Output 18 OUT74 O2 GPTA0 Output 74 OUT18 O3 LTCA2 Output 18 98 P1.3 I/O0 A1/ PU Port 1 General Purpose I/O Line 3 IN19 I GPTA0 Input 19 IN19 I LTCA2 Input 19 OUT19 O1 GPTA0 Output 19 OUT75 O2 GPTA0 Output 75 OUT19 O3 LTCA2 Output 19 107 P1.4 I/O0 A1/ PU Port 1 General Purpose I/O Line 4 IN20 I GPTA0 Input 20 IN20 I LTCA2 Input 20 EMGSTOP I Emergency Stop Input OUT20 O1 GPTA0 Output 20 OUT76 O2 GPTA0 Output 76 OUT20 O3 LTCA2 Output 20 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 24 V 1.4.1, 2014-05 108 P1.5 I/O0 A1/ PU Port 1 General Purpose I/O Line 35 IN21 I GPTA0 Input 21 IN21 I LTCA2 Input 21 OUT21 O1 GPTA0 Output 21 OUT77 O2 GPTA0 Output 77 OUT21 O3 LTCA2 Output 21 109 P1.6 I/O0 A1/ PU Port 1 General Purpose I/O Line 6 IN22 I GPTA0 Input 22 IN22 I LTCA2 Input 22 OUT22 O1 GPTA0 Output 22 OUT78 O2 GPTA0 Output 78 OUT22 O3 LTCA2 Output 22 110 P1.7 I/O0 A1/ PU Port 1 General Purpose I/O Line 7 IN23 I GPTA0 Input 23 IN23 I LTCA2 Input 23 OUT23 O1 GPTA0 Output 23 OUT79 O2 GPTA0 Output 79 OUT23 O3 LTCA2 Output 23 94 P1.8 I/O0 A1+/ PU Port 1 General Purpose I/O Line 8 IN24 I GPTA0 Input 24 IN48 I GPTA0 Input 48 MTSR1B I SSC1 Slave Receive Input B (Slave Mode) OUT24 O1 GPTA0 Output 24 OUT48 O2 GPTA0 Output 48 MTSR1B O3 SSC1 Master Transmit Output B (Master Mode) Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 25 V 1.4.1, 2014-05 95 P1.9 I/O0 A1+/ PU Port 1 General Purpose I/O Line 9 IN25 I GPTA0 Input 25 IN49 I GPTA0 Input 49 MRST1B I SSC1 Master Receive Input B (Master Mode) OUT25 O1 GPTA0 Output 25 OUT49 O2 GPTA0 Output 49 MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode) 96 P1.10 I/O0 A1+/ PU Port 1 General Purpose I/O Line 10 IN26 I GPTA0 Input 26 IN50 I GPTA0 Input 50 OUT26 O1 GPTA0 Output 26 OUT50 O2 GPTA0 Output 50 SLSO17 O3 SSC1 Slave Select Output 7 97 P1.11 I/O0 A1+/ PU Port 1 General Purpose I/O Line 11 IN27 I GPTA0 Input 27 IN51 I GPTA0 Input 51 SCLK1B I SSC1 Clock Input B OUT27 O1 GPTA0 Output 27 OUT51 O2 GPTA0 Output 51 SCLK1B O3 SSC1 Clock Output B 73 P1.12 I/O0 A1/ PU Port 1 General Purpose I/O Line 12 IN16 I LTCA2 Input 16 AD0EMUX0 O1 ADC0 External Multiplexer Control Output 0 AD0EMUX0 O2 ADC0 External Multiplexer Control Output 0 OUT16 O3 LTCA2 Output 16 72 P1.13 I/O0 A1/ PU Port 1 General Purpose I/O Line 13 IN17 I LTCA2 Input 17 AD0EMUX1 O1 ADC0 External Multiplexer Control Output 1 AD0EMUX1 O2 ADC0 External Multiplexer Control Output 1 OUT17 O3 LTCA2 Output 17 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 26 V 1.4.1, 2014-05 71 P1.14 I/O0 A1/ PU Port 1 General Purpose I/O Line 14 IN18 I LTCA2 Input 18 AD0EMUX2 O1 ADC0 External Multiplexer Control Output 2 AD0EMUX2 O2 ADC0 External Multiplexer Control Output 2 OUT18 O3 LTCA2 Output 18 117 P1.15 I/O0 A2/ PU Port 1 General Purpose I/O Line 15 BRKIN I Break Input Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O Break Output (controlled by OCDS module) Port 2 74 P2.0 I/O0 A2/ PU Port 2 General Purpose I/O Line 0 IN32 I GPTA0 Input 32 OUT32 O1 GPTA0 Output 32 TCLK0 O2 MLI0 Transmitter Clock Output 0 OUT28 O3 LTCA2 Output 28 75 P2.1 I/O0 A2/ PU Port 2 General Purpose I/O Line 1 IN33 I GPTA0 Input 33 TREADY0A I MLI0 Transmitter Ready Input A OUT33 O1 GPTA0 Output 33 SLSO03 O2 SSC0 Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 76 P2.2 I/O0 A2/ PU Port 2 General Purpose I/O Line 2 IN34 I GPTA0 Input 34 OUT34 O1 GPTA0 Output 34 TVALID0 O2 MLI0 Transmitter Valid Output OUT29 O3 LTCA2 Output 29 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 27 V 1.4.1, 2014-05 77 P2.3 I/O0 A2/ PU Port 2 General Purpose I/O Line 3 IN35 I GPTA0 Input 35 OUT35 O1 GPTA0 Output 35 TDATA0 O2 MLI0 Transmitter Data Output OUT30 O3 LTCA2 Output 30 78 P2.4 I/O0 A2/ PU Port 2 General Purpose I/O Line 4 IN36 I GPTA0 Input 36 RCLK0A I MLI Receiver Clock Input A OUT36 O1 GPTA0 Output 36 OUT36 O2 GPTA0 Output 36 OUT31 O3 LTCA2 Output 31 79 P2.5 I/O0 A2/ PU Port 2 General Purpose I/O Line 5 IN37 I GPTA0 Input 37 OUT37 O1 GPTA0 Output 37 RREADY0A O2 MLI0 Receiver Ready Output A OUT110 O3 LTCA2 Output 110 80 P2.6 I/O0 A2/ PU Port 2 General Purpose I/O Line 6 IN38 I GPTA0 Input 38 RVALID0A I MLI Receiver Valid Input A OUT38 O1 GPTA0 Output 38 OUT38 O2 GPTA0 Output 38 OUT111 O3 LTCA2 Output 111 81 P2.7 I/O0 A2/ PU Port 2 General Purpose I/O Line 7 IN39 I GPTA0 Input 39 RDATA0A I MLI Receiver Data Input A OUT39 O1 GPTA0 Output 39 OUT39 O2 GPTA0 Output 39 Reserved O3 - Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 28 V 1.4.1, 2014-05 164 P2.8 I/O0 A2/ PU Port 2 General Purpose I/O Line 8 SLSO04 O1 SSC0 Slave Select Output 4 SLSO14 O2 SSC1 Slave Select Output 4 EN00 O3 MSC0 Enable Output 0 160 P2.9 I/O0 A2/ PU Port 2 General Purpose I/O Line 9 SLSO05 O1 SSC0 Slave Select Output 5 SLSO15 O2 SSC1 Slave Select Output 5 EN01 O3 MSC0 Enable Output 1 161 P2.10 I/O0 A1+/ PU Port 2 General Purpose I/O Line 10 MRST1A I SSC1 Master Receive Input A IN10 I LTCA2 Input 10 MRST1A O1 SSC1 Slave Transmit Output OUT0 O2 LTCA2 Output 0 Reserved O3 - 162 P2.11 I/O0 A1+/ PU Port 2 General Purpose I/O Line 11 SCLK1A I SSC1 Clock Input A IN11 I LTCA2 Input 11 SCLK1A O1 SSC1 Clock Output A OUT1 O2 LTCA2 Output 1 FCLP0B O3 MSC0 Clock Output Positive B 163 P2.12 I/O0 A1+/ PU Port 2 General Purpose I/O Line 12 MTSR1A I SSC1 Slave Receive Input A IN12 I LTCA2 Input 12 MTSR1A O1 SSC1 Master Transmit Output A OUT2 O2 LTCA2 Output 2 SOP0B O3 MSC0 Serial Data Output Positive B Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 29 V 1.4.1, 2014-05 165 P2.13 I/O0 A1/ PU Port 2 General Purpose I/O Line 13 SLSI11 I SSC1 Slave Select Input 1 SDI0 I MSC0 Serial Data Input 0 IN13 I LTCA2 Input 13 OUT3 O1 LTCA2 Output 3 Reserved O2 - Reserved O3 - Port 3 136 P3.0 I/O0 A1+/ PU Port 3 General Purpose I/O Line 0 RXD0A I ASC0 Receiver Input A (Async. & Sync. Mode) RXD0A O1 ASC0 Output (Sync. Mode) RXD0A O2 ASC0 Output (Sync. Mode) OUT84 O3 GPTA0 Output 84 135 P3.1 I/O0 A1+/ PU Port 3 General Purpose I/O Line 1 TXD0 O1 ASC0 Output TXD0 O2 ASC0 Output OUT85 O3 GPTA0 Output 85 129 P3.2 I/O0 A1+/ PU Port 3 General Purpose I/O Line 2 SCLK0 I SSC0 Clock Input (Slave Mode) SCLK0 O1 SSC0 Clock Output (Master Mode) SCLK0 O2 SSC0 Clock Output (Master Mode) OUT86 O3 GPTA0 Output 86 130 P3.3 I/O0 A1+/ PU Port 3 General Purpose I/O Line 3 MRST0 I SSC0 Master Receive Input (Master Mode) MRST0 O1 SSC0 Slave Transmit Output (Slave Mode) MRST0 O2 SSC0 Slave Transmit Output (Slave Mode) OUT87 O3 GPTA0 Output 87 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 30 V 1.4.1, 2014-05 132 P3.4 I/O0 A2/ PU Port 3 General Purpose I/O Line 4 MTSR0 I SSC0 Slave Receive Input (Slave Mode) MTSR0 O1 SSC0 Master Transmit Output (Master Mode) MTSR0 O2 SSC0 Master Transmit Output (Master Mode) OUT88 O3 GPTA0 Output 88 126 P3.5 I/O0 A1+/ PU Port 3 General Purpose I/O Line 5 SLSO00 O1 SSC0 Slave Select Output 0 SLSO10 O2 SSC1 Slave Select Output 0 SLSOANDO0 O3 SSC0 AND SSC1 Slave Select Output 0 127 P3.6 I/O0 A1+/ PU Port 3 General Purpose I/O Line 6 SLSO01 O1 SSC0 Slave Select Output 1 SLSO11 O2 SSC1 Slave Select Output 1 SLSOANDO1 O3 SSC0 AND SSC1 Slave Select Output 1 131 P3.7 I/O0 A2/ PU Port 3 General Purpose I/O Line 7 SLSI01 I SSC0 Slave Select Input 1 SLSO02 O1 SSC0 Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTA0 Output 89 128 P3.8 I/O0 A2/ PU Port 3 General Purpose I/O Line 8 SLSO06 O1 SSC0 Slave Select Output 6 TXD1 O2 ASC1 Transmit Output OUT90 O3 GPTA0 Output 90 138 P3.9 I/O0 A1/ PU Port 3 General Purpose I/O Line 9 RXD1A I ASC1 Receiver Input A RXD1A O1 ASC1 Receiver Output A (Synchronous Mode) RXD1A O2 ASC1 Receiver Output A (Synchronous Mode) OUT91 O3 GPTA0 Output 91 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 31 V 1.4.1, 2014-05 137 P3.10 I/O0 A1/ PU Port 3 General Purpose I/O Line 10 REQ0 I External Request Input 0 Reserved O1 - Reserved O2 - OUT92 O3 GPTA0 Output 92 144 P3.11 I/O0 A1/ PU Port 3 General Purpose I/O Line 11 REQ1 I External Request Input 1 Reserved O1 - Reserved O2 - OUT93 O3 GPTA0 Output 93 143 P3.12 I/O0 A1/ PU Port 3 General Purpose I/O Line 12 RXDCAN0 I CAN Node 0 Receiver Input RXD0B I ASC0 Receiver Input B RXD0B O1 ASC0 Receiver Output B (Synchronous Mode) RXD0B O2 ASC0 Receiver Output B (Synchronous Mode) OUT94 O3 GPTA0 Output 94 142 P3.13 I/O0 A2/ PU Port 3 General Purpose I/O Line 13 TXDCAN0 O1 CAN Node 0 Transmitter Output TXD0 O2 ASC0 Transmit Output OUT95 O3 GPTA0 Output 95 134 P3.14 I/O0 A1/ PU Port 3 General Purpose I/O Line 14 RXDCAN1 I CAN Node 1 Receiver Input RXD1B I ASC1 Receiver Input B SDI2 I MSC0 Serial Data Input 2 RXD1B O1 ASC1 Receiver Output B (Synchronous Mode) RXD1B O2 ASC1 Receiver Output B (Synchronous Mode) OUT96 O3 GPTA0 Output 96 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 32 V 1.4.1, 2014-05 133 P3.15 I/O0 A2/ PU Port 3 General Purpose I/O Line 15 TXDCAN1 O1 CAN Node 1 Transmitter Output TXD1 O2 ASC1 Transmit Output OUT97 O3 GPTA0 Output 97 Port 4 86 P4.0 I/O0 A1+/ PU Port 4 General Purpose I/O Line 0 IN28 I GPTA0 Input 28 IN52 I GPTA0 Input 52 RXDCAN2 I CAN Node 2 Receiver Input OUT28 O1 GPTA0 Output 28 OUT52 O2 GPTA0 Output 52 Reserved O3 - 87 P4.1 I/O0 A1+/ PU Port 4 General Purpose I/O Line 1 IN29 I GPTA0 Input 29 IN53 I GPTA0 Input 53 OUT29 O1 GPTA0 Output 29 OUT53 O2 GPTA0 Output 53 TXDCAN2 O3 CAN Node 2 Transmitter Output 88 P4.2 I/O0 A2/ PU Port 4 General Purpose I/O Line 2 IN30 I GPTA0 Input 30 IN54 I GPTA0 Input 54 OUT30 O1 GPTA0 Output 30 OUT54 O2 GPTA0 Output 54 EXTCLK1 O3 External Clock 1 Output 90 P4.3 I/O0 A2/ PU Port 4 General Purpose I/O Line 3 IN31 I GPTA0 Input 31 IN55 I GPTA0 Input 55 OUT31 O1 GPTA0 Output 31 OUT55 O2 GPTA0 Output 55 EXTCLK0 O3 External Clock 0 Output Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 33 V 1.4.1, 2014-05 Port 5 1 P5.0 I/O0 A1+/ PU Port 5 General Purpose I/O Line 0 IN40 I GPTA0 Input 40 IN26 I LTCA2 Input 26 OUT40 O1 GPTA0 Output 40 OUT8 O2 LTCA2 Output 8 SLSO20 O3 SSC2 Slave Select Output 0 2 P5.1 I/O0 A1+/ PU Port 5 General Purpose I/O Line 1 IN41 I GPTA0 Input 41 IN27 I LTCA2 Input 27 OUT41 O1 GPTA0 Output 41 OUT9 O2 LTCA2 Output 9 SLSO21 O3 SSC2 Slave Select Output 1 3 P5.2 I/O0 A1+/ PU Port 5 General Purpose I/O Line 2 IN42 I GPTA0 Input 42 IN28 I LTCA2 Input 28 OUT42 O1 GPTA0 Output 42 OUT10 O2 LTCA2 Output 10 SLSO22 O3 SSC2 Slave Select Output 2 4 P5.3 I/O0 A1+/ PU Port 5 General Purpose I/O Line 3 IN43 I GPTA0 Input 43 OUT43 O1 GPTA0 Output 43 OUT11 O2 LTCA2 Output 11 SLSO23 O3 SSC2 Slave Select Output 3 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 34 V 1.4.1, 2014-05 5 P5.4 I/O0 A1+/ PU Port 5 General Purpose I/O Line 4 IN44 I GPTA0 Input 44 IN29 I LTCA2 Input 29 SLSI2A I SSC2 Slave Select Input A OUT44 O1 GPTA0 Output 44 OUT12 O2 LTCA2 Output 12 SLSO24 O3 SSC2 Slave Select Output 4 6 P5.5 I/O0 A1+/ PU Port 5 General Purpose I/O Line 5 IN45 I GPTA0 Input 45 IN30 I LTCA2 Input 30 MRST2A I SSC2 Master Receive Input (Master Mode) OUT45 O1 GPTA0 Output 45 OUT13 O2 LTCA2 Output 13 MRST2 O3 SSC2 Master Transmit Input (Slave Mode) 7 P5.6 I/O0 A1+/ PU Port 5 General Purpose I/O Line 6 IN46 I GPTA0 Input 46 IN31 I LTCA2 Input 31 MTSR2A I SSC2 Slave Receive Input (Slave Mode) OUT46 O1 GPTA0 Output 46 OUT14 O2 LTCA2 Output 14 MTSR2 O3 SSC2 Master Transmit Output (Master Mode) 8 P5.7 I/O0 A1+/ PU Port 5 General Purpose I/O Line 7 IN47 I GPTA0 Input 47 SCLK2A I SSC2 Clock Input (Slave Mode) OUT47 O1 GPTA0 Output 47 OUT15 O2 LTCA2 Output 15 SCLK2 O3 SSC2 Clock Output (Master Mode) Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 35 V 1.4.1, 2014-05 13 P5.8 I/O0 A2/ PU Port 5 General Purpose I/O Line 8 RDATA0B I MLI0 Receiver Data Input B Reserved O1 - TXDA1 O2 E-Ray Channel A transmit Data Output 1) OUT89 O3 LTCA2 Output 89 14 P5.9 I/O0 A2/ PU Port 5 General Purpose I/O Line 9 RVALID0B I MLI0 Receiver Data Valid Input B Reserved O1 - TXDB1 O2 E-Ray Channel B transmit Data Output 1) OUT90 O3 LTCA2 Output 90 15 P5.10 I/O0 A2/ PU Port 5 General Purpose I/O Line 10 RREADY0B O1 MLI0 Receiver Ready Input B TXENA O2 E-Ray Channel A transmit Data Output enable OUT91 O3 LTCA2 Output 91 16 P5.11 I/O0 A2/ PU Port 5 General Purpose I/O Line 11 RCLK0B I MLI0 Receiver Clock Input B Reserved O1 - TXENB O2 E-Ray Channel B transmit Data Output enable OUT92 O3 LTCA2 Output 92 17 P5.12 I/O0 A1+/ PU Port 5 General Purpose I/O Line 12 TDATA0 O1 MLI0 Transmitter Data Output SLSO07 O2 SSC0 Slave Select Output 7 OUT93 O3 LTCA2 Output 93 18 P5.13 I/O0 A1+/ PU Port 5 General Purpose I/O Line 13 TVALID0B O1 MLI0 Transmitter Valid Input B SLSO16 O2 SSC1 Slave Select Output 6 Reserved O3 - Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 36 V 1.4.1, 2014-05 19 P5.14 I/O0 A1+/ PU Port 5 General Purpose I/O Line 14 TREADY0B I MLI0 Transmitter Ready Input B RXDA1 I E-Ray Channel A Receive Data Input 1 1) Reserved O1 - Reserved O2 - OUT94 O3 LTCA2 Output 94 9 P5.15 I/O0 A1+/ PU Port 5 General Purpose I/O Line 15 RXDB1 I E-Ray Channel B Receive Data Input 1 1) TCLK0 O1 MLI0 Transmitter Clock Output Reserved O2 - OUT95 O3 LTCA2 Output 95 Port 6 156 P6.0 I/O0 A1/ PU Port 6 General Purpose I/O Line 0 IN14 I LTCA2 Input 14 FCLN0 O1 MSC0 Clock Output Negative OUT80 O2 GPTA0 Output 80 OUT4 O3 LTCA2 Output 4 157 P6.1 I/O0 A1/ PU Port 6 General Purpose I/O Line 1 IN15 I LTCA2 Input 15 FCLP0A O1 MSC0 Clock Output Positive A OUT81 O2 GPTA0 Output 81 OUT5 O3 LTCA2 Output 5 158 P6.2 I/O0 A1/ PU Port 6 General Purpose I/O Line 2 IN24 I LTCA2 Input 24 SON0 O1 MSC0 Serial Data Output Negative OUT82 O2 GPTA0 Output 82 OUT6 O3 LTCA2 Output 6 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 37 V 1.4.1, 2014-05 159 P6.3 I/O0 A1/ PU Port 6 General Purpose I/O Line 3 IN25 I LTCA2 Input 25 SOP0A O1 MSC0 Serial Data Output Positive A OUT83 O2 GPTA0 Output 83 OUT7 O3 LTCA2 Output 7 Analog Input Port

67 AN0 I D ADC0 Analog Input Channel 0

66 AN1 I D ADC0 Analog Input Channel 1

65 AN2 I D ADC0 Analog Input Channel 2

64 AN3 I D ADC0 Analog Input Channel 3

63 AN4 I D ADC0 Analog Input Channel 4

62 AN5 I D ADC0 Analog Input Channel 5

61 AN6 I D ADC0 Analog Input Channel 6

36 AN7 I D ADC0 Analog Input Channel 7

60 AN8 I D ADC0 Analog Input Channel 8

59 AN9 I D ADC0 Analog Input Channel 9

58 AN10 I D ADC0 Analog Input Channel 10

57 AN11 I D ADC0 Analog Input Channel 11

56 AN12 I D ADC0 Analog Input Channel 12

55 AN13 I D ADC0 Analog Input Channel 13

50 AN14 I D ADC0 Analog Input Channel 14

49 AN15 I D ADC0 Analog Input Channel 15

48 AN16 I D ADC1 Analog Input Channel 16

47 AN17 I D ADC1 Analog Input Channel 17

46 AN18 I D ADC1 Analog Input Channel 18

45 AN19 I D ADC1 Analog Input Channel 19

44 AN20 I D ADC1 Analog Input Channel 20

43 AN21 I D ADC1 Analog Input Channel 21

42 AN22 I D ADC1 Analog Input Channel 22

41 AN23 I D ADC1 Analog Input Channel 23

Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 38 V 1.4.1, 2014-05

40 AN24 I D ADC1 Analog Input Channel 24

39 AN25 I D ADC1 Analog Input Channel 25

38 AN26 I D ADC1 Analog Input Channel 26

37 AN27 I D ADC1 Analog Input Channel 27

35 AN28 I D ADC1 / FADC Analog Input Channel 28

34 AN29 I D ADC1 / FADC Analog Input Channel 29

33 AN30 I D ADC1 / FADC Analog Input Channel 30

32 AN31 I D ADC1 / FADC Analog Input Channel 31

31 AN32 I D FADC Analog Input P Channel 0

30 AN33 I D FADC Analog Input N Channel 0

29 AN34 I D FADC Analog Input P Channel 1

28 AN35 I D FADC Analog Input N Channel 1

54 VDDM -- ADC Analog Part Power Supply (3.3V - 5V)

53 VSSM -- ADC Analog Part Ground

52 VAREF0 -- ADC0 and ADC1 Reference Voltage

51 VAGND0 -- ADC Reference Ground

24 VDDMF -- FADC Analog Part Power Supply (3.3V) 23 VDDAF -- FADC Analog Part Logic Power Supply (1.3V)

25 VSSMF -- FADC Analog Part Ground

VSSAF -- FADC Analog Part Ground

26 VFAREF -- FADC Reference Voltage

27 VFAGND -- FADC Reference Ground

10, 212), 68, 84, 91, 99, 123, 153, 170 VDD -- Digital Core Power Supply (1.3V) Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 39 V 1.4.1, 2014-05 11, 20, 69, 83, 89, 100, 124, 139, 154, 171 VDDP -- Port Power Supply (3.3V) 12, 22, 70, 82, 85, 92, 101, 125, 140, 155, 172 VSS -- Digital Ground 105 VDDOSC -- Main Oscillator and PLL Power Supply (1.3V) 106 VDDOSC3 -- Main Oscillator Power Supply (3.3V)

104 VSSOSC -- Main Oscillator and PLL Ground

141 VDDFL3 -- Power Supply for Flash (3.3V)

102 XTAL1 I Main Oscillator Input

103 XTAL2 O Main Oscillator Output

111 TDI I A2/

BRKIN I OCDS Break Input Line BRKOUT O OCDS Break Output Line

112 TMS I A2/

JTAG State Machine Control Input DAP1 I/O Device Access Port Line 1 Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 40 V 1.4.1, 2014-05 Legend for Table 2 Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X00B O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2) O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column “Type”: A1 = Pad class A1 (LVTTL) A1+ = Pad class A1+ (LVTTL) A2 = Pad class A2 (LVTTL)

113 TDO I/O A2/

DAP2 I/O Device Access Port Line 2 BRKIN I OCDS Break Input Line BRKOUT O OCDS Break Output Line

114 TRST I I /

115 TCK I A1/

DAP0 I Device Access Port Line 0

118 TESTMODE I I /

120 ESR1 I/O A2/

External System Request Reset Input 1

121 PORST I I /

122 ESR0 I/O A2 External System Request Reset Input 0

Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. 1) Only available for SAK-TC1782F-320F180HR, SAK-TC1782F-320F180HL, and SAK-TC1782F-320F160HR. 2) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the production devide device, this pin is bonded to a VDD pad. Table 2 Pin Definitions and Functions (PG-LQFP-176-10 / PG-LQFP-176-20 Package) (cont’d) Pin Symbol Ctrl. Type Function

PinningTC1782 Pin Configuration Data Sheet 41 V 1.4.1, 2014-05 F = Pad class F (LVDS/CMOS) D = Pad class D (ADC) I = Pad class I (LVTTL) PU = with pull-up device connected during reset (PORST = 0) PD = with pull-down device connected during reset (PORST = 0) TR = tri-state during reset (PORST = 0)

Data Sheet 42 V 1.4.1, 2014-05

4 Identification Registers

The Identification Registers uniquely identify the whole device. Table 3 SAK-TC1782F-320F180HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 8500 9310 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 4 SAK-TC1782F-320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 0500 9310 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 5 SAK-TC1782N-320F180HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 8500 9410 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 6 SAK-TC1782N-320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 0500 9410 H F000 0640H BA

Data Sheet 43 V 1.4.1, 2014-05 SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 7 SAK-TC1782N-256F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 9400 9410 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 8 SAK-TC1782N-256F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 1400 9410 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 9 SAK-TC1782F-320F160HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID A500 9310 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 6 SAK-TC1782N-320F180HL Identification Registers (cont’d) Short Name Value Address Stepping

Data Sheet 44 V 1.4.1, 2014-05 Table 10 SAK-TC1782F-320F160HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 2500 9310 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 11 SAK-TC1782N-320F160HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID A500 9410 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA Table 12 SAK-TC1782N-320F160HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H BA CBS_JTAGID 1018 E083 H F000 0464H BA SCU_CHIPID 2500 9410 H F000 0640H BA SCU_MANID 0000 1820 H F000 0644H BA SCU_RTID 0000 0000 H F000 0648H BA

Electrical ParametersGeneral Parameters Data Sheet 45 V 1.4.1, 2014-05

5 Electrical Parameters

This specification provides all electrical parameters of the TC1782.

5.1 General Parameters

5.1.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1782 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1782 and must be regarded for a system design.
• SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1782 designed in.

Electrical ParametersGeneral Parameters Data Sheet 46 V 1.4.1, 2014-05

5.1.2 Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1. Table 13 Pad Driver and Pad Classes Overview Class Power Supply Type Sub Class Speed Grade 1) These values show typical application configurations for the pad. Complete and detailed pad parameters are available in the individual pad parameter table on the following pages. Load Leakage 150oC 1) Termination A 3.3 V LVTTL I/O, LVTTL outputs (e.g. GPIO)

6 MHz 100 pF 500 nA No

(e.g. serial I/Os) MHz 50 pF 1 μAS e r i e s termination recommended (e.g. serial I/Os) MHz 50 pF 3 μAS e r i e s termination recommended F 3.3 V LVDS – 50 MHz –– P a r a l l e l termination, 100 Ω ± 10% 2) In applications where the LVDS pins are not used (d isabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 Ω ±1 0 % . CMOS – 6 MHz 50 pF – DE 5V A D C – – – – I 3.3 V LVTTL (input only) –– – –

Electrical ParametersGeneral Parameters Data Sheet 47 V 1.4.1, 2014-05

5.1.3 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 14 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Note / Test Con dition Min. Typ. Max. Storage temperature TST SR -65 – 150 °C Voltage at 1.3 V power supply pins with respect to VSS VDD SR – – 2.0 V Voltage at 3.3 V power supply pins with respect to VSS VDDP SR ––4 . 3 3 V Voltage at 5 V power supply pins with respect to VSS VDDM SR – – 7.0 V Voltage on any Class A input pin and dedicated input pins with respect to VSS VIN SR -0.6 – VDDP + 0.7 or max. 4.33 V Whatever is lower Voltage on any Class D analog input pin with respect to VAGND0 VAIN VAREF0 SR -0.6 – 7.0 V Voltage on any shared Class D analog input pin with respect to VSSAF, if the FADC is switched through to the pin. VAINF SR -0.6 – 7.0 V Input current on any pin during overload condition IIN -10 – +10 mA Absolute maximum sum of all input circuit currents for one port group during overload condition1) 1) The port groups are defined in Table 19. IIN -25 – +25 mA Absolute maximum sum of all input circuit currents during overload condition ΣIIN ––| 2 0 0 | m A

Electrical ParametersGeneral Parameters Data Sheet 48 V 1.4.1, 2014-05

5.1.4 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 15 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time (24000 h) is not exceeded
• Operating Conditions are met for – pad supply levels ( VDDP or VDDM) – temperature If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operat ion is still possible in mo st cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Note: FADC input pins count as analog pin as they are overlayed with an ADC pins. Table 15 Overload Parameters Parameter Symbol Values Unit Note / Test Con dition Min. Typ. Max. Input current on any digital pin during overload condition except LVDS pins IIN -5 – +5 mA Input current on LVDS pins IINLVDS -3 – +3 mA Absolute sum of all input circuit currents for one port group during overload condition 1) The port groups are defined in Table 19. IING -20 – +20 mA Input current on analog pins IINANA -3 – +3 mA Absolute sum of all analog input currents for analog inputs of a single ADC during overload condition IINSAS -15 – +15 mA Absolute sum of all input circuit currents during overload condition ΣIINS -100 – 100 mA

Electrical ParametersGeneral Parameters Data Sheet 49 V 1.4.1, 2014-05 Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life-time. Table 16 PN-Junction Characteris itics for positive Overload Pad Type I IN =3m A I IN =5m A A1 / A1+ / F UIN = VDDP +0 . 6V UIN = VDDP +0 . 7V A2 UIN = VDDP +0 . 5V UIN = VDDP +0 . 6V LVDS UIN = VDDP +0 . 7V - D UIN = VDDM +0 . 6V - Table 17 PN-Junction Characterisitics for negative Overload Pad Type I IN =- 3m A I IN =- 5m A A1 / A1+ / F UIN = VSS -0 . 6V UIN = VSS -0 . 7V A2 UIN = VSS -0 . 5V UIN = VSS -0 . 6V LVDS UIN = VSS -0 . 7V - D UIN = VSSM -0 . 6V -

Electrical ParametersGeneral Parameters Data Sheet 50 V 1.4.1, 2014-05

5.1.5 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC1782. Digital supply voltages applied to the TC178 2 must be static regulated voltages which allow a typical voltage swing of ± 5 %. All parameters specified in the following tables refer to these operating conditions (Table 18), unless otherwise noticed in the Note / Test Condition column. The Voltage Operating Timing Profiles did not increase area of validity of the parameters defined in table 8 and later. Table 18 Operating Conditions Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Overload coupling factor for analog inputs, negative KOVAN CC −− 0.000 IOV≤ 0m A ; IOV≥ - 2 mA; analog pad= 5.0 V Overload coupling factor for analog inputs, positive KOVAP CC −− 0.000 IOV≤ 3m A ; IOV≥ 0 mA; analog pad= 5.0 V CPU Frequency fCPU SR −− 133 MHz SAK-TC1782N- 256F133HR / SAK- TC1782N- 256F133HL −− 180 MHz SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL −− 160 MHz SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL

Electrical ParametersGeneral Parameters Data Sheet 51 V 1.4.1, 2014-05 FPI bus frequency fFPI SR −− 90 MHz SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL / SAK- TC1782F- 256F133HR / SAK- TC1782F- 256F133HL / SAK- TC1782N- 256F133HR / SAK- TC1782N- 256F133HL −− 80 MHz SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 52 V 1.4.1, 2014-05 LMB frequency fLMB CC −− 133 MHz SAK-TC1782N- 256F133HR / SAK- TC1782N- 256F133HL −− 180 MHz SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL −− 160 MHz SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 53 V 1.4.1, 2014-05 PCP Frequency fPCP SR −− 133 MHz SAK-TC1782N- 256F133HR / SAK- TC1782N- 256F133HL −− 180 MHz SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL −− 160 MHz SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL Inactive device pin current IID SR -1 − 1 mA All power supply voltagesVDDx = 0 Short circuit current of digital outputs1) ISC SR -5 − 5m A Absolute sum of short circuit currents of the device Σ ISC_D CC −− 100 mA Absolute sum of short circuit currents per pin group ΣISC_PG CC −− 20 mA Ambient Temperature TA SR -40 − 125 °C Junction temperature TJ SR -40 − 150 °C Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 54 V 1.4.1, 2014-05 Core Supply Voltage VDD SR 1.235 1.3 1.365 V SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL / SAK- TC1782N- 256F133HR / SAK- TC1782N- 256F133HL; for duration limitation see Voltage Operating Timing Profiles 1.17 1.3 1.43 2) V SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL; for duration limitation see Voltage Operating Timing Profiles Flash supply voltage 3.3V VDDFL3 SR 2.97 3.3 3.63 4) V for duration limitation see Voltage Operating Timing Profiles ADC analog supply voltage VDDM SR 2.97 3.3 5.5 3) V Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 55 V 1.4.1, 2014-05 Oscillator core supply voltage VDDOSC SR 1.235 1.3 1.365 2 V SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL / SAK- TC1782N- 256F133HR / SAK- TC1782N- 256F133HL; for duration limitation see Voltage Operating Timing Profiles 1.17 1.3 1.43 2) V SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL; for duration limitation see Voltage Operating Timing Profiles Oscillator 3.3V supply voltage VDDOSC3 SR 2.97 3.3 3.63 4) V for duration limitation see Voltage Operating Timing Profiles Digital supply voltage for IO pads VDDP SR 2.97 3.3 3.63 4) V for duration limitation see Voltage Operating Timing Profiles Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 56 V 1.4.1, 2014-05 VDDP voltage to ensure defined pad states5) VDDPPA CC 0.65 −− V Digital ground voltage VSS SR 0 −− V Analog ground voltage for VDDM VSSM SR -0.1 0 0.1 V Analog core supply VDDAF SR 1.235 1.3 1.365 2 V SAK-TC1782F- 320F180HR / SAK- TC1782F- 320F180HL / SAK- TC1782N- 320F180HR / SAK- TC1782N- 320F180HL / SAK- TC1782N- 256F133HR / SAK- TC1782N- 256F133HL; for duration limitation see Voltage Operating Timing Profiles 1.17 1.3 1.43 2) V SAK-TC1782F- 320F160HR / SAK- TC1782F- 320F160HL / SAK- TC1782N- 320F160HR / SAK- TC1782N- 320F160HL; for duration limitation see Voltage Operating Timing Profiles Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 57 V 1.4.1, 2014-05 Voltage Operating Timing Profiles

• 1 . 3 V < VDD / VDDOSC / VDDAF <1 . 3 V+ 5%: – limited to Operation Lifetime ( tOP) (see Table 46)
• 1 . 3 V + 5 % < VDD / VDDOSC / VDDAF <1 . 3 V+ 7.5% (overvoltage condition): – limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress.
• 1.3V + 7.5% < VDD / VDDOSC / VDDAF <1 . 3 V+ 10% (overvoltage condition): – limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress.
• 3 . 3 V < VDDP / VDDOSC3 / VDDFL3 / VDDMF <3 . 3 V+ 5%: – limited to Operation Lifetime ( tOP) (see Table 46)
• VDDP / VDDOSC3 / VDDFL3 / VDDMF<3 . 3V + 10% –3 . 3 V + 5 % <VDDP / VDDOSC3 / VDDFL3 / VDDMF<3 . 3 V+ 10% (overvoltage condition): limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress.
• 5 V < VDDM <5 V + 10%: – limited to Operation Lifetime ( tOP) (see Table 46) FADC / ADC analog supply voltage VDDMF SR 2.97 3.3 3.63 4) V for duration limitation see Voltage Operating Timing Profiles Analog ground voltage for VDDMF VSSAF SR -0.1 0 0.1 V 1) Applicable for digital outputs. 2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 5) This parameter is valid under the assumption the PORST signal is constantly at low level during the power- up/power-down of VDDP. Table 18 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersGeneral Parameters Data Sheet 58 V 1.4.1, 2014-05 Table 19 Pin Groups for Overload / Short-Circuit Current Sum Parameter Group Pins 1 P5.[7:2], P5.15 2 P5.[9:8] 3 P5.[11:10] 4 P5.[14:12] 5 P1.[14:12], P2.0 6 P2.[4:1] 7 P2.[7:5] 8 P4.[2:0] 9P 4 . 3 10 P1.2, P1.8 11 P1.[10:9] 12 P1.3, P1.11 13 P1.[7:4] 14 P1.[1:0], P1.15 19 P0.[11:10] 20 P6.[3:0] 21 P2.[13:8]

Electrical ParametersDC Parameters Data Sheet 59 V 1.4.1, 2014-05

5.2 DC Parameters

5.2.1 Input/Output Pins

Table 20 Standard_Pads Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Pin capacitance (digital inputs/outputs) CIO CC −− 10 pF TA=2 5° C ; f=1M H z Pull-down current | IPDL| CC −− 150 μA Vi≥ 0.6 x VDDP V 10 −−μ A Vi≥ 0.36 x VDDP V Pull-Up current | IPUH| CC 10 −−μ A Vi≤ 0.6 x VDDP V −− 100 μA Vi≤ 0.36 x VDDP V Spike filter always blocked pulse duration tSF1 CC −− 10 ns only PORST pin Spike filter pass-through pulse duration tSF2 CC 100 −− ns only PORST pin Table 21 Standard_Pads Class_A1 Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis for A1 pads 1) HYSA1 CC 0.1 x VDDP −− V Input Leakage Current Class A1 IOZA1 CC -500 − 500 nA Vi≥ 0V ; Vi≤ VDDP V Ratio Vil/Vih, A1 pads VILA1 / VIHA1 CC 0.6 −− On-Resistance of the class A1 pad, weak driver RDSONW CC − 450 600 Ohm IOH<- 0 . 5m A ; P_MOS − 210 340 Ohm IOL<0 . 5m A ; N_MOS

Electrical ParametersDC Parameters Data Sheet 60 V 1.4.1, 2014-05 On-Resistance of the class A1 pad, medium driver RDSONM CC −− 155 Ohm IOH<- 2m A ; P_MOS −− 110 Ohm IOL<2m A ; N_MOS Fall time, pad type A1 tFA1 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Table 21 Standard_Pads Class_A1 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 61 V 1.4.1, 2014-05 Rise time, pad type A1 tRA1 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage class A1 pads VIHA1 SR 0.6 x VDDP − min(V DDP+ 0.3,3.6 V Input low voltage class A1 pads VILA1 SR -0.3 − 0.36 x VDDP V Table 21 Standard_Pads Class_A1 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 62 V 1.4.1, 2014-05 Output voltage high class A1 pads VOHA1 CC VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= medium 2.4 −− V IOH≥ -2 mA; pin out driver= medium VDDP - 0.4 −− V IOH≥ -400 μA; pin out driver= weak 2.4 −− V IOH≥ -500 μA; pin out driver= weak Output voltage low class A1 pads VOLA1 CC −− 0.4 V IOL≤ 2 mA; pin out driver= medium −− 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 22 Standard_Pads Class_A1+ Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis for A1+ pads 1) HYSA1 + CC 0.1 x VDDP −− V Input Leakage Current Class A1+ IOZA1+ CC -1000 − 1000 nA On-Resistance of the class A1+ pad, weak driver RDSONW CC − 450 600 Ohm IOH<- 0 . 5m A ; P_MOS − 210 340 Ohm IOL<0 . 5m A ; N_MOS Table 21 Standard_Pads Class_A1 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 63 V 1.4.1, 2014-05 On-Resistance of the class A1+ pad, medium driver RDSONM CC −− 155 Ohm IOH<- 2m A ; P_MOS −− 110 Ohm IOL<2m A ; N_MOS On-Resistance of the class A1+ pad, strong driver RDSON1+ CC −− 100 Ohm IOH<- 2m A ; P_MOS −− 80 Ohm IOL<2m A ; N_MOS Fall time, pad type A1+ tFA1+ CC −− 150 ns CL= 20 pF; pin out driver= weak −− 28 ns CL=5 0p F ; edge= slow ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Table 22 Standard_Pads Class_A1+ (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 64 V 1.4.1, 2014-05 Rise time, pad type A1+ tRA1+ CC −− 150 ns CL= 20 pF; pin out driver= weak −− 28 ns CL=5 0p F ; edge= slow ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage, Class A1+ pads VIHA1+ SR 0.6 x VDDP − min(V DDP+ 0.3,3.6 V Input low voltage Class A1+ pads VILA1+ SR -0.3 − 0.36 x VDDP V Ratio Vil/Vih, A1+ pads VILA1+ / VIHA1+ CC 0.6 −− Table 22 Standard_Pads Class_A1+ (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 65 V 1.4.1, 2014-05 Output voltage high class A1+ pads VOHA1+ CC VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= medium VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= strong 2.4 −− V IOH≥ -2 mA; pin out driver= medium 2.4 −− V IOH≥ -2 mA; pin out driver= strong VDDP - 0.4 −− V IOH≥ -400 μA; pin out driver= weak 2.4 −− V IOH≥ -500 μA; pin out driver= weak Output voltage low class A1+ pads VOLA1+ CC −− 0.4 V IOL≤ 2 mA; pin out driver= medium −− 0.4 V IOL≤ 2 mA; pin out driver= strong −− 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 22 Standard_Pads Class_A1+ (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 66 V 1.4.1, 2014-05 Table 23 Standard_Pads Class_A2 Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis for A2 pads 1) HYSA2 CC 0.1 x VDDP −− V Input Leakage current Class A2 IOZA2 CC -6000 − 6000 nA Vi< VDDP / 2 - 1V ; Vi> VDDP / 2 + 1 V; Vi≥ 0V ; Vi≤ VDDP V -3000 − 3000 nA Vi> VDDP / 2 - 1V ; Vi< VDDP / 2 + 1 V Ratio Vil/Vih, A2 pads VILA2 / VIHA2 CC 0.6 −− On-Resistance of the class A2 pad, weak driver RDSONW CC − 450 600 Ohm IOH<- 0 . 5m A ; P_MOS − 210 340 Ohm IOL<0 . 5m A ; N_MOS On-Resistance of the class A2 pad, medium driver RDSONM CC −− 155 Ohm IOH<- 2m A ; P_MOS −− 110 Ohm IOL<2m A ; N_MOS On-Resistance of the class A2 pad, strong driver RDSON2 CC −− 28 Ohm IOH<- 2m A ; P_MOS −− 22 Ohm IOL<2m A ; N_MOS

Electrical ParametersDC Parameters Data Sheet 67 V 1.4.1, 2014-05 Fall time, pad type A2 tFA2 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 7n s CL=5 0p F ; edge= medium ; pin out driver= strong −− 10 ns CL=5 0p F ; edge= medium- minus ; pin out driver= strong −− 3.7 ns CL=5 0p F ; edge= sharp ; pin out driver= strong −− 5n s CL=5 0p F ; edge= sharp- minus ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 7.5 ns CL=1 0 0p F ; edge= sharp ; pin out driver= strong −− 140 ns CL= 150 pF; pin out driver= medium Table 23 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 68 V 1.4.1, 2014-05 −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Table 23 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 69 V 1.4.1, 2014-05 Rise time, pad type A2 tRA2 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 7.0 ns CL=5 0p F ; edge= medium ; pin out driver= strong −− 10 ns CL=5 0p F ; edge= medium- minus ; pin out driver= strong −− 3.7 ns CL=5 0p F ; edge= sharp ; pin out driver= strong −− 5n s CL=5 0p F ; edge= sharp- minus ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 7.5 ns CL=1 0 0p F ; edge= sharp ; pin out driver= strong −− 140 ns CL= 150 pF; pin out driver= medium Table 23 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 70 V 1.4.1, 2014-05 −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage, class A2 pads VIHA2 SR 0.6 x VDDP − min(V DDP + 0.3, 3.6) V Input low voltage Class A2 pads VILA2 SR -0.3 − 0.36 x VDDP V Output voltage high class A2 pads VOHA2 CC VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= medium VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= strong 2.4 −− V IOH≥ -2 mA; pin out driver= medium 2.4 −− V IOH≥ -2 mA; pin out driver= strong VDDP - 0.4 −− V IOH≥ -400 μA; pin out driver= weak 2.4 −− V IOH≥ -500 μA; pin out driver= weak Table 23 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 71 V 1.4.1, 2014-05 Output voltage low class A2 pads VOLA2 CC −− 0.4 V IOL≤ 2 mA; pin out driver= medium −− 0.4 V IOL≤ 2 mA; pin out driver= strong −− 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 24 Standard_Pads Class_F Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis F1) HYSF CC 0.05 x VDDP −− V Input Leakage Current Class F IOZF CC -6000 − 6000 nA Vi< VDDP / 2 - 1V ; Vi> VDDP / 2 + 1 V; Vi≥ 0V ; Vi≤ VDDP V -3000 − 3000 nA Vi> VDDP / 2 - 1V ; Vi< VDDP / 2 + 1 V Ratio Vil/ Vih, F pads VILF / VIHF CC 0.6 −− On-Resistance of the class F pad, medium driver RDSONM CC −− 170 Ohm IOH<- 2m A ; P_MOS −− 175 Ohm IOH<- 2m A ; P_MOS; VDDP≥±5% * VD DP −− 145 Ohm IOL<2m A ; N_MOS Table 23 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 72 V 1.4.1, 2014-05 Fall time, pad type F, CMOS mode tFF CC −− 60 ns CL=5 0p F Rise time, pad type F, CMOS mode tRF CC −− 60 ns CL=5 0p F Input high voltage, pad class F, CMOS mode VIHF SR 0.6 x VDDP − min(V DDP+ 0.3, 3.6) V Input low voltage, Class F pads, CMOS mode VILF SR -0.3 − 0.36 x VDDP V Output high voltage, class F pads, CMOS mode VOHF CC VDDP- 0.4 −− V IOH≥ -1.4 mA 2.4 −− V IOH≥ -2 mA Output low voltage, class F pads, CMOS mode VOLF CC −− 0.4 V IOL≤ 2m A 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 25 Standard_Pads Class_I Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis Class I1) HYSI CC 0.1 x VDDP −− V Input Leakage Current IOZI CC -1000 − 1000 nA Ratio between low and high input threshold VILI / VIHI CC 0.6 −− Input high voltage, class I pins VIHI SR 0.6 x VDDP − min(V DDP+ 0.3, 3.6) V Input low voltage, Class I pads VILI SR -0.3 − 0.36 x VDDP V Table 24 Standard_Pads Class_F (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 73 V 1.4.1, 2014-05 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 26 LVDS_Pa ds Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Output impedance, pad class F, LVDS mode RO CC 40 − 140 Ohm Fall time, pad type LVDS tFL CC −− 2 ns termination 100 Ω ±1% Rise time, pad type LVDS tRL CC −− 2 ns termination 100 Ω ±1% Pad set-up time tSET_LVD S CC −− 13 μs termination 100 Ω ±1% Output Differential Voltage VOD CC 150 − 400 mV termination 100 Ω ±1% Output voltage high, pad class F, LVDS mode VOH CC −− 1525 mV termination 100 Ω ±1% Output voltage low, pad class F, LVDS mode VOL CC 875 −− mV termination 100 Ω ±1% Output Offset Voltage VOS CC 1075 − 1325 mV termination 100 Ω ±1%

Electrical ParametersDC Parameters Data Sheet 74 V 1.4.1, 2014-05

5.2.2 Analog to Digital Converters (ADCx)

Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Switched capacitance at the analog voltage inputs1) CAINSW CC − 92 0 p F Total capacitance of an analog input CAINTOT CC − 20 30 pF Switched capacitance at the positive reference voltage input2)3) CAREFSW CC − 15 30 pF Total capacitance of the voltage reference inputs2) CAREFTO T CC − 20 40 pF Differential Non-Linearity Error4)5)6)7) EADNL CC -3 − 3 LSB ADC resolution= 12- bit 8) 9) Gain Error4)6)5)7) EAGAIN CC -3.5 − 3.5 LSB ADC resolution= 12- bit 8) 9) Integral Non- Linearity 4)6)5)7) EAINL CC -3 − 3 LSB ADC resolution= 12- bit 8) 9) Offset Error4)6)5)7) EAOFF CC -4 − 4 LSB ADC resolution= 12- bit 8) 9)

Electrical ParametersDC Parameters Data Sheet 75 V 1.4.1, 2014-05 Converter clock fADC SC 4 − 90 MHz fADC= fFPI; SAK- TC1782F- 320F180HR / S AK-TC1782F- 320F180HL / S AK-TC1782N- 320F180HR / S AK-TC1782N- 320F180HL / S AK-TC1782N- 256F133HR / S AK-TC1782N- 256F133HL 4 − 80 MHz fADC= fFPI; SAK- TC1782F- 320F160HR / S AK-TC1782F- 320F160HL / S AK-TC1782N- 320F160HR / S AK-TC1782N- 320F160HL Internal ADC clock fADCI CC 1 − 18 MHz Charge consumption per conversion QCONV CC 70 85 10) 100 pC charge needs to be provided via VAREF0 Table 27 ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 76 V 1.4.1, 2014-05 Input leakage at analog inputs11) IOZ1 CC -100 − 500 nA Vi≤ VDDM V; Vi≥ 0.97 x VDDM V; overlayed= No -100 − 600 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= Yes -500 − 100 nA Vi≤ 0.03 x VDDM V; Vi≥ 0V ; overlayed= No -600 − 100 nA Vi≤ 0.03 x VDDM V; Vi≥ 0V ; overlayed= Yes -100 − 200 nA Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= No -100 − 300 nA Vi< 0.97 x VDDM V; Vi> 0.03 x VDDM V; overlayed= Yes Input leakage current at Varef0 IOZ2 CC -2 − 2 μA VAREF0≤ VDDM V Input leakage current at Vagnd0 IOZ3 CC -2 − 2 μA VAGND0≤ VDDM V ON resistance of the transmission gates in the analog voltage path RAIN CC − 900 1500 Ohm ON resistance for the ADC test (pull down for AIN7) RAIN7T CC 180 550 900 Ohm Table 27 ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 77 V 1.4.1, 2014-05 Resistance of the reference voltage input path RAREF CC − 500 1000 Ohm Sample time tS CC 2 − 257 T ADCI Calibration time after bit ADC_GLOBCFG.SUCAL is set tCAL CC −− 4352 cycle s Total Unadjusted Error6)5)12) TUE CC -4 − 413) LSB ADC resolution= 12- bit Analog reference ground2) VAGND0 SR VSSM - 0.05 − VAREF0 - 1 V Analog input voltage VAIN SR VAGND0 − VAREF0 V Analog reference voltage2) VAREF0 SR VAGND0 + 1 − VDDM + 0.0514) 15) V Analog reference voltage range6)5)2) VAREF0 - VAGND0 SR VDDM/2 − VDDM + 0.05 V 1) The sampling capacity of the conversion C-network is pre-charged to VAREF0/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx can deviate from VAREF0/2. 2) Applies to AINx, when used as auxiliary reference input. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage. 4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error. 5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in the ADC speed and accuracy. 6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. 7) If the analog reference voltage is > VDDM, then the ADC converter errors increase. 8) For 10-bit conversions the error value must be multiplied with a factor 0.25. 9) For 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) For a conversion time of 1 µs a rms value of 85µA result for IAREF0. 11) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. Table 27 ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 78 V 1.4.1, 2014-05 The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles. Figure 7 ADCx Input Circuits 12) Measured without noise. 13) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB 14) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 15) If the reference voltage VAREF0 increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decrease by 4LSB12. Table 28 Conversion Time (Operating Conditions apply) Parameter Symbol Values Unit Note Conversion time with post-calibration tC CC 2 × TADC +( 4+S T C+n ) × TADCI μs n = 8, 10, 12 for n - bit conversion TADC =1/ fFPI TADCI =1/ fADCIConversion time without post-calibration 2 × TADC +( 2+S T C+n ) × TADCI Reference Voltage Input Circuitry Analog Input Circuitry Analog_InpRefDiag REXT =VAIN CEXT RAIN, On CAINTOT - CAINSW CAINSW ANx VAREF RAREF, On CAREFTOT - CAREFSW CAREFSW VAGNDx VAREFx RAIN7TVAGNDx

Electrical ParametersDC Parameters Data Sheet 79 V 1.4.1, 2014-05 Figure 8 ADCx Analog Inputs Leakage VIN[VDDM%]200nA 500nA 3% 100%97% Ioz1 100nA -500nA -100nA VIN[VDDM%]300nA 600nA 3% 100%97% Ioz1 100nA -600nA -100nA Single ADC Input Overlayed ADC/FADC Input

Electrical ParametersDC Parameters Data Sheet 80 V 1.4.1, 2014-05

5.2.3 Fast Analog to Digital Converter (FADC)

Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input current at VFAREF IFAREF CC −− 120 μA Input leakage current at VFAREF1) IFOZ2 CC -500 − 500 nA VFAREF≤ VDDMF V; VFAREF≥ 0V Input leakage current at VFAGND IFOZ3 CC -500 − 500 nA

Electrical ParametersDC Parameters Data Sheet 81 V 1.4.1, 2014-05 DNL error EFDNL CC -1 − 1L S B VIN mode= differential; Gain = 1 or 2; Gain = 4 or 8 and VDDAF / VDDMF≤ ±5% * VDDAF / V DDMF[Typ] -1 − 1L S B VIN mode= single ended; Gain = 1 or 2; Gain = 4 or 8 and VDDAF / VDDMF≤ ±5% * VDDAF / V DDMF[Typ] -2 − 2L S B VIN mode= differential; Gain = 4 or 8 and VDDAF / VDDMF> ±5% * VDDAF / V DDMF[Typ]2) -2 − 2L S B VIN mode= single ended; Gain = 4 or 8and VDDAF / VDDMF> ±5% * VDDAF / V DDMF[Typ]2) Table 29 FADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 82 V 1.4.1, 2014-05 GRADient error EFGRAD CC -5 − 5% VIN mode= differential ; Gain≤ 4 -5 − 5% VIN mode= single ended ; Gain≤ 4 -6 − 6% VIN mode= differential ; Gain= 8 -6 − 6% VIN mode= single ended ; Gain= 8 INL error EFINL CC -4 − 4L S B VIN mode= differential -4 − 4L S B VIN mode= single ended Offset error EFOFF CC -90 − 90 mV VIN mode= differential ; Calibration= No -90 − 90 mV VIN mode= single ended ; Calibration= No -20 − 20 mV VIN mode= differential ; Calibration= Ye s 3)4) -20 − 20 mV VIN mode= single ended ; Calibration= Ye s 3)4) Error of commen mode voltage VFAREF/2 EFREF CC -60 − 60 mV Channel amplifier cutoff frequency fCOFF CC 2 −− MHz Table 29 FADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 83 V 1.4.1, 2014-05 Converter clock fFADC SC 1 − 90 MHz fFADC= fFPI; SAK-TC1782F- 320F180HR / S AK-TC1782F- 320F180HL / S AK-TC1782N- 320F180HR / S AK-TC1782N- 320F180HL / S AK-TC1782N- 256F133HR / S AK-TC1782N- 256F133HL 1 − 80 MHz fFADC= fFPI; SAK-TC1782F- 320F160HR / S AK-TC1782F- 320F160HL / S AK-TC1782N- 320F160HR / S AK-TC1782N- 320F160HL Conversion time tC CC −− 21 1 / fFADC For 10-bit conversion Input resistance of the analog voltage path (Rn, Rp) RFAIN CC 100 − 200 kOh m Settling time of a channel amplifier after changing ENN or ENP tSET CC −− 5 μs Analog input voltage range VAINF SR VFAGND − VDDMF V Analog reference ground VFAGND SR VSSAF - 0.05 − VSSAF + 0.05 V Analog reference voltage VFAREF SR 3.0 − 3.635) V Table 29 FADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 84 V 1.4.1, 2014-05 The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. Figure 9 FADC Input Circuits 1) This value applies in power-down mode. 2) No missing codes. 3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed minimium once per week. 4) The offser error voltage drifts over the whole temperature range maximum +-3LSB. 5) Voltage overshoot to 4V is permissible, pr ovided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots). FADC_InpRefDiag RN FAINxN FAINxP VFAGND FADC Analog Input Stage RP VFAREF /2 VFAREF FADC Reference Voltage Input Circuitry VFAGND VFAREF IFAREF

Electrical ParametersDC Parameters Data Sheet 85 V 1.4.1, 2014-05

5.2.4 Oscillator Pins

Note: It is strongly recomm ended to measure the oscill ation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Table 30 OSC_XTAL Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input current at XTAL1 IIX1 CC -25 − 25 μA VIN<VDDOSC3 ; VIN>0 V Input frequency fOSC SR 4 − 40 MHz Direct Input Mode selected 8 − 25 MHz External Crystal Mode selected Oscillator start-up time1) 1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDOSC3. The external oscillator circuitry must be opti mized by the customer and checked for negative resistance as recommended and specified by crystral suppliers. tOSCS CC −− 10 ms Input high voltage at XTAL12) 2) If the XTAL1 pin is driven by a crystal, reac hing a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is necessary. VIHX SR 0.7 x VDDOS − VDDOS C3 + 0.5 V Input low voltage at XTAL1 VILX SR -0.5 − 0.3 x VDDOS V Input Hysteresis for XTAL1 pad 3) 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. HYSAX CC −− 200 mV

Electrical ParametersDC Parameters Data Sheet 86 V 1.4.1, 2014-05

5.2.5 Temperature Sensor

The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the DTSSTAT register. (1) Table 31 DTS Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Measurement time tM CC −− 100 μs Temperature sensor range TSR SR -40 − 150 °C Sensor Accuracy (calibrated) TTSA CC -6 − 6° C Start-up time after resets inactive tTSST SR −− 20 μs Tj DTSSTAT RESULT 596–

Electrical ParametersDC Parameters Data Sheet 87 V 1.4.1, 2014-05

5.2.6 Power Supply Current

The total power supply current defined below consists of leakage and switching component. Application relevant values are typically lower than those given in the following two tables and depend on the customer 's system operating conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=180 / 160 MHz / 133 MHz, TJ=150 oC The realisic power pattern defines the following conditions:

• TJ=150 oC
• fLMB = fPCP = fCPU = 180 / 160 MHz / 133 MHz
• fFPI =9 0M H z/8 0M H z/6 6 . 5 M H z
• VDD = VDDOSC = VDDAF =1 . 3 2 6V
• VDDP = VDDOSC3 = VDDFL3 = VDDMF =3 . 3 6 6V
• VDDM =5 . 1V The max power pattern defines the following conditions: TJ=150 oC
• fLMB = fPCP = fCPU = 180 / 160 MHz / 133 MHz
• fFPI =9 0M H z/8 0M H z/6 6 . 5 M H z
• VDD = VDDOSC = VDDAF = 1.365 V / 1.43 V / 1.365 V
• VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.47 V / 3.63 V / 3.47 V
• VDDM =5 . 5V

Electrical ParametersDC Parameters Data Sheet 88 V 1.4.1, 2014-05 Table 32 Power Supply Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Core active mode supply current1)2) IDD CC −− 4863) mA power pattern= max ; SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL −− 5503) mA power pattern= max ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N-320F180HL −− 550 3) mA power pattern= max ; SAK-TC1782F-320F160HR SAK-TC1782F-320F160HL SAK-TC1782N-320F160HR SAK-TC1782N-320F160HL −− 370 4) mA power pattern= realistic ; SAK-TC1782N-256F133HR SAK-TC1782N- 256F133HL; VDD=1.326 V −− 3984) mA power pattern= realistic ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N- 320F180HL; VDD=1.326 V −− 3864) mA power pattern= realistic ; SAK-TC1782F-320F160HR SAK-TC1782F-320F160HL SAK-TC1782N-320F160HR SAK-TC1782N- 320F160HL; VDD=1.326 V IDD current at PORST Low IDD_PORS T CC −− 300 mA −− 291 mA VDD=1.326 V −− 314 mA VDD=1.43 V Analog core supply current IDDAF CC −− 23 mA

Electrical ParametersDC Parameters Data Sheet 89 V 1.4.1, 2014-05 Oscillator core supply current IDDOSC CC −− 4m A IDDP current at PORST Low IDDP_POR ST CC −− 2.5 mA IDDP current no pad activity, LVDS off 5) IDDP CC −− IDDP_P ORST + mA including flash read current −− IDDP_P ORST + mA including flash programming current 6) −− IDDP_P ORST + 20 7) mA including flash erase current Flash memory current IDDFL3 CC −− 56 mA flash read current −− 21 mA flash programming current 6) −− 56 mA flash erase current 6) Oscillator power supply current, 3.3V IDDOSC3 CC −− 15 mA FADC analog supply current, 3.3V IDDMF CC −− 15 mA Current Consumption of LVDS Pad Pairs ILVDS CC −− 12 mA for all LVDS pads in total ADC 5V power supply current IDDM CC −− 2m A Table 32 Power Supply Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 90 V 1.4.1, 2014-05 Maximum power dissipation PD CC −− 1143 mW power pattern= max ; SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL −− 1231 mW power pattern= max ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N-320F180HL −− 1231 mW power pattern= max ; SAK-TC1782F-320F160HR SAK-TC1782F-320F160HL SAK-TC1782N-320F160HR SAK-TC1782N-320F160HL −− 957 mW power pattern= realistic ; SAK-TC1782N-256F133HR SAK-TC1782N- 256F133HL; VDD=1.326 V −− 994 mW power pattern= realistic ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N- 320F180HL; VDD=1.326 V −− 979 mW power pattern= realistic ; SAK-TC1782F-320F160HR SAK-TC1782F-320F160HL SAK-TC1782N-320F160HR SAK-TC1782N- 320F160HL; VDD=1.326 V 1) Infineon Power Loop: CPU and PCP running, all peripher als active. The power consumption of each customer application will most probably be lower than this value, but must be evaluated seperately. 2) This current includes the E-Ray module power consumption, including the PCP operation component. 3) The IDD decreases typically by 68mA if the fCPU decreases by 50MHz, at constant TJ 4) The IDD decreases typically by 30mA if the fCPU decreases by 50MHz, at constant TJ 5) For operations including the D-Flash the required cu rrents are always lower than the currents for non D-Flash operation. 6) Relevant for the power supply dimensi oning, not for thermal considerations. Table 32 Power Supply Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max.

Electrical ParametersDC Parameters Data Sheet 91 V 1.4.1, 2014-05 5.2.6.1 Calculating the 1.3 V Current Consumption The current consumption of the 1.3 V rail compose out of two parts:

• Static current consumption
• Dynamic current consumption The static current consumption is related to the device temperature TJ and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption. (2) (3) Function 2 defines the typical static curren t consumption and Function 3 defines the maximum static current consumption. Both functions are valid for VDD =1 . 3 2 6V . For the dynamic current consumption using the application pattern and fLMB =2* fFPI the function 4 applies: (4) and this finally results in (5) 7) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes of up to 15 mA for maximum 5 ms per flash module. I0 2 20897 mA I0 10 68 mA IDym 06 mA IDD I0 IDYM+=

Electrical ParametersAC Parameters Data Sheet 92 V 1.4.1, 2014-05

5.3 AC Parameters

All AC parameters are defined with maximum driver strength unless otherwise noted.

5.3.1 Testing Waveforms

Figure 10 Rise/Fall Time Parameters Figure 11 Testing Waveform, Output Delay Figure 12 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR rise_fall tF mct 04881_a.vsd VDDE / 2 Test Points VDDE / 2 VSS VDDP MCT04880_new VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Electrical ParametersAC Parameters Data Sheet 93 V 1.4.1, 2014-05

5.3.2 Power Sequencing

Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence for 10% Operating Range Power-Up 10.vsd 1.3V 3.3V t V t -12% -12% PORST 0.5V0.5V 0.5V VDDP VAREF power down power fail 3.63V 2.97V 1.17V 1.43V 4.5V 5.5V

Electrical ParametersAC Parameters Data Sheet 94 V 1.4.1, 2014-05 Figure 14 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence for 5% Operating Range The following list of rules applies to the power-up/down sequence:

• All ground pins VSS must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected.
• At any moment in time to avoid increased latch-up risk, each power supply must be higher then any lower_power_supply - 0.5 V, or: – The latch-up risk is minimized if the I/O currents are limited to: – 20 mA for one pin group – AND 100 mA for the completed device I/Os – AND additionally before power-up / after power-down: 1 mA for one pin in inactive mode (0 V on all power supplies)
• During power-up and power-down, the volt age difference between the power supply pins of the same voltage (3.3 V, 1.3 V, an d 5 V) with different names (for example VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV. On the other hand, all power supply pins with the same name (for example all VDDP), are internally directly connected. It is recommended that the power pins of the same voltage are driven by a single power supply. Power-Up 5.vsd 1.3V 3.3V t V t -12% -12% PORST 0.5V0.5V 0.5V VDDP VAREF power down power fail 3.47V 2.97V 1.235V 1.365V 4.5V 5.5V

Electrical ParametersAC Parameters Data Sheet 95 V 1.4.1, 2014-05 1. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF power- supplies and the oscillator have reac hed stable operation, within the normal operating conditions. 2. At normal power down the PORST signal should be activated within the normal operating range, and then the power supp lies may be switched off. Care must be taken that all Flash write or delete sequences have been completed. 3. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V power supply voltage falls 12% below the no minal level. If, under these conditions, the PORST is activated during a Flash write, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. In order to ensure clean power-down behavior, the PORST signal should be activated as close as possible to the normal operating voltage range. 4. In case of a power-loss at any power-supply, all power supplies must be powered- down, conforming at the same time to the rules number 2 and 4. 5. Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. 6. Additionally, regarding the ADC reference voltage VAREF: – VAREF must power-up at the same time or later then VDDM, and – VAREF must power-down either earlier or at latest to satisfy the condition VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter capacitance through the ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA.

Electrical ParametersAC Parameters Data Sheet 96 V 1.4.1, 2014-05

5.3.3 Power, Pad and Reset Timing

Table 33 Reset Timings Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Application Reset Boot Time1)2) tB CC 150 − 810 μs SAK-TC1782N- 256F133HR SAK-TC1782N- 256F133HL 150 − 665 μs SAK- TC1782F320F1 80HR SAK- TC1782F320F1 80HL SAK-TC1782N- 320F180HR SAK-TC1782N- 320F180HL 150 − 740 μs SAK-TC1782F- 320F160HR SAK-TC1782F- 320F160HL / S AK-TC1782N- 320F160HR SAK-TC1782N- 320F160HL Power on Reset Boot Time 3)4) tBP CC −− 2.5 ms HWCFG pins hold time from ESR0 rising edge tHDH SR 16 / fFPI −− ns HWCFG pins setup time to ESR0 rising edge tHDS CC 0 −− ns Ports inactive after ESR0 reset active tPI CC −− 8 / fFPI ns Ports inactive after PORST reset active5) tPIP CC −− 150 ns

Electrical ParametersAC Parameters Data Sheet 97 V 1.4.1, 2014-05 Minimum PORST active time after power supplies are stable at operating levels tPOA CC 10 −− ms TESTMODE /T R S T hold time from PORST rising edge tPOH SR 100 −− ns PORST rise time tPOR SR −− 50 ms TESTMODE /T R S T setup time to PORST rising edge tPOS SR 0 −− ns 1) The duration of the boot time is defined between the ri sing edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 2) The given time includes the time of the internal reset extension for a configured value of SCU_RSTCNTCON.RELSA = 0x05BE. 3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 4) The given time includes the internal reset extension time for the System and Application Reset which is visible through ESR0. 5) This parameter includes the delay of the analog spike filter in the PORST pad. Table 33 Reset Timings Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersAC Parameters Data Sheet 98 V 1.4.1, 2014-05 Figure 15 Power, Pad and Reset Timing reset_beh2 As programmed VDDP Pads Pad-state undefined VDD VDDPPA VDDPPA thd tPOA tPOA TRST TESTMODE ESR 0 PORST tPOH HWCFG tHDH tPIP tPI Tri -state or pull device active thd tPOH tHDH t PIP tPIt PIP tPI tPI tHDH tPI VDDP -12% VDD -12%

Electrical ParametersAC Parameters Data Sheet 99 V 1.4.1, 2014-05

5.3.4 Phase Locked Loop (PLL)

Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB- Bus clock fLMB) is constantly adjusted to the sele cted frequency. The PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter t hat is limited. This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. This is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in [ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the number m of consecutive fLMB clock periods. (6) (7) With rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum Table 34 PLL_SysClk Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Accumulated Jitter DP CC -7 − 7n s PLL base frequency fPLLBASE CC 50 200 320 MHz VCO input frequency fREF CC 8 − 16 MHz VCO frequency range fVCO CC 400 − 720 MHz PLL lock-in time tL CC 14 − 200 μsN > 3 2 14 − 400 μsN ≤ 32 for K2 100 ≤() and m fLMB MHz[]() 2⁄≤() Dmn s[] 740 ⎛⎞×= else Dmn s[] 740 K2 fLMB MHz[]×

Electrical ParametersAC Parameters Data Sheet 100 V 1.4.1, 2014-05 accumulated jitter remains at a constant valu e. Further, a lower LMB-Bus clock frequency fLMB results in a higher absolute maximum jitter value. Note: The specified PLL jitter values are va lid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the pad supply voltage, measured between VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. The maximum peak-to peak noise on the pad supply voltage, measured between VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appr opriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Oscillator Watchdog (OSC_WDT) The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The OSC_WDT checks for too low frequencies and for too high frequencies. The frequency that is monitored is fOSCREF which is derived for fOSC. (8) The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is 2.5 MHz. Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2.5 MHz. The monitored frequency is too low if it is below 1.25 MHz and too high if it is above 7.5 MHz. This leads to the following two conditions:

• T o o l o w : fOSC <1 . 2 5M H z× (SCU_OSCCON.OSCVAL+1)
• Too high: fOSC >7 . 5M H z× (SCU_OSCCON.OSCVAL+1) Note: The accuracy is 30% for these boundaries. f OSCREF f OSC

Electrical ParametersAC Parameters Data Sheet 101 V 1.4.1, 2014-05

5.3.5 ERAY Phase Locked Loop (ERAY_PLL)

Note: The specified PLL jitter values are va lid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the pad supply voltage, measured between VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appr opriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Table 35 PLL_ERAY Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Accumulated jitter at SYSCLK pin DPP CC -0.8 − 0.8 ns Accumulated_Jitter DP CC -0.5 − 0.5 ns PLL Base Frequency of the ERAY PLL fPLLBASE_ ERAY CC 50 250 360 MHz VCO input frequency of the ERAY PLL fREF CC 20 − 40 MHz VCO frequency range of the ERAY PLL fVCO_ERA Y CC 450 − 500 MHz PLL lock-in time tL CC 5.6 − 200 μs

Electrical ParametersAC Parameters Data Sheet 102 V 1.4.1, 2014-05

5.3.6 JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 36 JTAG Interface Timing Parameters (Operating Conditions apply) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. TCK clock period t1 SR 25 – – ns – TCK high time t2 SR 10 – – ns – TCK low time t3 SR 10 – – ns – TCK clock rise time t4 S R ––4n s – TCK clock fall time t5 S R ––4n s – TDI/TMS setup to TCK rising edge t6 S R 6––n s – TDI/TMS hold after TCK rising edge t7 S R 6––n s – TDO valid after TCK falling edge1) (propagation delay) 1) The falling edge on TCK is used to generate the TDO timing. t8 C C ––1 3 n s C L =5 0p F t8 C C 3––n s C L =2 0p F TDO hold after TCK falling edge1) t18 C C 2––n s TDO high imped. to valid from TCK falling edge1)2) 2) The setup time for TDO is given implicitly by the TCK cycle time. t9 C C ––1 4 n s C L =5 0p F TDO valid to high imped. from TCK falling edge1) t10 CC – – 13.5 ns C L =5 0p F

Electrical ParametersAC Parameters Data Sheet 103 V 1.4.1, 2014-05 Figure 16 Test Clock Timing (TCK) Figure 17 JTAG Timing MC_JTAG _TCK

0.9 VDDP

0.5 VDDP

0.1 VDDP

MC_JTAG t18

Electrical ParametersAC Parameters Data Sheet 104 V 1.4.1, 2014-05

5.3.7 DAP Interface Timing

The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Figure 18 Test Clock Timing (DAP0) Table 37 DAP Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. DAP0 clock period1) 1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state. tTCK SR 12.5 −− ns DAP0 high time t12 SR 4 −− ns DAP0 low time1) t13 SR 4 −− ns DAP0 clock rise time t14 SR −− 2n s DAP0 clock fall time t15 SR −− 2n s DAP1 setup to DAP0 rising edge t16 SR 6.0 −− ns DAP1 hold after DAP0 rising edge t17 SR 6.0 −− ns DAP1 valid per DAP0 clock period2) 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t19 CC 8 −− ns CL=2 0p F ; f=8 0M H z 10 −− ns CL=5 0p F ; f=4 0M H z MC_DAP0

Electrical ParametersAC Parameters Data Sheet 106 V 1.4.1, 2014-05

5.3.8 Peripheral Timings

Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization.

5.3.8.1 Micro Link Interface (MLI) Timing

Figure 21 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. t27 t25 t26 t16 t17 t15t15 MLI_Tmg_2.vsd TDATAx TVALIDx TCLKx RDATAx RVALIDx RCLKx TREADYx RREADYx t10 t13 t11 t12 t14 t20 t27 MLI Transmitter Timing MLI Receiver Timing t23 t21 t22 t24

Electrical ParametersAC Parameters Data Sheet 107 V 1.4.1, 2014-05 The MLI parameters are vaild for CL = 50 pF and for strong driver medium edge. Table 38 MLI Receiver Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. RCLK clock period t20 SR 1 / fFPI −− ns RCLK high time1)2) 1) The following formula is valid: t21 + t22 = t20. 2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver timing parameters. t21 SR − 0.5 x t20 − ns RCLK low time1)2) t22 SR − 0.5 x t20 − ns RCLK rise time3) 3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower input signal rise/fall times can be used for longer RCLK clock periods. t23 SR −− 4n s RCLK fall time3) t24 SR −− 4n s RDATA/RVALID setup time before RCLK falling edge t25 SR 4.2 −− ns RDATA/RVALID hold time after RCLK falling edge t26 CC 2.2 −− ns RREADY output delay time t27 CC 0 − 16 ns Table 39 MLI Transmitter Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. TCLK clock period t10 CC 2 x 1 / fFPI −− ns TCLK high time1)2) t11 CC 0.45 x t10 0.5 x t10 0.55 x t10 ns TCLK low time1)2) t12 CC 0.45 x t10 0.5 x t10 0.55 x t10 ns TCLK rise time t13 CC −− 0.3 x t10 ns

Electrical ParametersAC Parameters Data Sheet 108 V 1.4.1, 2014-05

5.3.8.2 Micro Second Channel (MSC) Interface Timing

The MSC parameters are vaild for CL =5 0p F . TCLK fall time t14 CC −− 0.3 x t10 ns TDATA/TVALID output delay time t15 CC -3 − 4.4 ns TREADY setup time before TCLK rising edge t16 SR 18 −− ns TREADY hold time after TCLK rising edge t17 SR -2 −− ns 1) The following formula is valid: t11 + t12 = t10. 2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be regarded additionally to t11 / t12. 3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended for TCLK. Table 40 MSC Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. FCLP clock period1)2) t40 CC 2 x TMSC −− ns SOP4)/ENx outputs delay from FCLP4) rising edge t45 CC -2 − 5 ns ENx with strong driver and sharp (minus ) edge -2 − 10 ns ENx with strong driver and medium (minus) edge 0 − 21 ns ENx with strong driver and soft edge Table 39 MLI Transmitter (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersAC Parameters Data Sheet 109 V 1.4.1, 2014-05 Figure 22 MSC Interface Timing Note: The data at SOP should be sampled with the falling edge of FCLP in the target device. SDI bit time t46 CC 8 x TMSC −− ns SDI rise time 5) t48 SR −− 200 ns SDI fall time 5) t49 SR −− 200 ns 1) FCLP signal rise/fall times are only defined by the pad rise/fall times. 2) FCLP signal high and low can be minimum 1xT MSC 3) TMSC = TSYS = 1 / fSYS. 4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge. 5) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated. Table 40 MSC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. MSC_Tmg_1.vsd t45 t45 t40

Electrical ParametersAC Parameters Data Sheet 110 V 1.4.1, 2014-05

5.3.8.3 SSC Master/Slave Mode Timing

The SSC parameters are vaild for CL = 50 pF and for strong driver medium edge. Table 41 SSC Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. SCLK clock period1)2)3) 1) SCLK signal rise/fall times are the same as the rise/fall times of the pad. 2) SCLK signal high and low times can be minimum 1xTSSC. 3) TSSCmin = TSYS = 1/fSYS. t50 CC 2 x 1 / fFPI −− ns MTSR/SLSOx delay form SCLK rising edge t51 CC 0 − 8n s MRST setup to SCLK falling edge3) t52 SR 16.5 −− ns MRST hold from SCLK falling edge3) t53 SR 0 −− ns SCLK input clock period1)3) t54 SR 4 x 1 / fFPI −− ns SCLK input clock duty cycle t55_t54 SR 45 − 55 % MTSR setup to SCLK latching edge3)4) 4) Fractional divider switched off, SSC internal baud rate generation used. t56 CC 1 / fFPI −− ns MTSR hold from SCLK latching edge t57 CC 1 / fFPI + 5 −− ns SLSI setup to first SCLK latching edge t58 CC 1 / fFPI + 5 −− ns SLSI hold from last SCLK latching edge5) 5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair of shifting / latching edges. t59 CC 7 −− ns MRST delay from SCLK shift edge t60 CC 0 − 16.5 ns SLSI to valid data on MRST t61 CC −− 16.5 ns

Electrical ParametersAC Parameters Data Sheet 112 V 1.4.1, 2014-05

5.3.8.4 ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with CL = 25 pF. The ERAY interface is only availa ble for the SAK-TC1782F-320F180HR / SAK- TC1782F-320F180HL / SAK-TC1782F-320F160HR / SAK-TC1782F- 320F160HL / SAK-TC1782F-320F133HR / SAK-TC1782F-320F133HL. Table 42 ERAY Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Time span from last BSS to FES without the influence of quartz tolerancies (d10Bit_TX) 1) This includes the PLL_ERAY accumulated jitter. t60 CC 997.75 − 1002.2 ns TxD data valid from fsample flip flop txd_reg TxDA, TxDB (dTxAsym)2)3) 2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers. Quarz tolerance and PLL_ERAY accumulated jitter are not included. 3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of | tFA2 - tRA2| ≤ 1 ns. t61-t62 CC −− 1.5 ns Asymmetrical delay of rising and falling edge (TxDA, TxDB) Time span between last BSS and FES without influence of quartz tolerancies (d10Bit_RX) 1)4)5) 4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied. t63 SR 966 − 1046.1 ns RxD capture by fsample (RxDA/RxDB sampling flip-flop) (dRxAsym) t64-t65 CC −− 3.0 ns Asymmetrical delay of rising and falling edge (RxDA, RxDB) TxD data delay from sampling flip-flop dTxdly CC −− 10.0 ns Px_PDR.PDy = 000B −− 15.0 ns Px_PDR.PDy = 001B RxD capture delay by sampling flip-flop dRxdly CC −− 10.0 ns

Electrical ParametersAC Parameters Data Sheet 113 V 1.4.1, 2014-05 Figure 25 ERAY Timing 5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns. TXD t60

0.7 VDD

0.3 VDD

(Byte Start Sequence) Last CRC Byte FES (Frame End Sequence) ERAY_TIMING RXD t63 (Byte Start Sequence) Last CRC Byte FES (Frame End Sequence)

0.9 VDD

0.1 VDD

Electrical ParametersPackage and Reliability Data Sheet 114 V 1.4.1, 2014-05

5.4 Package and Reliability

5.4.1 Package Parameters

Table 43 Thermal Characteristics of the Package Device Package R ΘJCT 1) The top and bottom thermal resistances between the case and the ambient ( RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient ( RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA is the total thermal resistance between the junction an d the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1). RΘJCB 1) RΘJLead Unit Note TC1782 PG-LQFP-176- 10 / PG-LQFP- 176-20 8,1 0,3 30,9 K/W with soldered exposed pad 2) 2) It is recommended by Infineon Techno logies AG to connect the exposed pad. TC1782 PG-LQFP-176- 10 / PG-LQFP- 176-20 8,1 12,6 30,9 K/W with not soldered exposed pad

Electrical ParametersPackage and Reliability Data Sheet 115 V 1.4.1, 2014-05

5.4.2 Package Outline

Figure 26 Package Outlines PG -LQFP-176-10 / PG-LQFP-176-20 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.

5.4.3 Flash Memory Parameters

The data retention time of the TC1782’s Flash memory depends on the number of times the Flash memory has been erased and programmed. Table 44 Exposed pad Dimensions Ex 7.8 mm Ey 7.8 mm Exposed DIPAD

Electrical ParametersPackage and Reliability Data Sheet 116 V 1.4.1, 2014-05 Table 45 FLASH32 Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Data Flash Erase Time per Sector tERD CC −− 31) s Program Flash Erase Time per 256 KByte Sector tERP CC −− 5s Program time data flash per page2) tPRD CC −− 5.3 ms without reprogramming −− 15.9 ms with two reprogramming cycles Program time program flash per page tPRP CC −− 5.3 ms without reprogramming −− 10.6 ms with one reprogramming cycle Data Flash Endurance NE CC 60000 −− cycle s Min. data retention time 5 years Erase suspend delay tFL_ErSusp CC −− 15 ms Wait time after margin change tFL_Margin Del CC 10 −−μ s Program Flash Retention Time, Physical Sector5)6) tRET CC 20 −− year s Max. 1000 erase/program cycles Program Flash Retention Time, Logical Sector 5)6) tRETL CC 20 −− year s Max. 100 erase/program cycles UCB Retention Time5)6) tRTU CC 20 −− year s Max. 4 erase/program cycles per UCB Wake-Up time tWU CC −− 270 μs

Electrical ParametersPackage and Reliability Data Sheet 117 V 1.4.1, 2014-05

5.4.4 Quality Declarations

1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can increase by up to 100%. 2) In case the Program Verify featur e detects weak bits, these bits will be programmed up to twice more. Each reprogramming takes additional 5 ms. 3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5 ms. 4) Only valid when a robust EEPROM emulation algorith m is used. For more details see the User´s Manual. 5) Storage and inactive time included. 6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is minimum 0.7 years. Table 46 Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Operation Lifetime1) tOP – – 24000 hours – 2) ESD susceptibility according to Human Body Model (HBM) VHBM – – 2000 V Conforming to JESD22-A114-B ESD susceptibility of the LVDS pins VHBM1 –– 5 0 0V – ESD susceptibility according to Charged Device Model (CDM) VCDM – – 500 V Conforming to JESD22-C101-C Moisture Sensitivity Level MSL – – 3 – Conforming to Jedec J-STD-020C for 240°C Table 45 FLASH32 Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Electrical ParametersPackage and Reliability Data Sheet 118 V 1.4.1, 2014-05 1) This lifetime refers only to the time when the device is powered on. 2) For worst-case temperature profile equivalent to: 1200 hours at Tj = 125...150oC 3600 hours at Tj = 110...125oC 7200 hours at Tj = 100...110oC 11000 hours at Tj = 25...100oC 1000 hours at Tj = -40...25oC

Data Sheet 119 V 1.4.1, 2014-05 6H i s t o r y The following changes where done between Version 0.7 and 0.8 of this document:

• Change product name from SAK-TC17 82-320F180HL to SAK-TC1782-320F180HR
• Change product name from SAK-TC17 82-256F133HL to SAK-TC1782-256F133HR
• Change DFLASH size from 64Kbyte to 128Kbyte in chapter 1
• Add ADC module abbreviation to table 1 Analog Input Port Function description
• Change SCU_RTID and SCU_CHIPID values to match the step
• Extend VDDOSC3 to -7.5 %
• Add parameter HYSA1+
• Add parameter HYSA2
• Add parameter VILF / VIHF
• Add parameter RDSONF
• Changed typical value of CAINSW from 7 to 9 pF
• Changed typical value of CAINTOT from 25 to 20 pF
• Remove 3.3 V values from ADC section
• Add parameter fADC
• Changed max. value of fADCI from 20 to 18 MHz
• Remove parameter IAIN7T (covered by RAIN7T )
• Replace parameter IAREF by QCONV
• Changed typical value of RAIN from 700 to 900 Ohm
• Add parameter tS
• Add footnote to max value of TUE
• Add parameter fFADC
• Add parameter tC
• Add formula for DTS temperature calculation
• Adapt current values to reduced limits of BA step
• Add clarification to parameter ILVDS
• Remove parameter RTHJA (not required)
• Add clarification to parameter tPOH description
• Add clarification to parameter tPOS description
• Add min. value to parameters tL
• Changed typical value of fPLLBASE_ERAY from 200 to 250 MHz
• Add MSC t45 behavior for CMOS / LVDS usage
• Add RTHs for non soldered exposed pad
• Add table 33
• Change DTS accuracy to 6°C of the complete temperature range
• Remove limitations of the DFLASH and PFLASH operating in extended Range operating conditions
• Change package version von PG-LQFP-176-6 to PG-LQFP-176-12 The following changes where done between Version 0.8 and 1.0 of this document:
• Change package version von PG-LQFP-176-12 to PG-LQFP-176-10

Data Sheet 120 V 1.4.1, 2014-05

• improve description in table 2 for analog channels
• add class A1+ to type list of table 2
• add clarification that table 7 defines the conditions for all other parameters
• add note the spike filter is only available for the PORST pin
• add Vil to Vih ratio for A1+ pad
• remove irritating Note / Test Conditions
• adapt maximum power dissipation values
• add conditions for MLI, MSC, SSC, parameters
• changed definition for t13 and t14 of the MLI timing
• changed definition for t45 of the MSC timing
• add parameters dTxdly an d dRxdly to ERAY parameters
• correct ERAY parameters t60 and t63 values
• correct footnotes for ERAY parameters
• split flash parameters tPRD and tPRP in two conditions
• add conditions to LVDS pad parameters
• Changed VAREFx to VAREF 0 and VAGNDx to VAGND0
• remove Pin Reliability in Overload section
• add parameters IIN and Sum IIN to absolute ratings
• adjust thresholds in figure 28 (ERAY)
• add parameter HYSX to PSC_XTAL
• added RDSON values for all driver settings (weak, medium, and strong)
• removed footnote 2 of table 6
• change conditions for RDSON weak parameters
• change load for timing of SSC, MSC, and MLI from C L =2 5p F t o CL = 50 pF (typical)
• add type I to legend of table 2
• add SAK-TC1782-320F180HL and SAK-TC1782-256F133HL
• changed timing checkpoints in figure 23
• add section 5.2.6.1
• add to parameters t RF and tFF condition CL =5 0p F
• add new footnote 7) to ADC parameter table
• add min and max value for Q CONV and adapt typ value
• add load conditions for t FF1 and tRF1
• add conditions to PLL parameter t L
• change DAP parameter t 19 from SR to CC classification
• remove footnote 2 for the FADC
• increase current for IDDP_POR from 2 to 2.5mA
• add footnote 3 to table 9
• change SAK-TC1782-320F180HR / SAK-TC1782-320F180HL to SAK-TC1782F- 320F180HR / SAK-TC1782F-320F180HL
• change SAK-TC1782-256F133HR / SAK-TC1782-256F133HL to SAK-TC1782F- 256F133HR / SAK-TC1782F-256F133HL
• add information for the following products: – SAK-TC1782N-320F180HR

Data Sheet 121 V 1.4.1, 2014-05 – SAK-TC1782N-320F180HL – SAK-TC1182N-320F180HR – SAK-TC1182N-320F180HL – SAK-TC1782N-256F133HR – SAK-TC1782N-256F133HL – SAK-TC1182N-256F133HR – SAK-TC1182N-156F133HL The following changes where done between Version 1.0 and 1.1 of this document:

• add section Pin Reliability in Overload
• remove sentence ‘Exposure to conditions within the maximum ratings will not affect device reliability. To replace this sentenc e section Pin Reliability in Overload was added.
• increase values for abso lute maximum parameters IIN and SumIIN
• remove capacitance conditions for LV DS pad parameters as loads are defined by interface (MSC) timings
• remove term typical from load of Peripheral Timings
• add definition of driver strength settings for ERAY Interface Timing
• change footnote 4 wording for ERAY timing back to TC1797 wording
• increase flash parameters tPRD and tPRP values
• rework the 3.3 V current part of the Powe r Supply Parameters for better description and usage – Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following way – IDDP_FP is replaced by IDDP with the condition including flash programming current – IDDFL3E is replaced by IDDP with the condition including flash erase verify current – IDDFL3R is replaced by IDDP with the condition including flash read current – parameter IDDFL3R was renamed to IDDFL3 The rework of the 3.3 V current part of the Power Supply Parameters was done for simplification and clarification. Former given values could still be used if liked, the new definition results in the same resulting values or slightly better values. The flash module is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case different allocations for the two domains resulting. The application typical case ‘flash read’ has max IDDP of 12 mA and max IDDFL3 of 56 mA resulting is a sum of 68 mA. The case ‘flash programming’ has max IDDP of 27 mA and max IDDFL3 of 21 mA resulting is a sum of 48 mA. The case ‘flash erase verify’ has max IDDP of 20 mA and max IDDFL3 of 56 mA resulting is a sum of 76 mA. So for the old parameter IDDP with 15 mA, the new version reads as IDDP = 12+IDDP_PORST = 14.5 mA for the same application relevant case. The following changes where done between Version 1.1 and 1.2 of this document:

Data Sheet 122 V 1.4.1, 2014-05

• removed products SAK-TC1182N-320F180HR, SAK-TC1182N-320F180HL, SAK- TC1182N-256F133HR, and SAK-TC1182N-256F133HL
• improve parameters IDDFL3
• change for parameter NE note from Max. data retention to Min.
• removed the term (typical)
• change description of parameter tCAL for the ADC
• correct typo for class D pads in tables 14 and 15
• adapt Absolute Maximun Rating
• add footnote to Flash parameter tERD
• add note at the end of Pin Reliability in Overload section
• clearify pad supply levels in Pin Reliability in Overload section
• add footnote for D-Flash currents in power section The following changes where done between Version 1.2 and 1.3 of this document:
• add product option SAK-TC1782F-3 20F160HL, SAK-TC1782F-320F160HR, SAK- TC1782N-320F160HL and SAK-TC1782N-320F160HR
• update block diagrams to cover new option
• add identification registers for new product option
• rework first sentence for chapter 5.3
• reduce min value for tL for both PLLs
• add for MLI and SSC parameter: valid strong driver medium edge only
• add footnote 5) for SSC parameters
• update FADC parameter EFDNL
• change MLI parameter t17 min value
• rename section Extented Range Operating Conditions to Voltage Operating timing Profiles and remove limitions on GPIOs
• split RDSONM for class F pads into two conditions The following changes where done between Version 1.3 and 1.3.1 of this document:
• correct typos in table 1 – SAK-TC1782N-320N160HR -> SAK-TC1782F-320F160HR – SAK-TC1782N-320N160HL -> SAK-TC1782F-320F160HL
• reduce current for ILVDS from 24mA to 12mA (only 2 pairs are available) The following changes where done between Version 1.3.1 and 1.4 of this document:
• remove the following product options: – SAK-TC1782F-256F133HR – SAK-TC1782F-256F133HL
• change t48 from 100ns to 200ns in table 42
• change t49 from 100ns to 200ns in table 42
• extend KOVAN conditon from IOV≤ 0m A ; IOV≥ -1 mA to IOV≤ 0m A ; IOV≥ -2 mA
• change parameter EFOFF from +-90mV to +-120 for condition Calibration = No The following changes where done between Version 1.4 and 1.4.1 of this document:
• change parameter EFOFF from +-120mV to +-90 for condition Calibration = No

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