S9840

S9840 HAMAMATSU | Alldatasheet

Document overview

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Technical content

Features

/K6C Optimized structure for full line binning (1D operation) /K6C High quantum efficiency in UV region /K6C Stable UV response /K6C Low dark current (MPP operation) /K6C No image-lag

Applications

/K6C Spectrometer, etc. CCD image sensor High UV sensitivity CCD image sensor S9840 I General ratings Parameter Specification Pixel size 14 (H) × 14 (V) µm Number of pixels 2080 × 20 pixels Number of active pixels 2048 × 14 pixels Active area 28.672 (H) × 0.196 (V) mm Vertical clock phase 2-phases Horizontal clock phase 2-phases Output circuit Two-stage MOSFET source follower Package 22-pin ceramic PGA Window Quartz glass I Absolute maximum ratings (Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Operating temperature Topr -50 - +50 °C Storage temperature Tstg -50 - +70 °C OD voltage V OD -0.5 - +25 V RD voltage VRD -0.5 - +18 V OFD voltage V OFD -0.5 - +18 V ISH voltage VISH -0.5 - +18 V IGH voltage V IGH -10 - +15 V SG voltage VSG -10 - +15 V OG voltage V OG -10 - +15 V RG voltage VRG -10 - +15 V TG voltage V TG -10 - +15 V Vertical clock voltage VP1V, VP2V -10 - +15 V Horizontal clock voltage V P1H, VP2H -10 - +15 V

I Operating conditions (MPP mode, Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Output transistor drain voltage V OD 18 20 22 V Reset drain voltage VRD 11.5 12 12.5 V Over flow drain voltage V OFD 11.5 12 12.5 V Output gate voltage VOG 1 3 5 V Substrate voltage V SS -0- V Test point (input source) VISH - VRD - V Test point (input gate) V IGH -8 0 - V High VP1VH, VP2VH 4 6 8Vertical shift register clock voltage Low VP1VL, VP2VL -9 -8 -7 V High V P1HH, VP2HH 468Horizontal shift register clock voltage Low V P1HL, VP2HL -9 -8 -7 V High VOFGH 4 6 8Over flow gate voltage Low VOFGL -9 -8 -7 V High V SGH 468Summing gate voltage Low V SGL -9 -8 -7 V High VRGH 4 6 8Reset gate voltage Low VRGL -9 -8 -7 V High V TGH 468Transfer gate voltage Low V TGL -9 -8 -7 V I Electrical characteristics (Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Vertical shift register capacitance C P1V, CP2V - 300 - pF Horizontal shift register capacitance CP1H CP2H - 160 - pF Summing gate capacitance C SG -5- p F Reset gate capacitance CRG - 10 - pF Transfer gate capacitance C TG -6 0- p F I Electrical and optical characteristics (Ta=25 °C, unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Saturation output voltage Vsat - Fw × Sv - V Full well capacity Fw - 130 - ke- CCD node sensitivity Sv - 4.0 - µV/e - Dark current *1 DS - 40 120 pA/cm2 Readout noise *2 Nr - 25 30 e - rms Readout speed fc - - 5 MHz Dynamic range *3 DR - 5200 - - Spectral response range λ - 200 to 1100 - nm Photo response non-uniformity *4 PRNU - ±3 ±10 % *1: Dark current nearly doubles for every 5 to 7 °C increase in temperature. *2: At 2 MHz readout. *3: Dynamic range (DR) = Full well/Readout noise *4: Measured at the half of the full well capacity output. Fixed pattern noise (peak to peak) Signal × 100 [%]PRNU =

INTEGRATION PERIOD INTEGRATION PERIOD P1V P2H SG READOUT PERIODVERTICAL BINNING PERIOD Tpwv Tovr P2V, TG P1H, OFG RG Vos Tpwh, Tpws Tpwr I Timing chart (Line binning) KMPDC0211EA Parameter Symbol Remark Min. Typ. Max. Unit Pulse width Tpwv 1 - - µsP1V, P2V, TG Rise and fall time Tprv, Tpfv 20 - - ns Pulse width Tpwh 50 - - ns Rise and fall time Tprh, Tpfh 10 - - nsP1H, P2H, OFG Duty ratio - - 50 - % Pulse width Tpws 50 - - ns Rise and fall time Tprs, Tpfs 10 - - nsSG Duty ratio - -5 0- % Pulse width Tpwr 15 - - nsRG Rise and fall time Tprr, Tpfr - 10 - - ns TG (P2V) - P1H Overlap time Tovr - 3 - - µs *5: Symmetrical pulses should be overlapped at 50 % of maximum amplitude. I Device structure (Conceptual drawing of top view) KMPDC0210EA

14 SIGNAL OUT

3 BEVEL 3 BEVEL

V 12345 H

8 BLANK 2048 SIGNAL OUT 8 BLANK

8 BEVEL 8 BEVEL

WAVELENGTH (nm) QUANTUM EFFICIENCY (%) 200 400 600 800 1000 100 1200 (Typ. Ta=25 ˚C) I Spectral response (without window) KMPDB0247EA

HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2007 Hamamatsu Photonics K.K. Cat. No. KMPD1082E09 Aug. 2007 DN I Dimensional outline (unit: mm) ACTIVE AREA 28.672 3.1 ± 0.25 0.457 9.0 2.0 * ± 0.153.5 PHOTOSENSITIVE SURFACE 7.62 2.54 A11 B11 INDEX MARK PIN No. 1 * Distance between window surface and photosensitive surface 14.0 +0.6 -0.2 40.0 +0.7 -0.4 KMPDA0186ED I Pin connections Pin No. Symbol Function Remark (standard operation) A1 OS Output transistor source, internal R L Output signal A2 OD Output transistor drain DC (+20 V) A3 SS Substrate (GND) GND A4 RD Reset drain DC (+12 V) A5 RG Reset gate Clock (+6/-8 V) A6 OG Output gate DC (+3 V) A7 OFD Output flow drain DC (+12 V) A8 OFG Output flow gate Same pulse as P1H A9 P2H CCD horizontal register clock-2 Clock (+6/-8 V) A10 P1H CCD horizontal resister clock-1 Clock (+6/-8 V) A11 ISH Test point (input source) DC (+12 V) B1 SG Summing gate Same pulse as P2H B2 P2V CCD vertical register clock-2 Clock (+6/-8 V) B3 P1V CCD vertical register clock-1 Clock (+6/-8 V) B4 TG *6 Transfer gate Same pulse as P2V B5 - - - B6 - - - B7 RD Reset drain DC (+12 V) B8 SS Substrate (GND) GND B9 P1V CCD vertical register clock-1 Clock (+6/-8 V) B10 P2V CCD vertical register clock-2 Clock (+6/-8 V) B11 IGH Test point (input gate) GND *6: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as P2V.